A low-temperature hybrid bonding interconnect structure and its manufacturing method
By using a polycrystalline AlN bonding auxiliary layer and ultra-vacuum oxygen-free surface activation bonding technology, the problems of dielectric bonding strength and electrode contact resistance in low-temperature hybrid bonding were solved, and the fabrication of high-density interconnect structures at low temperatures was realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUBEI JIUFENGSHAN LAB
- Filing Date
- 2024-12-09
- Publication Date
- 2026-06-30
AI Technical Summary
Existing hybrid bonding technologies struggle to achieve strong bonding between dielectrics at low temperatures, and the use of amorphous silicon bonding layers results in high electrode contact resistance. Traditional high-temperature processes also lead to severe wafer warping.
By employing a polycrystalline bonding auxiliary layer such as AlN and using ultra-vacuum oxygen-free surface activation bonding technology, bonding of the amorphous dielectric layer is achieved at low temperature. The polycrystalline AlN layer also blocks Cu diffusion, thereby reducing the Cu-Cu interface resistance.
It achieves strong bonding between media at low temperatures or even room temperature, reduces Cu-Cu interface resistance and thermal stress, and improves bonding strength and integration density.
Smart Images
Figure CN119786476B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of microelectronics integration technology, specifically relating to a hybrid bonding interconnect structure and its manufacturing method. Background Technology
[0002] With the rapid development of artificial intelligence, high-performance computing, and the Internet of Things, the semiconductor industry is approaching the limits of Moore's Law. Enhancing device functionality by increasing the number of transistors on a two-dimensional plane and shrinking feature sizes is becoming increasingly challenging, leading to expectations for further increases in chip density through three-dimensional integration. Hybrid bonding, as a leading technology for high-density interconnects in three-dimensional integration, has attracted widespread attention. Hybrid bonding, by combining dielectric bonding with embedded metal, enables interconnects between electrodes smaller than 10 μm, an interconnect density difficult to achieve with traditional bump bonding and copper pillar interconnects. This technology is currently being used in applications such as back-illuminated CMOS image sensor chips, stacked integration of Micro-LED microdisplay chips and CMOS driver chips, and integration of GaN RF chips and CMOS digital chips. Cu pad pitch is a key factor affecting interconnect density and spacing. As the Cu pad pitch further decreases, the proportion of surface Cu and SiO2 dielectric increases further, significantly increasing the difficulty of thermal and stress management. Due to the approximately 400% and -83% thermal expansion coefficient mismatch between Cu metal and Si and SiO2 dielectrics, respectively, the high temperatures (300-400°C) during traditional hybrid bonding processes become increasingly critical. This can easily cause significant wafer deformation, making bonding impossible. Developing low-temperature or even room-temperature hybrid bonding processes is a key technology that future high-density interconnect technologies need to overcome. However, current traditional hybrid bonding processes are limited by their process principles, making it difficult to achieve process temperatures below 200°C. Therefore, it is essential to develop new hybrid bonding technologies to meet the needs of future high interconnect density and low temperature (<200) requirements. Even the need for room temperature mixed bonding.
[0003]
[0004] There are two main types of bonding technologies in the existing technology, and their process flow and defects are as follows.
[0005] The first technical solution: typical key processes of hybrid bonding technology, such as... Figure 1As shown. After the RDL wiring layer is completed on the upper and lower chip wafers, SiO2 dielectric is deposited on the surface. Through a series of processes such as photolithography, etching, Cu metal electroplating, and chemical mechanical polishing, the SiO2 / Cu mixed surface is planarized and polished, so that the Cu metal surface is about 3~5nm lower than the SiO2 surface, which is the so-called Cu electrode dishing effect. Then, through fusion bonding technology, the SiO2 dielectric is first bonded together. Then, heating causes the Cu electrodes on the upper and lower wafer surfaces to expand and form a contact. Finally, annealing is carried out at a high temperature of 300~400℃ for half an hour to several hours, so that the Cu atoms of the upper and lower Cu electrodes diffuse into each other at the contact interface and form a good conductive connection.
[0006] The first drawback is that Cu metal is easily oxidized, so in typical hybrid bonding processes, an oxide layer usually forms on the Cu surface. When the upper and lower Cu electrodes expand due to heat to form a contact, a copper oxide layer of about a few nanometers exists at the interface. This oxide layer hinders the diffusion of Cu atoms, thereby increasing the interconnect resistance. Therefore, to allow Cu atoms of the upper and lower Cu electrodes to diffuse into each other and form a lower contact resistance, a higher annealing temperature (e.g., 400°C) and annealing time are usually required. Since the coefficients of thermal expansion of Cu metal and SiO2 dielectric differ by tens of times (~35 times), large thermal stress is easily generated, leading to large wafer deformation and causing alignment misalignment between electrodes. (See reference...) Figure 2 (From Investigation and Effects of Wafer Bow in 3D Integration Bonding Schemes, Journal of ELECTRONIC MATERIALS, Vol. 39, No. 12, 2010 DOI: 10.1007 / s11664-010-1341-y2010 TMS) and Figure 3 (From Kim, Sarah Eunkyung; Kim, Sungdong. (2015). Wafer level Cu–Cu direct bonding for 3D integration. Microelectronic Engineering, 137(), 158–163. doi:10.1016 / j.mee.2014.12.012). Especially when interconnect density is further increased, the proportion of metal to dielectric increases, and the stress caused by the mismatch of thermal expansion coefficients will be more severe under high-temperature processes.
[0007] The second technical solution: To reduce the process temperature, a low-temperature hybrid bonding technology based on surface activated bonding (SAB) has been proposed, such as... Figure 4 As shown. Surface activation bonding technology refers to bonding in ultra-high vacuum (10⁻⁶ m² / h⁻¹). -8 In an environment of mbar, high-energy ions bombard the wafer surface, creating a high density of dangling bonds. Then, at room temperature, the dangling bonds on the upper and lower wafer surfaces combine to achieve wafer bonding. During this process, high-energy ions effectively remove the oxide layer on the Cu electrode surface, and because bonding occurs in an ultra-high vacuum environment, oxidation of the Cu electrode surface is effectively suppressed. This allows the annealing temperature to be lowered to below 150°C, significantly reducing the process thermal budget.
[0008] The second drawback: While SAB bonding technology can achieve strong bonding between metals and crystalline materials at low temperatures, it cannot achieve strong bonding between dielectric materials, especially in SiO2 dielectrics, where the bonding strength is only 0.5 J / m. 2 Therefore, in order to improve the hybrid bonding strength, Figure 5 In the process, a layer of amorphous silicon bonding material, several nanometers thick, is intentionally deposited on the surfaces of the upper and lower wafers. Figure 5 (b) is a transmission electron microscope image of the Cu-Cu interface based on SAB hybrid bonding. Figure 5 Image (c) is a transmission electron microscope (TEM) image of the SiO2-SiO2 interface based on SAB hybrid bonding. This amorphous silicon bonding layer can increase the bonding strength to 1.5 J / m. 2 However, this also increases the contact resistance between the Cu electrodes. Figure 5 In example (b), the contact resistance of the Cu electrode is as high as 4.1 Ω. In addition, the amorphous silicon adhesive layer covering the surfaces of both Cu and SiO2 dielectrics may cause leakage between the electrodes. Summary of the Invention
[0009] Based on the above description, the present invention provides a low-temperature hybrid bonding interconnect structure and manufacturing method to solve the problem that it is difficult to achieve strong bonding between dielectrics in SAB low-temperature bonding technology and the problem of high electrode contact resistance in SAB hybrid bonding using amorphous silicon adhesive layers.
[0010] A low-temperature hybrid bonding interconnect structure includes a first interconnect structure and a second interconnect structure, both of which have the same structure.
[0011] Both the first interconnect structure and the second interconnect structure include a substrate with an embedded metal structure connected to it, and an etch barrier layer, an amorphous dielectric layer and a bonding aid layer are sequentially connected to one side of the substrate.
[0012] A countersunk hole is formed in the middle of the first interconnect structure and the second interconnect structure at the position corresponding to the embedded metal. The countersunk hole spans the bonding auxiliary layer, the amorphous dielectric layer, and the etching barrier layer.
[0013] The inner wall of the countersunk hole is connected to a diffusion barrier and a seed layer, while the top surface of the embedded metal structure has no diffusion barrier and a seed layer.
[0014] Interconnecting metal is embedded in the countersunk holes of both interconnecting structures, and its two ends are respectively connected to the embedded metal of the first interconnecting structure and the second interconnecting structure; the interconnecting metal, the embedded metal structure of the first interconnecting structure, and the embedded metal structure of the second interconnecting structure can form an electrical connection;
[0015] The first interconnect structure and the second interconnect structure are directly connected together by surface-atomic covalent bonds formed by their bonding auxiliary layers.
[0016] Furthermore, in the aforementioned low-temperature hybrid bonding interconnect structure, the bonding auxiliary layer is polycrystalline and insulating, and the material is AlN, AlON, Al2O3, HfO2, or ZrO2.
[0017] Furthermore, in the aforementioned low-temperature hybrid bonding interconnect structure, the bonding auxiliary layer is made of polycrystalline AlN, and the bonding auxiliary layers are connected by Al-N bonds instead of Al-O-Al bonds.
[0018] Furthermore, in the aforementioned low-temperature hybrid bonding interconnect structure, the surface roughness of the bonding auxiliary layer is less than 1 nm, and the surface impurity atom concentration is less than 1E15 / cm². 3 .
[0019] Furthermore, in the aforementioned low-temperature hybrid bonding interconnect structure, the amorphous dielectric layer is amorphous and insulating, and the material is SiO2, SiN, or Al2O3.
[0020] Furthermore, in the aforementioned low-temperature hybrid bonding interconnect structure, the diffusion barrier and seed layer are conductive and can prevent the interconnect metal from diffusing into the amorphous dielectric layer and the substrate, and are Ti or Ta.
[0021] A method for manufacturing a low-temperature hybrid bonding interconnect structure includes the following steps: under an ultra-vacuum, oxygen-free environment, plasma bombardment is used to bond the surfaces of a first interconnect structure and a second interconnect structure together; under low-temperature conditions (≤ 100 ℃, including room temperature), the bonding auxiliary layers of the first interconnect structure and the second interconnect structure are bonded together; the interconnect metals are aligned vertically; and the bonding vacuum degree is ≤10. -7 mbar, temperature ≤100℃; annealing at a low temperature of 100~150℃, so that the interconnect metals of the first interconnect structure and the second interconnect structure are bonded together to obtain a hybrid bonded interconnect structure.
[0022] Furthermore, in the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure, the bonding auxiliary layer and amorphous dielectric layer are etched downwards through a mask, and the lower surface reaches the surface of the substrate and the embedded metal structure to form a countersunk hole;
[0023] Deposit diffusion barrier and seed layers on the upper surface of the bonding aid layer, the sidewalls and bottom of the counterbore (deposit the diffusion barrier layer first, then deposit the seed layer).
[0024] A layer of interconnect metal is deposited using CVD or electroplating methods, and the interconnect metal covers the entire surface;
[0025] Chemical mechanical polishing is used to remove part of the interconnect metal, diffusion barrier layer, seed layer and part of the bonding auxiliary layer, exposing the surface of the bonding auxiliary layer, so that the surface roughness of the bonding auxiliary layer is less than 1 nm, and the surface of the interconnect metal is lower than the surface of the auxiliary layer, with a height difference of less than 10 nm; thus obtaining the first interconnect structure.
[0026] Furthermore, the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure,
[0027] A first substrate and a second substrate are provided, which include an embedded metal structure and are used to form a first interconnect structure and a second interconnect structure, respectively.
[0028] An etching barrier layer is deposited on the surface of the first substrate using physical vapor deposition or chemical vapor deposition methods.
[0029] An amorphous dielectric layer is deposited on the etching barrier layer using PVD or CVD processes;
[0030] Deposit a bonding auxiliary layer on an amorphous dielectric layer;
[0031] The processing method for the second substrate is the same as that for the first substrate.
[0032] Furthermore, in the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure, a polycrystalline AlN bonding auxiliary layer is deposited by magnetron sputtering or pulsed laser sputtering. During the deposition process, Y2O3 impurities are incorporated to enhance the insulation capability of the polycrystalline AlN bonding auxiliary layer.
[0033] Furthermore, in the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure, the embedded metal is Al, Cu, or W; and the interconnect metal is Cu, Al, or Ti.
[0034] Furthermore, in the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure, the seed layer is an AlCu alloy or Cu.
[0035] Compared with the prior art, the beneficial effects of the present invention are:
[0036] By using a polycrystalline bonding auxiliary layer, such as polycrystalline AlN material, amorphous media can be bonded together through ultra-vacuum oxygen-free surface activation bonding technology. Compared with the second technical solution that uses an amorphous Si nano-adhesive layer, it has greater bonding strength and lower Cu-Cu interface contact resistance.
[0037] The ultra-vacuum oxygen-free surface activation bonding technology can achieve oxygen-free, room temperature bonding between Cu-Cu electrodes, which has a lower mixing bonding temperature (≤ 150 ℃) and lower Cu-Cu interface resistance compared with the first technology.
[0038] Polycrystalline bonding auxiliary layer materials (AlN) can also serve as a barrier layer against Cu diffusion. For example, when there is an alignment error between the upper and lower Cu metal layers, a diffusion channel exists in the Cu metal. If only an amorphous dielectric layer (SiO2) is used, Cu can easily diffuse into it. However, by using a polycrystalline bonding auxiliary layer, Cu diffusion can be blocked.
[0039] Through doping, the polycrystalline bonding auxiliary layer can also achieve a higher resistivity, resulting in better isolation.
[0040] This hybrid bonding structure and hybrid bonding method can be implemented at low temperatures or even room temperature, and can be applied to three-dimensional integration between chips or between wafers, thereby shortening interconnect spacing, reducing interconnect resistance and increasing integration density, and obtaining higher performance microelectronic systems. Attached Figure Description
[0041] Figure 1 The flowchart of the key process of the typical hybrid bonding technology mentioned in the first process of the background technology is as follows: (a) Cu electrodes are embedded in SiO2, and the surface is chemically and mechanically polished so that the surface of the Cu electrode is within 5 nm lower than the surface of the SiO2 dielectric; (b) the SiO2 dielectric is first bonded together by a melt bonding process; (c) the upper and lower Cu electrodes are heated to expand and form a contact; (d) further annealing is carried out at a high temperature of 300-400℃ to allow the upper and lower Cu electrodes to interdiffuse and form a good conductive connection.
[0042] Figure 2 This is a typical warpage curve of a Si wafer using the first process in the background technology during the bonding process;
[0043] Figure 3 The wafer warpage in the first process described in the background art causes electrode alignment deviations during the bonding process;
[0044] Figure 4 The second process mentioned in the background technology is a schematic diagram of the low-temperature hybrid bonding process based on surface activated bonding (SAB) technology;
[0045] Figure 5 (a) is a transmission electron microscope (TEM) image of the interface based on SAB hybrid bonding in the second process of the background technology, (b) is a TEM image of the Cu-Cu interface based on SAB hybrid bonding, and (c) is a TEM image of the SiO2-SiO2 interface based on SAB hybrid bonding.
[0046] Figure 6 This is a schematic diagram of a low-temperature hybrid bonding interconnect structure provided in an embodiment of the present invention;
[0047] Figure 7 The present invention provides a process flow diagram of a method for manufacturing a low-temperature hybrid bonding interconnect structure, wherein (a) is a substrate containing an embedded metal structure, (b) an etch barrier layer is deposited on the substrate, (c) an amorphous dielectric layer is deposited on the etch barrier layer, (d) a bonding auxiliary layer is deposited on the amorphous dielectric layer, (e) a hole is formed by etching downward through a mask, (f) a diffusion barrier and a seed layer are deposited on the upper surface of the bonding auxiliary layer, the sidewalls and the bottom surface of the hole (the diffusion barrier layer is deposited first, and then the seed layer is deposited), (g) an interconnect metal is deposited, (h) a portion of the interconnect metal, the diffusion barrier layer, the seed layer and a portion of the bonding auxiliary layer are removed by chemical mechanical polishing to expose the surface of the bonding auxiliary layer, (i) a first interconnect structure and a second interconnect structure are interconnected, and (j) annealing is performed at low temperature to bond the interconnect metals of the first interconnect structure and the second interconnect structure together to obtain a hybrid bonding interconnect structure;
[0048] Figure 8 This invention provides a low-temperature hybrid bonding interconnect structure and the diffusion path of Cu when there is alignment error between the upper and lower Cu metals.
[0049] The attached diagram lists the components represented by each number as follows:
[0050] 1. Substrate; 2. Embedded metal structure; 3. Etching barrier layer; 4. Amorphous dielectric layer; 5. Bonding aid layer; 6. Diffusion barrier and seed layer; 7. Interconnect metal; 100. First interconnect structure; 200. Second interconnect structure. Detailed Implementation
[0051] To facilitate understanding of this application, a more complete description will be provided below. This application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0053] It is understood that spatial relation terms such as "below," "under," "below," "below," "above," "above," etc., can be used here to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as "below" or "below" of the other element or feature will be oriented "above" the other element or feature. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0054] To address the challenges of achieving strong bonding between dielectrics in SAB low-temperature bonding technology and the issue of high electrode contact resistance in SAB hybrid bonding using amorphous silicon adhesive layers, this invention provides a low-temperature hybrid bonding interconnect structure and manufacturing method, as detailed below.
[0055] A low-temperature hybrid bonding interconnect structure includes a first substrate with an embedded metal structure 2 and a second substrate with an embedded metal structure 2, an etch barrier layer 3, an amorphous dielectric layer 4, and a bonding auxiliary layer 5 disposed between the first and second substrates, and an interconnect metal 7 embedded in the bonding auxiliary layer 5, the amorphous dielectric layer 4, and the etch barrier layer 3. The interconnect metal 7 has conductive diffusion barriers and seed layers at its contact interfaces with the bonding auxiliary layer 5, the amorphous dielectric layer 4, and the etch barrier layer 3. The interconnect metal 7 forms an electrical connection with the embedded metal structure 2 of the first substrate and the embedded metal structure 2 of the second substrate.
[0056] The bonding auxiliary layer 5 is characterized by being polycrystalline and insulating, including but not limited to AlN, AlON, Al2O3, HfO2, and ZrO2. Polycrystalline AlN is preferred as the bonding auxiliary layer 5. The bonding auxiliary layer 5 assists in achieving bonding between the amorphous dielectric layers 4 at low / room temperature. The surface roughness of the bonding auxiliary layer 5 is less than 1 nm, and the surface impurity atom concentration is less than 1E15 / cm². 3 (Surface impurity atoms refer to atoms other than those contained in the bonding auxiliary layer 5 material. For example, when the bonding auxiliary layer 5 is AlN, the surface does not contain elements such as H, O, or Si.) The bonding auxiliary layers 5 are directly connected by covalent bonds between surface atoms, and there is no indirect bonding with other atoms. For example, when the bonding auxiliary layer 5 material is AlN, the bonding auxiliary layers 5 are connected by Al-N bonds, not by Al-O-Al bonds.
[0057] 4. Characteristics of amorphous dielectric layer: amorphous and insulating, including but not limited to SiO2, SiN, Al2O3, etc., with SiO2 being the typical choice.
[0058] Substrate 1 with embedded metal structure 2 features: wafer with completed end-of-line (BEOL) RDL wiring, the embedded metal is usually Al, Cu or W metal.
[0059] Etching barrier layer 3 has the following characteristics: In dry etching processes, its etching rate is slower than that of the amorphous dielectric layer 4. For example, when the amorphous dielectric layer 4 is SiO2, the etching barrier layer 3 can be SiN or SiON.
[0060] Interconnect metal 7 features include, but are not limited to, Cu, Al, and Ti, with Cu being preferred. Interconnect metal 7 has no oxide layer at the bonding interface.
[0061] Diffusion barrier and seed layer characteristics: conductive, which can block the diffusion of interconnect metal 7 into amorphous dielectric layer 4 and substrate 1, typically Ti or Ta, and the seed layer is AlCu or Cu.
[0062] A method for manufacturing a low-temperature hybrid bonding interconnect structure:
[0063] A first substrate comprising an embedded metal structure 2 is provided;
[0064] An etching barrier layer 3 is deposited on the surface using physical vapor deposition (PVD) or chemical vapor deposition (CVD) methods;
[0065] An amorphous dielectric layer 4 is deposited on the etch barrier layer 3 using PVD or CVD processes;
[0066] A bonding auxiliary layer 5 is deposited on the amorphous dielectric layer 4, for example, by magnetron sputtering or pulsed laser sputtering to deposit a polycrystalline AlN layer. During the deposition process, other impurities, such as Y2O3, can be incorporated to enhance the insulation ability of the polycrystalline AlN layer.
[0067] By etching the bonding auxiliary layer 5 and the amorphous dielectric layer 4 downward through a mask, the lower surface reaches the surface of the substrate 1 and the embedded metal structure 2 to form a counter-hole.
[0068] Deposit diffusion barrier and seed layers on the upper surface of bonding aid layer 5, the sidewalls and bottom of the counterbore (deposit diffusion barrier layer first, then deposit seed layer).
[0069] A layer of interconnect metal 7 is deposited using CVD or electroplating methods, and the interconnect metal 7 covers the entire surface;
[0070] Chemical mechanical polishing (CMP) is used to remove part of the interconnect metal 7, diffusion barrier layer, seed layer, and part of the bonding auxiliary layer 5, exposing the surface of the bonding auxiliary layer 5, so that the surface roughness of the bonding auxiliary layer 5 is less than 1 nm, and the surface of the interconnect metal 7 is lower than the surface of the bonding auxiliary layer 5, with a height difference of less than 10 nm; thus obtaining the first interconnect structure 100.
[0071] A second substrate comprising an embedded metal structure 2 is provided, and steps (2)-(8) are repeated to obtain a second interconnect structure 200;
[0072] In an ultra-vacuum, oxygen-free environment, plasma bombardment is used to bond the bonding auxiliary layers 5 of the first interconnect structure 100 and the second interconnect structure 200 together under low-temperature conditions (25~100 °C), with the interconnect metals 7 aligned vertically. The bonding vacuum degree is ≤10. -7 mbar, temperature ≤100℃ (including room temperature).
[0073] Annealing at low temperature (100~150℃) allows the interconnect metals 7 of the first interconnect structure 100 and the second interconnect structure 200 to be bonded together, resulting in a hybrid bonded interconnect structure.
[0074] Example 1
[0075] A low-temperature hybrid bonding interconnect structure includes a first substrate with an embedded metal structure 2 and a second substrate with an embedded metal structure 2, an etch barrier layer 3, an amorphous dielectric layer 4, and a bonding auxiliary layer 5 disposed between the first and second substrates, and an interconnect metal 7 embedded in the bonding auxiliary layer 5, the amorphous dielectric layer 4, and the etch barrier layer 3. The interconnect metal 7 has a conductive diffusion barrier and a seed layer at its contact interface with the bonding auxiliary layer 5, the amorphous dielectric layer 4, and the etch barrier layer 3 (the diffusion barrier layer is deposited first, followed by the seed layer). The interconnect metal 7 forms an electrical connection with the embedded metal structure 2 of the first substrate and the embedded metal structure 2 of the second substrate.
[0076] Bonding auxiliary layer 5 is characterized as polycrystalline, insulating, and made of AlN. The surface roughness of bonding auxiliary layer 5 is 0.9 nm, and the surface impurity atom concentration is 5E14 / cm². 3 The bonding auxiliary layer 5 between the first interconnect structure and the second interconnect structure is connected by Al-N bonds, rather than by Al-O-Al bonds.
[0077] Amorphous dielectric layer 4 is characterized by being SiO2.
[0078] Substrate 1 with embedded metal structure 2 features: a wafer with completed end-of-line (BEOL) RDL wiring, and the embedded metal is Al.
[0079] Features of etching barrier layer 3: Etching barrier layer 3 is SiN.
[0080] Interconnect metal 7 is characterized by being made of Cu. Interconnect metal 7 has no oxide layer at the bonding interface.
[0081] Diffusion barrier and seed layer characteristics: conductive, which can block the diffusion of interconnect metal 7 into amorphous dielectric layer 4 and substrate 1, which is Ti, and the seed layer is an AlCu alloy.
[0082] A method for manufacturing a low-temperature hybrid bonding interconnect structure:
[0083] A first substrate comprising an embedded metal structure 2 is provided;
[0084] An etching barrier layer 3 is deposited on the surface using physical vapor deposition (PVD) or chemical vapor deposition (CVD) methods;
[0085] An amorphous dielectric layer 4 is deposited on the etch barrier layer 3 using PVD or CVD processes;
[0086] A bonding auxiliary layer 5 is deposited on the amorphous dielectric layer 4, that is, a polycrystalline AlN layer is deposited by magnetron sputtering. During the deposition process, Y2O3 is incorporated to enhance the insulation ability of the polycrystalline AlN layer.
[0087] By etching the bonding auxiliary layer 5 and the amorphous dielectric layer 4 downward through a mask, the lower surface reaches the surface of the substrate 1 and the embedded metal structure 2 to form a counter-hole.
[0088] A diffusion barrier and a seed layer are deposited on the upper surface of the bonding auxiliary layer 5, the sidewalls of the countersink, and the bottom surface;
[0089] A layer of interconnect metal 7 was deposited using CVD, and the interconnect metal 7 covered the entire surface.
[0090] Chemical mechanical polishing was used to remove part of the interconnect metal 7, the diffusion barrier layer, the seed layer, and part of the bonding auxiliary layer 5, exposing the surface of the bonding auxiliary layer 5. The surface roughness of the bonding auxiliary layer 5 was 0.9 nm, and the surface of the interconnect metal 7 was lower than the surface of the bonding auxiliary layer 5, with a height difference of 9 nm; thus, the first interconnect structure 100 was obtained.
[0091] A second substrate including an embedded metal structure 2 is provided, and the above steps are repeated to obtain a second interconnect structure 200;
[0092] In an ultra-vacuum, oxygen-free environment, plasma is used to bombard the surfaces of the first interconnect structure 100 and the second interconnect structure 200. At 25 °C, the bonding auxiliary layer 5 of the first interconnect structure 100 and the second interconnect structure 200 are bonded together, with the interconnect metals 7 aligned vertically. The bonding vacuum level is 1E-7 mbar, and the temperature is 25 °C.
[0093] Annealing at 120 °C causes the interconnect metals 7 of the first interconnect structure 100 and the second interconnect structure 200 to bond together, resulting in a hybrid bonded interconnect structure.
[0094] Example 2
[0095] Example 2 is basically the same as Example 1, except that:
[0096] Bonding auxiliary layer 5 is characterized as polycrystalline, insulating, and composed of HfO2. The surface roughness of bonding auxiliary layer 5 is 0.5 nm, and the surface impurity atom concentration is 1E14 / cm². 3 .
[0097] Amorphous dielectric layer 4 is characterized as SiN.
[0098] Substrate 1 with embedded metal structure 2 features: wafer with completed end-of-line (BEOL) RDL wiring, the embedded metal is Cu.
[0099] Etching barrier layer 3 is characterized by a slower etching rate compared to the amorphous dielectric layer 4 during dry etching. Etching barrier layer 3 is made of SiN.
[0100] Interconnect metal 7 is characterized by being made of Al. Interconnect metal 7 has no oxide layer at the bonding interface.
[0101] Diffusion barrier and seed layer characteristics: conductive, able to block the diffusion of interconnect metal 7 into amorphous dielectric layer 4 and substrate 1, which is Ta, and the seed layer is Cu.
[0102] A method for manufacturing a low-temperature hybrid bonding interconnect structure:
[0103] A first substrate comprising an embedded metal structure 2 is provided;
[0104] An etching barrier layer 3 was deposited on the surface using chemical vapor deposition (CVD).
[0105] An amorphous dielectric layer 4 is deposited on the etch barrier layer 3 using a CVD process;
[0106] A bonding auxiliary layer 5 is deposited on the amorphous dielectric layer 4, that is, a polycrystalline HfO2 layer is deposited by pulsed laser sputtering.
[0107] By etching the bonding auxiliary layer 5 and the amorphous dielectric layer 4 downward through a mask, the lower surface reaches the surface of the substrate 1 and the embedded metal structure 2 to form a counter-hole.
[0108] A diffusion barrier and a seed layer are deposited on the upper surface of the bonding auxiliary layer 5, the sidewalls of the countersink, and the bottom surface;
[0109] An interconnect metal 7 is deposited using an electroplating method, and the interconnect metal 7 covers the entire surface;
[0110] Chemical mechanical polishing (CMP) is used to remove part of the interconnect metal 7, diffusion barrier layer, seed layer, and part of the bonding auxiliary layer 5, exposing the surface of the bonding auxiliary layer 5. The surface roughness of the bonding auxiliary layer 5 is 0.5 nm, and the surface of the interconnect metal 7 is lower than the surface of the bonding auxiliary layer 5, with a height difference of less than 5 nm; thus obtaining the first interconnect structure 100.
[0111] A second substrate including an embedded metal structure 2 is provided, and the above steps are repeated to obtain a second interconnect structure 200;
[0112] In an ultra-vacuum, oxygen-free environment, plasma is used to bombard the surfaces of the first interconnect structure 100 and the second interconnect structure 200. At 25 °C, the bonding auxiliary layer 5 of the first interconnect structure 100 and the second interconnect structure 200 are bonded together, with the interconnect metals 7 aligned vertically. The bonding vacuum level is 1E-7 mbar, and the temperature is 25 °C.
[0113] Annealing at 120 °C causes the interconnect metals 7 of the first interconnect structure 100 and the second interconnect structure 200 to bond together, resulting in a hybrid bonded interconnect structure.
[0114] Example 3
[0115] Example 3 is basically the same as Example 1, except that:
[0116] Bonding auxiliary layer 5 is characterized as polycrystalline, insulating, and composed of ZrO2. The surface roughness of bonding auxiliary layer 5 is 0.3 nm, and the surface impurity atom concentration is 5E14 / cm². 3 .
[0117] Amorphous dielectric layer 4 is characterized by being Al2O3.
[0118] Substrate 1 with embedded metal structure 2 features: wafer with completed end-of-line (BEOL) RDL wiring, the embedded metal is W metal.
[0119] Etching barrier layer 3 is characterized by a slower etching rate compared to the amorphous dielectric layer 4 during dry etching. Etching barrier layer 3 is made of SiN.
[0120] Interconnect metal 7 is characterized by being made of Ti. Interconnect metal 7 has no oxide layer at the bonding interface.
[0121] Diffusion barrier and seed layer characteristics: conductive, which can block the diffusion of interconnect metal 7 into amorphous dielectric layer 4 and substrate 1, which is Ti, and the seed layer is Cu.
[0122] A method for manufacturing a low-temperature hybrid bonding interconnect structure:
[0123] A first substrate comprising an embedded metal structure 2 is provided;
[0124] An etching barrier layer 3 was deposited on the surface using physical vapor deposition (PVD).
[0125] An amorphous dielectric layer 4 is deposited on the etch barrier layer 3 using a PVD process;
[0126] A bonding auxiliary layer 5 is deposited on the amorphous dielectric layer 4, that is, a polycrystalline ZrO2 layer is deposited by magnetron sputtering.
[0127] By etching the bonding auxiliary layer 5 and the amorphous dielectric layer 4 downward through a mask, the lower surface reaches the surface of the substrate 1 and the embedded metal structure 2 to form a counter-hole.
[0128] A diffusion barrier and a seed layer are deposited on the upper surface of the bonding auxiliary layer 5, the sidewalls of the countersink, and the bottom surface;
[0129] A layer of interconnect metal 7 was deposited using CVD, and the interconnect metal 7 covered the entire surface.
[0130] Chemical mechanical polishing (CMP) was used to remove part of the interconnect metal 7, the diffusion barrier layer, the seed layer, and part of the bonding auxiliary layer 5, exposing the surface of the bonding auxiliary layer 5. The surface roughness of the bonding auxiliary layer 5 was 0.3 nm, and the surface of the interconnect metal 7 was lower than the surface of the bonding auxiliary layer 5, with a height difference of 3 nm; thus, the first interconnect structure 100 was obtained.
[0131] A second substrate including an embedded metal structure 2 is provided, and the above steps are repeated to obtain a second interconnect structure 200;
[0132] In an ultra-vacuum, oxygen-free environment, plasma is used to bombard the surfaces of the first interconnect structure 100 and the second interconnect structure 200. At 60°C, the bonding auxiliary layer 5 of the first interconnect structure 100 and the second interconnect structure 200 are bonded together, with the interconnect metals 7 aligned vertically. The bonding vacuum level is 1E-8 mbar, and the temperature is 60°C.
[0133] Annealing at 100°C causes the interconnect metals 7 of the first interconnect structure 100 and the second interconnect structure 200 to bond together, resulting in a hybrid bonded interconnect structure.
[0134] The advantages of this invention are:
[0135] Using a polycrystalline bonding auxiliary layer 5, such as polycrystalline AlN material, amorphous media can be bonded together through ultra-vacuum oxygen-free surface activation bonding technology. Compared with the second technical solution that uses an amorphous Si nano-adhesive layer, it has greater bonding strength and lower Cu-Cu interface contact resistance.
[0136] The ultra-vacuum oxygen-free surface activation bonding technology can achieve oxygen-free, room temperature bonding between Cu-Cu electrodes, which has a lower mixing bonding temperature (≤ 150 ℃) and lower Cu-Cu interface resistance compared with the first technology.
[0137] The polycrystalline bonding auxiliary layer 5 (AlN) can also serve as a barrier layer for Cu diffusion. For example, when there is an alignment error between the upper and lower Cu metals, a diffusion channel exists in the Cu metal. If only the amorphous dielectric layer 4 (SiO2) is used, Cu can easily diffuse into it. However, by using the polycrystalline bonding auxiliary layer 5, Cu cannot diffuse into the amorphous dielectric layer 4 due to the barrier effect of the polycrystalline bonding auxiliary layer 5.
[0138] Through doping, the polycrystalline bonding auxiliary layer 5 can also achieve a higher resistivity, resulting in better isolation.
[0139] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. In the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have the transmission of electrical signals or data between them.
[0140] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.
[0141] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A low-temperature hybrid bonding interconnect structure, characterized in that, It includes a first interconnect structure (100) and a second interconnect structure (200), both of which have the same structure; Both the first interconnect structure (100) and the second interconnect structure (200) include a substrate (1) connected to an embedded metal structure (2), and an etch barrier layer (3), an amorphous dielectric layer (4), and a bonding auxiliary layer (5) are sequentially connected to one side of the substrate (1). A countersunk hole is formed in the middle of the first interconnect structure (100) and the second interconnect structure (200) at the position corresponding to the embedded metal. The countersunk hole spans the bonding auxiliary layer (5), the amorphous dielectric layer (4), and the etching barrier layer (3). The inner wall of the counterbore is connected to a diffusion barrier and a seed layer (6), while the top surface of the embedded metal structure has no diffusion barrier and a seed layer (6). Interconnecting metal (7) is embedded in the countersunk holes of both, and its two ends are respectively connected to the embedded metal of the first interconnecting structure (100) and the second interconnecting structure (200); the interconnecting metal (7), the embedded metal structure (2) of the first interconnecting structure (100) and the embedded metal structure (2) of the second interconnecting structure (200) can form an electrical connection; The first interconnect structure (100) and the second interconnect structure (200) are directly connected together by surface-atomic covalent bonds formed by their bonding auxiliary layers (5); The bonding auxiliary layer (5) is made of polycrystalline AlN, and the bonding auxiliary layers (5) are connected by Al-N bonds instead of Al-O-Al bonds. The method for manufacturing the low-temperature hybrid bonding interconnect structure includes the following steps: In an ultra-vacuum, oxygen-free environment, the surfaces of the first interconnection structure (100) and the second interconnection structure (200) are bombarded by plasma, and the bonding auxiliary layer (5) of the first interconnection structure (100) and the bonding auxiliary layer (5) of the second interconnection structure (200) are combined together under low-temperature conditions, with the interconnection metal (7) aligned up and down, and the bonding vacuum degree ≤10 -7 mbar and the temperature ≤100℃. Annealing at a low temperature of 100~150℃ allows the interconnect metals (7) of the first interconnect structure (100) and the second interconnect structure (200) to be bonded together to obtain a hybrid bonded interconnect structure.
2. The low-temperature hybrid bonding interconnect structure according to claim 1, characterized in that, The surface roughness of the bonding auxiliary layer (5) is less than 1 nm, and the surface impurity atom concentration is less than 1E15 / cm. 3 .
3. The low-temperature hybrid bonding interconnect structure according to claim 1, characterized in that, The amorphous dielectric layer (4) is amorphous and insulating, and the material is SiO2, SiN or Al2O3.
4. The low-temperature hybrid bonding interconnect structure according to claim 1, characterized in that, The diffusion barrier and seed layer are conductive and can block the diffusion of interconnect metal (7) into the amorphous dielectric layer (4) and the substrate (1), which is Ti or Ta.
5. The low-temperature hybrid bonding interconnect structure according to claim 1, characterized in that, By etching the bonding auxiliary layer (5) and the amorphous dielectric layer (4) downward through a mask, the lower surface reaches the surface of the substrate (1) and the embedded metal structure (2) to form a countersunk hole; A diffusion barrier and a seed layer are deposited on the upper surface of the bonding auxiliary layer (5), the sidewalls of the countersink, and the bottom surface; An interconnect metal layer (7) is deposited using CVD or electroplating, and the interconnect metal (7) covers the entire surface; Chemical mechanical polishing was used to remove part of the interconnect metal (7), diffusion barrier layer, seed layer and part of the bonding auxiliary layer (5), exposing the surface of the bonding auxiliary layer (5) so that the surface roughness of the bonding auxiliary layer (5) is less than 1 nm and the surface of the interconnect metal (7) is lower than the surface of the auxiliary layer, with a height difference of less than 10 nm; the first interconnect structure (100) was obtained, and the second interconnect structure (200) was processed in the same way.
6. The low-temperature hybrid bonding interconnect structure according to claim 5, characterized in that, A first substrate (1) and a second substrate (1) are provided, which include an embedded metal structure (2) and are used to form a first interconnect structure (100) and a second interconnect structure (200) respectively. An etching barrier layer (3) is deposited on the surface of the first substrate (1) using physical vapor deposition or chemical vapor deposition methods. An amorphous dielectric layer (4) is deposited on the etching barrier layer (3) using PVD or CVD processes. A bonding auxiliary layer (5) is deposited on the amorphous dielectric layer (4); The processing method of the second substrate (1) is the same as that of the first substrate (1).
7. The low-temperature hybrid bonding interconnect structure according to claim 6, characterized in that, A polycrystalline AlN bonding auxiliary layer (5) is deposited by magnetron sputtering or pulsed laser sputtering. During the deposition process, Y2O3 impurities are introduced to enhance the insulation ability of the polycrystalline AlN bonding auxiliary layer (5).