Fpga implementation method, system, device and medium of polyphase filter channelizer

Abstract

The application relates to an FPGA implementation method, system, device and medium of a polyphase filtering channelizer, which performs serial-parallel conversion and data shaping on serial data to obtain parallel shaped data, multiplies the parallel shaped data with a filter coefficient array, performs summation accumulation operation to obtain parallel data after polyphase filtering calculation, uses a RAM to complete buffer shaping and serial-parallel conversion on the parallel data to obtain a serial polyphase filtering data block, feeds the serial polyphase filtering data block into an IFFT module to obtain data after channelization, and then performs frequency offset compensation and cycle counting to obtain parallel data; an FPGA implementation system of the polyphase filtering channelizer comprises a data shaping module, a polyphase filtering operation module, a serial-parallel conversion module, an inverse fast Fourier transform module, a frequency offset compensation module and a parallel data output module; the device and the medium are used for storing a computer program, and when the program is executed, the FPGA implementation method is completed; and the method can realize digital channelization function by using less FPGA resources.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology for satellite communication, and in particular to a method, system, device and medium for implementing a polyphase filter channelizer using an FPGA (Field-Programmable Gate Array). Background Technology

[0002] With the rapid development of satellite communication technology and the widespread adoption of intelligent terminals, various Internet of Things (IoT) and Internet terminals have seen an explosive increase. These combined factors have led to increasingly tight spectrum resources and more complex usage conditions. In the field of wireless communication, receivers may receive data signals from multiple channels simultaneously. To distinguish these signals, the received broadband signals need to be divided into sub-channels according to a certain bandwidth to meet the demodulation requirements of the subsequent receiver. Furthermore, in electronic radar reconnaissance applications, there are numerous signals of varying energy, modulation methods, and bandwidth emitted by communication, jamming, and radar reconnaissance devices, making the competition for electromagnetic spectrum resources particularly fierce.

[0003] To meet these requirements, digital channelized receivers, which integrate digital polyphase filter technology and channelization processing technology, have emerged. They possess the high integration capabilities of channelized receivers while also having the stability and flexibility of digital receivers. This greatly reduces the receiver's power consumption, resource consumption, and complexity, outputs small-bandwidth signals, and lowers the data processing rate of the back-end processing modules. On the other hand, since the 1990s, with the rapid development of semiconductor digital chip design and manufacturing technology, digital receivers have replaced analog receivers as the mainstream development trend of current receiving and demodulation equipment. They have better stability, can preserve the integrity of the signal as much as possible, and can make full and flexible use of various digital signal demodulation technologies. Especially in scenarios such as satellite IoT with massive numbers of terminals and radar electronic reconnaissance, multi-channel digital channelized receivers can use large-scale parallel channels to process data, further increasing the ability to process multiple pieces of information at the same time and ensuring the normal operation of the receiver's subsequent demodulation process.

[0004] Digital channelization technologies can be categorized based on their core principles into: single-channel digital channelizers, which construct the channelizer by performing parallel ensemble reception processing on multiple single channels; FFT (Fast Fourier Transform)-based digital channelizers, which utilize FFT or windowed STFT (Short-Time Fourier Transform) to divide the signal frequency band; and WOLA (Weighted Overlap-Add) and polyphase filtering structures, which mainly combine weighted digital filtering and polyphase efficient structures with IDFT (Inverse Discrete Fourier Transform) for implementation.

[0005] Existing channelizers mainly utilize multiphase efficient structures combined with DFT (Discrete Fourier Transform) for implementation. However, most of them are based on specific project requirements and have poor flexibility. Under harsh conditions, it is urgent to enable digital receivers to meet the requirements of high-precision and fast data processing with large bandwidth, low latency, and low complexity.

[0006] In the prior art, the invention with patent publication number "CN118353749B" and title "An Improved Digital Channelization FPGA Implementation Method" realizes multiphase wave calculation by combining data weighting with array grouping and folding addition. On this basis, frequency correction and FFT calculation are performed to realize channelization, which has good real-time performance and flexibility, and realizes the division of 16 effective bandwidth 75M subbands. However, this multiphase FPGA (Field-Programmable Gate Array) architecture consumes a lot of resources. In the case of very high-order prototype filters, large-scale cluster subband division and non-critical decimation, the number of multipliers used is directly related to the length of the prototype filter. Considering the limited FPGA resources, it is difficult to implement in actual engineering. At the same time, the patent does not provide a specific and clear FPGA engineering implementation architecture.

[0007] In the existing technology, the master's thesis entitled "Research and FPGA Implementation of Channel Digitization of Wireless Receiver" (Li Chao. Research and FPGA Implementation of Channel Digitization of Wireless Receiver [D]. University of Electronic Science and Technology of China, 2018) completed the FPGA architecture design and verification of a 256-channel digital channelizer, which can be applied to various application scenarios. At the same time, it conducted relevant research on the potential blind zone coverage between adjacent subbands, channel ambiguity, and cross-channel interference of signals in the digital structure. Furthermore, the combination of parallel DDC (Digital Down Converter) gives the entire digital channelizer good performance. Its data extraction part is implemented using a 256-depth register combined with a counter, which can save some storage resources compared to using FIFO (First In First Out) or RAM. However, it is based on a theoretical polyphase structure, but the number of polyphase branches used is the same as the number of subband divisions. If a high-order prototype filter is used to perform convolution calculations on each branch, the multiplier resources consumed will be large. In addition, it does not conduct in-depth research on the implementation of the polyphase architecture. Summary of the Invention

[0008] To overcome the shortcomings of the prior art, the present invention aims to propose an FPGA implementation method, system, device, and medium for a polyphase filter channelizer. This method establishes a polyphase filter computational architecture based on the convolution law of the fundamental theory of polyphase filtering. Combined with flexibly configurable parameters, it can achieve low-resource-consumption polyphase filtering operations under conditions such as non-critical decimation (i.e., decimation factor and channel division number are not equal) and extremely high-order prototype filters. Under the premise that the signal has a large duty cycle and low rate, it can significantly reduce the resource consumption of DSP (Digital Signal Processor) and realize signal frequency band division and variable rate processing in the scenario of demodulation of burst signals from massive terminals in satellite IoT.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0010] In a first aspect, the present invention proposes an FPGA implementation method for a polyphase filter channelizer, comprising the following steps:

[0011] S1: Set the Nth-order prototype filter coefficients of the channelizer, the number of sub-band channels M, and the data decimation factor D. Use FIFO and counter to perform serial-to-parallel conversion and data shaping on the serial signal input to the channelizer to obtain I sets of parallel shaped data, where I = N / M.

[0012] S2: The Nth-order prototype filter coefficients in step S1 are evenly divided into I groups of branch filter coefficients. The I groups of branch filter coefficients are reversed and multiplied with the I groups of parallel shaped data in step S1 to obtain convolution operation parallel data. The data of the same channel in the convolution operation parallel data are summed and accumulated to obtain the parallel data after multiphase filtering calculation.

[0013] S3: Use RAM to perform buffering, reshaping, and parallel-to-serial conversion on the parallel data after the multiphase filtering calculation described in step S2 to obtain a serial multiphase filtering data block;

[0014] S4: Send the serial multiphase filter data block described in step S3 into the IFFT module to complete the inverse fast Fourier transform and obtain the M-point IFFT output data.

[0015] S5: After frequency offset compensation, the M-point IFFT output data described in step S4 is output as serial data.

[0016] S6: Set a loop counter to count the serial data described in step S5 to obtain the loop counter value, select the corresponding channel data according to the loop counter value and complete the parallel data output.

[0017] Furthermore, step S1 includes the following steps:

[0018] S1.1: Set the Nth-order prototype filter coefficients of the channelizer, the number of sub-band channels M, and the data decimation factor D. Use FIFO to divide the serial signal input to the channelizer into I groups of single-channel data, where I = N / M, and each group of single-channel data is separated by M clock delays.

[0019] S1.2: Set the value of the counter mentioned in step S1 to 0 to X, where X = M·(M / D-1). When the counter value is an integer multiple of D, assign values ​​to the second to M / D data according to the first data of each group of single-channel data. I groups of parallel shaped data can be obtained in this way. Each group of I groups of parallel shaped data contains M / D channels, and the serial signal completes the serial-to-parallel conversion.

[0020] Furthermore, step S2 includes the following steps:

[0021] S2.1: The Nth-order prototype filter coefficients described in step S1.1 are divided into phases according to the number M of subband channels, resulting in I groups of branch filter coefficients, where I = N / M, and the I groups of branch filter coefficients are then reversed.

[0022] S2.2: For each data path in the I-group parallel shaping data described in step S1.2, a counter with a value from 0 to M-1 is set. Using the counter with a value from 0 to M-1, the branch filter coefficients of the I-group after reversal described in step S2.1 are selected according to the numerical correspondence principle. Each branch filter coefficient and the I-group parallel shaping data in step S1.2 are fed into the multiplier to complete the corresponding multiplication operation to obtain the convolution operation parallel data.

[0023] S2.3: Sum the data of the same channel in the parallel data of the convolution operation described in step S2.2 to obtain the parallel data after multiphase filtering calculation.

[0024] Furthermore, step S3 includes the following steps: setting up p RAMs with a depth of M, where p = M / D; buffering and shaping the parallel data after multiphase filtering calculation output in step S2; after the RAM data in the corresponding channel of the parallel data after multiphase filtering calculation, i.e., the p-channel parallel shaped data, is full, using an auxiliary counter to read the data out in reverse order from the high address to the low address of the RAM; and finally converting the p-channel parallel shaped data into serial multiphase filtering data blocks, where each data block contains M data units.

[0025] Furthermore, step S5 includes the following steps:

[0026] S5.1: Set up two two-dimensional arrays for the real part and imaginary part of the phase adjustment coefficient group in the frequency offset compensation operation. Each two-dimensional array contains M / D data elements, and the number of bits of M / D data elements is M / D·16.

[0027] S5.2: Set a data block counter to complete the block counting of the M-point IFFT output data described in step S4, and set a compensation factor selection counter to complete the selection of the phase adjustment coefficient group data described in step S5.1. Send the M-point IFFT output data after block counting and its corresponding selected phase adjustment coefficient group data into a complex multiplier to complete the frequency offset compensation operation and obtain serial data. The frequency offset compensation formula is as follows:

[0028]

[0029] In formula (1), v k (n) represents the k-th channel data after frequency offset compensation, x k (n) represents the serial data of the k-th channel after inverse fast Fourier transform, where k is the channel number, M is the number of sub-band channels, D is the data decimation factor, j is the imaginary unit, and n is the index of the M-point IFFT output data sequence.

[0030] Furthermore, in step S6, the value of the loop counter is set to 0 to M.

[0031] Secondly, an FPGA implementation system for a polyphase filter channelizer is provided, which applies the FPGA implementation method of the polyphase filter channelizer. The FPGA implementation system includes a data shaping module, a polyphase filter operation module, a parallel-to-serial conversion module, an inverse fast Fourier transform module, a frequency offset compensation module, and a parallel data output module.

[0032] Data shaping module: Sets the Nth-order prototype filter coefficients of the channelizer, the number of sub-band channels M, and the data decimation factor D. It uses FIFO and counter to perform serial-to-parallel conversion and data shaping on the serial signal input to the channelizer, and obtains I sets of parallel shaped data, where I = N / M.

[0033] The multiphase filtering operation module: uniformly divides the coefficients of the Nth-order prototype filter into I groups of branch filter coefficients. The I groups of branch filter coefficients are multiplied by the I groups of parallel shaped data after being reversed to obtain convolution operation parallel data. The data of the same channel in the convolution operation parallel data are summed and accumulated to obtain the parallel data after multiphase filtering calculation.

[0034] Parallel-to-serial conversion module: Utilizes RAM to perform buffering, shaping, and parallel-to-serial conversion on the parallel data after the multiphase filtering calculation, to obtain a serial multiphase filtering data block;

[0035] Inverse Fast Fourier Transform (IFFT) module: The serial multiphase filter data block is fed into the IFFT module to complete the inverse fast fourier transform and obtain the M-point IFFT output data.

[0036] Frequency offset compensation module: After performing frequency offset compensation on the IFFT output data at point M, it outputs serial data;

[0037] Parallel data output module: Sets a loop counter to count the serial data to obtain the loop counter value, selects the corresponding channel data according to the loop counter value, and completes the parallel data output.

[0038] Thirdly, an electronic device including a memory and a processor:

[0039] Memory: Used to store the computer program for implementing the FPGA method of the polyphase filter channelizer;

[0040] Processor: An FPGA implementation method for implementing the polyphase filter channelizer when executing the computer program.

[0041] Fourthly, a computer-readable storage medium storing a computer program that, when executed by a processor, implements an FPGA implementation method for the polyphase filter channelizer.

[0042] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0043] 1. In steps S1 to S2 of this method, a multiphase filtering computational architecture is established based on the convolution law of the fundamental theory of multiphase filtering. Combined with flexibly configurable parameters, namely the number of sub-band channel divisions M and the downsampling data decimation factor D, low-resource-consumption multiphase filtering operations can be achieved under conditions such as non-critical decimation (i.e., the decimation factor is not equal to the number of channel divisions) and extremely high-order prototype filters.

[0044] 2. In the case of non-critical decimation, i.e., when the decimation factor and the number of channel divisions are unequal, in steps S1 to S6 of this method, based on the convolution law of polyphase filtering fundamental theory, the serial data can be divided into N / M groups of parallel data, each group having M / D sub-data paths, by the prototype filter order N, the number of sub-band channel divisions M, and the downsampling decimation factor D (adjustable). When processing extremely low-rate signals, the front-end will perform multi-stage sampling and decimation on the ADC (Analog-to-Digital Converter) signal. Under the premise that the signal has a large duty cycle and low rate, only N / D multipliers are needed to complete the polyphase filtering calculation. Compared with directly using the polyphase theoretical structure for convolution operation, which consumes the same multiplication resources as the prototype filter order, it can significantly reduce DSP resource consumption. At the same time, combined with IFFT channelization operation, it can realize the uniform division of broadband signals according to a certain sub-band channel bandwidth, which is suitable for satellite IoT massive terminal communication scenarios, and is conducive to engineering implementation, with better engineering practicality and the ability to process low-rate signals at varying rates.

[0045] In summary, in the scenario of ultra-narrowband ultra-low symbol rate subband channel partitioning for massive terminal signal demodulation of satellite IoT, and under conditions such as ultra-high order prototype filters, large-scale cluster subband low symbol rate signal partitioning and non-critical decimation, this invention can realize digital channelization function with relatively few FPGA resources. Attached Figure Description

[0046] Figure 1 This is a flowchart illustrating an FPGA implementation method for a polyphase filter channelizer according to the present invention.

[0047] Figure 2 This is an algorithm flowchart of an FPGA implementation method for a polyphase filter channelizer in this invention.

[0048] Figure 3 This is an FPGA architecture flowchart of an FPGA implementation method for a multiphase filter channelizer in this invention.

[0049] Figure 4This is a schematic diagram of the sub-band distribution of an FPGA implementation method for a polyphase filter channelizer in this invention.

[0050] Figure 5 This is a schematic diagram of the FPGA multiphase filter convolution calculation waveform when the number of sub-band channels M and the data extraction multiple D are both set to 512, according to an embodiment of the present invention.

[0051] Figure 6 The input channelizer provided in this embodiment of the invention contains serial combined data spectrum diagrams with two different symbol rates.

[0052] Figure 7 This is a schematic diagram of the channelized spectrum of 350sps (symbol rate) data provided in an embodiment of the present invention.

[0053] Figure 8 This is a schematic diagram of the channelized spectrum of 500sps (symbol rate) data provided in an embodiment of the present invention.

[0054] Figure 9 This is a schematic diagram of data constellation recovery quality after processing by a digital channelizer, provided in an embodiment of the present invention.

[0055] Figure 10 This is a diagram illustrating the quality of data constellation recovery after low-pass filtering provided by the comparison structure. Detailed Implementation

[0056] The following is combined Figures 1 to 10 The present invention will be further described in detail below:

[0057] Firstly, this invention proposes an FPGA implementation method for a polyphase filter channelizer, comprising the following steps, such as... Figure 1 The following is a flowchart illustrating the FPGA implementation method of the present invention:

[0058] S1: Set the Nth-order prototype filter coefficients of the (digital) channelizer, the number of sub-band channels M, and the data decimation factor D. Use FIFO and counter to perform serial-to-parallel conversion and data shaping on the serial signal input to the channelizer to obtain I sets of parallel shaped data, where I = N / M.

[0059] S2: The Nth-order prototype filter coefficients in step S1 are evenly divided into I groups of branch filter coefficients. The I groups of branch filter coefficients are reversed and multiplied with the I groups of parallel shaped data in step S1 to obtain convolution operation parallel data. The data of the same channel in the convolution operation parallel data are summed and accumulated to obtain the parallel data after multiphase filtering calculation.

[0060] S3: Use RAM to perform buffering, reshaping, and parallel-to-serial conversion on the parallel data after the multiphase filtering calculation described in step S2 to obtain a serial multiphase filtering data block;

[0061] S4: Send the serial multiphase filter data block described in step S3 into the IFFT module to complete the inverse fast Fourier transform and obtain the M-point IFFT output data.

[0062] S5: After frequency offset compensation, the M-point IFFT output data described in step S4 is output as serial data.

[0063] S6: Set a loop counter to count the serial data described in step S5 to obtain the loop counter value, select the corresponding channel data according to the loop counter value and complete the parallel data output.

[0064] Furthermore, step S1 includes the following steps:

[0065] S1.1: First, set the floating-point Nth-order prototype filter coefficients of the channelizer. Perform normalization and fixed-point operations on the floating-point Nth-order prototype filter coefficients to generate Nth-order prototype filter coefficients. Set the Nth-order prototype filter coefficients, the number of sub-band channels M, and the data decimation factor D of the (digital) channelizer. Use FIFO to divide the serial signal input to the channelizer into I groups of single-channel data, where I = N / M. Use I-1 FIFOs to delay the serial signal so that each group of single-channel data is delayed by M clock cycles.

[0066] S1.2: Set the value of the counter mentioned in step S1 to 0 to X, where X = M·(M / D-1). When the counter value is an integer multiple of D, assign values ​​to the second to M / D data according to the first data of each group of single-channel data. I groups of parallel shaped data can be obtained in this way. Each group of I groups of parallel shaped data contains M / D channels, and the serial signal completes the serial-to-parallel conversion.

[0067] Step S2 mainly designs the corresponding FPGA hardware implementation architecture based on the software algorithm of the multi-phase channelizer, namely the multi-phase filter convolution calculation law. In actual engineering, if a bandpass filter and digital frequency conversion are directly used to realize digital channelization of the sub-band channel, it will result in a large amount of hardware resources being occupied. At the same time, the front-end filter will have a large processing pressure due to the large data rate. Therefore, the multi-phase structure can be used for optimization. Compared with the ordinary filter's order of filtering first and then decimating, the multi-phase filter is calculated in the order of decimation plus filtering. This ensures that the data discarded by decimation will not be filtered again, which greatly reduces the computational complexity and resource consumption.

[0068] Figure 2The flowchart of the FPGA implementation method of the polyphase filter channelizer is shown. The core idea is to divide a broadband signal into multiple narrow sub-band signals. Let h(n) be the coefficients of the Nth order filter bank, with the bandwidth evenly distributed in each sub-channel. The number of sub-channels is M, and the decimation factor is D. M and D satisfy an integer multiple relationship, M = FD. Then the output formula (2) of the kth sub-channel is as follows:

[0069]

[0070] In formula (2), y k (m) represents the output of the k-th sub-channel, x(n) is the input data, and h k (n) represents the coefficients of the polyphase branch filter for the k sub-channels, ω k The center frequency of the kth subchannel is represented by m, the output data index is represented by n, the input data index is represented by j, and the convolution calculation variable is represented by i. This indicates that the sample data is moved to the frequency band of the low-pass filter, and h(n) are the coefficients of the prototype filter; for example, let i = rM + p, r ∈ (-∞, ∞), p ∈ (0, M-1), where r is the data segment number, the index of the sample data point in this segment is set as p, l is a transient variable, specifically represented as l = rF, F is the ratio between the number of sub-band channel divisions M and the data decimation factor D, F = M / D, at this time, x p (m) and h p (m) can be expressed as formula (3) and formula (4) respectively:

[0071] x p (m)=x(mD-p) (3)

[0072] h p (m)=h(mM+p) (4)

[0073] y in formula (2) k (m) can be further expressed by formula (5):

[0074]

[0075] In formula (5), m is the subscript of the output data; h p (r) represents the coefficients of each group of multiphase branch filters, i.e., the prototype filter coefficients h. lp (n) obtained after M times extraction, for h p (l) Perform F-fold interpolation to obtain

[0076] As ordered Then we have formula (6):

[0077]

[0078] In formula (6), x p (m) represents the new sequence after the input data x(m) is extracted by a factor of D, where m is the index of the output data, D is the data extraction factor, and g is the index of the data. p (m), g p (l) are the coefficients of the multiphase branch filter after decimation and interpolation, respectively, where j is the imaginary unit and ω is the multiphase branch filter coefficient. k Let S′ be the center frequency of the k-th sub-channel. p (m) represents the extracted data and the rotation factor. The result of the multiplication is the spectrum shift to baseband, S p (m) represents the result of low-pass filtering after shifting the extracted data spectrum to the baseband; then the output y of the kth sub-channel in formula (5) k (m) is shown in formula (7):

[0079]

[0080] In formula (7), y k (m) represents the output of the k-th sub-channel, p∈(0,M-1) is the index of the segmented sample data, and M represents the number of sub-channel divisions. Based on the derivation, it can be concluded that the polyphase filtering process of the digital channelization software algorithm mainly involves sampling the data sample x(n) by D times and then combining it with g. p (m) Perform convolution filtering. In addition, if the downsampling factor D is inconsistent with the number of channel divisions M, i.e., F is not equal to 0, the branch filter coefficients can be interpolated according to the value of F, and then convolution filtering can be performed with the parallel shaped data.

[0081] Based on the above algorithm formula derivation, combined with the convolution law of polyphase filtering, the corresponding FPGA polyphase convolution calculation architecture can be designed; assuming the input signal is x(n), the prototype filter coefficient is h(n), the polyphase filter coefficient length is N, the number of sub-band channels is M, and the data decimation factor is D, where M = FD, then we have formula (8):

[0082] m I′P′ (n)=x I′P′ (n+I′M+P′D)h(M(I′+1)-(n mod M)) (8)

[0083] Formula (8) is the result of multiplication of multiphase structures, where Indicates the number of data groups per channel. This represents the number of parallel integer data paths in each group, where n represents the data index, and x represents the number of paths. I′P′ (n) represents the calculation of the nth data in the P′th path of the I′th group of the input, m I′P′(n) represents the nth data in the P'th path of the I'th group of the calculated output, and mod represents the modulo operation; subsequently, the parallel data of the convolution operation needs to be summed to complete the multiphase filtering calculation of the hardware architecture. The specific formula (9) is as follows:

[0084]

[0085] In formula (9), y P′ (n) represents the parallel data after multiphase filtering calculation, where n is the index of the output data. Indicates the number of data groups per channel. Indicates the number of parallel integer data paths in each group, m I′P′ (n) represents the nth data in the P′th channel of the I′th group of the calculated output; as shown in formula (9), after multiplication and summation calculations by the multiphase filter hardware architecture, there are a total of M / D channels of data; such as Figure 5 This represents the multiphase operation form of the first two sets of data when M=D=512. By completing the operation of 16 sets of data using this rule, multiphase filtering with a downsampling factor of 512 can be completed.

[0086] Furthermore, the parallel shaped data of group I mentioned in step S1 is multiplied and accumulated with the corresponding reversed branch filter coefficients of group I to obtain the parallel data after multiphase filtering calculation, thus completing the multiphase filtering operation. Step S2 specifically includes the following steps:

[0087] S2.1: The N-order prototype filter coefficients described in step S1.1 are divided into phases according to the number M of subband channels, resulting in I groups of branch filter coefficients, where I = N / M. The I groups of branch filter coefficients are then reversed. In the FPGA, a two-dimensional array can be used to define the reversed I groups of branch filter coefficients. The reversed I groups of branch filter coefficients correspond one-to-one with the I groups of parallel shaped data in step S1.2.

[0088] S2.2: For each data path in the I-group parallel shaping data described in step S1.2, a counter with a value from 0 to M-1 is set. Using the counter with a value from 0 to M-1, the branch filter coefficients of the I-group after reversal described in step S2.1 are selected according to the numerical correspondence principle. Each branch filter coefficient and the I-group parallel shaping data in step S1.2 are fed into the multiplier to complete the corresponding multiplication operation to obtain the convolution operation parallel data.

[0089] S2.3: Sum the data of the same channel in the parallel data of the convolution operation described in step S2.2 to obtain the parallel data after multiphase filtering calculation.

[0090] Furthermore, step S3 includes the following steps: setting up p RAMs with a depth of M (i.e., RAM containing p IP cores with a depth of M), where p = M / D; buffering and shaping the parallel data after multiphase filtering calculation output in step S2; after the RAM data in the corresponding channel of the parallel data after multiphase filtering calculation, i.e., the p-way parallel shaped data, is full, using an auxiliary counter to read the data out in reverse order from the high address to the low address of the RAM; and finally converting the p-way parallel shaped data into serial multiphase filtering data blocks, where each data block contains M data units.

[0091] Furthermore, step S4 mainly utilizes the IFFT module to perform M-point IFFT calculations on the serial polyphase filtered data block described in step S3. Figure 4 This is a schematic diagram of the sub-band distribution, where the center frequency of the k-th sub-band channel is ω. k =2πk / M, indicating that the sampling rate f s Divide into M parts, where M is the number of sub-band channel divisions. For ease of derivation, assume that the number of sub-band channel divisions M is the same as the data extraction factor D, i.e., F = 1, and set ω... k Substituting =2πk / M into formula (7), we can obtain formula (10):

[0092]

[0093] In formula (10), the e in the second row -j2kπm =cos(2kπm)-jsin(2kπm)=1,y k (m) represents the output of the k-th sub-channel, p∈(0,M-1) is the index of the segmented sample data, M represents the number of sub-channel divisions, x p (m) represents the data after extraction and spectrum shifting, g p (m) represents the coefficients of the multiphase branch filter, m represents the subscript of the output data, k represents the current subband channel number, j represents the imaginary unit, D is the data decimation factor, and IDFT represents the inverse Fourier transform; Formula (10) shows that after convolving each group of data samples with the corresponding filter group coefficients, m M-point IDFT (inverse Fourier transform) calculations are performed on them to obtain y k (m) represents the m-th output data of the k-th sub-channel.

[0094] Based on the formula derivation of the above algorithm and combined with the convolution law of its multiphase filtering, the corresponding FPGA multiphase convolution calculation architecture can be designed.

[0095] When the number of sub-band channels M is 512, the data sample decimation factor D is 64, and the polyphase filter length N is 8192, the overall digital channelization FPGA architecture is as follows: Figure 3 As shown.

[0096] Furthermore, step S5 includes the following steps:

[0097] S5.1: If each data block (M / D data blocks) in the M-point IFFT output data in step S4 is set as a group, then the compensation factor of each group of data is exactly the same, and the compensation factor of each data block changes cyclically with M / D data as a group. Based on this, a two-dimensional array can be set to define the compensation factor of each data block. According to the above analysis, two two-dimensional arrays are set for the real part and the imaginary part of the phase adjustment coefficient group in the frequency offset compensation operation. Each two-dimensional array contains M / D data elements, and the number of bits of M / D data elements is M / D·16.

[0098] S5.2: Set a data block counter to complete the block counting of the M-point IFFT output data described in step S4, and set a compensation factor selection counter to complete the selection of the phase adjustment coefficient group data described in step S5.1. Send the M-point IFFT output data after block counting and the corresponding selected phase adjustment coefficient group data into a complex multiplier to complete the frequency offset compensation operation and obtain serial data. Because it involves signal rate change processing, it is necessary to multiply the data of each channel to be output in this step with the corresponding compensation factor to complete the corresponding frequency offset compensation. The frequency offset compensation formula (1) is as follows:

[0099]

[0100] In formula (1), v k (n) represents the k-th channel data after frequency offset compensation, x k (n) represents the serial data of the k-th channel after inverse fast Fourier transform, where k is the channel number, M is the number of sub-band channels, D is the data decimation factor, j is the imaginary unit, and n is the index of the M-point IFFT output data sequence.

[0101] Furthermore, in step S6, the value of the loop counter is set to 0 to M.

[0102] Example 1

[0103] This embodiment illustrates the actual effect of the FPGA implementation method of the multiphase filter channelization processor in this invention through simulation experiments. The software simulation experiment was conducted using MATLAB 2023 software, and the hardware simulation experiment was conducted using Vivado 2020.2 software. The FPGA chip selected was Vu13p. A channelizer (i.e., a digital channel demodulator) with 512 sub-band channels M, a sub-bandwidth of 750Hz, and a downsampling factor D of 64 was used as an example for detailed explanation.

[0104] Simulation content and result analysis:

[0105] A MATLAB simulation model and an FPGA engineering module were built for the algorithm theory and engineering implementation of this invention, respectively. The FilterDesigner tool in MATLAB was used to design an 8192nd order prototype filter with a passband bandwidth of 375Hz. The filter was divided into 16 groups and subjected to 8x interpolation to obtain multiphase components. The sample rate was 384kHz, including two low symbol rates, and the spectrum is shown below. Figure 6 The data shown is subjected to digital channelization simulation. The spectrum of data with different symbol rates and a sampling rate of 6000Hz after polyphase filtering decimation and channelization processing is shown in the figure. Figure 7 , Figure 8 As shown, their out-of-band suppression ratios are all around 40dB.

[0106] Figure 9 , Figure 10 The diagrams show the data performance recovery of the multiphase digital channelization structure (i.e., the present invention) under noise-free conditions and the low-pass filter decimation structure (i.e., the comparison structure) after the data has been downsampled at varying rates and output by the subsequent demodulation module. It is clear that the performance of the multiphase digital channelization structure of the present invention is not significantly different from that of the ordinary downsampling filter structure. It can be seen that after processing by the multiphase digital channelization FPGA architecture, the frequency band division and sampling rate conversion of the combined signal can be completed well.

[0107] After synthesis and implementation using Vivado 2020.2, with the current stage input sampling rate of 384kHz and the combined data with a duty cycle of 1:191, and performing a 64x downsampling operation, the resource consumption of this invention is shown in Table 1. Because an optimized polyphase convolution computation structure is used, only 256 multipliers are needed to complete the 64x downsampling of the real and imaginary parts of the data into an 8192-order filter. Compared to using a polyphase filtering algorithm divided into 512 polyphase branches for computation, which consumes the same number of multipliers as the prototype filter (8192), the former can save a significant amount of FPGA resources. It is suitable for variable sampling rate channelization operations of low-speed data and has good practicality in engineering implementation. The specific implementation method of the overall FPGA hardware architecture is as follows: Figure 3 As shown, this invention also has good versatility, and the parameters can be adjusted and the architecture modified according to requirements to achieve the corresponding functions.

[0108] Table 1 Resource Usage Table

[0109]

[0110] Secondly, an FPGA implementation system for a polyphase filter channelizer is provided, which applies the FPGA implementation method of the polyphase filter channelizer. The FPGA implementation system includes a data shaping module, a polyphase filter operation module, a parallel-to-serial conversion module, an inverse fast Fourier transform module, a frequency offset compensation module, and a parallel data output module.

[0111] Data shaping module: Sets the Nth-order prototype filter coefficients of the channelizer, the number of sub-band channels M, and the data decimation factor D. It uses FIFO and counter to perform serial-to-parallel conversion and data shaping on the serial signal input to the channelizer, and obtains I sets of parallel shaped data, where I = N / M.

[0112] The multiphase filtering operation module: uniformly divides the coefficients of the Nth-order prototype filter into I groups of branch filter coefficients. The I groups of branch filter coefficients are multiplied by the I groups of parallel shaped data after being reversed to obtain convolution operation parallel data. The data of the same channel in the convolution operation parallel data are summed and accumulated to obtain the parallel data after multiphase filtering calculation.

[0113] Parallel-to-serial conversion module: Utilizes RAM to perform buffering, shaping, and parallel-to-serial conversion on the parallel data after the multiphase filtering calculation, to obtain a serial multiphase filtering data block;

[0114] Inverse Fast Fourier Transform (IFFT) module: The serial multiphase filter data block is fed into the IFFT module to complete the inverse fast fourier transform and obtain the M-point IFFT output data.

[0115] Frequency offset compensation module: After performing frequency offset compensation on the IFFT output data at point M, it outputs serial data;

[0116] Parallel data output module: Sets a loop counter to count the serial data to obtain the loop counter value, selects the corresponding channel data according to the loop counter value, and completes the parallel data output.

[0117] Thirdly, an electronic device including a memory and a processor:

[0118] Memory: Used to store the computer program for implementing the FPGA method of the polyphase filter channelizer;

[0119] Processor: An FPGA implementation method for implementing the polyphase filter channelizer when executing the computer program.

[0120] Fourthly, a computer-readable storage medium stores a computer program that, when executed by a processor, implements the FPGA implementation method of the multiphase filter channelizer; the computer-readable storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0121] The working principle of this invention is as follows:

[0122] In this invention, the necessary parameters of the digital channelizer are first set according to actual needs, such as the coefficients of the Nth-order prototype filter, the number of sub-band channels M, and the data decimation factor D. Based on the convolution law of polyphase theory, the serial data with a large duty cycle input to the channelizer is converted into parallel shaped data groups using parallel-to-serial conversion and data shaping. These data groups are then multiplied and accumulated with the coefficients of the polyphase branch filter to complete the polyphase filtering operation. Subsequently, RAM is used to convert the parallel polyphase filtering operation results into serial polyphase filtering data blocks, where the number of data units in each block is the same as the number of sub-band channels M. The serial polyphase filtering data blocks are subjected to an M-point IFFT transformation and the data is output. Subsequently, a fixed phase adjustment coefficient group combined with a counter is used to complete the frequency offset compensation of the IFFT calculation results (i.e., the output data). Finally, the corresponding channel data is selected according to the value of the cyclic counter from 0 to M-1 to complete the parallel data output.

Claims

1. An FPGA implementation method for a polyphase filter channelizer, characterized in that, Includes the following steps: S1: Set the Nth-order prototype filter coefficients of the channelizer, the number of sub-band channels M, and the data decimation factor D. Use FIFO and counter to perform serial-to-parallel conversion and data shaping on the serial signal input to the channelizer to obtain I sets of parallel shaped data, where I = N / M. S2: The Nth-order prototype filter coefficients in step S1 are evenly divided into I groups of branch filter coefficients. The I groups of branch filter coefficients are reversed and multiplied with the I groups of parallel shaped data in step S1 to obtain convolution operation parallel data. The data of the same channel in the convolution operation parallel data are summed and accumulated to obtain the parallel data after multiphase filtering calculation. S3: Use RAM to perform buffering, reshaping, and parallel-to-serial conversion on the parallel data after the multiphase filtering calculation described in step S2 to obtain a serial multiphase filtering data block; S4: Send the serial multiphase filter data block described in step S3 into the IFFT (Inverse Fast Fourier Transform) module to complete the inverse fast Fourier transform and obtain the M-point IFFT output data. S5: After frequency offset compensation, the M-point IFFT output data described in step S4 is output as serial data. S6: Set a loop counter to count the serial data described in step S5 to obtain the loop counter value, select the corresponding channel data according to the loop counter value and complete the parallel data output.

2. The FPGA implementation method of the polyphase filter channelizer as described in claim 1, characterized in that, Step S1 includes the following steps: S1.1: Set the Nth-order prototype filter coefficients of the channelizer, the number of sub-band channels M, and the data decimation factor D. Use FIFO to divide the serial signal input to the channelizer into I groups of single-channel data, where I = N / M, and each group of single-channel data is separated by M clock delays. S1.2: Set the value of the counter mentioned in step S1 to 0 to X, where X = M·(M / D-1). When the counter value is an integer multiple of D, assign values ​​to the second to M / D data according to the first data of each group of single-channel data. I groups of parallel shaped data can be obtained in this way. Each group of I groups of parallel shaped data contains M / D channels, and the serial signal completes the serial-to-parallel conversion.

3. The FPGA implementation method of the polyphase filter channelizer as described in claim 2, characterized in that, Step S2 includes the following steps: S2.1: The Nth-order prototype filter coefficients described in step S1.1 are divided into phases according to the number M of subband channels, resulting in I groups of branch filter coefficients, where I = N / M, and the I groups of branch filter coefficients are then reversed. S2.2: For each data path in the I-group parallel shaping data described in step S1.2, a counter with a value from 0 to M-1 is set. Using the counter with a value from 0 to M-1, the branch filter coefficients of the I-group after reversal described in step S2.1 are selected according to the numerical correspondence principle. Each branch filter coefficient and the I-group parallel shaping data in step S1.2 are fed into the multiplier to complete the corresponding multiplication operation to obtain the convolution operation parallel data. S2.3: Sum the data of the same channel in the parallel data of the convolution operation described in step S2.2 to obtain the parallel data after multiphase filtering calculation.

4. The FPGA implementation method of the polyphase filter channelizer as described in claim 1, characterized in that, Step S3 includes the following steps: Set up p RAMs of depth M, where p = M / D, and perform buffering and shaping on the parallel data after multiphase filtering calculation output in step S2. After the RAM data in the corresponding channel of the parallel data after multiphase filtering calculation, i.e. the p-way parallel shaped data, is full, use an auxiliary counter to read the data out in reverse order from the high address to the low address of the RAM. Finally, convert the p-way parallel shaped data into serial multiphase filtering data blocks, where each data block contains M data units.

5. The FPGA implementation method of the polyphase filter channelizer as described in claim 1, characterized in that, Step S5 includes the following steps: S5.1: Set up two two-dimensional arrays for the real part and imaginary part of the phase adjustment coefficient group in the frequency offset compensation operation. Each two-dimensional array contains M / D data elements, and the number of bits of M / D data elements is M / D·16. S5.2: Set a data block counter to complete the block counting of the M-point IFFT output data described in step S4, and set a compensation factor selection counter to complete the selection of the phase adjustment coefficient group data described in step S5.

1. Send the M-point IFFT output data after block counting and its corresponding selected phase adjustment coefficient group data into a complex multiplier to complete the frequency offset compensation operation and obtain serial data. The frequency offset compensation formula is as follows: In formula (1), v k (n) represents the k-th channel data after frequency offset compensation, x k (n) represents the serial data of the k-th channel after inverse fast Fourier transform, where k is the channel number, M is the number of sub-band channels, D is the data decimation factor, j is the imaginary unit, and n is the index of the M-point IFFT output data sequence.

6. The FPGA implementation method of the polyphase filter channelizer as described in claim 1, characterized in that, In step S6, the value of the loop counter is set from 0 to M.

7. An FPGA implementation system for a polyphase filter channelizer, using the FPGA implementation method for the polyphase filter channelizer as described in any one of claims 1 to 6, wherein the FPGA implementation system includes a data shaping module, a polyphase filter operation module, a parallel-to-serial conversion module, an inverse fast Fourier transform module, a frequency offset compensation module, and a parallel data output module; Data shaping module: Sets the Nth-order prototype filter coefficients of the channelizer, the number of sub-band channels M, and the data decimation factor D. It uses FIFO and counter to perform serial-to-parallel conversion and data shaping on the serial signal input to the channelizer, and obtains I sets of parallel shaped data, where I = N / M. The multiphase filtering operation module: uniformly divides the coefficients of the Nth-order prototype filter into I groups of branch filter coefficients. The I groups of branch filter coefficients are multiplied by the I groups of parallel shaped data after being reversed to obtain convolution operation parallel data. The data of the same channel in the convolution operation parallel data are summed and accumulated to obtain the parallel data after multiphase filtering calculation. Parallel-to-serial conversion module: Utilizes RAM to perform buffering, shaping, and parallel-to-serial conversion on the parallel data after the multiphase filtering calculation, to obtain a serial multiphase filtering data block; Inverse Fast Fourier Transform (IFFT) module: The serial multiphase filter data block is fed into the IFFT module to complete the inverse fast fourier transform and obtain the M-point IFFT output data. Frequency offset compensation module: After performing frequency offset compensation on the IFFT output data at point M, it outputs serial data; Parallel data output module: Sets a loop counter to count the serial data to obtain the loop counter value, selects the corresponding channel data according to the loop counter value, and completes the parallel data output.

8. An electronic device comprising a memory and a processor, characterized in that: Memory: for storing a computer program that implements the FPGA implementation method of the polyphase filter channelizer as described in any one of claims 1 to 6; Processor: for implementing the FPGA implementation method of the polyphase filter channelizer as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium storing a computer program that, when executed by a processor, implements an FPGA implementation method for a polyphase filter channelizer as described in any one of claims 1 to 6.

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