FPGA-Based Digital Transformer Signal Decoding Method and Device

Abstract

The present application relates to a digital transformer signal decoding method and device based on FPGA, including: according to a reference clock that is 16 times higher than the Manchester signal frequency, at the rising edge of each clock cycle, use a receiving module to receive a serial Manchester data signal. When a correct rising edge is detected, start a synchronous clock to provide timing support for subsequent decoding. According to the 1 / 4 and 3 / 4 positions of each bit period of the data cell, generate central samples to extract valid data. According to the Manchester coding rule, convert the extracted valid data into NRZ code, and store the decoded NRZ code into a shift register. The present application can achieve the efficiency of the decoding process and the flexibility of system operation. This design fully combines the parallel processing ability of FPGA and the control advantages of the processor, ensuring fast and reliable information flow in the system.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and particularly to a digital transformer signal decoding method and device based on FPGA. Background Art

[0002] Digital transformers are core devices in smart grids and are widely used in current and voltage measurement and protection devices. To achieve reliable data transmission, digital transformers usually adopt Manchester coding technology, which is widely used in the industry due to its excellent synchronization and anti-interference performance. However, existing decoding methods have obvious limitations in processing speed and data management, making it difficult to meet the requirements of high-efficiency and real-time decoding. Therefore, developing a new decoding method and device with higher decoding efficiency and system flexibility has become an urgent need to improve the performance of digital transformers. Summary of the Invention

[0003] This application provides a digital transformer signal decoding method based on FPGA, which is characterized by including:

[0004] Receiving a serial Manchester data signal using a receiving module at the rising edge of each clock cycle according to a reference clock that is 16 times higher than the Manchester signal frequency;

[0005] When a correct rising edge is detected, starting a synchronous clock to provide timing support for subsequent decoding;

[0006] Generating valid data by extracting central samples according to the 1 / 4 and 3 / 4 positions of each bit period of the data cell;

[0007] Converting the extracted valid data into NRZ code according to the Manchester coding rule and storing the decoded NRZ code in a shift register.

[0008] Optionally, the digital transformer signal decoding method based on FPGA is characterized in that:

[0009] The receiving module consists of two registers for receiving serial Manchester data;

[0010] The receiving module generates a reference clock with a frequency that is 16 times the Manchester signal frequency, and uses the FPGA to process the data by detecting the rising edge of the reference clock;

[0011] By non-blocking assignment operation, register 2 <= register 1, register 1 <= serial Manchester data, to achieve the necessary delay of the signal.

[0012] Optionally, the detecting of the correct rising edge includes:

[0013] When the rising edge of the signal is detected, that is, when register 1 is 1 and register 2 is 0, a synchronous clock with the same frequency as the Manchester signal is started;

[0014] When the synchronous clock enable signal is valid, it is counted through a 4-bit register. The value of the synchronous clock is determined by the highest bit of the 4-bit register, thus realizing the accurate generation of the synchronous clock.

[0015] The initial value of the synchronization clock is set to 0 to comply with the signal timing;

[0016] According to the characteristics of Manchester encoding, during the initial communication establishment or the reconstruction after data anomalies, the synchronous clock needs to be triggered by specific conditions.

[0017] Optionally, the FPGA-based digital transformer signal decoding method is characterized by:

[0018] The communication protocol of the device is based on the standard FT3 communication protocol, which requires that the idle state is represented by binary 1 and the value 1 is continuously transmitted between two frames of data using Manchester encoding.

[0019] Optionally, the generating of the central sample extracting valid data includes:

[0020] The valid data is generated when the 4-bit register value is 3 or 12, corresponding to the 1 / 4 and 3 / 4 positions of the bit period, ensuring that the sampling point is located at the center of the Manchester encoded signal.

[0021] Optionally, the detecting a correct rising edge includes:

[0022] The detection of a correct rising edge refers to detecting a falling edge, and triggering the synchronization clock when a rising edge including a bit 0 is immediately followed.

[0023] Optionally, converting the extracted valid data into NRZ code and storing the decoded NRZ code into a shift register includes:

[0024] When the rising edge of the reference clock is detected and the sample value is 1, the value of the NRZ code is determined by the XOR operation result of the current Manchester encoding state and the synchronization clock;

[0025] The storing in the shift register refers to using a 16-bit shift register to store the latest decoded NRZ data starting from the lowest bit, and shifting the nth bit of data to the n+1th bit until 16 bits are filled.

[0026] The present application also provides a digital mutual inductor signal decoding device based on FPGA, characterized in that the device includes an FPGA chip and a shift register.

[0027] Optionally, the FPGA-based digital transformer signal decoding device is characterized in that the FPGA chip is embedded with an ARM Cortex-M3 processor, which is responsible for system management and data processing functions, while the FPGA focuses on signal decoding.

[0028] The present application also provides an electronic device, which is characterized by including:

[0029] An MCU that communicates bidirectionally with the master device through a serial port and uploads the calculated effective value and fault information to the master device regularly or when an abnormality occurs for real-time monitoring and analysis.

[0030] The beneficial effect of the present application is to achieve the high efficiency of the decoding process and the flexibility of system operation. This design fully combines the parallel processing ability of the FPGA and the control advantages of the processor, ensuring fast and reliable information flow in the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following briefly introduces the drawings required in the description of the embodiments or the prior art. Obviously, the following drawings are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0032] Figure 1 The flowchart showing a method for decoding digital transformer signals based on FPGA disclosed in the present application. DETAILED DESCRIPTION

[0033] The following will describe in detail various exemplary embodiments, features, and aspects of the present application with reference to the drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0034] Among them, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0035] The special term "exemplary" herein means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" herein need not be construed as superior to or better than other embodiments.

[0036] In addition, for better illustration of this application, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that this application can still be implemented without certain specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail to highlight the gist of this application.

[0037] This application relates to the processing and analysis of the collected digital signals of current transformers, including data frame parsing, timing signal analysis and synchronization, protocol analysis and implementation. The core of this application consists of an FPGA+ARM chip in a system-in-package form. This chip embeds an ARM Cortex-M3 processor, which is responsible for system management and data processing functions. At the same time, the FPGA focuses on the signal decoding process. The decoded data is efficiently transmitted between the FPGA and the processor through the AHB bus, and the ARM Cortex-M3 further performs anomaly detection and management tasks, thus realizing the efficiency of the decoding process and the flexibility of system operation.

[0038] The FPGA (Field-Programmable Gate Array) is a semiconductor device that can be programmed on-site, with high flexibility and reconfigurability. Different from traditional ASICs (Application-Specific Integrated Circuits), the FPGA can implement different logic functions by modifying software codes without changing the hardware circuit.

[0039] The ARM Cortex-M3 is a microprocessor core that supports single-cycle multiplication, hardware division, branch prediction, and the Thumb-2 instruction set.

[0040] The AHB (Advanced High-performance Bus) is a bus mainly used for connecting high-performance modules. The decoded data is transmitted to the MCU through the AHB bus for data frame judgment, thus effectively improving the response ability and reliability of the system.

[0041] As Figure 1 shown, the flowchart of the digital current transformer signal decoding method based on FPGA includes:

[0042] S100, according to a reference clock that is 16 times higher than the Manchester signal frequency, at the rising edge of each clock cycle, use the receiving module to receive the serial Manchester data signal.

[0043] Specifically, the reference clock is generated by the receiving module, and the reference clock frequency is 16 times that of the Manchester signal frequency to improve the decoding accuracy. The receiving module consists of two registers and is used to receive the serial Manchester data.

[0044] Among them, the Manchester signal frequency is twice the original data frequency. In Manchester coding, the transmission of each bit is divided into a first half-cycle and a second half-cycle. The inverse code of the bit is transmitted in the first half-cycle, and the original code of the bit is transmitted in the second half-cycle. This design causes a level transition in the middle of each bit, and the level transition can be used to generate a synchronization signal for both the transmitter and the receiver.

[0045] S200, detect the correct rising edge, start the synchronization clock, and provide timing support for subsequent decoding.

[0046] Specifically, the rising edge of the signal refers to generating a synchronization clock through a register when the value of register 1 is 1 and the value of register 2 is 0.

[0047] Among them, each count of the 4-bit register increments the value by 1, and the value of the synchronization clock is determined by the highest bit of the 4-bit register value, thereby realizing the generation of the synchronization clock.

[0048] S300, generate central samples to extract valid data according to the 1 / 4 and 3 / 4 positions of each bit period of the data cell.

[0049] Specifically, the valid data refers to valid Manchester signal samples, which are generated when the 4-bit register value is 3 or 12, and the corresponding bit period positions are 1 / 4 and 3 / 4. Extracting at this time can ensure that the acquisition point is at the center position of the Manchester coding signal.

[0050] S400, according to the Manchester coding rule, convert the extracted valid data into NRZ code, and store the decoded NRZ code in the shift register.

[0051] Specifically, detecting a high-level change within the bit period is converted to 1 of the NRZ code, detecting a low-level change is converted to 0 of the NRZ code, and stored in the shift register. According to specific start and end bits, the valid data in the shift register is transmitted to the data register, and then the decoded data is sent to the main control device using the hardware SPI interface.

[0052] The Manchester coding is a self-synchronizing coding method, whose characteristic is that within each clock cycle, the state of the signal changes at the midpoint of the clock cycle, so there is a transition in the middle of each bit. This coding method can generate two transitions within each bit period, representing logical "0" and logical "1" respectively, and there is a transition in the middle of each bit, which enables the receiver to synchronize the clock by observing the signal transitions. The disadvantage of Manchester coding is that the data transmission rate is only half of the maximum theoretical rate because each bit requires two cycles to transmit.

[0053] The NRZ (Non-Return-to-Zero Code) code is a non-return-to-zero coding method, which uses a low level to represent binary 0 and a high level to represent binary 1. The disadvantage of the NRZ code is that it is impossible to determine the start and end of each bit. Therefore, it is necessary to transmit a synchronization signal through another channel while transmitting the NRZ code.

[0054] The beneficial effects of the above content are that when processing Manchester signals, it not only significantly improves the decoding efficiency and accuracy, but also enhances the flexibility and scalability of the system, providing an efficient and reliable solution for related applications.

[0055] Specifically, this application designs a receiving module that receives serial Manchester data (mdi) through two registers (mdi1 and mdi2).

[0056] This module generates a reference clock (clk16x) with a frequency 16 times that of the Manchester signal, and uses the FPGA to process the data by detecting the rising edge of the reference clock (clk16x).

[0057] Necessary signal delays are achieved through non-blocking assignment operations: mdi2 <= mdi1; mdi1 <= mdi.

[0058] Specifically, when the rising edge of the signal is detected (i.e., mdi1 is 1 and mdi2 is 0), a synchronous clock (clk1x) with the same frequency as the Manchester signal is started for subsequent processing.

[0059] The generation of the synchronous clock (clk1x) is performed when the rising edge of the high-frequency reference clock (clk16x) is detected. And when the enable signal of the same-frequency clock is valid, the system counts through a 4-bit register (clkdiv), incrementing the value of clkdiv by 1 each time. The value of the same-frequency clock (clk1x) is determined by the highest bit (clkdiv[3]) of clkdiv, thus achieving the accurate generation of the same-frequency clock.

[0060] Based on the characteristics of Manchester coding (a transition from low to high in the middle level represents "1", and a transition from high to low represents "0"), during the initial communication establishment or the reconstruction process after data anomalies, it is necessary to trigger the synchronous clock (clk1x) through specific conditions.

[0061] Specifically, when a falling edge is detected, and immediately followed by a rising edge containing a bit of 0, the synchronous clock (clk1x) is triggered to ensure the accurate decoding and timing synchronization of subsequent data.

[0062] Specifically, during the decoding process, data sampling is performed at the 1 / 4 and 3 / 4 positions of the bit period. This design ensures that the sampling points are located at the center of the Manchester-encoded signal, thereby improving the accuracy of signal extraction. Specifically, valid Manchester signal samples are generated when the clkdiv value is 3 or 12, corresponding to the 1 / 4 and 3 / 4 positions of the bit period. By sampling at the optimal moment of signal transition, the bit error rate caused by timing deviation is minimized, thus improving the reliability and accuracy of decoding.

[0063] Specifically, according to the rules of Manchester coding, the received signal is converted into NRZ (Non-Return-to-Zero) code. Specifically, when the rising edge of the high-frequency reference clock (clk16x) is detected, the current sample value is checked. If sample = 1, the value of the NRZ code is determined by the exclusive OR operation result of the current Manchester coding state (mdi2) and the synchronous clock (clk1x), where mdi2 is used to represent the current Manchester coding state. Through this process, the accurate conversion of the Manchester-encoded signal into the NRZ code is achieved, providing a reliable basis for subsequent data processing.

[0064] When the rising edge of the synchronous clock (clk1x) is detected, the following non-blocking assignment operations are performed: rsr[15:1] <= rsr[14:0]; rsr[0] <= nrz; Through this process, a 16-bit shift register (rsr) is used to store the decoded NRZ data. Each bit of the shift register can be regarded as an independent storage unit, and the data is shifted according to the following rules: the data in the 14th bit is shifted to the 15th bit, the data in the 13th bit is shifted to the 14th bit, and so on, while the newly decoded data is stored in the lowest bit (rsr[0]). This design ensures that the shift register always stores the latest 16-bit data in the first-in-first-out order. When the register is filled with 16 bits, the data can be further processed or sent according to requirements, thus achieving efficient decoded data management and subsequent operations.

[0065] Specifically, the communication protocol of this device is based on the standard FT3 communication protocol, which is a common serial communication protocol that ensures the effective transmission of data in strict accordance with specifications. According to the GB / T 20840.8-2007 standard, this protocol requires the idle state to be represented by binary 1, and this value 1 is continuously transmitted in Manchester coding between two frames of data. In this device, when the rising edge of the synchronous clock (clk1x) occurs, the system checks the value of the NRZ signal: if NRZ = 1, the counter is incremented; if NRZ = 0, the counter is reset to 0.

[0066] Meanwhile, when the NRZ signal returns to zero, the system will detect the value of the counter. When the counter reaches or exceeds 70, the starting position of the data frame header can be determined. This is because according to the FT3 protocol, data frames usually start with a specific identifier (0x0564), and the state change of the NRZ signal is an important basis for detecting this identifier. Once the starting position of the data frame header is determined, the system will extract 16 consecutive bits of data from the shift register (rsr) and transfer it to the data register (data_register). This transfer is achieved through a simple assignment operation, such as data_register <= rsr, thus completing the effective decoding and storage of the data.

[0067] Among them, in the FT3 communication protocol, each data frame contains 56 bytes. According to the end signal of data transmission or the complete reception of the frame, it can be judged when to stop the synchronous clock. Usually, when 56 bytes are received completely, the synchronous clock will stop. When new data frames need to be transmitted continuously, the synchronous clock will be restarted. When restarting the clock, just detect the rising edge of the Manchester-encoded signal mdi2 at the rising edge of the reference clock (clk16x), and the clock can be started immediately. This operation ensures the synchronization between each data frame and the clock. Through the identification of the frame header and clock control, the integrity and accuracy of each data frame can be effectively guaranteed. At each rising edge of the clock, the system will perform the same NRZ data storage and shifting operations as described above to ensure that the newly received data is accurately recorded and stored.

[0068] Moreover, in the FT3 communication protocol, it shows how to ensure data integrity and reliability through multiple mechanisms. CRC16 (Cyclic Redundancy Check) is a common algorithm used to detect data transmission errors. In the FT3 protocol, each frame of data contains three independent CRC16 check values. The receiving party will calculate the CRC16 value based on the received frame data and then compare it with the three received CRC16 check values. If the calculated CRC16 value is inconsistent with the received one, it indicates that an error occurred during data transmission. At the same time, in the FT3 communication protocol, each frame of data also has a sample counter. The role of the sample counter is to ensure the correct order of data transmission, prevent data loss or duplication. Each frame of data contains a sample counter value, which increments between each frame. If the received sample counter value is inconsistent with the locally stored counter value (such as the counter skipping or repeating), it will trigger the frame loss handling mechanism, which can timely detect problems such as transmission interruptions or data disorders. The MCU (Microcontroller Unit) can take corresponding measures in a timely manner by detecting data errors, frame losses, or other potential faults. When detecting abnormal situations (such as data verification failures, frame losses, counter inconsistencies, etc.), the MCU will trigger a processing mechanism, usually resetting the data reception on the FPGA (Field Programmable Gate Array) side to the initial state, resynchronizing the data stream or re-establishing the connection.

[0069] Specifically, the device used in this application transfers the decoded data to the MCU through the Advanced High-performance Bus (AHB) for data frame judgment, thereby effectively improving the system's response ability and reliability. Using the AHB bus can provide high-bandwidth data transmission to ensure that the decoded data can be quickly transmitted to the MCU. After receiving a data frame, the MCU first performs an integrity check, including verifying the frame start symbol, frame length, checksum, and sample counter, etc. If the MCU detects an abnormality (such as data error, frame loss, or other faults), it will trigger the corresponding processing mechanism. The MCU notifies the FPGA of the abnormality through the AHB bus. After receiving the MCU's abnormality notification, the FPGA will reset the condition for enabling the same-frequency clock and prepare to receive a new data frame, thereby ensuring the continuity of the data stream. This method significantly enhances the system's robustness and real-time performance by combining the MCU's abnormality detection and the FPGA's reconnection mechanism, and can quickly respond and restore the connection when a data transmission error occurs. This solution is particularly suitable for application scenarios with high requirements for data transmission reliability.

[0070] Among them, the MCU can perform statistical analysis on the sampled data, calculate parameters such as the effective value (e.g., RMS value), and conduct fault judgment. In the FT3 protocol, each frame of data contains the sampled value data of neutral point current, phase A current, phase B current, phase C current, phase A voltage, phase B voltage, phase C voltage, neutral point voltage, etc. According to the storage order of the sampled values and the specified sampling rate, the corresponding effective values can be calculated.

[0071] Moreover, the MCU communicates bidirectionally with the master device through the serial port. Regularly or when an anomaly occurs, it uploads the calculated effective values and fault information to the master device for real-time monitoring and analysis. In addition, the MCU can also receive instructions and new configuration parameters from the master device, adjust its operating mode or data processing method, and reset the system according to the instructions to ensure rapid recovery in case of a fault or when re-initialization is required. Through the calculation and upload functions of the MCU, the master device can achieve real-time monitoring of the entire system, enhancing the reliability of the system. The independent processing ability of the MCU makes the system more flexible, capable of being adjusted according to different application requirements, and also facilitating future function expansion.

[0072] In summary, the purpose of this application is to provide a data decoding and transmission system based on Manchester coding, which has the following advantages:

[0073] Device structure: The core of this device consists of an FPGA chip in a system-in-package form, with an embedded ARM Cortex-M3 processor. The FPGA is responsible for decoding Manchester signals, and the ARM Cortex-M3 processor undertakes the functions of system management and data processing. The two exchange data through the AHB bus to ensure efficient information flow.

[0074] Efficient decoding: Use a reference clock that is 16 times higher than the Manchester signal frequency. At the rising edge of each clock cycle, use two FF registers to receive the serial Manchester data signal. When the correct rising edge is detected, start a clock with the same frequency as the Manchester signal (i.e., 1 / 16 of the reference clock frequency) for decoding. Generate central samples at the 1 / 4 and 3 / 4 points of each bit period of the data cell to extract the valid data.

[0075] Simplified hardware design: Use simple flip-flops and clock control to reduce system complexity. Decode the received Manchester signal into NRZ code and define the conditions for logic "1" and "0". Use a shift register to store the decoded NRZ data and transfer the data to the data register according to specific conditions.

[0076] Data transmission: Use the hardware SPI interface to send the decoded data to the master device to ensure data integrity and transmission speed. Specific embodiments:

[0078] For example, assuming the input Manchester signal frequency is 1 MHz, the system of the present application will use a 16 MHz clock for sampling. In each bit period, the system generates a central sample and decodes it, and finally transmits the data to the master device through the SPI interface.

[0079] The beneficial effects of the present application are as follows: through the combination of FPGA and MCU, efficient decoding of Manchester signals and intelligent data management are achieved, significantly improving the real-time performance and reliability of the system. At the same time, this method has flexibility and can adapt to various data transmission requirements, having a broad market application prospect.

[0080] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A digital transformer signal decoding method based on FPGA, characterized in that, Including: Receiving a serial Manchester data signal using a receiving module at the rising edge of each clock cycle according to a reference clock that is 16 times higher than the Manchester signal frequency; When a correct rising edge is detected, start a synchronous clock to provide timing support for subsequent decoding; Generate central samples according to the 1 / 4 and 3 / 4 positions of each bit period of the data cell to extract valid data; According to the Manchester coding rule, convert the extracted valid data into NRZ code and store the decoded NRZ code in a shift register; When a high-level change is detected within a bit period, it is converted to 1 of the NRZ code, and when a low-level change is detected, it is converted to 0 of the NRZ code and stored in the shift register. According to specific start and end bits, the valid data in the shift register is transmitted to the data register, and then the decoded data is sent to the master device using the hardware SPI interface.

2. The digital transformer signal decoding method based on FPGA according to claim 1, characterized in that: The receiving module consists of two registers for receiving serial Manchester data; The receiving module generates a reference clock with a frequency 16 times that of the Manchester signal frequency, and uses the FPGA to process the data by detecting the rising edge of the reference clock; Through non-blocking assignment operations, register 2 <= register 1, register 1 <= serial Manchester data, to achieve the necessary delay of the signal.

3. The digital transformer signal decoding method based on FPGA according to claim 1, wherein, The detection of the correct rising edge includes: When the rising edge of the signal is detected, that is, when register 1 is 1 and register 2 is 0, start a synchronous clock with the same frequency as the Manchester signal; When the synchronous clock enable signal is valid, count through a 4-bit register, and the value of the synchronous clock is determined by the highest bit of the 4-bit register to achieve the accurate generation of the synchronous clock; The initial value of the synchronous clock is set to 0 to comply with the signal timing; According to the characteristics of Manchester coding, during the initial communication establishment or the reconstruction process after data anomaly, the synchronous clock needs to be triggered by specific conditions.

4. The digital transformer signal decoding method based on FPGA according to claim 1, characterized in that: The communication protocol of this device is based on the standard FT3 communication protocol, which requires the idle state to be represented by binary 1 and continuously transmit the value 1 in Manchester coding between two frames of data.

5. The digital transformer signal decoding method based on FPGA according to claim 1, characterized in that The generation of central samples to extract valid data includes: The valid data is generated when the value of the 4-bit register is 3 or 12, corresponding to the 1 / 4 and 3 / 4 positions of the bit period, ensuring that the sampling points are located at the center position of the Manchester coding signal.

6. The digital transformer signal decoding method based on FPGA according to claim 3, wherein The need to trigger the synchronous clock by specific conditions includes: The specific condition refers to detecting a falling edge and then immediately followed by a rising edge containing a bit of 0 to trigger the synchronous clock.

7. The digital transformer signal decoding method based on FPGA according to claim 1, characterized in that, The conversion of the extracted valid data into NRZ code and the storage of the decoded NRZ code in the shift register includes: When the rising edge of the reference clock is detected and the sample value is 1, the value of the NRZ code is determined by the exclusive OR operation result of the current Manchester coding state and the synchronous clock; Said storing into the shift register means using a 16-bit shift register to store the latest decoded NRZ data starting from the least significant bit, and shifting the n-th bit data to the (n + 1)-th bit until 16 bits are filled.

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