System and method for optimizing network-on-chip generation of switches using incremental topology synthesis

Abstract

The present disclosure relates to systems and methods for network-on-chip generation of switches optimized with incremental topology synthesis. Systems and methods implemented by a tool for generation and synthesis of networks, such as network-on-chip (NoC), are disclosed. The tool receives input from a user, either as a data file or as input through a graphical user interface (display). The tool generates a NoC from a set of physical constraints and performance constraints. The tool generates a NoC with all its elements, which is legal and satisfies the constraints. The tool also receives as input a performance scenario or performance requirement that can be used to transform an existing topology to meet the requirements of a new addition. The tool identifies and reuses switches to reduce the number of switches. The output generated represents a network that meets the requirements, such as a NoC.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application Serial No. 63 / 543,028, filed by Amir CHARIF et al. on October 6, 2023, entitled “SYSTEM AND METHOD FOR GENERATION OF NETWORKS-ON-CHIP (NoCs) USING INCREMENTAL TOPOLOGY SYNTHESIS FOR OPTIMIZATION OF SWITCHES” and U.S. Patent Application No. 18 / 907,613, filed on October 7, 2024, the entire disclosures of which are incorporated herein by reference. Technical Field

[0003] The presented techniques are in the field of electronic system design and more particularly relate to the generation of Networks on Chip (NoC). Background Art

[0004] A multiprocessor system has been implemented in a system on chip (SoC) that communicates through one or more networks on chip (NoCs). The SoC includes instances of intellectual property (IP) that communicate using the NoC. Examples of IP include initiators and targets. The initiator sends data that may be a transaction to the target. The transaction is sent from the initiator to one or more targets in the form of a packet using an industry standard protocol. The initiator, connected to the NoC through a network interface unit (NIU), sends a request transaction to the target using an address for selecting the target. The NoC decodes the address and transmits the request from the initiator to the target. The target processes the transaction and sends a response transaction, which is transmitted back to the initiator by the NoC. The NoC is an example of a scalable communication architecture designed for the SoC. When designing an application to use the NoC, it is more desirable to eliminate conditions that lead to deadlocks in the network. It is currently known to route messages through an array of data processing nodes, thereby facilitating multiple paths to the destination without incurring message delays caused by routing deadlocks. An important aspect in designing a dedicated NoC is to achieve more ideal deadlock-free operation while using minimal power and area overhead. It is known that two major types of deadlocks can occur in NoCs. The first type of deadlock is a routing-dependent deadlock. The second type of deadlock is message-dependent deadlock.

[0005] For a given set of performance requirements (such as connectivity and latency between source and destination, frequency of each element, maximum available area of ​​NoC logic, minimum throughput between source and destination, location of elements connected to NoC on floor plan), creating an optimal NoC with the minimum number of logic and wires is a complex task. Creating such an optimal NoC is a routine job for chip architects or chip manufacturers, and it is a difficult and time-consuming task. Designing NoC is not only a difficult task, but also the design of NoC usually needs to be improved every time one of the requirements changes (such as modification of chip floor plan or modification that affects expected performance). Therefore, the task needs to be repeated frequently during chip design. The process is time-consuming, which causes delays in production. Therefore, it is necessary to efficiently generate a system and method for NoC from a set of constraints and a set of element inputs listed as requirements. The system needs to generate a NoC that meets the constraints and all its elements are placed on the floor plan of the chip.

[0006] There are currently problems during the synthesis of a new NoC for making connections in an existing NoC, as reusing the existing topology is challenging and the production costs associated with the wires are expensive. One problem that exists is verifying whether the existing NoC can provide enough bandwidth to accommodate the number of communication scenarios given as output.

[0007] Another problem is the lack of tools that can automatically configure the NoC in an optimal way, ensuring that it has sufficient bandwidth to accommodate the several communication scenarios that may be given as input.

[0008] Another problem is that when synthesizing a set of connections in a NoC and reusing wires to minimize global wire costs, too many switches may be created. Therefore, a system and method is needed that can significantly reduce the number of switches created during the synthesis process without requiring a slow post-processing step to globally reorganize switches based on proximity (i.e., switch clustering).

[0009] Another problem exists during NoC topology synthesis (even with knowledge of all performance scenarios at the outset), the configuration process cannot guarantee to find a solution that supports running several user-provided performance scenarios. A newly created NoC (generated by topology synthesis or manually) may not support the load generated by the scenario.

[0010] Another problem exists when designers provide performance requirements to a NoC generation tool or topology synthesis process by defining a set of scenarios, which are a set of communications that occur in parallel at a given speed to drive the shape of the topology using performance constraints. It is difficult and time consuming to define all the scenarios required to achieve a specific traffic distribution, and it is also very difficult to input these scenarios.

[0011] Another problem that arises when performing environmental NoC synthesis occurs after a specification change. For example, when a new connection is added, the previous results are overwritten. Therefore, there is a need for a method for designing a NoC that avoids both routing-dependent and message-dependent deadlocks and is integrated with the topology synthesis phase of the NoC design flow. Considering the deadlock avoidance problem during topology synthesis can achieve a more ideal NoC design than conventional methods that manage deadlock avoidance problems separately. In addition, there is a need to add new connections without overwriting previous results. Summary of the invention

[0012] According to various embodiments and aspects of the present invention, systems and methods are disclosed for generating a network on chip (NoC) using a set of constraints and inputs to produce or generate a NoC having all elements that satisfy the defined constraints while avoiding deadlock.

[0013] Another system and method performed by a tool is shown that significantly reduces the number of switches created during the synthesis process without requiring slow post-processing steps to globally reorganize switches based on proximity.

[0014] The elements of the NoC are placed on the floor plan of the chip. One advantage of the present invention is the simplification of the design process and the work of the chip architect or designer. The NoC generation or synthesis method has an incremental design, so the NoC generates or synthesizes one connection at a time. In particular, the set of nodes of the source-destination pair and each new connection are synthesized by taking the set of existing connections as input. New components are not limited to switches and / or links, which can be created when synthesizing new connections to define the network route from the source to the destination. Within the scope of the present invention, the destination includes but is not limited to a list of components to be traversed. In addition, the configuration of the newly created components includes but is not limited to the time and / or data width, which is an important aspect when synthesizing new connections. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A shows a logical view of a network on a chip (NoC), including the various elements that create the NoC;

[0016] Figure 1B shows a NoC with elements placed on a network plan;

[0017] Figure 2A A method for generating a NoC description based on a set of constraints according to various aspects and embodiments of the present invention is shown;

[0018] Figure 2B A block diagram of a NoC synthesis tool according to various aspects and embodiments of the present invention is shown;

[0019] Figure 3 A graphical view of a chip floor plan with blocking regions and interface locations to a NoC is shown according to various aspects and embodiments of the present invention;

[0020] Figure 4 shows a NoC connection table according to various aspects and embodiments of the present invention;

[0021] Figure 5 A table showing scenarios defined for throughput of read and write transactions according to various aspects and embodiments of the present invention;

[0022] Figure 6 shows the creation of a network with three traffic classes according to various aspects and embodiments of the present invention;

[0023] Figure 7 The invention shows a method for using a combiner and a splitter according to various aspects and embodiments of the present invention. Figure 6 Decomposition of the network;

[0024] Figure 8 According to various aspects and embodiments of the present invention, Figure 6 A roadmap in the plane of one initiator of the network;

[0025] Fig. 9 According to various aspects and embodiments of the present invention, Figure 6 A roadmap in the plane of a target of the network;

[0026] Fig.10 It is shown that according to various aspects and embodiments of the present invention, the main node separator is decomposed into Figure 8 Roadmap for physically distributed cascade separators;

[0027] Fig.11 It is shown that according to various aspects and embodiments of the present invention, the master node merger is decomposed into Fig. 9 A roadmap of physically distributed cascade combiners;

[0028] Fig.12 An example of two nodes approaching and merging according to various aspects and embodiments of the present invention is shown;

[0029] Fig.13 illustrates a NoC topology on a planar graph of a deadlock-free network with segments and turns according to various aspects and embodiments of the present invention;

[0030] Fig.14A illustrates a NoC topology on a planar graph with separated segments "S" to "D" according to various aspects and embodiments of the present invention;

[0031] Fig. 14B illustrates a NoC topology on a floor plan with a split segment "S" to "D" updated to use two new sub-segments "S" to "N" and "N" to "D" in accordance with various aspects and embodiments of the present invention;

[0032] Fig. 14C illustrates a NoC topology on a plan view with sub-segments "N" and "S" merged into separate segments according to various aspects and embodiments of the present invention;

[0033] Fig.14D illustrates a NoC topology on a planar graph with sub-segments represented by channels between nodes "N" and "S" bifurcated into separate segments according to various aspects and embodiments of the present invention;

[0034] Fig.15 is a flow chart illustrating a method for single connection NoC topology synthesis processing according to various aspects and embodiments of the present invention;

[0035] Fig.16A illustrates a NoC topology on a planar graph with a request to connect a node "S" to a node "D" according to various aspects and embodiments of the present invention;

[0036] Fig. 16B illustrates a NoC topology on a floor plan with incremental synthesis results of a routing configuration from "S" to "D" with a new ingress segment, a new internal segment, and an existing egress segment according to various aspects and embodiments of the present invention;

[0037] Fig.17A Illustrated is a NoC topology on a floor plan with a communication strategy 1700 that optimizes wire length for best performance according to various aspects and embodiments of the present invention;

[0038] Fig. 17B A NoC topology on a floor plan of a communication strategy 1710 with low latency communication is illustrated according to various aspects and embodiments of the present invention.

[0039] Fig.18A illustrates an incremental synthesis of an initial setup for a segment connecting from a node "S" to a node "D" in accordance with various aspects and embodiments of the present invention;

[0040] Fig.18B illustrates an incremental synthesis mode 1810 for physical invariance of segments with minimally varying parameters, in accordance with various aspects and embodiments of the present invention;

[0041] Fig. 18C Illustrated is an incremental synthesis mode 1820 for logical invariance of segments with optimized topology and preserving configured parameters in accordance with various aspects and embodiments of the present invention;

[0042] Fig.18D illustrates an incremental synthesis mode 1830 for variability of network elements with optimized topology and adjustment of configured parameters in accordance with various aspects and embodiments of the present invention; and

[0043] Fig.19 The diagram illustrates a process of NoC synthesis based on mesh custom subnetwork description according to various aspects and embodiments of the present invention.

[0044] Fig. 20 A process for verifying a NoC configuration according to various aspects and embodiments of the present invention is illustrated.

[0045] Fig.21 A process for configuring a NoC according to various aspects and embodiments of the present invention is illustrated.

[0046] Fig. 22 A table illustrating various scenarios for connectivity using a NoC according to various aspects and embodiments of the present invention.

[0047] Fig.23 The process of inputting a physical location into a design tool according to various aspects and embodiments of the present invention is illustrated.

[0048] Fig.24 The process of inputting clock constraints into a design tool according to various aspects and embodiments of the present invention is illustrated.

[0049] Fig.25 The process of inputting into a design tool according to various aspects and embodiments of the present invention is illustrated.

[0050] Fig.26 A portion of a NoC topology between IP blocks sharing a segment is illustrated.

[0051] Fig. 27 The diagram shows that according to various aspects and embodiments of the present invention, Fig. 20 Steps in the process of sharing segments.

[0052] Fig.28 The diagram shows that according to various aspects and embodiments of the present invention, Fig. 20 Steps in the process of sharing segments.

[0053] Fig.29 The diagram shows that according to various aspects and embodiments of the present invention, Fig. 20 Steps in the process of sharing segments.

[0054] Fig.30 A NoC topology with segments shared among multiple initiators to reduce wire costs is illustrated.

[0055] Fig.31 A graphical user interface of a topology generation tool having sections for sharing creation and labeling according to various aspects and embodiments of the present invention is illustrated.

[0056] Fig.32 Possible scenarios for a NoC used by a topology generation tool are illustrated according to various aspects and embodiments of the present invention.

[0057] Fig.33 The diagram illustrates new channels created in a NoC topology structure by a topology generation tool according to various aspects and embodiments of the present invention.

[0058] Fig.34 It illustrates the reuse of switches in a NoC as input switches for a new segment in accordance with various aspects and embodiments of the present invention.

[0059] Fig.35 It illustrates the reuse of switches in a NoC as output switches for a new segment according to various aspects and embodiments of the present invention.

[0060] Fig.36 Illustrated is the reuse of switches in a NoC to separate existing segments using new switches for new segments in accordance with various aspects and embodiments of the present invention.

[0061] Fig.37 The process of selecting a reusable switch in a topology according to various aspects and embodiments of the present invention is illustrated. DETAILED DESCRIPTION

[0062] Each example of the prior art is described below, which illustrates various aspects and embodiments of the present invention. In general, examples can use the described aspects in any combination. All principles, aspects and embodiments listed herein and their specific examples are intended to cover their structural and functional equivalents. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents (i.e. any element developed to perform the same function, no matter how its structure) developed in the future.

[0063] It should be noted that the singular forms "a", "an", and "the" used herein include plural references unless the context clearly dictates otherwise. References throughout the specification to "one aspect", "an aspect", "certain aspects", "various aspects", or similar language mean that the particular aspect, feature, structure, or characterization described in connection with any embodiment is included in at least one embodiment of the present invention.

[0064] The phrases "according to one or more embodiments," "in one embodiment," "in at least one embodiment," "in certain embodiments," and similar language throughout the specification may, but need not, all refer to the same embodiment or similar embodiments. In addition, the aspects and embodiments of the invention described herein are merely exemplary and should not be construed as limitations on the scope or spirit of the invention as understood by those skilled in the art. The disclosed invention is effectively made and used in any embodiment including any novel aspect described herein. All statements of the principles, aspects, and embodiments of the invention listed herein are intended to include structural and functional equivalents thereof. Such equivalents are intended to include both currently known equivalents and equivalents to be developed in the future.

[0065] As used herein, "initiator" refers to similar intellectual property (IP) modules or units and the term can be used interchangeably within the scope and embodiments of the present invention. As used herein, "target" refers to similar IP modules or units and the term can be used interchangeably within the scope and embodiments of the present invention. As used herein, a transaction can be a request transaction or a response transaction. Non-limiting examples of request transactions include write requests and read requests.

[0066] As used herein, a node is defined as a distribution point and / or a communication endpoint that is capable of creating, receiving and / or transmitting information across a communication path or channel. A node may refer to any of the following: a switch, a splitter, a combiner, a buffer, and an adapter. As used herein, splitters and combiners are switches; not all switches are splitters or combiners. As used herein and in accordance with various aspects and embodiments of the present invention, the term "splitter" describes a switch having a single inlet port and multiple outlet ports. As used herein and in accordance with various aspects and embodiments of the present invention, the term "combiner" describes a switch having a single outgoing port and multiple incoming ports.

[0067] In one embodiment, the set of existing connections may be empty. Thus, the NoC will be synthesized from the beginning of the process without existing connections.

[0068] The order in which the connections are implemented affects the quality of the topology. In one embodiment, the order can be determined based on a plurality of mathematical optimization techniques and / or an exhaustive method. For example, the order can be determined by the area of ​​the plan spanned by the connections. In another example, the order can be a latency-based communication strategy configured to measure the delay of a packet arriving at a destination and implement more sensitive connections with a higher priority. Within the scope of the present invention, the synthesis order is an input to a method for deterministic and incremental physical-aware NoC topology synthesis.

[0069] A system configured to automatically generate or synthesize a deadlock-free NoC from a specification includes: a floor plan, which is the physical layout of a chip; technical parameters, including but not limited to wire delays and / or logic density; floor plan areas, including but not limited to module and / or clock constraints; clock domain crossing (CDC), which is the traversal of a signal from a first clock domain to a second clock domain in a synchronous digital circuit; performance requirements; and components, which have a configuration and location on the floor plan, connectivity requirements between the first component and the second component, and a communication strategy between the first component and the second component.

[0070] A method for converting an existing deadlock-free network-on-chip (NoC) configuration (the existing deadlock-free network-on-chip configuration includes a plurality of existing physical segments and an existing set of turns allowed between the segments), the plurality of existing physical segments and the existing set of turns forming a plurality of existing routes. The method includes generating a new NoC configuration by generating and / or synthesizing at least one new connection into the existing deadlock-free network-on-chip configuration, the first new connection having a source and a destination, the generating creating a first new deadlock-free route from the source to the destination, so that the new network-on-chip configuration is deadlock-free, and wherein the generating of the first new deadlock-free route from the source to the destination preserves the existing route.

[0071] The generating includes: for each existing route, converting the route into segments and turns; identifying one or more new connections for integration, each of the multiple new connections having an undefined route, a source, and a destination associated therewith, the one or more new connections being identified together in an integrated order; for each of the one or more new connections, and based on the ordering, identifying multiple possible routes from the source to the destination for the new connection.

[0072] Possible routes include one or more of the following: a new ingress segment connecting a source to an existing deadlock-free NoC configuration; a new egress segment connecting an existing deadlock-free NoC network-on-chip configuration to a destination; one or more new internal segments connecting existing segments of an existing deadlock-free network-on-chip configuration, such that one or more new internal segments connect the source to the destination, where the new internal segments are not considered if they create a circular dependency between the segments, thereby causing a deadlock; and existing segments only.

[0073] Filtering multiple possible routes based on one or more criteria, including: a communication policy criterion based on an allowed delay for a route from a source to a newly connected destination; any of multiple user-defined criteria; selecting one of the multiple possible routes for synthesis; and / or synthesizing the selected possible route into an existing deadlock-free on-chip network configuration.

[0074] According to one or more embodiments of the invention, the first new deadlock-free route includes at least one of an existing physical segment and a new physical segment.

[0075] According to one or more embodiments of the invention, generating a first new deadlock-free route from a source to a destination preserves all existing routes.

[0076] According to one or more embodiments of the invention, new deadlock-free routes are generated incrementally and repeatedly.

[0077] According to one or more embodiments of the invention, identifying the comprehensive order includes ordering the one or more new connections according to an exhaustive method.

[0078] According to one or more embodiments of the invention, at least a portion of an existing segment is physically immutable.

[0079] According to one or more embodiments of the present invention, an endpoint of at least one portion of the existing segment is a switch. The switch is physically immutable.

[0080] According to one or more embodiments of the invention, any component is logically changeable, which causes at least one existing component to be reconfigured in response to a newly generated topology.

[0081] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes use of an existing deadlock-free network-on-chip configuration, wherein the existing segments are physically immutable except for an ingress segment and an egress segment, the switches are physically immutable, and at least one network element is logically immutable.

[0082] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that minimizes routing delay.

[0083] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes use of an existing deadlock-free network-on-chip configuration, wherein existing segments are physically immutable, switches are allowed to have new connections, and existing network elements are logically immutable, including keeping clock frequencies and other properties unchanged.

[0084] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting when existing segments are not physically immutable, switches are allowed to have new connections, and existing network elements are reconfigurable.

[0085] A method for incremental synthesis and transformation of a deadlock-free on-chip network topology includes receiving an input that is a network topology, transforming the network topology into an existing segment, reusing the existing segment in a new route, the existing segment being formed by a path between a first node and a second node, recursively splitting the existing segment along the path between the first node and the second node at an arbitrary geographic point to form a split segment, synthesizing a new route by adding a new segment and a new turn to the split segment in response to the split, and generating a deadlock-free on-chip network topology by routing packets from the turn of the existing segment to the new segment, thereby avoiding deadlock in the network.

[0086] According to one or more embodiments of the invention, identifying the comprehensive order includes ordering the one or more new connections according to an exhaustive method.

[0087] According to one or more embodiments of the invention, at least a portion of an existing segment is physically immutable.

[0088] According to one or more embodiments of the present invention, at least a portion of the endpoints of the existing segments are switches. The switches are physically immutable.

[0089] According to one or more embodiments of the invention, any component is logic-changeable, which causes at least one existing component to be reconfigured in response to a newly generated topology.

[0090] A non-transitory computer readable medium for storing code, which when executed by one or more processors will cause the processor to: receive an input topology of a network on chip (NoC) to determine a source-destination pair selected for synthesis and at least one existing connection; transcribe the source-destination pair into a pair of segments; transcribe the at least one existing connection into a pair of existing segments; determine whether the NoC is deadlock-free; in response to determining that if the NoC is deadlock-free, extract the pair of segments that do not have a defined route and sort them using an exhaustive method; input the pair of segments and the pair of existing segments into a configuration browser, and the configuration browser uses a communication strategy to determine the pair of segments; A configuration for a route from a source to a destination of a source-destination pair is determined, the communication strategy is configured to receive user-defined parameters related to the source-destination pair, the communication strategy communicates with a configuration filtering module, and the configuration filtering module is configured to output a configuration that meets the conditions; using a configuration selection module, a final configuration to be implemented is selected for connecting the source-destination pair; separating the pair of existing segments, which need to be connected to the pair of segments at a point specified by the final configuration; creating a new segment specified by the final configuration; activating a corresponding turn, which connects the pair of existing segments with the pair of segments; and calculating a route from the source to the destination of the source-destination pair.

[0091] Reference now Figure 1A , a network on chip (NoC) 100 is shown according to various aspects and embodiments of the present invention. A NoC is an example of a network. According to various aspects and embodiments of the present invention, a network includes a set of nodes and a set of edges, each of which has a model and can be used at a comprehensive core to perform and implement transformations across the network and converge to an optimal solution suitable for a specific requirement. NoC 100 includes nodes and endpoints and uses assembled primary network functions such as: network interface units (NIUs) 102, NIU 104, NIU 106, NIU 108, NIU 110, NIU 112, NIU 130, NIU 132, and NIU 134, nodes / switches 114, nodes / switches 116, nodes / switches 118, nodes / switches 120, and nodes / switches 122; adapters (such as adapter 126); and buffers (such as buffer 124). NoC primary network functions communicate with each other using an internal transmission protocol specific to NoC 100, typically based on packet transmission. The NIU converts the protocol used by an attached system-on-chip (SoC) unit (not shown) to the transport protocol used inside the NoC 100. The switch routes traffic between sources and destinations. Buffers 124 are used to insert pipeline elements to span long distances, or store packets to handle rate adaptation between fast senders and slow receivers, or vice versa. Adapters 126 handle various conversions between data width, clock, and power domains.

[0092] Reference now Figure 1B , showing a NoC 150 with various elements such as NIUs, switches, and blocking areas in a floor plan. NoC 150 includes various connectivity elements through various switches. According to one aspect of the present invention, a set of constraints are used as input to a tool, which will be discussed in more detail below. According to some aspects of the present invention, the tool performs a set of sub-steps and generates a description (synthesis) of a final NoC such as NoC 150 using its configured elements and the location of each element on the floor plan. The generated description is used to actually implement the NoC hardware, using the generated physical information to provide guidance to the back-end implementation process.

[0093] Reference now Figure 2A According to some aspects of the present invention, a set of constraints (210, 212, 214, 216 and scenarios) are provided to a synthesis tool 220. According to some embodiments and aspects of the present invention, the performance and functionality of tool 220 may include third-party ASIC implementation tools, such as logic synthesis, placement and routing back-end tools, etc. A designer or user establishes a set of constraints provided to tool 220. These constraints are captured in a machine-readable form, such as a computer file that captures information using a defined format, which is understood and processed by the tool. According to one aspect of the present invention, the format is XML. According to another aspect of the present invention, the format is JSON. The scope of the present invention is not limited by the specific format used.

[0094] Reference now Figure 2B , the tool reads a file containing a description of the constraints and performs the synthesis process. According to some aspects of the present invention, the synthesis process is broken down into multiple steps. Sequencer 250 is responsible for executing each step of the process. According to some aspects of the present invention, a set of steps is executed by sequencer 250 of tool 220 according to the constraints proposed by the user / designer. The scope of the present invention is not limited by the number and type of steps that sequencer 250 can call and execute.

[0095] Reference again Figure 2A as well as Figure 2BAccording to various aspects of the present invention, a designer of a network provides and defines a set of constraints, such as constraints 210, 212, 214, and 216. Sequencer 250 receives various inputs, including: input 251, which includes a global merged roadmap with connectivity between initiators and targets, including roadmap creation and information between each initiator and target; input 252, which includes service class and master switch creation; input 254, which includes a master switch decomposed into mergers and splitters; input 258, which includes information about the physical distribution of splitters and mergers in the roadmap; input 259, which includes information about edge clustering; and input 260, which includes information about performance-aware node clustering. According to one aspect of the present invention, sequencer 250 also receives input 262 including information about optimization and network reconstruction. According to one aspect of the present invention, sequencer 250 receives 264 including information about routing and legalization. According to various aspects and embodiments of the present invention, sequencer 250 uses all inputs 251-264 to generate a network. According to various aspects and embodiments of the present invention, sequencer 250 generates a network using a combination of inputs 251 - 264 .

[0096] According to various aspects of the invention, input 251 includes input regarding a global merge roadmap. The global merge roadmap includes a merge model that captures a global physical view of the connectivity of the free space of the floor plan, as well as the connectivity between initiators and targets. The global merge roadmap is modeled by a graph of physical nodes and normalized segments used to locate the nodes. The network's (splitters, mergers, switches, adapters) is being built. The global merge roadmap is used to tighten the computation. According to various aspects of the invention, the global merge roadmap is persistent, meaning that it is data that is output and re-consumed by the system in incremental synthesis and subsequent runs.

[0097] According to some aspects of the invention, input 259 includes information about edge clustering. Edge clustering is intended to minimize resources and enhance performance goals through appropriate algorithms and techniques. According to some aspects of the invention, edge clustering is applied in conjunction with input 260 (node ​​clustering) and is applied in cooperation with input 260. Edge clustering and node clustering can be used in combination by mixing, by being applied simultaneously or by being applied sequentially. The advantage and goal is to expand the comprehensive spectrum and span a larger solution space for the network.

[0098] According to various aspects of the invention, input 262 includes information about the reconstruction. Reconstruction includes various transformations and capabilities. According to some aspects of the invention, the transformation is logical because there is a change in the structure of the network. According to some aspects of the invention, the transformation is physical because there is a physical change in the network, such as moving a node to a new location. Other examples of reconstruction include: splitting a node into smaller nodes; reparenting between nodes; duplication of sub-sections of the network to avoid deadlock and deal with congestion; and physically rerouting links to avoid congested areas or meet timing constraints.

[0099] Reference now Figure 3 , according to various aspects of the present invention, a floor plan 300 of a chip on which a NoC is implemented is shown, with locations for various initiator interfaces and target interfaces. Physical constraints 210 provide physical information about the design, including: the size of the chip on which the NoC will be implemented; various blockages on the floor plan, which are rectangles representing areas of the chip on which NoC logic cannot exist or be placed; free space, which is an area in the chip where NoC logic exists and is defined by areas not covered by blockers; and the locations of interfaces between SoC units and the NoC, which are the locations of initiator interfaces and target interfaces (such as NIUs).

[0100] According to various aspects of the present invention, another constraint may also be provided that includes the extension of clock domains and power domains 212. Domains 212 include areas of the chip in which logic belonging to a particular domain is allowed to be placed.

[0101] According to various aspects of the present invention, the capabilities of the logic library to be used to implement the NoC are provided. The information includes the size of the reference logic gates, and the time it takes for the signal to cover a distance of 1 mm.

[0102] Reference again Figure 2A According to various aspects of the present invention, the SoC includes multiple clock domains and multiple power domains. The clock domain is defined by all logic fed by a given clock input. The clock input is characterized by the frequency of the clock, which is the most important parameter of the clock input. The power domain is defined by all logic that obtains power from the same power supply. According to various aspects of the present invention, the power supply is gated, so that the power domain can be turned on or off, or isolated from other power domains. In this way, the designer provides a set of clock domain and power domain constraints 212 as part of the initial design.

[0103] According to various aspects of the present invention, initiators and targets are communicatively connected to NoC. An initiator is a unit that sends requests (usually read and write commands). A target is a unit that serves or responds to requests (usually read and write commands). Each initiator is attached to or connected to NoC via an NIU. The NIU attached to the initiator is called an initiator network interface unit (INIU). In addition, each target is connected to NoC via an NIU. The NIU connected to the target is called a target network interface unit (TNIU). The main function of NoC is to transmit each request from the initiator to the desired destination target, and if the request requires or needs a response, the NoC transmits the response of each target to the corresponding request initiator. Initiators and targets have many different parameters that characterize them. According to various aspects of the present invention, for each initiator and target, the clock domain and power domain to which they belong are defined. The width of the data bus they use to send write and receive read payloads is multiple bits. According to various aspects of the present invention, the width of the data bus for the connection (communication path to / from the target) for sending write requests and receiving write responses is also defined. Additionally, the clock and power domain definitions are references to the previously described clock and power domains that exist in the SOC.

[0104] continue Figure 2A and Figure 2B And also refer to Figure 4 , a connectivity table 400 is shown. According to various aspects of the present invention, table 400 allows services to be defined by classification. The tool allows the use of service class labels for each connection between an initiator and a target. As shown in table 400, there are three service classes: L1, L2, and L3. The service class label is an arbitrary label selected by the user or designer. Any number of labels can be defined, and the scope of the present invention is not limited by the number of labels. The present invention will assign a different subnetwork to each label, which can be physically different or use virtual networks - if the underlying NoC technology supports it.

[0105] According to various aspects of the present invention, an initiator need not be able to send requests to all or multiple targets connected to the NoC. The precise definition of the targets that can receive requests from the initiator is outlined or set forth in a connectivity table such as table 400. The connectivity and service class labeling information can be represented as a matrix. Each initiator has a row and each target has a column. If the initiator must be able to send services to the target, the service class label must appear at the intersection between the initiator row and the target column. If there is no label at the intersection, the tool does not require connectivity between the initiator and the target. For example, initiator 1 (M1) communicates with target 1 (S1) using a defined label 1 (L1) connectedly, while M1 does not communicate with S2, so there is no label in the intersection of M1 and S2. According to various aspects of the present invention, as long as each pair of initiator-target combinations has a precise definition of its service class, the actual format used to represent connectivity can be different, or there is no classification label if there is no connectivity.

[0106] Reference now Figure 5 , a table 500 is shown including various scenarios for read (RD) and write (WR) transactions according to various aspects of the present invention. Figure 2A ). Table 500 includes information defining the various throughput rates provided to the tool. The scenarios define the expected performance in terms of data throughput between the initiator and the target. Each scenario describes the expected required read bandwidth and the expected required write bandwidth between each initiator and each target. Throughput is defined in bytes / second (B / s). A typical SoC will have multiple operating modes. For example, a SoC for a smartphone may have a gaming operating mode, an audio call operating mode, an idle operating mode, etc. These define scenarios that depend on different throughput rates. Therefore, a set of scenarios represents the different operating modes supported by the SoC, and accordingly, represents the expected NoC minimum performance in terms of throughput between the initiator and the target.

[0107] The scenario can be represented as 2 matrices, one defining the read throughput and one defining the write throughput. According to various aspects of the present invention, the read throughput requirement will be used to adjust the size of the response network, which handles the data returned from the target to the initiator. According to various aspects of the present invention, the write throughput requirement will be used to adjust the size of the request network, which is the data from the initiator to the target. According to various aspects of the present invention, examples of throughput requirements for various scenarios are shown in Table 500. The actual format used to represent the scenario can be different, as long as each pair (initiator, target) has a precise definition of the minimum throughput required for its reads and writes. In Table 500, a read transaction from M1 to S1 has a minimum performance throughput of 100MB / s. In Table 500, a write transaction from M1 to S1 has a minimum throughput of 50MB / s.

[0108] According to some aspects of the invention, scenarios are not defined for the tool, in which case the tool optimizes the NoC synthesis process for physical cost (eg, lowest gate cost and / or lowest wire cost).

[0109] Reference now Figure 6 as well as Figure 2B , an initial network 600 is created according to various aspects of the present invention. The network 600 implements a connectivity matrix with the following defined parameters or components:

[0110] One network interface unit per initiator,

[0111] One network interface unit per target,

[0112] · Create a switch for each defined service class, called the master switch for that class.

[0113] A switch after each initiator / initiator NIU that distributes traffic to different master switches that the initiator needs to reach,

[0114] A switch before each destination / target NIU that merges traffic from different master switches that are sending traffic to that destination

[0115] The data width of each switch, and the clock domain it belongs to, is calculated using the data width of each attached interface, and their clock domain as input to the tool. According to various aspects of the invention, each step of transforming a network that is part of a NoC also performs calculations of the data width and clock domain of the newly created network elements.

[0116] Reference now Figure 7 and Figure 2B , showing Figure 6 A network 600, wherein the tool process transforms the network 600 according to various aspects of the present invention. The sequencer 250 has an input 254 representing the decomposition of a master switch into a combiner and a splitter. The tool decomposes each master switch of the network 600 into its equivalent implementation having a splitter and a combiner. According to various aspects of the present invention, some switches have a single inlet port and multiple egress ports. According to various aspects of the present invention, some switches have multiple inlet ports and a single egress port. Each master switch inlet port is connected to a splitter, and each master switch egress port is connected to a combiner. For the master switches, the splitters and combiners are connected together according to a connection table.

[0117] Reference now Figure 8, a floor plan 800 is shown according to various aspects of the present invention. The sequencer 250 has an input 256 representing the creation of a roadmap between each initiator and a target. The floor plan 800 includes physical paths 802 calculated between an initiator interface (M0) on the floor plan and each of its connected targets (e.g., target S0, target S1, target S2, and target S3). Paths 802 are referred to as the splitter roadmap of initiator M0; although not shown, each initiator will have a splitter roadmap. The tool uses any algorithm suitable for finding a path between a source point and multiple destination points, including an algorithm that minimizes the length of the path.

[0118] Reference now Fig. 9 , the floor plan 800 has a physical path 902 calculated between the target interface for the target S0 on the floor plan and each of its connected initiators. Path 902 is a merged roadmap for the target S0. Obviously, each target will have a merged roadmap. The tool uses any algorithm suitable for finding paths between multiple source and destination points, including algorithms that minimize path lengths. According to various aspects of the present invention, the tool transforms the network in a manner that maintains its functionality and adds location information to network elements.

[0119] Reference now Fig.10 , the floor plan 800 shows a path 1002 according to various aspects of the present invention. The sequencer 250 has an input 258 that provides the physical distribution of splitters and mergers on the roadmap. Using this tool, each switch is decomposed into mergers and splitters. Using this tool, each splitter in the main switch is further decomposed into a cascade of splitters, and each splitter of the cascade is placed at a branch point of the splitter roadmap of the attached initiator. The branch point of the roadmap is defined by the fact that the path is divided into two or more branches.

[0120] Reference now Fig.11, the plan view 800 shows a path 1102 according to various aspects of the present invention. Using the tool, for each switch of each combiner in the main switch, the combiner is further decomposed into a cascade of combiners, each combiner of the cascade being placed at a branch point of the merged roadmap of the attached target. The branch point of the roadmap is defined by the fact that the path is divided into two or more branches. The process of decomposing the splitters in the splitter cascade retains the original splitter functionality, because the number of inputs to the cascade is still one, and the number of outputs of the cascade is the same as the number of outputs of the original splitter. The process of decomposing the combiners in the combiner cascade retains the original combiner functionality, because the number of outputs of the cascade is still one, and the number of inputs of the cascade is the same as the number of inputs of the original combiner. According to various aspects of the present invention, the effect of the process is to obtain a set of basic switches, represented by combiners and splitters, physically placed close to where actual connections are required between switches.

[0121] According to various aspects of the invention, the tool transforms the network to reduce the number of wires used between switches that can be realized while maintaining performance as defined in the scenario, which is a set of minimum throughputs required between initiators and targets. According to various aspects of the invention, switches are clustered for performance-aware switching, and mergers and splitters that have been distributed on a roadmap are treated similar to ordinary switches.

[0122] According to one aspect of the invention, the tool uses an iterative process and will merge switches while performance is still satisfied until no further switch merging can occur. The tool uses the process described below:

[0123] 1) Although switch convergence is no longer possible, do the following:

[0124] a) Select a candidate switch for fusion with one of its neighbors. The selection process ensures that all switches in the network are ultimately candidate switches.

[0125] b) When a candidate is selected, search for neighbors to merge with it. The neighbor criteria is based on the evaluation of a cost function. The cost function should return the switch that is "best fit" to merge with the candidate. The definition of "best fit" is implementation dependent, but the cost function should be such that the potential fusion of the two switches maximizes the gain in at least one metric including: line length; logic area; power; performance, etc.

[0126] c) In the event that convergence occurs, test whether the performance scenario will still meet the minimum throughput requirement. If not, the two switches cannot be merged. The process performed by the tool searches for another neighbor until no more neighbors can be found, in which case all switches remain intact, or one neighbor is found that can be merged with the candidate switch without violating the minimum throughput requirement for all cases, in which case the network is modified by merging the candidate switch with the neighbor.

[0127] According to various aspects of the invention, this process makes it possible to ensure that a switch does not grow beyond a certain size (maximum number of ingress ports, maximum number of egress ports). If the combined switches are above a set threshold, merging is prevented.

[0128] Reference now Fig.12 , a candidate switch SW3 is shown next to switch SW4 for a combiner in accordance with various aspects of the present invention. The sequencer 250 has an input 260 that provides performance-aware switch clustering. The tool performs a process for merging two switches. When switches are merged, wires from different switches are simplified to one wire from each connected switch to the combined switch. In accordance with various aspects of the present invention, switches SW3 and SW4 are merged. The connections between SW1 and SW4 and SW3 are combined and replaced by a single connection between SW1 and SW3_4. Thus, long connections between far switches are removed and reduced to a minimum, while connections between near switches are removed and completed within the switches themselves.

[0129] Reference again Figure 2B , the input 262 of the sequencer 250 includes various optimizations that can be performed to further reduce the number of wires used by the network, the area of ​​the network elements, and the power consumed by the network elements. Examples of such optimizations include: detecting links that can be removed due to unuse, or their traffic can be rerouted; reducing the width of the link if it is wider than the scenario requires; and performing wiring length optimization by finding the best arrangement of all switch elements that minimizes the total wiring length of the network, where the total wiring length of the network is the sum of the distance spanned by each connection between network elements multiplied by the width of the connection.

[0130] continue Figure 2B, the input 264 of the sequencer 250 includes generating a legal NoC by modifying the position of the network elements so that the network elements fit into the allocated free space and do not overlap, and they exist within the corresponding clock and power domain constraints. According to various aspects of the present invention, the area occupied by each network element on the die is calculated using the information provided about the technical capabilities, such as the area of ​​the reference logic gates. The correctness of the placement of each element is then tested (there is enough free space for the element and no other elements overlap). If the test fails, the element is moved until an appropriate position is found where the test passes.

[0131] Formal system

[0132] Reference now Fig.13 , the floor plan 1300 shows a deadlock-free NoC, which can be represented by multiple segments and turns. A segment represents a directional channel between two components, such as "A" 1311 and "B" 1301, "B" 1301 and "C" 1302, "C" 1302 and "D" 1303, and / or "D" 1303 and "A" 1311. The first segment 1304 holds the physical path between "A" 1311 and "B" 1301 in the floor plan, the second segment 1305 holds the physical path between "B" 1301 and "C" 1302 in the floor plan, the third segment 1306 holds the physical path between "C" 1302 and "D" 1303 in the floor plan, and the fourth segment 1307 holds the physical path between "D" 1303 and "A" 1311 in the floor plan, which is the physical coordinate (x i ,y i ). Within the scope of the present invention, a segment has one or more associated cost metrics that can be used during synthesis and / or generation to track the cost of certain routes.

[0133] Turns as a pair of segments can be used in a way to avoid deadlock in the network. Given the allowed turns 1308, turns 1309 and turns 1310, the network remains deadlock-free as long as there is no cycle between the segments. According to another aspect or embodiment of the present invention, loops can exist between nodes. Turns have dependencies between segments, which is a basic mechanism to ensure that the network is deadlock-free. Within the scope of the present invention, there are cycles between nodes to reuse lines without causing deadlock, thereby only allocating necessary channels to prevent node cycles. As a result, this eliminates unnecessary channels and reduces the associated wiring costs associated with it.

[0134] Reference again Fig.13, the presence of a first turn 1308 from the first segment 1304 to the second segment 1305 indicates that the packet can be routed from the first segment 1304 to the second segment 1305. The presence of a second turn 1309 from the second segment 1305 to the third segment 1306 indicates that the packet can be routed from the second segment 1305 to the third segment 1306. The presence of a third turn 1310 from the third segment 1306 to the fourth segment 1307 indicates that the packet can be routed from the third segment 1306 to the fourth segment 1307. With respect to segment separation, the segments "S1" to "S2" can be routed at any point in their physical routing (x i ,y i ), resulting in two new segments. When the turn (D, A) approaches (A, B) without existence, the network is deadlock-free.

[0135] Reference now Figures 14A-14D , showing an embodiment of segment separation on NoC 1400. Segment 1403 ( Fig.14A ) is defined by node "A" 1401 to node "B" 1402. Segment 1403 can be at any point in its physical route (x i ,y i ) was separated at 1404( Fig.14A ) into the new first segment 1409A ( Figure 14B-Figure 14D ) and the new second subsection 1409B ( Figure 14B-Figure 14D ). Figure 14B-Figure 14D This separation is best described by Fig.14A ) results in a newly created node "S" 1408 ( Figure 14B-Figure 14D ). The first turn 1405 and the second turn 1406 are shown. Figure 14B-Figure 14D ) and the third turn 1407.

[0136] Fig. 14B Illustrated is a segment separation of a NoC topology, where a split segment "A" 1401 to "B" 1402 is updated to use two new sub-segments "A" 1401 to "S" 1408 and "S" 1408 to "B" 1402. The newly created node "S" 1408 is a new switch in the NoC. A set of turns involving the split segment is updated to use the two new sub-segments. A new turn 1406 is added while turn 1407 is retained.

[0137] A segment that has been separated is no longer considered "as is" because the separation has produced a sub-segment with a variable route. This recursive representation is necessary for the increment because it ensures that when an existing route is reconstructed, a segment that was part of the existing route and may need to be separated can still be recovered as a series of sub-segments. Separating a segment allows the segment to be connected to a new segment. This results in a new set of turns.

[0138] Fig. 14C Depicted is a new segment 1411 represented by the channel between node “N” 1410 and node “S” 1408 being merged into the split segment, resulting in a new turn 1412 .

[0139] Fig.14D A new segment 1413 represented by the channel between node "N" 1410 and node "S" 1408 is depicted being forked into the split segment, resulting in a new turn 1414. The added node "N" 1410 may include, but is not limited to, an IP block and / or an initiator.

[0140] According to one aspect and embodiment of the present invention, the system performs a generation and synthesis process, and all existing network routes are converted into segments and turns. In an embodiment, the entire NoC is described as a set of at least one segment defined by a physical path between two nodes (S, D), for example. According to various aspects and embodiments of the present invention, if the network is not deadlock-free, the system provides a "failure" notification and returns it to the user, because according to one or more aspects of the present invention, the network or NoC must initially be deadlock-free. The system also extracts a set of connections that do not have defined routes and / or connections that need to be synthesized. Given a heuristic, the extracted connection sets are sorted. According to various aspects and embodiments of the present invention, for each connection source "S" to a destination "D", a single connection synthesis process involves using a configuration browser, a configuration filtering module, a configuration selection module, segmentation, creation, and routing calculation. Each of the newly created components, switches, and links is configured by assigning clock domains and data width settings so that bandwidth requirements are met.

[0141] Fig.15 1503A may be a new connection 1501 and / or an input 1503B may be an existing segment 1502. The new connection 1501 includes creating new components, such as switches and / or links, that define a network route from "S" to "D". The existing segment 1502 may be re-represented as at least one segment and / or a pair of segments with at least one turn. The existing network has a set of turns that cannot be changed. When a new segment is added, a turn associated with the newly added segment is also added to complete the route from "S" to "D". The added turn does not create a loop and / or deadlock with the existing turn.

[0142] The configuration browser 1504 receives input 1503A as a new connection 1501 and input 1503B as an existing segment 1502. Since there are multiple ways to connect to segment "S" to "D", the configuration browser 1504 affects the best configuration based on each segment being assigned a communication strategy 1506. The configuration browser 1504 uses an exploration of legal configurations 1505 to explore different ways to connect "S" to "D". Legal configurations 1505 are lists of described parameters. The configuration browser 1504 is configured to explore and / or view and analyze at least one configuration indicating the possibility of splitting the location of the segment (traversing the segment) from a list of meaningful configurations stored in memory. The configuration browser 1504 can have a configuration with a new entry segment for connecting "S" to a segment of the NoC. If "S" is already connected, it already has an entry segment. The configuration browser 1504 can have a configuration with a new exit segment for connection.

[0143] The cost of a given path is updated at each step according to the communication strategy 1506. In an example, moving away from a destination within an existing segment may cost more or less than creating a new segment that goes directly to the destination, depending on whether the communication strategy 1506 favors wire length and / or latency. It is within the scope of the present invention to have a complete shortest path algorithm that uses cost updates as a way to efficiently implement several communication strategies to both explore specific segments and identify potential future segments.

[0144] The main configuration exploration process 1504 can be designed as a specialized version of a public shortest path algorithm including, but not limited to, A* and / or Dijkstra. A given step in the shortest path algorithm considers different points that can be reached from the current point. The current point is at least one point along the physical path of the existing segment. The path from the current point in the current segment to the subsequent point is considered.

[0145] In an embodiment, the path may advance one step along the path of the current segment. In an embodiment, if the end of the path of the segment has been reached, the path may advance to the first point in the path of any of the next segments (such as a segment that is directly connected to the current segment and to which the current segment can "turn").

[0146] In an embodiment, if the destination is not connected (such as if no exit segment exists), the path can jump directly to the destination point. This corresponds to creating a new exit segment. Then, new and / or future exit segments are added to the configuration.

[0147] In yet another embodiment, the path can jump to any point of any segment as long as no circular dependency is created, the two segments have compatible communication policies and the communication policies allow the merge. This corresponds to creating a new internal segment, which is added to the configuration.

[0148] Refer to Fig.15 , the configuration filtering module 1507 has a predetermined list containing data, including but not limited to which configurations are legal, which configurations cause deadlocks, and which configurations are not optimal. The configuration filtering module 1507 filters the configurations given multiple criteria and only keeps a subset, and the multiple criteria include but are not limited to the criteria based on the communication strategy 1506 and / or any custom criteria. In an example of a custom criterion, a user (such as a programmer) can make the parameter based on a low latency defined by a shorter length between routes from "S" to "D". The user can define the maximum length of the path. If the length of the path exceeds a user-defined threshold, the configuration filtering module 1507 of the communication strategy 1506 will remove the route. In another example, the parameter can be based on the use of the minimum number of additional wires. In another example, the parameter can be based on a cost function that favors the route from "S" to "D" to have the lowest cost. The configuration filtering module 1507 can be customized for user-defined parameters in advance. Users can set their own filters and discard certain types of configurations.

[0149] The first criterion is a criterion based on communication policy 1506. The user can control the way to create a new segment. Communication policy 1506 is a set of parameters that can be associated with any given connection in the network. The system can have multiple communication policies defined, and each connection can be associated with a communication policy 1506. Communication policy 1506 has parameters and flags. In the example of the flag, low latency is when the connection should be implemented in a way that minimizes the total path length from the source to the destination. In another example of the flag, enabling serialization is when the links involved in the path from the source to the destination are allowed to adopt serialization to save wires. Some configurations of a given connection may be illegal relative to the communication policy 1506 that manages the connection. Qualified configuration 1508 is a filtered version of a legal configuration. In the example, if the connection "S" to "D" is set to have a low latency communication policy, restrictions on the total length and number of hops or components traversed on the route must be applied, and configuration candidates that do not fall within these restrictions are discarded.

[0150] Refer to Fig.15, after filtering, the configuration filtering module 1507 outputs a qualified configuration 1508. It is desirable to select a qualified configuration performed by the configuration selection module 1509. The best configuration selection is implemented using the configuration selection module 1509, which retains only one final configuration implemented as the final synthesis of connecting "S" to "D". The metric used to select the best configuration is configurable and several parameters can be considered based on the communication strategy 1506. In an embodiment, the communication strategy parameter is the total additional wire length. The length of the additionally created segments creates the wires required to traverse the route. There is a cost associated with the wire. It should be more desirable that the parameter aims to minimize the total wire length to reduce the topological cost. In an embodiment, the communication strategy parameter is the total route length. The total route length is the sum of the existing segments plus the combination of the newly added segments. This parameter focuses on minimizing latency. In another embodiment, the communication strategy parameter is based on bandwidth distribution. This parameter optimizes performance by focusing on the traffic distribution on the segments and the associated congestion level.

[0151] Once the best configuration 1510 is selected, the system will implement 1511 the best configuration 1510 by splitting the segments involved and creating 1512 new segments and turns, and apply it to the network. It is within the scope of the present invention that the best configuration is the final configuration. When splitting a segment, it will be split at all existing segments that need to be connected to the new segment at the point specified by the selected configuration. Regarding optimization, if the split point is within a certain distance from one of the endpoints of the segment and the endpoint is a switch, the endpoint should be reused for connection instead of creating a new switch. This can reduce the number of switches created. Create 1512 the required new segments specified by the selected configuration and activate the corresponding turns. The combination of the newly created 1512 segments and turns with the existing 1502 segments and turns is input into the routing tool 1513 that generates the final route 1514. Given the newly created segment, the route from "S" to "D" is calculated. The route is stored in the memory. Routing tool 1513 is a routing connection on a geographical floorplan, as segments are defined in terms of their geographical paths following the floorplan.

[0152] Fig.16A A NoC topology on a floorplan is shown with node "S" 1601 to node "D" 1602. If there is an existing network and a change is requested (such as a request to add a new connection from node "S" 1601 to node "D" 1602), incremental synthesis will need to be performed. IP blocks are examples of restrictions on floorplans that require routing to navigate around. Existing nodes are connected to each other. It is desirable to create routes for new connections in the existing network without having to make changes to the existing structure.

[0153] Fig. 16BThe NoC topology on the floorplan is illustrated with the incremental synthesis result of the routing configuration from "S" 1601 to "D" 1602, with a new ingress segment 1603 having node "S" 1601 and node "D" 1606, a new internal segment 1604 having a node, and an egress segment 1605. Fig. 16B The exploration of legal configurations 1505 is shown in the configuration illustrated in , where if the node is not already connected to the NoC, an ingress segment 1603 is added. In an embodiment, the new ingress segment 1603 can connect "S" 1601 to the segment of the NoC. If "S" 1601 is already connected to the segment of the NoC, it already has an ingress segment.

[0154] exist Fig. 16B In the illustration of , egress segment 1605 is existing because "D" is already connected to another node. Therefore, if "D" is already connected, it already has an egress segment. A new egress segment can be a configuration option for connecting a segment of the NoC to "D".

[0155] Refer to Fig. 16B , it is within the scope of the present invention that there are any number of internal segments 1604. At least one and / or more new internal segments may connect existing segments such that the ingress segment reaches the egress segment. A connection between two existing segments is only considered if it does not create a circular dependency between the segments, thereby ensuring that only deadlock-free configurations are considered. The synthesis may include calculating network routes without creating any new switches and / or segments. This is the case if both "S" and "D" are connected to the network and the ingress segment can already reach the egress segment given only the existing turns. An important aspect of the present invention is that the configuration may define future segments, whereby no specific segments are created in the topology during the exploration phase.

[0156] In an embodiment, the system may pre-set multiple common communication strategies to make it easier for the user to make a selection. It is more desirable that the user picks from a pre-set list rather than requiring the user to create a communication strategy. Connections associated with different communication strategies will have physically separate integrated routes. During integration, the configuration filter module 1507 ( Fig.15 ) and configuration selection module 1509 ( Fig.15 ) depends on communication policy 1506 ( Fig.15 ) to output the optimal configuration 1510 for implementing 1511 routing.

[0157] Fig.17A A NoC topology on a floorplan is illustrated with a communication strategy 1700 to optimize wire length with best effort performance. Fig.17A and Fig. 17BIt shows how the same connection can result in different implementations based on the chosen communication strategy. Fig.17A In the illustration of FIG. 1704 , the focus is on connecting node “S” to node “D”, and the parameter of wire length is the main criterion for optimization. The configuration selection module selects the implementation that creates the least additional wire. It is shown that the parameter requirements are met with a short entrance segment 1703 and one turn 1704 activated.

[0158] Fig. 17B A NoC topology on a floorplan is illustrated with a communication strategy 1710 to be used for low-latency communication. In this example, there is a preference for a direct connection 1713 between node "S" 1711 and node "D" 1712, rather than across several switches. One turn 1714 activated is near "D". Although this configuration creates more additional wires and is more costly, it is the path from "S" to "D" that the user chooses to have the shortest length.

[0159] exist Figures 1A to 17B The basic method of incrementally synthesizing new connections while reusing existing segments is best shown in Figures 20 to 33 Additional features are shown in . According to some embodiments, the tool splits existing segments to fork new segments. At the end of the process, only the newly created components (such as clock and / or data width) are configured, and existing components remain unchanged. Fig.15 , changing existing segments and turns 1502 at incremental levels through user control. The user utilizes communication policies 1506 to control not only the creation and selection of new segments in the network, but also to modify existing topologies or segments. In the example, it may not be desirable to reuse existing segments in new routes due to performance considerations or previous optimizations that the user may have implemented and depend on the segments remaining unchanged. When splitting segments, jumps may be added to traverse multiple routes, which may not be the desired result. As a result, the system defines multiple incremental levels or patterns based on the physical volatility of the segments, the physical volatility of the switches, and the logical volatility of the network elements. It is more desirable to capture the user's intent when synthesizing a new set of connections in the presence of an existing NoC topology.

[0160] In an alternative embodiment, the incremental synthesis mode allows the user to customize how the existing topology is changed.

[0161] Regarding the physical volatility of a segment, by default a segment is volatile. A segment can be split to fork out a new segment. For example, if it is not expected to add a switch to an existing route, the user can make a segment non-volatile.

[0162] Referring to the physical volatility of a switch, if an existing endpoint of a non-volatile segment is a switch, a new segment can be connected to that endpoint. If it is not desired to modify the physical size of the switch, the switch can be non-volatile so that no new segments can be connected to the non-volatile switch.

[0163] Referring now to the logic volatility of network elements, by default, existing network elements are not reconfigured through the incremental synthesis process, including but not limited to data width and / or assigned clocks. Only newly created switches and adapters are configured. This may result in inefficient configurations, such as insufficient bandwidth and / or too many clock domain crossings. Any component can be marked as logic volatile to allow existing components to be reconfigured given the resulting new topology. In an example of how pre-set incremental synthesis modes can be defined in a system based on the aforementioned concepts, three pre-set modes are discussed.

[0164] Fig.18A The incremental synthesis mode 1800 for the initial setup of a segment connecting from node "S" 1801 to node "D" 1802 is illustrated. The high bandwidth segment 1803 and the low bandwidth segment 1804 traverse the existing NoC topology route. During the initial setup, the user parameters will determine how to change the existing topology to connect "S" 1801 to "D" 1802.

[0165] Fig.18B An incremental synthesis pattern 1810 for physical mutability of segments with minimally changing parameters is illustrated. Segments are split 1811 to fork 1812 new segments and create U-turns in a deadlock-free network to connect "S" 1801 to "D" 1802 with minimal changes. High bandwidth segments 1803 are unchanged to prevent splitting, and low bandwidth segments 1804 are routed around traversing existing NoC topology routing.

[0166] It is more desirable to preserve the maximum amount of existing topology. Make all segments physically non-volatile, except for the ingress and egress segments, because the ingress and egress segments are required to implement new connections. All switches are physically non-volatile, and all network elements are logically non-volatile. In the example, if one segment from "S" 1801 to "D" 1802 is marked as non-volatile, it will prevent the splitting of the segment and facilitate routing around the existing segments. As a result, the existing segments remain unchanged.

[0167] Fig. 18CAn incremental synthesis pattern 1820 for logical immutability of a segment is illustrated, with parameters being optimized topology and preserved configuration. A low bandwidth 1804 segment is split 1821 and a new segment 1822 is forked, and a new turn is created to connect "S" 1801 to "D" 1802. The high bandwidth is not fully utilized because it is connected to a lower bandwidth and the switch cannot be changed. It would be more desirable to change some switches to adapt. This pre-setting allows existing segments to be split and allows switches to have new connections for a more optimized topology. As a result, better costs can be achieved by reusing existing elements. Existing network element logic can be made immutable to keep, for example, clock frequency, clocks assigned to switches, and / or other attributes unchanged.

[0168] Fig.18D An incremental synthesis mode 1830 for flexibility of network elements with optimized topology and adapted configured parameters is illustrated. A high bandwidth 1803 segment is split 1831 and a new segment 1832 is forked, and a new turn is created to connect "S" 1801 to "D" 1802. The high bandwidth is fully utilized because it is connected to a higher bandwidth and because the switch is changed. Greater flexibility in the synthesis process is achieved when all segments can be split, switches can be connected to new segments, and / or components can be reconfigured if they improve the results (e.g., when changing the clock to improve performance).

[0169] Fig.19 The process of NoC synthesis based on a mesh custom subnetwork description is illustrated. First, mesh segments are generated and optimally physically placed on the requested space. Second, the new mesh segments, now treated as pre-existing segments by the incremental synthesis process, are used in a timely manner when appropriate to generate the final routes. The result is a topology that mixes the automatically generated regular mesh topology with the new optimal synthesized segmentation. In a fully connected system, the NoC 1900 has each node 1901 connected to every other node. The area 1902 is specified for the 3×3 grid using the XY routing algorithm. As a result of the synthesis process 1903, the NoC 1905 uses the requested mesh segmentation and the newly synthesized segmentation. The automatically synthesized local tree 1904 is shown. The mesh is generated and optimally placed within the specified area 1906.

[0170] According to other aspects of the invention, an extension of the clock and power domains on the layout plan is provided, and each component is tested to ensure that it is within the boundaries of the specified clock and power domains. If the test fails, the component is moved until a suitable position is found for the test to pass. Once the suitable position for each component is found, the routing of each connection between the components is completed. The routing process will find the appropriate path for the set of wires that form the connections between the components. After the routing is completed, if necessary, based on how long it takes for the signal to cover a distance of 1mm, using the information provided about the technical capabilities, a cross-distance pipeline element is inserted on the link.

[0171] According to some aspects and embodiments of the present invention, the tool generates one or more computer files describing the generated NoC, the computer files comprising:

[0172] List of network elements and their configuration: data width, clock domain.

[0173] The location of each network element on the generated floorplan.

[0174] A collection of routes through network elements that implement a connection.

[0175] According to aspects of the invention, a route is an ordered list of network elements, one for each (initiator, target) pair and one for each (target, initiator) pair. A route indicates how traffic between pairs will flow and through which elements.

[0176] According to various aspects of the invention, the tool is used to generate metrics about the generated NoC such as: histogram of wire length distribution, number of switches, histogram of switch sizes.

[0177] Now refer to Figure 20 to Figure 25 , according to various aspects of the present invention, the tool automatically assigns clock and data widths to each of the network nodes such that all input constraints (performance, physical clock area, etc.) are met.

[0178] According to various aspects of the invention, the tool is capable of selecting clock and data widths for network parameters from a range of clock speeds and data widths selected in accordance with input constraints. Thus, the automatic selection includes using feedback to improve the machine learning model that makes the selection through artificial intelligence.

[0179] The various inputs 2000 are provided to the tool's checker 2010. At step 2020, the checker 2010 determines whether the current configuration is legal. The analysis performed by the checker is outlined herein and includes looking at constraints and parameters to ensure that the configuration is legal.

[0180] Performance scenarios are given at the transaction level (i.e., high-level communication speeds between components). The process automatically converts them into bandwidth requirements on each network segment. For example, according to various aspects of the present invention, the tool's machine learning model can identify bandwidth requirements and receive feedback to improve automatic selection. According to various aspects of the present invention, the tool includes a constraint solver 2110 that is used to generate an optimal configuration that complies with one or more of the following parameters or criteria:

[0181] 1) Cost (wires, energy)

[0182] 2) Number of adapters (clock domain crossing, packet width adapters, etc.)

[0183] According to various aspects of the invention, the tool includes a process for checking whether the existing NoC topology can accommodate a given high-level transaction scenario by verifying that the current configuration is legal at step 2020. According to various aspects of the invention, if the performance check fails, the segments that do not have sufficient bandwidth are highlighted so that the designer or user can take action. The information collected from the performance check can also be provided to the machine learning model as feedback to an artificial intelligence (AI) machine implemented as part of the tool.

[0184] According to various aspects of the invention, the tool receives as input a high-level specification of the transactions that constitute running applications (scenarios) to ensure that each application can be run individually at the required speed.

[0185] Specific reference Fig. 22 According to various aspects of the present invention, the tool interprets a scenario, such as the one shown. From the high-level transactions found in the scenario, the tool infers the actual amount of bandwidth required at each element of each network involved. According to various aspects of the present invention, the tool receives transactions that can be multi-phase and can consume control and / or data BW in multiple networks. According to various aspects of the present invention and as a non-limiting example, a READ transaction in an incoherent scenario generates a request in the requesting network (often 1 cycle, but can also be multiple cycles) and generates multiple data in the responding network (multiple cycles). According to various aspects of the present invention, for each transaction, a list of affected networks is automatically inferred and the bandwidth requirements of each network component (nodes and segments) are generated accordingly. According to various aspects of the present invention, the tool performs legal configuration generation. Therefore, for each node, given the bandwidth requirements, current layout, clock physical constraints, the tool:

[0186] 1) Infer the possible configurations (clock + data widths) that can be applied to the node; and

[0187] 2) Expressed as a collection of constraints, rather than an exhaustive list.

[0188] According to various aspects of the invention, the tool selects the best configuration. The tool uses a constraint solver when seeking the best legal configuration. The constraint solver is used to minimize the cost using a heuristic as input, the input including but not limited to at least one or more of:

[0189] The cost of clock adapters (e.g., clock domain changes between two nodes) to minimize area;

[0190] Wiring length (lower data width is preferred);

[0191] Power consumption (choose a slower clock where legal); and

[0192] Technical parameters,

[0193] According to various aspects of the invention, the tool converts high-level transaction speed requirements into bandwidth annotations for segments in several networks of a NoC. According to various aspects of the invention, the tool considers clock tree propagation constraints (areas of the floor plan where a given clock can reside) to filter out illegal configurations. According to various aspects of the invention, the tool uses a constraint solver to not only optimize routing cost and performance, but also reduce the number of required adapters (including adapters for clock domain crossings).

[0194] Specific reference Figure 26 to Figure 29 , according to various aspects of the invention, the tool includes a process in which elements of a newly created NoC (generated by topology synthesis or manually created), including clock allocation and data width allocation, are configured to meet performance goals provided by a user in the form of a collection of performance scenarios.

[0195] refer to Fig.26 , the scenario depicted in the figure would require intermediate segmentation to maintain 6GB / s bandwidth, which cannot be achieved even if two switches are assigned to the fastest clock in the design. The tool provides an incremental topology synthesis process, which allows the user to provide performance requirements later in the design flow, after the topology has been created. To achieve this, the tool includes a method for converting an existing topology to meet the newly added bandwidth requirements.

[0196] According to various aspects of the invention, the tool identifies segments that cannot meet bandwidth requirements. A segment is defined as a section between two switches, and a segment may already have several channels that include different communications. For each such segment, the tool creates an additional channel for the segment. According to various aspects of the invention, the tool uses a conservative number of channels, for example, one channel for each communication through the segment. The tool optimally distributes communications through the segments (routes) on the new channels such that:

[0197] Each channel will group as many communications as possible and use as much of its bandwidth as possible; and

[0198] Each performance scenario is satisfied by the current routing redistribution; and

[0199] New routing groupings will not introduce new deadlocks (by merging routes that were previously separated into different existing channels).

[0200] Specific reference Fig. 27 , according to various aspects of the present invention, the tool generates the route redistribution shown. Thus, when the routes are redistributed across all the violated segments, the internal arbiter of the switch is changed, sometimes without the need to maintain the switch. Fig.28 ,The tool detects the real arbitrators inside the remaining switches and splits the switches with multiple unconnected arbitrators or removes the switches that no longer have arbitrators.

[0201] As the shape of the topology changes due to adding new channels and removing / splitting switches, the current physical locations are no longer considered optimal. According to various aspects of the invention, the tool invokes global placement to find a suitable placement for the newly modified topology. In the non-limiting example provided, the new placement is as follows: Fig.29 shown.

[0202] According to various aspects of the invention, the tool uses the configuration process outlined herein to configure the remaining switches. For newly created channels, a valid configuration is guaranteed to be found as long as the scenario provided by the user is valid.

[0203] According to various aspects of the invention, the tool can incrementally add new channels to the topology (after initial topology synthesis) to maintain specified bandwidth scenarios. According to various aspects of the invention, the tool can redistribute routes on new channels to minimize the number of required channels without introducing new deadlocks. According to various aspects of the invention, the tool can split and delete switches that no longer serve arbitration purposes after route redistribution. According to various aspects of the invention, the tool can recall data width and clock configuration processes and adjust them as needed. According to various aspects of the invention, the tool globally adjusts placement positions on a floor plan. According to various aspects of the invention, the tool includes a machine learning model that can receive feedback for further training the model.

[0204] According to various aspects of the invention, the tool includes a topology synthesis process, wherein a topology is initially created by ignoring the provided performance scenarios and focusing on optimizing routing costs, to which the tool applies the above-described topology transformation process to support the performance scenarios in the second phase. This speeds up the NoC generation or topology synthesis process by considering only one requirement at a time. Furthermore, by first focusing on optimizing routing routing and overall length, the tool ensures that any segments that might be merged have already been merged by the initial synthesis, and that only paths that require more bandwidth are ultimately duplicated.

[0205] Specific reference Figure 30 to Figure 33 According to various aspects of the present invention, the tool allows a user to provide performance requirements for the topology synthesis process by defining a collection of scenarios, where a scenario is a collection of communications occurring in parallel at a given speed. While this makes it possible to use performance constraints to drive the shape of the topology, it can be difficult and time consuming to define and enter all the scenarios required to obtain a certain business distribution. To alleviate this, the tool introduces a new process that allows the user to select a business pattern from a list of predefined patterns and apply it to a collection of connections. The tool then automatically generates the collection of required scenarios. According to various aspects of the present invention, the user provides or creates a business class for a collection of connections and selects a business pattern for the business class from a list of predefined business patterns. The tool generates all scenarios from the collection of connections contained in the business class for each business class that has a business pattern.

[0206] Fig.30 An example topology is shown. In this topology, segments are shared between multiple initiators to reduce wiring costs. In a non-limiting example, a user wants to ensure that selected initiators and targets can communicate at the same time with full available bandwidth, which is equivalent to having a central crossbar switch in terms of bandwidth.

[0207] Specific reference Fig.31 , the user can simply define traffic classes for these connections as shown. A new traffic class named "CROSSBAR" is created and set to use the "Reserve Bandwidth" traffic mode to ensure that the bandwidth is equal to that of a full crossbar. In accordance with various aspects of the present invention, the tool then automatically uses this input to generate a collection of scenarios. Each possible set of synchronized communications is treated as a separate scenario, where each active input / output pair in the "virtual" crossbar communicates at maximum bandwidth, such as Fig.32as shown. Having defined these scenarios, the tool performs a topology synthesis process and is now able to incrementally modify the topology to maintain the desired bandwidth. According to various aspects of the invention, the tool creates new channels in previously shared segments. According to various aspects of the invention, the tool can apply the process to any set of traffic patterns, not just the crossbar example. According to various aspects of the invention, the tool can receive feedback from a user or as input to an adversarial machine learning model, which is used to further train the tool's machine learning model.

[0208] According to another aspect of the invention, the tool automatically inserts various adapters and buffers in the network. The tool inserts adapters based on the required adaptation between two components with different data widths, different clock and power domains. The tool inserts buffers based on scenarios and detected rate mismatches.

[0209] According to some aspects and embodiments, the tool may be used to ensure that multiple iterations of synthesis are completed for incremental optimization of a NoC, including cases where one of the constraints provided to the tool is information about a previous run.

[0210] Reference now Figure 34 to Figure 36 According to various embodiments and aspects of the present invention, the optimization occurs when a new connection is about to be implemented after the configuration exploration step has selected a configuration (entrance, exit and internal segments and points). If an existing switch within a certain distance can be safely reused, the tool will try to avoid creating a new switch when splitting the segment. According to various embodiments and aspects of the present invention, a switch can be safely reused when it does not violate any performance requirements or constraints. According to various embodiments and aspects of the present invention, the switch reuse distance is a parameter selected by the user. According to various embodiments and aspects of the present invention, the switch reuse distance is provided and determined by a machine learning model that is trained using input from the user and / or based on feedback from an adversarial model or the user. Therefore, in terms of the additional turns created, the tool can ensure that reusing an existing switch is equivalent to creating a new switch, thereby ensuring that no new deadlocks are introduced.

[0211] According to various embodiments and aspects of the present invention, when a switch is reused, its location (placement) is optimized given the newly connected segments. The conditions for switch reusability are simple and are defined by the requirements, parameters and constraints of the NoC (such as avoiding deadlock). Therefore, switches can be evaluated during the exploration step (i.e., when selecting the best configuration) to prefer configurations that are likely to allow reuse of existing switches.

[0212] According to various embodiments and aspects of the present invention, Fig.34An example is shown where switches can be safely reused when an input switch of an existing segment is reused due to the entry of a new segment. An initiator or source (S) 3410 displays the communication requirements with a target or destination (D) 3420. A selected configuration with possible switches 3412 and 3422 is shown in accordance with various embodiments and aspects of the present invention. The tool chooses (based on the user or artificial intelligence using a machine learning model) to eliminate switch 3412 and use the existing switch of source 3410.

[0213] According to various embodiments and aspects of the present invention, Fig.35 An example is illustrated in which switches can be safely reused when an output switch of an existing segment is reused for a new segment being added or output. An initiator or source (S) 3510 displays communication requirements with a target or destination (D) 3520. In accordance with various embodiments and aspects of the present invention, a selected configuration with possible switches 3512 and 3522 is shown. The tool chooses (based on the user or artificial intelligence using a machine learning model) to eliminate switch 3522 and use the existing switch of source 3520. In accordance with various embodiments and aspects of the present invention, the tool inserts or uses a new segment including at least one new switch, and the new switch is selected as a reusable switch. In accordance with various embodiments and aspects of the present invention, the tool uses or inserts a new segment including at least one new switch, and the tool replaces the new switch with a reusable switch.

[0214] According to various embodiments and aspects of the present invention, Fig.36 An implementation of the tool is illustrated when the switches used to segment the first segment are used (reused) to segment the second segment. An initiator or source (S) 3610 displays communication requirements with a target or destination (D) 3620 and multiple routes that can be used to merge communications between the source 3610 and the destination 3620. A selected configuration with possible switches 3612, 3622, 3630, and 3632 is shown in accordance with various embodiments and aspects of the present invention. The tool chooses (based on the user or artificial intelligence using a machine learning model) to eliminate switch 3632 and use an existing switch.

[0215] Reference now Fig.37, shows a method 3700 for optimizing the topology of a NoC according to various aspects and embodiments of the present invention, the method 3700 determines the reusability of certain elements of the NoC by exploring the topology. The process starts at step 3710, where the tool explores the topology of the NoC to identify multiple existing segments, each segment having at least one existing switch. The tool also predicts the availability of each existing switch and identifies at least one switch that can be reused from the existing switches. In step 3720, the tool receives an input that identifies at least one new segment to be added to the topology. In step 3730, a configuration for adding the new segment is identified. In step 3740, the tool inserts the new segment in the configuration. In step 3750, the tool determines at least one reusable switch selected from the existing switches that are reused in the configuration. In step 3760, the tool adjusts the position of the reusable switch in the topology of the NoC by repositioning the reusable switch to optimize the configuration that meets the performance requirements.

[0216] According to various embodiments and aspects of the present invention, the switches that are reused during the synthesis process are applicable to the various scenarios or situations described and other scenarios and situations that follow the same logic. According to various embodiments and aspects of the present invention, the tool can reposition the switches when reused as needed. According to various embodiments and aspects of the present invention, the tool can predict the availability of switches in a segment when selecting the best configuration during the exploration phase.

[0217] After the software performs the synthesis process, the results are produced in a machine-readable form, such as a computer file that uses a well-defined format to capture information. An example of such a format is XML, and another example of such a format is JSON. The scope of the present invention is not limited by the specific format.

[0218] Certain aspects of the present invention employ an incremental approach to network synthesis. This incremental approach is useful in many contexts. For example, in some embodiments, the incremental process begins with a specification and a clean floor plan. In these and other embodiments, some of them have been discussed above.

[0219] According to some aspects and embodiments, a connection may have a communication policy that specifies, for example, the sensitivity of the connection to latency.

[0220] Certain methods according to various aspects of the present invention may be performed by instructions stored on a non-transitory computer-readable medium. The non-transitory computer-readable medium stores code including instructions that, if executed by one or more processors, will enable a system or computer to perform the steps of the methods described herein. The non-transitory computer-readable medium includes: a rotating magnetic disk, a rotating optical disk, a flash random access memory (RAM) chip, and other mechanically movable or solid-state storage media. According to various examples, any type of computer-readable medium is suitable for storing code including instructions.

[0221] Certain examples have been described herein, and it will be noted that different combinations of different components from different examples may be possible. The highlighted features are for better explanation of the examples; however, it is apparent that certain features may be added, modified and / or omitted without modifying the functional aspects of the examples described.

[0222] Each example is a method of behavior using any machine or combination of machines. The method examples are complete anywhere in the world where most of the constituent steps occur. For example and in accordance with various aspects and embodiments of the present invention, the IP elements or units include: a processor (e.g., a CPU or GPU), a random access memory (RAM—e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connections, such as Ethernet, WiFi, 3G, 4G Long Term Evolution (LTE), 5G and other wireless interface standard radios. The IP may also include various I / O interface devices to meet the needs of different peripherals, such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices, such as keyboards and mice. By executing instructions stored in the RAM device, the processor performs the steps of the method as described herein.

[0223] Some examples are one or more non-transitory computer-readable media arranged to store such instructions for the methods described herein. Any machine having a non-transitory computer-readable medium including any necessary code can implement the examples. Some examples can be implemented as: a physical device, such as a semiconductor chip; a hardware description language representation of the logical or functional behavior of such a device; and one or more non-transitory computer-readable media for storing such hardware description language representations. The description of the principles, aspects, and embodiments described herein include their structural and functional equivalents. The elements described herein as coupled have an effective relationship that can be achieved by direct or indirect connection with one or more other intermediate elements.

[0224] Those skilled in the art will recognize many modifications and variations. Modifications and variations include any relevant combination of disclosed features. The description of the principles, aspects, and embodiments described herein include their structural and functional equivalents. Elements described herein as "coupled" or "communicatively coupled" have an effective relationship that can be achieved by direct or indirect connection using one or more other intermediate elements. Embodiments described herein as "communicating" or "communicating" with another device, module, or element include any form of communication or link and include an effective relationship. For example, a wired connection, wireless protocol, near field protocol, or RFID can be used to establish a communication link.

[0225] To the extent that the terms "including," "includes," "having," "has," "with," or variations thereof are used in the detailed description and claims, such terms are intended to be inclusive in a manner similar to the term "comprising."

[0226] Therefore, the scope of the present invention is not intended to be limited to the exemplary embodiments and aspects shown and described herein. Rather, the scope and spirit of the present invention are embodied by the appended claims.

Claims

1. A tool for incremental generation of a network-on-chip (NoC), wherein the tool comprises a non-transitory computer-readable medium for storing code, which, when executed by one or more processors, causes the tool to: Explore the NoC topology to: identifying a plurality of existing segments, each of the plurality of existing segments having at least one existing switch; as well as Predict the availability of each existing switch; as well as receiving as input at least one new segment to be added to the topology, selecting a configuration for adding the new segment; inserting the new segment in the configuration; selecting at least one reusable switch from existing switches to be reused in the configuration; as well as By repositioning the reusable switch, the position of the reusable switch in the topology of the NoC is adjusted to optimize the configuration to meet performance requirements.

2. The tool of claim 1, wherein the new segment includes at least one new switch, and the new switch is selected as the reusable switch.

3. The tool of claim 1, wherein the new segment includes at least one new switch, and the new switch is replaced with the reusable switch.

4. The tool of claim 1, further resulting in identifying at least one switch selected from the existing switches that can be reused.

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