Cascade type video monitoring module based on FPGA (Field Programmable Gate Array)

Abstract

The invention belongs to the technical field of airborne image processing, and particularly relates to a cascaded video monitoring module based on an FPGA (Field Programmable Gate Array), which comprises a cascaded sub-module formed by one FPGA and one embedded CPU (Central Processing Unit), the FPGAs of the cascaded sub-modules are cascaded through an ARINC818 bus, and the embedded CPUs of the cascaded sub-modules are interconnected through the same network router; the input end of each cascade sub-module is connected with a plurality of paths of ARINC818 video inputs respectively; according to the invention, monitoring functions of video stitching, compression, recording and playback are realized based on multiple groups of cascaded FPGAs and embedded CPUs, multiple input video resolutions are supported, the number of input video channels can be expanded in a cascaded manner, and related application scenes of airborne video monitoring can be better satisfied.

Description

Technical Field

[0001] The invention belongs to the technical field of airborne image processing, and in particular relates to a cascade video monitoring module based on FPGA. Background Art

[0002] With the advancement of avionics technology, the types and quantities of airborne optoelectronic equipment are increasing, and the resolutions of various airborne optoelectronic equipment are becoming more diversified, which has put higher requirements on the multi-resolution support and interface scalability of airborne monitoring systems. Summary of the invention

[0003] In view of this, the present invention provides a cascade video surveillance module based on FPGA, which can better meet the relevant application scenarios of airborne video surveillance.

[0004] The technical solution of the present invention is:

[0005] A cascaded video surveillance module based on FPGA, comprising a cascaded submodule based on one FPGA and one embedded CPU, wherein the FPGAs of each cascaded submodule are cascaded through an ARINC818 bus, and the embedded CPUs of each cascaded submodule are interconnected through the same network router; and the input ends of each cascaded submodule are respectively connected to multiple ARINC818 video inputs;

[0006] The cascade video surveillance module also includes a display and control terminal; the display and control terminal is connected to an embedded CPU of the cascade sub-module, and after transmitting the display and control instructions to the connected embedded CPU, the display and control instructions are transmitted to the network router, and the router forwards the display and control instructions to at least one selected cascade sub-module. The selected cascade sub-module transmits the ARINC818 video cascade processed by itself to the display and control terminal according to the display and control instructions.

[0007] Furthermore, the display and control terminal is used to display a single-channel input video, a multi-channel monitoring spliced ​​video, or a recorded playback video;

[0008] The transmission, splicing and playback functions of the single-channel input video, multi-channel monitoring splicing video or recorded playback video are completed based on the FPGA.

[0009] Furthermore, the FPGA is internally composed of a MicroBlaze minimum system, a PCIE EP IP, a BT.656 timing generation module, a BT.1120 analysis module, an aggregation module, an OSD, multiple multiplexers, multiple scalers and multiple VDMAs.

[0010] Furthermore, the FPGA in each of the cascaded sub-modules receives multiple ARINC818 videos, 1 cascaded ARINC818 video input and 1 BT.1120 playback video input, which are aggregated by the aggregation module and sent to the first multiplexer of multiple-choice 1. The output of the first multiplexer is scaled by the Scaler and cached by the VDMA. Finally, MicroBlaze receives the display control instructions of the embedded CPU through the PCIE interface, controls the OSD and the first multiplexer to superimpose the images cached in the specified VDMA into a monitoring spliced ​​image at the specified resolution and position.

[0011] Furthermore, the multi-channel videos and the spliced ​​videos output by the aggregation module are output to the cascade ARINC818 output interface via the second multiplexer of multiple-choice 1 for use by the next-level cascade sub-module.

[0012] Furthermore, the FPGA is also used to send multiple video inputs to the embedded CPU via the BT.656 timing generation module for video compression and recording.

[0013] Furthermore, the embedded CPU in the cascade submodule has at least the same number of BT.656 interfaces and one BT.1120 interface as the number of ARINC818 video channels received by the FPGA, and the embedded CPU supports PCIE interface, SATA interface and Ethernet interface.

[0014] Furthermore, the embedded CPU receives the ARINC818 video forwarded by the FPGA through BT.656, compresses it, and records it to the SATA hard disk through the SATA interface; the embedded CPU receives the display control command of the monitoring terminal through the Ethernet port, and sends the display control command to the FPGA through the PCIE port, and the FPGA generates a monitoring splicing screen; the embedded CPU receives the playback command of the monitoring terminal through the Ethernet port, reads and decompresses the specified recorded video in the SATA hard disk, and sends it to the FPGA for playback via the BT.1120 interface.

[0015] Beneficial effects of the present invention:

[0016] Based on multiple sets of cascaded FPGAs and embedded CPUs, the monitoring functions of video splicing, compression, recording, and playback are realized. It supports multiple input video resolutions, and the number of input video channels can be cascaded and expanded, which can better meet the relevant application scenarios of airborne video monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 Cascade video surveillance system

[0019] Figure 2 FPGA / CPU video monitoring cascade submodule DETAILED DESCRIPTION

[0020] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0021] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0022] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0025] In one embodiment of the present invention, a cascaded video surveillance module based on FPGA is proposed, including a cascaded sub-module based on one FPGA and one embedded CPU, the FPGAs of each cascaded sub-module are cascaded through an ARINC818 bus, and the embedded CPUs of each cascaded sub-module are interconnected through the same network router; the input end of each cascaded sub-module is respectively connected to multiple ARINC818 video inputs;

[0026] The cascade video surveillance module also includes a display and control terminal; the display and control terminal is connected to an embedded CPU of the cascade sub-module, and after transmitting the display and control instructions to the connected embedded CPU, the display and control instructions are transmitted to the network router, and the router forwards the display and control instructions to at least one selected cascade sub-module. The selected cascade sub-module transmits the ARINC818 video cascade processed by itself to the display and control terminal according to the display and control instructions.

[0027] In this embodiment, the display and control terminal is used to display a single-channel input video, a multi-channel monitoring spliced ​​video, or a recorded playback video;

[0028] The transmission, splicing and playback functions of the single-channel input video, multi-channel monitoring splicing video or recorded playback video are completed based on the FPGA.

[0029] In this embodiment, the FPGA is internally composed of a MicroBlaze minimum system, a PCIE EP IP, a BT.656 timing generation module, a BT.1120 analysis module, an aggregation module, an OSD, multiple multiplexers, multiple scalers, and multiple VDMAs.

[0030] In this embodiment, the FPGA in each of the cascaded sub-modules receives 8 ARINC818 videos, 1 cascaded ARINC818 video input and 1 BT.1120 playback video input, which are aggregated by the aggregation module and sent to the first multiplexer of multiple-select-1. The output of the first multiplexer is scaled by the Scaler and cached by the VDMA. Finally, MicroBlaze receives the display control instructions of the embedded CPU through the PCIE interface, controls the OSD and the first multiplexer to superimpose the images cached in the specified VDMA into a monitoring spliced ​​image at the specified resolution and position.

[0031] In this embodiment, the multi-channel videos and the spliced ​​videos output by the aggregation module are output to the cascaded ARINC818 output interface via the second multiplexer of multiple-choice 1 for use by the next-level cascaded sub-module.

[0032] In this embodiment, the FPGA is also used to send 8-channel video input to the embedded CPU via the BT.656 timing generation module for video compression and recording.

[0033] In this embodiment, the embedded CPU in the cascade submodule has at least the same number of BT.656 interfaces and one BT.1120 interface as the number of ARINC818 video channels received by the FPGA, and the embedded CPU supports PCIE interface, SATA interface and Ethernet interface.

[0034] In this embodiment, the embedded CPU receives the ARINC818 video forwarded by the FPGA through BT.656, compresses it and records it to the SATA hard disk through the SATA interface; the embedded CPU receives the display control command of the monitoring terminal through the Ethernet port, sends the display control command to the FPGA through the PCIE port, and the FPGA generates a monitoring splicing screen; the embedded CPU receives the playback command of the monitoring terminal through the Ethernet port, reads and decompresses the recorded video specified in the SATA hard disk, and sends it to the FPGA for playback via the BT.1120 interface.

[0035] This embodiment provides an expandable FPGA-based cascade video surveillance module, which consists of an FPGA and an embedded CPU to form an FPGA / CPU video surveillance cascade sub-module. The FPGAs between the sub-modules are cascaded through ARINC818, and the embedded CPUs are interconnected through an Ethernet router to form a cascade video surveillance system. Figure 1 shown.

[0036] The FPGA is composed of MicroBlaze minimum system, PCIE EP IP, BT.656 timing generation module, BT.1120 analysis module, aggregation module, OSD, multiple MUX multiplexers, multiple Scalers and multiple VDMAs. Figure 2 As shown, the functions of splicing output, sending to the embedded BT.656 interface for compression recording and playing back the video through the BT.1120 interface are realized. At the same time, FPGA has cascade output and cascade input ARINC818 interfaces, so that the module at this level can process and use the output video of the previous level, and can provide the video at this level for the next level module to use and process.

[0037] The embedded CPU has at least 8 BT.656 interfaces and 1 BT.1120 interface, and supports PCIE interface, SATA interface and Ethernet interface. The embedded CPU receives the ARINC818 video forwarded by the FPGA through BT.656, compresses it and records it to the SATA hard disk through the SATA interface; receives the command of the monitoring terminal through the Ethernet port, reads and decompresses the specified recorded video, and sends it to the FPGA through the BT.1120 interface for playback.

[0038] By cascading multiple levels of FPGA / CPU modules, the ARINC818 input video, spliced ​​video or recorded video of any level module can be output to the monitoring terminal through the cascaded ARINC818 interface.

[0039] The FPGA of this embodiment receives 8-channel ARINC818 video, 1-channel cascade ARINC818 video input and 1-channel BT.1120 playback video input, and aggregates them into 10-channel video through the aggregation module and sends them to each 10-choose-1 MUX multiplexer. The MUX output is scaled by the Scaler and cached by the VDMA. Finally, MicroBlaze receives the display control instructions of the embedded CPU through the PCIE interface, controls the OSD and the 10-choose-1 MUX to superimpose the VDMA cached specified picture at the specified resolution and position to synthesize the monitoring splicing picture. The 10-channel video output of the aggregation module and the splicing are output to the cascade ARINC818 output interface via the 11-choose-1 MUX multiplexer for use by the next-level cascade sub-module.

[0040] The FPGA sends the 8-channel video input to the embedded CPU via the BT.656 timing generation module for video compression and recording. The embedded CPU of this embodiment has at least 8 BT.656 interfaces and 1 BT.1120 interface, and supports PCIE interface, SATA interface and Ethernet interface, such as Figure 2As shown. The embedded CPU receives the ARINC818 video forwarded by the FPGA through BT.656, compresses it, and records it to the SATA hard disk through the SATA interface; receives the display command of the monitoring terminal through the Ethernet port, sends the monitoring display command to the FPGA through the PCIE port, and the FPGA generates a monitoring splicing screen; receives the playback command of the monitoring terminal through the Ethernet port, reads and decompresses the specified recorded video in the SATA hard disk, and sends it to the FPGA for playback via the BT.1120 interface. The cascaded video monitoring system of this embodiment is composed of at least two cascaded FPGA / CPU video monitoring cascade sub-modules. The FPGA / CPU video monitoring cascade sub-modules are cascaded through the ARINC818 interface and Ethernet. The command of the monitoring terminal can be received through Ethernet, and the ARINC818 input video, monitoring splicing video or recorded playback video of any first-level module can be output to the monitoring terminal through the cascaded ARINC818 interface.

[0041] In this embodiment, the FPGA / CPU video monitoring cascade submodules are cascaded through the ARINC818 interface and Ethernet, and can receive the command of the monitoring terminal through Ethernet, and output the ARINC818 input video, monitoring spliced ​​video or recorded playback video of any first-level module to the monitoring terminal through the cascade ARINC818 interface. The application can select the number of cascaded modules according to the needs, and has good scalability.

[0042] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A cascaded video surveillance module based on FPGA, characterized in that: It includes a cascade submodule based on one FPGA and one embedded CPU, the FPGAs of each cascade submodule are cascaded through an ARINC818 bus, and the embedded CPUs of each cascade submodule are interconnected through the same network router; the input end of each cascade submodule is respectively connected to multiple ARINC818 video inputs; The cascade video surveillance module also includes a display and control terminal; the display and control terminal is connected to an embedded CPU of the cascade sub-module, and after transmitting the display and control instructions to the connected embedded CPU, the display and control instructions are transmitted to the network router, and the router forwards the display and control instructions to at least one selected cascade sub-module. The selected cascade sub-module transmits the ARINC818 video cascade processed by itself to the display and control terminal according to the display and control instructions.

2. The FPGA-based cascade video surveillance module according to claim 1, characterized in that: The display and control terminal is used to display input video, multi-channel monitoring spliced ​​video or record playback video; The transmission, splicing and playback functions of the single-channel input video, multi-channel monitoring splicing video or recorded playback video are completed based on the FPGA.

3. The FPGA-based cascade video surveillance module according to claim 2, characterized in that: The FPGA is internally composed of a MicroBlaze minimum system, a PCIE EP IP, a BT.656 timing generation module, a BT.1120 analysis module, an aggregation module, an OSD, multiple multiplexers, multiple scalers and multiple VDMAs.

4. The FPGA-based cascade video surveillance module according to claim 3, characterized in that: The FPGA in each of the cascaded sub-modules receives multiple ARINC818 videos, 1 cascaded ARINC818 video input and 1 BT.1120 playback video input, and after being aggregated by the aggregation module, is sent to the first multiplexer of multiple-select-1. The output of the first multiplexer is scaled by the Scaler and cached by the VDMA. Finally, MicroBlaze receives the display control instructions of the embedded CPU through the PCIE interface, controls the OSD and the first multiplexer to superimpose the images cached in the specified VDMA into a monitoring spliced ​​image at the specified resolution and position.

5. The FPGA-based cascade video surveillance module according to claim 4, characterized in that: The multi-channel video and the spliced ​​video output by the aggregation module are output to the cascade ARINC818 output interface via the second multiplexer of multiple choice 1 for use by the next-level cascade sub-module.

6. The FPGA-based cascade video surveillance module according to claim 5, characterized in that: The FPGA is also used to send multiple video inputs to the embedded CPU via the BT.656 timing generation module for video compression and recording.

7. The FPGA-based cascade video surveillance module according to claim 6, characterized in that: The embedded CPU in the cascade submodule has at least the same number of BT.656 interfaces and one BT.1120 interface as the number of ARINC818 video channels received by the FPGA, and the embedded CPU supports PCIE interface, SATA interface and Ethernet interface.

8. The FPGA-based cascade video surveillance module according to claim 7, characterized in that: The embedded CPU receives the ARINC818 video forwarded by the FPGA through BT.656, compresses it and records it to the SATA hard disk through the SATA interface; the embedded CPU receives the display control instructions of the monitoring terminal through the Ethernet port, and sends the display control instructions to the FPGA through the PCIE port, and the FPGA generates the monitoring splicing picture; The embedded CPU receives the playback command from the monitoring terminal through the Ethernet port, reads and decompresses the specified recorded video in the SATA hard disk, and sends it to the FPGA for playback via the BT.1120 interface.

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