Time synchronization device and method based on Beidou satellite time service signal security isolation

Abstract

The invention discloses a time synchronization device and method based on Beidou satellite time service signal security isolation. The device comprises a Beidou signal receiving module, a dual-core processor, a high-precision clock module and a time slice coordination module. Wherein the dual-core processor comprises a security isolation core and a time synchronization core; an isolation bridge is arranged between the security isolation core and the time synchronization core; the Beidou signal receiving module is connected with the security isolation core through a special data interface; and the high-precision clock module is connected with the time synchronization core through a special clock bus. According to the physical isolation design of the heterogeneous dual-core processor, strict separation of time service signal processing and time synchronization functions on a hardware level is realized, and a potential attack path is effectively blocked, so that the security, integrity and anti-interference capability of time service information are guaranteed on a system architecture level, and the time service performance is improved. The method can be widely applied to the computer technical field.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a time synchronization device and method based on the secure isolation of Beidou satellite timing signals. Background Art

[0002] As modern society's requirements for time synchronization accuracy continue to increase, high-precision time synchronization technology plays an increasingly important role in key infrastructure such as power systems, communication networks, and financial transactions. Among them, the Beidou satellite navigation system, as a global satellite navigation system independently developed by my country, has become an important means of achieving time synchronization in these fields with its high precision and high reliability. In the power system, Beidou timing technology is widely used in phasor measurement units (PMUs) and substation automation systems in smart grids, providing an accurate time reference for the stable operation of the power grid and fault location. At the same time, in the communication network, Beidou timing also provides key time synchronization support for 5G base stations, data centers and other facilities.

[0003] However, there are still some urgent problems to be solved in the existing time synchronization devices. The traditional single-core processor architecture is difficult to effectively isolate the timing signal processing from other system functions, which poses a security risk. When processing complex timing signals and executing time synchronization algorithms, the single-core architecture often cannot meet the requirements of high concurrency and low latency. Most existing systems lack effective task scheduling and resource management mechanisms and cannot fully utilize processor resources. This leads to a significant decrease in system performance under high load conditions, affecting the accuracy and stability of time synchronization. Although the Beidou system itself has high-precision characteristics, the existing time synchronization devices still have room for improvement in signal processing and clock calibration. In long-term operation and harsh environments, the performance of existing devices is prone to deterioration, making it difficult to ensure continuous and stable timing services. Summary of the invention

[0004] In order to solve at least one of the above problems, the main purpose of the embodiments of the present application is to propose a time synchronization device and method based on the safe isolation of Beidou satellite timing signals, which can improve the security, integrity and anti-interference capability of various systems.

[0005] To achieve the above purpose, one aspect of an embodiment of the present application proposes a time synchronization device based on Beidou satellite timing signal security isolation, the device comprising:

[0006] Beidou signal receiving module, dual-core processor, high-precision clock module and time-slicing coordination module;

[0007] Wherein, the dual-core processor includes a security isolation core and a time synchronization core; an isolation bridge is provided between the security isolation core and the time synchronization core;

[0008] The Beidou signal receiving module is connected to the security isolation core through a dedicated data interface;

[0009] The high-precision clock module is connected to the time synchronization core via a dedicated clock bus.

[0010] In some embodiments, the Beidou signal receiving module includes:

[0011] Beidou satellite signal receiving antenna, low noise amplifier, bandpass filter, multi-band receiver and high-speed analog-to-digital converter;

[0012] Wherein, the Beidou satellite signal receiving antenna is connected to the low noise amplifier via a coaxial cable;

[0013] An impedance network is provided between the Beidou satellite signal receiving antenna and the low noise amplifier;

[0014] The low noise amplifier is cascade-connected to the bandpass filter via a microstrip line;

[0015] The multi-band receiver is connected to a high-speed analog-to-digital converter via a high-speed digital interface;

[0016] The high-speed analog-to-digital converter is connected to the safety isolation core via a dedicated data interface.

[0017] In some embodiments, the secure isolation core includes:

[0018] CRC check unit, state machine check unit, digital signal processing unit, cache and multiplexer;

[0019] Wherein, the CRC check unit and the state machine check unit are connected in parallel to the digital signal processing unit;

[0020] The cache is connected to the digital signal processing unit via a multi-port interface;

[0021] The multiplexer adopts a cross switch structure;

[0022] The digital signal processing unit is connected to the Beidou signal receiving module through the dedicated data interface;

[0023] The degree-even multiplexer is connected to the isolation bridge;

[0024] The digital signal processing unit is connected to the time slicing coordination module via a control bus.

[0025] In some embodiments, the time synchronization core includes:

[0026] Local clock receiving unit, time deviation calculation unit, digital controlled oscillator, digital phase locked loop circuit and time output interface;

[0027] Wherein, the local clock receiving unit is connected to the high-precision clock module;

[0028] The time deviation calculation unit is connected to the safety isolation core;

[0029] The time deviation calculation unit is connected to the digital controlled oscillator and the digital phase locked loop circuit via a high-speed data channel;

[0030] The output end of the digital controlled oscillator is connected to the input end of the digital phase locked loop;

[0031] The time output interface is connected to the digital phase locked loop circuit and is connected to an external device through an output buffer.

[0032] In some embodiments, the high-precision clock module includes:

[0033] Dual oven-controlled crystal oscillators, spare atomic clock interface, clock switching control circuit, clock output unit;

[0034] Wherein, the dual constant temperature crystal oscillator is isolated from the main circuit board by a low noise power supply and a temperature control loop;

[0035] The clock switching control circuit communicates with the dual-core processor via a high-speed serial interface;

[0036] The clock output unit is connected to the dual oven controlled crystal oscillator and the backup atomic clock interface;

[0037] The clock output unit is connected to the local clock receiving unit of the time synchronization core through a dedicated low-jitter clock channel;

[0038] The clock switching control circuit is connected to the time synchronization core.

[0039] In some embodiments, the time slicing coordination module includes:

[0040] Hardware counters, status registers, task signature lookup tables, hardware priority queues, time-triggered schedulers, programmable timer arrays, DMA controllers, dual-port RAM, and on-chip memory;

[0041] Wherein, the hardware counter and the status register are connected to the time-triggered scheduler via a low-latency bus;

[0042] The task feature lookup table and the hardware priority queue are implemented using on-chip registers;

[0043] The time-triggered scheduler works in coordination with the programmable timer array via an internal high-speed interconnect bus;

[0044] The dual-port RAM is connected to the security isolation core and the time synchronization core through a high-speed data channel;

[0045] The DMA controller is connected to the dual-core processor via a PCIe interface; the DMA controller is also connected to the hardware priority queue via a control signal line;

[0046] The time-triggered scheduler is connected to the time synchronization core via a control bus.

[0047] In some embodiments, the digital phase locked loop comprises:

[0048] High-speed digital phase detector, adjustable digital loop filter, digitally controlled oscillator and programmable frequency divider;

[0049] Wherein, the high-speed digital phase detector is connected to the adjustable digital loop filter through a high-speed data channel;

[0050] The digitally controlled oscillator is connected to the programmable frequency divider through a low-jitter clock distribution network.

[0051] In some embodiments, the apparatus further comprises:

[0052] Non-volatile memory, power management unit and multi-interface input and output modules;

[0053] Wherein, the non-volatile memory adopts a dual-backup structure and is connected to the dual-core processor through an independent storage controller;

[0054] The power management unit is connected to each module that needs power supply through a star topology;

[0055] The multi-interface input and output module is connected to the dual-core processor via a high-speed serial interface.

[0056] To achieve the above purpose, the embodiment of the present application also provides a time synchronization method based on the above-mentioned time synchronization device based on Beidou satellite timing signal security isolation, and the method includes the following steps:

[0057] Receive an initial timing signal transmitted by a Beidou satellite through a Beidou signal receiving module, digitize the initial timing signal, obtain first timing signal data, and send the first timing signal data to the security isolation core of the dual-core processor;

[0058] receiving the first timing signal data through the security isolation core, performing a security check on the first timing signal data, and sending the checked first timing signal data to the time synchronization core of the dual-core processor;

[0059] Sending local clock information to the time synchronization core through a high-precision clock module;

[0060] Performing time synchronization processing according to the received first timing signal and the local clock information through the time synchronization core;

[0061] The scheduling of the high-precision clock module and the dual-core processor is coordinated through a time slicing coordination module.

[0062] In some embodiments, the method further comprises the following steps:

[0063] Storing the configuration information and log data of the dual-core processor via a non-volatile memory;

[0064] Power is supplied to each power-consuming module in the time synchronization device based on the safe isolation of Beidou satellite timing signals through the power management unit;

[0065] The communication of each module in the time synchronization device based on the safe isolation of Beidou satellite timing signals is realized through a multi-interface input and output module.

[0066] The embodiments of the present application include at least the following beneficial effects: The present application provides a time synchronization device and method based on the safe isolation of Beidou satellite timing signals, the scheme includes a Beidou signal receiving module, a dual-core processor, a high-precision clock module and a time slicing coordination module; wherein the dual-core processor includes a safe isolation core and a time synchronization core; an isolation bridge is provided between the safe isolation core and the time synchronization core; the Beidou signal receiving module is connected to the safe isolation core through a dedicated data interface; the high-precision clock module is connected to the time synchronization core through a dedicated clock bus. The device realizes the strict separation of timing signal processing and time synchronization functions at the hardware level through the physical isolation design of heterogeneous dual-core processors, effectively blocks potential attack paths, and thus ensures the security, integrity and anti-interference capability of timing information at the system architecture level. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0068] Figure 1 It is a schematic diagram of the overall architecture of a time synchronization device based on safe isolation of Beidou satellite timing signals provided in an embodiment of the present application;

[0069] Figure 2 is a schematic diagram of the internal structure of a dual-core processor provided in an embodiment of the present application;

[0070] Figure 3 It is a schematic diagram of the structure of the time slicing coordination module provided in an embodiment of the present application;

[0071] Figure 4 It is a schematic diagram of the steps of the time synchronization method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0073] Although the functional modules are divided in the system schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the system or the order in the flowchart. The terms "first / S100", "second / S200", etc. in the specification, claims and the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0074] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0075] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0076] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0078] In the related technologies, there are still some urgent problems to be solved in time synchronization devices. The traditional single-core processor architecture is difficult to effectively isolate the timing signal processing from other system functions, which poses a safety hazard. When processing complex timing signals and executing time synchronization algorithms, the single-core architecture often cannot meet the requirements of high concurrency and low latency. Most existing systems lack effective task scheduling and resource management mechanisms and cannot fully utilize processor resources. This leads to a significant decrease in system performance under high load conditions, affecting the accuracy and stability of time synchronization. Although the Beidou system itself has high-precision characteristics, the existing time synchronization devices still have room for improvement in signal processing and clock calibration. In long-term operation and harsh environments, the performance of existing devices is prone to deterioration, making it difficult to ensure continuous and stable timing services.

[0079] In view of this, the embodiments of the present application provide a time synchronization device and method based on the security isolation of Beidou satellite timing signals. This solution achieves strict separation of timing signal processing and time synchronization functions at the hardware level through the physical isolation design of heterogeneous dual-core processors, effectively blocking potential attack paths, thereby ensuring the security, integrity and anti-interference capability of timing information at the system architecture level.

[0080] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0081] Figure 1 It is a schematic diagram of the overall architecture of the device provided in an embodiment of the present application, and the time synchronization device based on the safe isolation of Beidou satellite timing signals includes: a Beidou signal receiving module, a dual-core processor, a high-precision clock module and a time slicing coordination module; each module is integrated on the same mainboard and interconnected through a high-speed data bus; the high-speed data bus adopts a multi-layer PCB design, including but not limited to a signal transmission layer, a power supply layer and a ground plane layer; the Beidou signal receiving module is connected to the safe isolation core in the dual-core processor through a dedicated data interface; the dedicated data interface is a high-speed serial interface, which adopts differential signal transmission technology; a dedicated isolation bridge is provided between the safe isolation core and the time synchronization core, and the isolation bridge adopts optoelectronic isolation technology to achieve physical isolation while ensuring high-speed data transmission; the high-precision clock module is connected to the time synchronization core through a dedicated clock bus, and the dedicated clock bus adopts a star topology; the time slicing coordination module is connected to the dual-core processor through a control bus; the control bus adopts a multi-master and multi-slave architecture to support concurrent communication between modules.

[0082] Furthermore, each module in the device of the embodiment of the present application is introduced in detail below. It should be noted that the example mentioned is only one of the implementation methods, and the specific elements and data therein are only used as an example, and the present application does not limit this.

[0083] (1) Beidou signal receiving module.

[0084] The Beidou signal receiving module includes: a Beidou satellite signal receiving antenna, a low-noise amplifier, a bandpass filter, a multi-band receiver, and a high-speed analog-to-digital converter; the receiving antenna is connected to the low-noise amplifier through a coaxial cable, and an impedance matching network is provided between the antenna and the low-noise amplifier; the low-noise amplifier and the bandpass filter are cascaded and realized through a microstrip line; the multi-band receiver adopts direct RF sampling technology and is connected to the high-speed analog-to-digital converter through a high-speed digital interface; the high-speed analog-to-digital converter is connected to the safety isolation core in the dual-core processor through a dedicated data interface, which is used to transmit the digitized Beidou signal data directly to the safety isolation core.

[0085] In some embodiments, exemplarily, the receiving antenna can be designed with a circularly polarized microstrip antenna, and the operating frequency band covers B1I, B1C and B3I, the antenna gain is ≥3dBi, and the axial ratio is <3dB. The receiving antenna is connected to the low-noise amplifier via a coaxial cable with a characteristic impedance of 50Ω, and a π-type impedance matching network is provided between the two to ensure that the signal transmission efficiency is maximized and the noise factor is minimized. The noise figure of the low-noise amplifier is 0.6dB and the gain is 20dB. The bandpass filter can be designed by combining SAW (Surface Acoustic Wave) technology and a hairpin resonator structure to achieve signal filtering and anti-interference. The center frequencies correspond to the B1I, B1C and B3I bands, respectively, with 3dB bandwidths of 4MHz and 20MHz, respectively, insertion losses <2dB, and out-of-band suppression >40dB. The multi-band receiver adopts direct RF sampling technology, uses a high-speed analog-to-digital converter, has a sampling rate of 500MSPS, and an effective number of bits of 14. It is connected to the digital signal processing unit (FPGA) in the dual-core processor through a high-speed digital interface to achieve digital down-conversion and filtering, and convert the sampled data into baseband I / Q signals.

[0086] (2)Dual-core processor.

[0087] Reference Figure 2 The dual-core processor adopts a heterogeneous architecture, including a safety isolation core and a time synchronization core. A dedicated isolation bridge is provided between the safety isolation core and the time synchronization core of the dual-core processor. The processor is used to process the digital signal received from the Beidou signal receiving module and realize safety isolation and high-precision time synchronization. Among them, the isolation bridge adopts photoelectric isolation technology, converts the electrical signal into an optical signal through a photoelectric coupler, transmits it, and then converts it back into an electrical signal, so as to realize the electrical isolation between the safety isolation core and the time synchronization core.

[0088] The security isolation core includes: a CRC check unit, a state machine check unit, a digital signal processing unit, a cache, and a multiplexer; wherein the CRC check unit and the state machine check unit are connected to the digital signal processing unit in parallel, using a high-speed parallel bus; the cache is connected to the digital signal processing unit through a multi-port interface, supporting concurrent reading and writing; the multiplexer adopts a cross switch structure; the digital signal processing unit is connected to the Beidou signal receiving module through the dedicated data interface, for receiving digitized Beidou signal data; the multiplexer is also connected to the isolation bridge, for transmitting the data that has passed the security check to the time synchronization core; the digital signal processing unit is connected to the time slicing coordination module through the control bus, for receiving task scheduling instructions.

[0089] The time synchronization core includes: a local clock receiving unit, a time deviation calculation unit, a high-precision digitally controlled oscillator (DCO), a digital phase locked loop (DPLL) circuit, and a time output interface; wherein: the local clock receiving unit adopts a high-speed differential receiver design, including a clock buffer, a frequency divider, and a phase alignment circuit, for receiving and processing clock signals from a high-precision clock module; the local clock receiving unit is connected to the high-precision clock module for receiving a local clock reference signal; the time deviation calculation unit is connected to the safety isolation core for receiving the Beidou satellite timing signal that has passed the safety inspection; the time deviation calculation unit is connected to the DCO and DPLL circuits through a high-speed data channel; the DPLL circuit is fully digitally implemented, and the internal units are interconnected through a synchronous clock domain; the time output interface supports a variety of standard protocols and is connected to external devices through a configurable output buffer. The time synchronization core is connected to external devices through a time output interface, which supports a variety of standard protocols such as IEEE1588PTP, IRIG-B, and 1PPS.

[0090] In some embodiments, illustratively, in the safety isolation core, the CRC check unit can use the CRC-32-IEEE802.3 polynomial to support single-cycle 32-bit data CRC calculation. The state machine check unit adopts a 7-state Moore-type finite state machine with a clock frequency of 500MHz. The two units are connected in parallel to the digital signal processing unit, using a high-speed parallel bus with a width of 128 bits and a clock frequency of 500MHz. The digital signal processing unit is implemented based on a high-performance FPGA and supports complex real-time signal processing algorithms. The cache adopts a four-channel interleaved structure with a total capacity of 1MB and is connected to the digital signal processing unit through four 32-bit wide, 1GHz clock frequency multi-port interfaces. The multiplexer adopts a 64×64 full cross switch structure with an insertion loss of <0.5dB and an isolation of >80dB. In the specific implementation of the safety isolation core, the digital signal processing unit first receives the digital timing signal data from the Beidou signal receiving module through a dedicated data interface. The digital signal processing unit transmits the data to the CRC check unit and the state machine check unit respectively through a high-speed parallel bus. Among them, the CRC check unit performs CRC-32-IEEE802.3 check calculation; the state machine check unit uses a 7-state Moore type finite state machine running at a clock frequency of 500MHz to check the state of the data. The checked data is uniformly processed by the digital signal processing unit and stored in the cache. The cache realizes concurrent reading and writing through a multi-port interface. After that, the data is transmitted to the time synchronization core through an isolation bridge through a multiplexer with a cross switch structure. In this process, the digital signal processing unit maintains a connection with the time slicing coordination module through the control bus, receives and responds to task scheduling instructions.

[0091] In some embodiments, illustratively, in the time synchronization core, each unit works together to achieve high-precision time synchronization. The time deviation calculation unit uses fixed-point arithmetic and supports 64-bit precision. Its basic processing flow is: first, the timing signal data that has been security checked is compared with the local clock information to calculate the deviation between the local time and the Beidou satellite time; then a control signal is generated according to the deviation value, and it is transmitted to the DCO and DPLL circuits in real time through a high-speed data channel. The digitally controlled oscillator (DCO) is based on a fractional-N phase-locked loop structure with a frequency resolution of 0.01Hz and a phase noise better than -130dBc / Hz@1kHz offset. The DCO receives a control signal from the TOC unit and dynamically adjusts its output frequency to compensate for the detected time deviation. The output of the DCO is used as the reference clock of the DPLL, and the feedback signal of the DPLL is used to further fine-tune the output of the DCO, ultimately achieving stable clock synchronization.

[0092] Furthermore, the DPLL circuit is fully digitally implemented, including a high-speed digital phase detector, an adjustable digital loop filter, a digitally controlled oscillator, and a programmable frequency divider. The high-speed digital phase detector adopts a parallel processing architecture, and the phase detector resolution is 1ps, which is connected to the adjustable digital loop filter through a high-speed data channel. The adjustable digital loop filter can adaptively adjust the loop bandwidth in the range of 1Hz to 1kHz, and dynamically optimize the system performance according to the current time synchronization requirements. The digitally controlled oscillator in the DPLL adopts multi-bit quantization technology and is connected to the programmable frequency divider through a low-jitter clock distribution network. The programmable frequency divider dynamically adjusts the division ratio according to system requirements, so that the DPLL can adapt to different input frequencies and output requirements. The entire DPLL circuit adopts a synchronous design method, and each unit is synchronized through a clock tree network, which ensures the stability and reliability of the circuit. The DPLL can quickly lock and track the input signal while maintaining extremely low phase noise and jitter.

[0093] Furthermore, the time output interface is directly connected to the DPLL circuit, supports multiple standard protocols such as IEEE 1588PTP, IRIG-B, 1PPS, etc., and realizes level conversion and impedance matching through a configurable output buffer to ensure the integrity of the output signal. The output jitter is controlled within 100ps peak-to-peak value, and the rise time is <1ns (10%-90%), providing high-precision time synchronization signals for external devices.

[0094] (3) High-precision clock module.

[0095] The high-precision clock module includes: a dual oven-controlled crystal oscillator (DOCXO), a backup atomic clock interface, a clock switching control circuit, and a clock output unit; wherein the DOCXO is isolated from the main circuit board by a low-noise power supply and a temperature control loop; the backup atomic clock interface adopts differential signal transmission and supports hot plugging; the clock switching control circuit is implemented using FPGA and communicates with the dual-core processor through a high-speed serial interface; the clock output unit is connected to the DOCXO and the backup atomic clock interface to output the selected clock signal; the clock output unit is connected to the local clock receiving unit of the time synchronization core through a dedicated low-jitter clock channel to provide a local clock reference for the time synchronization core; the clock switching control circuit is also connected to the time synchronization core to receive clock source switching instructions and feedback switching status.

[0096] The clock switching control circuit is configured to achieve seamless switching of the backup atomic clock, wherein the switching process achieves phase continuity through a phase accumulator and a digital filter, and the switching control signal is transmitted through an optical coupler to ensure electrical isolation of the main clock source and the backup clock source.

[0097] In some embodiments, the high-precision clock module includes a dual oven controlled crystal oscillator (DOCXO), a backup atomic clock interface, and a clock switching control circuit. The module is connected to the dual-core processor via a dedicated clock bus and adopts a star topology to minimize clock deviation.

[0098] DOCXO uses Wenzel Associates' Ultra-Performance SC series, and its performance indicators are as follows: frequency stability is better than 5×10^-13 / day, and phase noise is better than -130dBc / Hz@1Hz bias. To ensure the stable operation of DOCXO, the following measures are taken: Linear Technology's LT3045 linear regulator is used to provide low-noise power supply, and its noise density is <0.8nV / √Hz@10kHz, which effectively suppresses the impact of power supply noise on DOCXO performance; the temperature control loop uses a proportional-integral-differential (PID) algorithm, and the temperature control accuracy reaches ±0.01℃, ensuring the stability of DOCXO under different ambient temperatures; an elastic support structure is used between DOCXO and the main circuit board, which further reduces the impact of external mechanical vibration on DOCXO and improves overall stability.

[0099] The design of the backup atomic clock interface takes the following aspects into consideration: LVDS differential signal transmission technology is adopted to support 10MHz reference frequency input, ensuring signal integrity and anti-interference capability; the interface circuit design is compatible with 3.3V / 2.5V / 1.8V logic levels, enhancing the flexibility and compatibility of the system; an 8kV human body model standard ESD protection circuit is integrated to improve the reliability and durability of the interface; hot-swap control logic is integrated with a response time of <100μs to facilitate system maintenance and upgrades.

[0100] The clock switching control circuit is implemented based on Xilinx Artix-7 XC7A50T FPGA and has the following features: it communicates with the dual-core processor through a high-speed serial interface (above 3.125Gbps) with a delay of <1μs, ensuring fast response and precise control; it uses a phase accumulator and a digital filter to achieve phase continuity, where the phase accumulator has a resolution of 1ps and the digital filter uses a 256-order FIR structure to ensure that the phase continuity error is <1ns; the switching control signal is transmitted through a Broadcom ACPL-M61L optical coupler, providing a 5kV isolation voltage and a transmission delay of <20ns, effectively ensuring the electrical isolation of the main clock source and the backup clock source.

[0101] The dedicated clock bus of the high-precision clock module adopts a star topology, which is specifically implemented as follows: using differential LVPECL (Low Voltage Positive Emitter Random Logic) signals, the signal's anti-interference ability and transmission quality are improved; the main clock source is located in the center of the star structure, and is connected to the two cores of the dual-core processor and other modules that require high-precision clocks through equal-length differential pairs. The length of each clock line is strictly controlled, and the maximum length difference does not exceed 0.5mm to ensure that the clock signal reaches each module synchronously; the differential pair adopts 100Ω impedance control, and the terminal matching network uses a parallel 50Ω resistor grounded configuration to minimize signal reflection and distortion; buffers are set at each clock signal branch point to maintain signal integrity and minimize the impact of fan-out load.

[0102] Through the above design, the high-precision clock module achieves clock signal edge jitter control within 1ps RMS, providing a reliable foundation for the system's high-precision time synchronization. This design not only ensures high precision and low jitter of the clock signal, but also improves the reliability and stability of the system in complex environments.

[0103] (4) Time slicing coordination module.

[0104] The time-slicing coordination module is implemented based on FPGA, including: hardware counters, status registers, time-triggered schedulers, programmable timer arrays, DMA controllers and dual-port RAM. The time-slicing coordination module also has a task feature lookup table and a hardware priority queue. Among them, the hardware counters and status registers are connected to the time-triggered scheduler through a low-latency bus; the task feature lookup table and the hardware priority queue are implemented using on-chip memory to support parallel access; the time-triggered scheduler and the programmable timer array work together through an internal high-speed interconnect bus; the DMA controller is connected to the dual-core processor through a PCIe interface to achieve high-speed data transmission. The time-triggered scheduler is connected to the safety isolation core and the time synchronization core through the control bus, is connected to the hardware counter and status register through the low-latency bus, and works in conjunction with the programmable timer array through the internal high-speed interconnect bus; the programmable timer array receives clock signals and control instructions from the time-triggered scheduler through the internal high-speed interconnect bus; the dual-port RAM is connected to the safety isolation core and the time synchronization core through a high-speed data channel for temporary storage and exchange of data; the DMA controller is connected to the dual-core processor through the PCIe interface to achieve high-speed data transmission, and is connected to the hardware priority queue through the control signal line to receive data transmission priority instructions; the time synchronization core receives the clock signal from the high-precision clock module through a dedicated clock bus, and provides the processed clock signal and synchronization information to the time-triggered scheduler through the control bus.

[0105] In some embodiments, illustratively, the time slicing coordination module can be implemented based on the Xilinx Kintex UltraScale + XCKU5P FPGA development board, with an operating clock frequency of 500MHz. The module is connected to the dual-core processor via a control bus using the AXI4 protocol, supports a multi-master and multi-slave architecture, has a bus width of 128 bits, an operating frequency of 250MHz, provides a bandwidth of up to 4GB / s, and realizes concurrent communication between modules. The core function of the time slicing coordination module is to achieve efficient task allocation and resource scheduling, thereby improving the overall performance of the system.

[0106] The module contains several key components, among which the hardware counter adopts 64-bit high-precision design with a resolution of 2ns and a maximum counting time of more than 1000 years. The Gray code structure is used to ensure reliability when multiple bits are flipped at the same time. The 128 32-bit status registers adopt a dual-port structure to support simultaneous reading and writing, with a read delay of less than 3ns and a write delay of less than 5ns. The task feature lookup table is implemented based on content-addressable memory (CAM) with a capacity of 4K×64bit, supports 256 different task types, a lookup time of less than 5ns, and power consumption of less than 0.5W. The hardware priority queue is based on a heap data structure, supports 8 levels of priority, can manage 1024 tasks at the same time, uses a parallel comparator array, and the delay of enqueue / dequeue operations is less than 10ns.

[0107] The time-triggered scheduler uses a hybrid algorithm of polling and shortest job first. The scheduling period is configurable, with a minimum of 10μs. It supports dynamic time slice allocation, ranging from 100μs to 10ms, with a step of 1μs. The programmable timer array contains 64 independent high-precision timers with a resolution of 10ns, supporting single trigger and periodic trigger modes, and a maximum timing range of 1 hour. The DMA controller supports 8 independent channels, with a maximum transfer rate of 10GB / s for each channel. It uses a descriptor linked list structure and supports scatter-gather transfer mode. The dual-port RAM uses 18Mb high-speed SRAM with an access delay of less than 2ns, supporting true dual-port simultaneous read and write without conflict.

[0108] The internal interconnection of the module adopts an efficient bus structure. The hardware counter and status register are connected to the FPGA core through the AXI4-Lite bus (32-bit width, 250MHz clock), and the single read and write delay is less than 20ns. The task feature lookup table and hardware priority queue are implemented using the FPGA on-chip Block RAM, which supports 2 parallel accesses per clock cycle and a total bandwidth of 64GB / s. The time-triggered scheduler and programmable timer array work together through the AXI4-Stream bus (128-bit width, 500MHz clock), providing up to 64GB / s of internal data transmission capacity. The DMA controller is connected to the dual-core processor through the PCIe Gen4 x8 interface, with a theoretical maximum bandwidth of 64GB / s and an actual continuous transfer rate of more than 50GB / s.

[0109] In addition, in some embodiments, the device of the present application also includes a non-volatile memory, a power management unit, and a multi-interface input / output module; wherein the non-volatile memory adopts a dual backup structure and is connected to the dual-core processor through an independent storage controller; the power management unit adopts multi-stage DC-DC conversion and provides independent and isolated power supply for each module through a star topology; the multi-interface input / output module supports a configurable protocol stack and communicates with the dual-core processor through a high-speed serial interface.

[0110] It should be noted that the examples introduced above are only used as examples. In actual applications, other components with similar functions and appropriate numerical ranges can be used to implement them, and this application does not limit this.

[0111] In summary, the time synchronization device based on Beidou satellite timing signal security isolation in the embodiment of the present application has the following beneficial effects:

[0112] 1. Improved the security of Beidou satellite timing signal processing: The present invention adopts a dual-core processor architecture and realizes physical isolation of the security isolation core and the time synchronization core through a dedicated isolation bridge. The isolation bridge adopts photoelectric isolation technology, which realizes physical isolation while ensuring high-speed data transmission, effectively preventing potential security threats.

[0113] 2. Optimized resource scheduling efficiency: The time-slicing coordination module is implemented based on FPGA and includes components such as hardware counters, hardware priority queues, and time-triggered schedulers, which significantly improves the system's real-time task processing capabilities and resource utilization efficiency.

[0114] 3. Achieved efficient inter-module communication: The high-speed data bus with multi-layer PCB design and the control bus with multi-master and multi-slave architecture support concurrent communication between modules and improve the overall data transmission efficiency of the system.

[0115] 4. Improved time synchronization accuracy: The high-precision clock module uses a dual oven-controlled crystal oscillator (DOCXO) and a backup atomic clock interface, combined with a digital phase-locked loop (DPLL) circuit to achieve high-precision time synchronization. The loop bandwidth of the DPLL circuit can be adaptively adjusted in the range of hertz to kilohertz, further optimizing the synchronization performance.

[0116] Reference Figure 4 Another aspect of the embodiment of the present application further provides a time synchronization method based on the time synchronization device based on the Beidou satellite timing signal security isolation, the method comprising the following steps S100-S500:

[0117] Step S100, receiving an initial timing signal transmitted by a Beidou satellite through a Beidou signal receiving module, digitizing the initial timing signal, obtaining first timing signal data, and sending the first timing signal data to a security isolation core of a dual-core processor;

[0118] Step S200, receiving the first timing signal data through the security isolation core, performing a security check on the first timing signal data, and sending the checked first timing signal data to the time synchronization core of the dual-core processor;

[0119] Step S300, sending local clock information to the time synchronization core through a high-precision clock module;

[0120] Step S400, performing time synchronization processing according to the received first timing signal and the local clock information through the time synchronization core;

[0121] Step S500: Coordinate the scheduling of the high-precision clock module and the dual-core processor through a time slicing coordination module.

[0122] In some embodiments, the method may also include but is not limited to the following steps S600 to S800:

[0123] Step S600, storing the configuration information and log data of the dual-core processor via a non-volatile memory;

[0124] Step S700, supplying power to each power-consuming module in the time synchronization device based on Beidou satellite timing signal security isolation through the power management unit;

[0125] Step S800, realizing the communication among the modules in the time synchronization device based on the Beidou satellite timing signal security isolation through a multi-interface input and output module.

[0126] It can be understood that the beneficial effects achieved by the above method embodiments are the same as the beneficial effects achieved by the above device embodiments.

[0127] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0128] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0129] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0130] Those skilled in the art will appreciate that all or some of the steps, systems, devices, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0131] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0132] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0133] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0134] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0135] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0136] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0137] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A time synchronization device based on the safe isolation of Beidou satellite timing signals, characterized in that: The device comprises: Beidou signal receiving module, dual-core processor, high-precision clock module and time-slicing coordination module; Wherein, the dual-core processor includes a security isolation core and a time synchronization core; an isolation bridge is provided between the security isolation core and the time synchronization core; The Beidou signal receiving module is connected to the security isolation core through a dedicated data interface; The high-precision clock module is connected to the time synchronization core via a dedicated clock bus; The time slicing coordination module is connected to the dual-core processor via a control bus.

2. The device according to claim 1, characterized in that The Beidou signal receiving module comprises: Beidou satellite signal receiving antenna, low noise amplifier, bandpass filter, multi-band receiver and high-speed analog-to-digital converter; Wherein, the Beidou satellite signal receiving antenna is connected to the low noise amplifier via a coaxial cable; An impedance network is provided between the Beidou satellite signal receiving antenna and the low noise amplifier; The low noise amplifier is cascade-connected to the bandpass filter via a microstrip line; The multi-band receiver is connected to a high-speed analog-to-digital converter via a high-speed digital interface; The high-speed analog-to-digital converter is connected to the safety isolation core via a dedicated data interface.

3. The device according to claim 1, characterized in that The security isolation core includes: CRC check unit, state machine check unit, digital signal processing unit, cache and multiplexer; Wherein, the CRC check unit and the state machine check unit are connected in parallel to the digital signal processing unit; The cache is connected to the digital signal processing unit via a multi-port interface; The multiplexer adopts a cross switch structure; The digital signal processing unit is connected to the Beidou signal receiving module via the dedicated data interface; The multiplexer is connected to the isolation bridge; The digital signal processing unit is connected to the time slicing coordination module via a control bus.

4. The device according to claim 1, characterized in that The time synchronization core comprises: Local clock receiving unit, time deviation calculation unit, digital controlled oscillator, digital phase locked loop circuit and time output interface; Wherein, the local clock receiving unit is connected to the high-precision clock module; The time deviation calculation unit is connected to the safety isolation core; The time deviation calculation unit is connected to the digital controlled oscillator and the digital phase locked loop circuit via a high-speed data channel; The output end of the digital controlled oscillator is connected to the input end of the digital phase locked loop; The time output interface is connected to the digital phase locked loop circuit and is connected to an external device through an output buffer.

5. The device according to claim 1, characterized in that The high-precision clock module comprises: Dual oven-controlled crystal oscillators, spare atomic clock interface, clock switching control circuit, clock output unit; Wherein, the dual constant temperature crystal oscillator is isolated from the main circuit board by a low noise power supply and a temperature control loop; The clock switching control circuit communicates with the dual-core processor via a high-speed serial interface; The clock output unit is connected to the dual oven controlled crystal oscillator and the backup atomic clock interface; The clock output unit is connected to the local clock receiving unit of the time synchronization core through a dedicated low-jitter clock channel; The clock switching control circuit is connected to the time synchronization core.

6. The device according to claim 1, characterized in that The time slicing coordination module includes: Hardware counters, status registers, task signature lookup tables, hardware priority queues, time-triggered schedulers, programmable timer arrays, DMA controllers, dual-port RAM, and on-chip memory; Wherein, the hardware counter and the status register are connected to the time-triggered scheduler via a low-latency bus; The task feature lookup table and the hardware priority queue are implemented using on-chip registers; The time-triggered scheduler works in coordination with the programmable timer array via an internal high-speed interconnect bus; The dual-port RAM is connected to the security isolation core and the time synchronization core through a high-speed data channel; The DMA controller is connected to the dual-core processor via a PCIe interface; the DMA controller is also connected to the hardware priority queue via a control signal line; The time-triggered scheduler is connected to the time synchronization core via a control bus.

7. The device according to claim 4, characterized in that The digital phase locked loop comprises: High-speed digital phase detector, adjustable digital loop filter, digitally controlled oscillator and programmable frequency divider; Wherein, the high-speed digital phase detector is connected to the adjustable digital loop filter through a high-speed data channel; The digitally controlled oscillator is connected to the programmable frequency divider through a low-jitter clock distribution network.

8. The device according to any one of claims 1 to 7, characterized in that: The device also includes: Non-volatile memory, power management unit and multi-interface input and output modules; Wherein, the non-volatile memory adopts a dual-backup structure and is connected to the dual-core processor through an independent storage controller; The power management unit is connected to each module that needs power supply through a star topology; The multi-interface input and output module is connected to the dual-core processor via a high-speed serial interface.

9. A time synchronization method based on the time synchronization device for safe isolation of Beidou satellite timing signals according to claim 1, characterized in that: The method comprises the following steps: Receive an initial timing signal transmitted by a Beidou satellite through a Beidou signal receiving module, digitize the initial timing signal, obtain first timing signal data, and send the first timing signal data to the security isolation core of the dual-core processor; receiving the first timing signal data through the security isolation core, performing a security check on the first timing signal data, and sending the checked first timing signal data to the time synchronization core of the dual-core processor; Sending local clock information to the time synchronization core through a high-precision clock module; Performing time synchronization processing according to the received first timing signal and the local clock information through the time synchronization core; The scheduling of the high-precision clock module and the dual-core processor is coordinated through a time slicing coordination module.

10. The method according to claim 9, characterized in that The method further comprises the following steps: Storing the configuration information and log data of the dual-core processor via a non-volatile memory; Power is supplied to each power-consuming module in the time synchronization device based on the safe isolation of Beidou satellite timing signals through the power management unit; The communication of each module in the time synchronization device based on the safe isolation of Beidou satellite timing signals is realized through a multi-interface input and output module.

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