PCI device control method and device, storage medium and electronic device

Abstract

An embodiment of the present application provides a control method and apparatus for a PCI device, a storage medium, and an electronic device, relating to the field of computers, including: in response to a first trigger operation on a target component on a control panel of a target server, the target component enters an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link; a second processing unit, configured to set the interrupt status bit of the target system interrupt signal of the target PCI link to 1 in response to the target component entering the activated state; a search unit, configured to determine a target slot position of a target PCI device connected to the target PCI link by searching a system configuration file of an operating system, wherein the system configuration file is used to describe the CPU location information of the target server, and the CPU location information includes configuration information of the PCI link; and a hot removal unit, configured to perform a hot removal operation on the target PCI device based on the target slot position.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a method and apparatus for controlling a PCI device, a storage medium, and an electronic device. Background Art

[0002] In the server field, the core components of the server are CPU, memory, NVME hard disk and other devices. In addition, PCI interface devices are also required, such as PCI network card, PCI RAID card, PCI GPU card, PCI interface accelerator card, etc. These components are combined in the server configuration to form different configuration models, and the applicable scenarios are also different.

[0003] When using the terminal to operate various devices, for example, if the server's storage medium NVME hard disk encounters a failure during use, the hot-swap function of the NVME hard disk can be used to unplug the failed hard disk and insert a new hard disk to replace it, ensuring that the server does not need to be powered off and disassembled for replacement; or if the server is configured with a large amount of memory and in actual business applications, due to excessive memory energy consumption or low usage, the memory controller can be controlled to shut down the redundant and unused memory to reduce the overall power consumption of the server or extend the server's memory life.

[0004] For example, when using a network card, especially an OCP network card, hot-swap functionality must be supported based on actual usage. However, in actual use, in addition to the aforementioned devices, other PCI devices also need to support and implement similar hot-swap functionality, such as hot-swap functionality for GPU cards, PCI network cards, and PCI RAID cards.

[0005] In related technologies, memory resources are usually reserved in advance for devices that need to implement hot-swappable functions. However, this method is not suitable for PCI network card devices, and the hot removal function of some PCI devices cannot be realized, resulting in a technical problem of poor flexibility in the control process of PCI devices.

[0006] In the related art, there is no effective solution to the problem of poor flexibility in the control process of PCI devices. Summary of the Invention

[0007] The embodiments of the present application provide a method and apparatus for controlling a PCI device, a storage medium, and an electronic device, so as to at least solve the problem of poor flexibility that occurs during the control process of the PCI device.

[0008] According to one embodiment of the present application, a method for controlling a PCI device is provided, comprising: in response to a first trigger operation on a target component on a control panel of a target server, the target component enters an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link, and the target system interrupt signal is used to control and notify the operating system of the target server of the event status of a PCI device hot removal event; in response to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1; by searching a system configuration file of the operating system, a target slot position of a target PCI device connected to the target PCI link is determined, wherein the system configuration file is used to describe the CPU position information of the target server, the CPU position information includes configuration information of a PCI link connected to the CPU, the configuration information of the PCI link includes the slot number of each PCI slot in the PCI link and device information of a PCI device inserted into the PCI slot with each slot number, and each PCI slot corresponds to a system interrupt signal; and based on the target slot position, a hot removal operation is performed on the target PCI device.

[0009] In an exemplary embodiment, in response to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1, including: in response to the target component entering the activated state, the general input and output signal on the control panel is set to a high level; in response to the general input and output signal being set to a high level, the interrupt status bit of the target system interrupt signal that controls the target PCI link is set to 1.

[0010] In an exemplary embodiment, the above-mentioned determining the slot position of the target PCI device connected to the target PCI link by searching the system configuration file of the operating system includes: in response to the interrupt status bit of the system interrupt signal of the target PCI link being set to 1, calling the system configuration file of the ACPI protocol, wherein the ACPI protocol is used by the operating system to automatically configure hardware and provide power management functions; obtaining status information of the status register of the system interrupt signal corresponding to each PCI link by searching the system configuration file; and determining the target slot position of the target PCI device connected to the target PCI link based on the status information of the status register of the system interrupt signal corresponding to each PCI link.

[0011] In an exemplary embodiment, the above-mentioned determination of the target slot position of the target PCI device connected to the target PCI link based on the status information of the status register of the system interrupt signal corresponding to each PCI link includes: determining the target status information of the target status register corresponding to the target PCI link from the status information of the status register; when the target status information indicates that the target status register corresponding to the target PCI link is set, determining the target PCI slot where the target PCI device is located from multiple PCI slots included in the target PCI link based on the target status information; and determining the slot position where the target PCI slot is located as the target slot position.

[0012] In an exemplary embodiment, after the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1 in response to the target component entering the activated state, the above method also includes: in response to the interrupt status bit of the target system interrupt signal of the target PCI link being set to 1, triggering the call of the system configuration file of the ACPI protocol.

[0013] In an exemplary embodiment, the above method also includes: in a case where the target PCI device connected to the target PCI link includes a first PCI device and a second PCI device, performing at least one of the following: in response to a second trigger operation on a first component on the control panel, the first component enters an activated state, wherein the first component is connected to a first system interrupt signal of the first PCI link; in response to the first component entering the activated state, the interrupt status bit of the first system interrupt signal is set to 1; by searching a system configuration file of the operating system, determining the first slot position of the first PCI device connected to the first PCI link, and performing a hot removal operation on the first PCI device based on the first slot position; or in response to a third trigger operation on a second component on the control panel, the second component enters an activated state, wherein the second component is connected to a second system interrupt signal of the second PCI link. In response to the second component entering the activated state, the interrupt status bit of the second system interrupt signal is set to 1; by searching the system configuration file, the second slot position of the second PCI device connected to the second PCI link is determined, and based on the second slot position, a hot removal operation is performed on the second PCI device; or in response to the fourth trigger operation on the first component and the fifth trigger operation on the second component, the first component and the second component enter the activated state; in response to the first component and the second component entering the activated state, the interrupt status bit of the first system interrupt signal and the interrupt status bit of the second system interrupt signal are both set to 1; by searching the system configuration file, the first slot position of the first PCI device and the second slot position of the second PCI device are determined, and based on the first slot position and the second slot position, a hot removal operation is performed on the first PCI device and the second PCI device.

[0014] In an exemplary embodiment, the above method also includes: when the target server is running and the target component has not entered the activated state, in response to two consecutive trigger operations on the target component, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 0; in response to the interrupt status bit of the target system interrupt signal being set to 0, restarting the target server.

[0015] According to another embodiment of the embodiment of the present application, a control device for a PCI device is also provided, including: a first processing unit, for responding to a first trigger operation on a target component on a control panel of a target server, the target component entering an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link, and the target system interrupt signal is used to control and notify the operating system of the target server of the event status of a PCI device hot removal event; a second processing unit, for responding to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link being set to 1; a search unit, for determining a target slot position of a target PCI device connected to the target PCI link by searching a system configuration file of the operating system, wherein the system configuration file is used to describe the CPU location information of the target server, the CPU location information includes configuration information of a PCI link connected to the CPU, the configuration information of the PCI link includes the slot number of each PCI slot in the PCI link and device information of a PCI device inserted into the PCI slot with each slot number, and each PCI slot corresponds to a system interrupt signal; and a hot removal unit, for performing a hot removal operation on the target PCI device based on the target slot position.

[0016] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when running.

[0017] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0018] According to another embodiment of the present application, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0019] By adopting the above-mentioned embodiment provided by the present application, an operable target component is added to the control panel of the target server, and after the server is started and enters the operating system, the SCI interrupt signal of the corresponding PCI link is enabled by triggering the target component, and then the target slot position of the target PCI device connected to the target PCI link is determined by searching the system configuration file of the operating system, so as to perform a hot removal operation on the target PCI device at the target slot position. In other words, the embodiment of the present application adopts the method of physically introducing the target component into the control panel, and by physically connecting the target component with the SCI interrupt signal of the PCI link, the hot removal function of each device connected to the PCI link is controlled, which not only improves the accuracy of the hot removal operation of the PCI device, but also enhances the flexibility of the control of the PCI device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 This is a hardware structure block diagram of a server device according to a method for controlling a PCI device according to an embodiment of the present application;

[0022] Figure 2 is a flow chart of an optional method for controlling a PCI device according to an embodiment of the present application;

[0023] Figure 3 This is a physical connection diagram of an optional control panel and SCI signal according to an embodiment of the present application;

[0024] Figure 4 This is a physical connection diagram of an optional button and GPIO pin according to an embodiment of the present application;

[0025] Figure 5 is a code diagram of an optional ACPI protocol according to an embodiment of the present application;

[0026] Figure 6 is a code diagram of another optional ACPI protocol according to an embodiment of the present application;

[0027] Figure 7 This is a physical connection diagram of an optional button and power signal according to an embodiment of the present application;

[0028] Figure 8 is an overall flow chart of an optional PCI device control method according to an embodiment of the present application;

[0029] Figure 9is a schematic diagram of an optional interaction process between a server, an operating system, and a control panel according to an embodiment of the present application;

[0030] Figure 10 is a structural block diagram of a control device for a PCI device according to an embodiment of the present application;

[0031] Figure 11 It is a schematic structural diagram of an optional electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0034] The control method embodiment of the PCI device provided in the embodiment of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a server device of a PCI device control method according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown) a processor 102 (the processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data, wherein the above-mentioned server device may also include a transmission device 106 for communication functions and an input and output device 108. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0035] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the control method of the PCI device in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to a server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0036] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by a communication provider of the server device. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0037] Glossary:

[0038] BIOS: Basic Input Output System, basic input and output system;

[0039] CPU: Central Processing Unit, referred to as CPU;

[0040] X86: The X86 architecture, mainly refers to processors from Intel and AMD manufacturers;

[0041] RAS: Reliability, Availability, and Serviceability.

[0042] PCI: Peripheral Component Interconnect;

[0043] RC:Root Complex;

[0044] EP:Endpoint;

[0045] PCIEx1 slot: The theoretical maximum bandwidth is 1GB / s;

[0046] PCIEx4 slot: Theoretical maximum bandwidth is 4GB / s;

[0047] PCIEx8 slot: Theoretical maximum bandwidth is 8GB / s;

[0048] PCIEx16 slot: Theoretical maximum bandwidth is 16GB / s;

[0049] Slot: PCIE bandwidth slot identifier;

[0050] ACPI: Advanced Configuration and Power Management Interface, Advanced Configuration and Power Management Interface;

[0051] OSPM:OS Power Management;

[0052] NVME: Non Volatile Memory Express, non-volatile memory host controller interface;

[0053] RAID: Redundant Array of Independent Disks, Redundant Array of Independent Disks;

[0054] OCP: Open Compute Project Network Card;

[0055] DSDT: Differentiated System Description Table, the main table containing most of the hardware information;

[0056] SCI: System Control Interrupt, a system control interrupt used to notify the operating system of ACPI events;

[0057] GPIO: General-purpose input / output, general-purpose input and output;

[0058] ACPI: used to notify the operating system of ACPI events;

[0059] Control panel: A key control panel used to control the hot-swap function of PCI devices under the operating system.

[0060] In order to solve the above problems existing in the related art, a control method for a PCI device is provided in this embodiment, and its execution subjects include but are not limited to the client and the server motherboard, etc. Figure 2 As shown, the process includes the following steps S202-S208:

[0061] Step S202: In response to a first triggering operation on a target component on a control panel of a target server, the target component enters an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link, and the target system interrupt signal is used to control and notify an operating system of the target server of an event status of a PCI device hot removal event;

[0062] Step S204: in response to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1;

[0063] Step S206: Determine the target slot location of the target PCI device connected to the target PCI link by searching a system configuration file of the operating system, wherein the system configuration file is used to describe the CPU location information of the target server, the CPU location information includes configuration information of the PCI link connected to the CPU, the PCI link configuration information includes the slot number of each PCI slot in the PCI link and device information of the PCI device inserted into each PCI slot with the slot number, and each PCI slot corresponds to a system interrupt signal;

[0064] Step S208: performing a hot removal operation on the target PCI device based on the target slot location.

[0065] In order to better understand the control method of the above-mentioned PCI device, the following first briefly introduces the connection relationship between the control panel, CPU, PCI link connected to the CPU, and SCI signal (which can also be understood as system interrupt) in the target server in the embodiment of the present application.

[0066] like Figure 3 As shown, the server motherboard is the core component of the server, responsible for connecting and supporting various hardware devices on the server. Servers typically integrate various hardware devices, including the CPU (Central Processing Unit), memory, network adapters, and disk controllers. The control panel, typically a standalone hardware device, connects to the server motherboard via a network or other communication interface, or connects to the CPU via the system bus, enabling remote management and monitoring of the server.

[0067] like Figure 4As shown, in this embodiment, by adding a target component to the control panel of the target server, for example, adding a set of buttons, the SCI signal of the PCI link on the CPU side is physically connected to the GPIO signal of the GPIO chip on the control panel side. Therefore, when at least one button in the set of buttons is pressed, the state value of the GPIO pin corresponding to the SCI interrupt signal controlled by the control panel of the PCI link is set to a high level, thereby triggering the system interrupt signal of the target PCI link in the operating system. In other words, one button corresponds to one physical GPIO pin, and then one GPIO signal is connected to one SCI signal (which can also be understood as one system interrupt signal) of the PCI link on the CPU side.

[0068] When the target component is a button, if the button is pressed, the GPIO signal can be pulled high. Through the above physical connection method, in response to the GPIO signal being high, the interrupt status bit of the SCI signal on the corresponding PCI link is set to 1, then the PCI device connected to the PCI link supports the hot removal function under the system.

[0069] On the contrary, if the originally pressed button pops up, it means that the GPIO signal is pulled low. In response to the GPIO signal being low, the interrupt status bit of the SCI signal on the corresponding PCI link is set to 0, then the PCI device connected to the PCI link supports the hot plug-in function under the system.

[0070] Except for Figure 4 In addition to connecting the target component (button) to the GPIO pin of the GPIO chip as shown, you can also use Figure 7 As shown in , physical connection is directly made between the button and the power signal to realize physical control of each button.

[0071] Furthermore, each slot in the PCI link corresponds to a single SCI signal. Therefore, using this physical design, the hot-swap function of a PCI device inserted into a slot can be indirectly controlled by triggering a button. In other words, hot removal of a PCI device can be indirectly controlled by triggering the control panel.

[0072] Obviously, the above-mentioned target component can be, but is not limited to, a mechanical or touch-type button, and the embodiment of the present application does not limit this.

[0073] It's important to note that the PCI link on the CPU side of a server refers to the connection between the server's central processing unit (CPU) and the Peripheral Component Interconnect (PCI) bus. PCI links can be used, but are not limited to, to connect the CPU to various peripheral devices, such as graphics cards, network cards, and storage devices. These are connected to the server motherboard via PCI slots or dedicated PCIe (PCI Express) slots.

[0074] A server architecture can include, but is not limited to, multiple PCI links. PCI links refer to the PCI Express (PCIe) bus connections within the server. These connections connect the server's CPU to other hardware devices, such as graphics cards, network cards, and storage devices. Each PCI link provides one or more data channels, allowing high-speed data transfer between devices.

[0075] A PCIe link on a server motherboard can be split into multiple slots, allowing multiple devices to share the bandwidth of the same link. This split is usually achieved through a PCIe switch or switch, which can provide multiple PCIe ports, each port corresponding to a slot, and each slot allows a PCI device to be inserted. These devices share the resources of the PCI bus through the bus they are on.

[0076] The above-mentioned SCI signal is at a high level, indicating that the SCI interrupt is active. The system interrupt signal is used by the hardware to notify the operating system about ACPI (Advanced Configuration and Power Interface) events. In an embodiment of the present application, the system interrupt signal is used to control and notify the operating system of the target server whether the hot removal function of the PCI device is activated.

[0077] The above method is adopted to add an operable target component to the control panel of the target server, and after the server starts and enters the operating system, the SCI interrupt signal of the corresponding PCI link is enabled by triggering the target component. Then, by searching the system configuration file of the operating system, the target slot position of the target PCI device connected to the target PCI link is determined, so as to perform a hot removal operation on the target PCI device at the target slot position. In other words, the embodiment of the present application adopts the method of physically introducing the target component into the control panel, and by physically connecting the target component with the SCI interrupt signal of the PCI link, the hot removal function of each device connected to the PCI link is controlled, which not only improves the accuracy of the hot removal operation of the PCI device, but also enhances the flexibility of the control of the PCI device.

[0078] In an exemplary embodiment, in response to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1, including:

[0079] In response to the target component entering the activated state, the general input / output signal on the control panel is set to a high level;

[0080] In response to the general purpose input output signal being set to a high level, the interrupt status bit of the target system interrupt signal that controls the target PCI link is set to 1.

[0081] During physical design, the CPU-side PCI link's SCI signals must be physically connected to the control panel-side GPIO chip's GPIO signals. Furthermore, because the PCI link supports a maximum bandwidth of x16 by default and is backward compatible with x8, x4, x2, and x1 PCI devices, the GPIO signals must be physically connected to the SCI signals on the minimum x1 bandwidth pins.

[0082] The above physical design scheme is set for one PCI slot. If a PCI link is split into multiple slots, it is necessary to design the SCI signal of the PCI link on the minimum bandwidth link of each PCI slot and physically connect it to the GPIO pin of the CPU expansion GPIO chip.

[0083] Each PCI slot requires a physical connection between the GPIO signal of a GPIO chip on the control panel and the SCI signal of the PCI link on the CPU, as SCI signals are supported on every PCI link. Furthermore, each button on the server's front control panel corresponds to a physical GPIO signal. When pressed, the GPIO signal is pulled high; if it is released, the GPIO signal is pulled low. A high GPIO signal indicates hot-plug functionality, while a low GPIO signal indicates hot-plug functionality.

[0084] In this way, the control panel can indirectly control the SCI signal of the PCI link on the CPU side by setting the pin status of the GPIO chip through buttons, thereby physically supporting the conditions for triggering the SCI interrupt enable.

[0085] like Figure 3 As shown, the PCI link connected to CPU0 includes slots Slot0, Slot* and SlotN. The system interrupt signal corresponding to slot Slot0 is SCI0, the system interrupt signal corresponding to Slot* is SCI*, and the system interrupt signal corresponding to SlotN is SCIN.

[0086] At the same time, key Slot0 is used to control system interrupt signal SCI0, key Slot* is used to control system interrupt signal SCI*, and key SlotN is used to control system interrupt signal SCIN. When key Slot0 is pressed (which can also be understood as key Slot0 being activated), the enable bit of system interrupt signal SCI0 is set to a high level. In response to the enable bit of system interrupt signal SCI0 being set to a high level, the interrupt status bit of system interrupt signal SC10 is set to 1.

[0087] Similarly, when the key Slot* is pressed (which can also be understood as the key Slot* being activated), the enable bit of the system interrupt signal SCI* is set to a high level. In response to the enable bit of the system interrupt signal SCI* being set to a high level, the interrupt status bit of the system interrupt signal SCI* is set to 1. Similarly, when the key SlotN is pressed, the interrupt status bit of the system interrupt signal SCIN is set to 1.

[0088] Through the above method, the control panel of the target server is connected to the GPIO chip through the control board I2C to realize the transmission of key signals, thereby improving the efficiency of signal transmission. In scenarios where space is limited or lightweight design is required, this connection method can provide a simpler and more efficient hot-swap solution.

[0089] In an exemplary embodiment, the above-mentioned determining the slot location of the target PCI device connected to the target PCI link by searching the system configuration file of the operating system includes:

[0090] In response to an interrupt status bit of a system interrupt signal of a target PCI link being set to 1, calling a system configuration file of an ACPI protocol, wherein the ACPI protocol is used by an operating system to automatically configure hardware and provide a power management function;

[0091] By searching the system configuration file, the status information of the status register of the system interrupt signal corresponding to each PCI link is obtained;

[0092] Based on the status information of the status register of the system interrupt signal corresponding to each PCI link, the target slot position where the target PCI device connected to the target PCI link is located is determined.

[0093] After the target server is powered on and the operating system boots normally, a button is set for the PCI device that needs to be hot-removed under the system. At this time, when the button is pressed, the corresponding GPIO signal output is a high signal and the SCI interrupt of the corresponding PCI link is enabled. At the same time, the corresponding SCI interrupt status register is set to 1. At this time, the DSDT table of the ACPI protocol of the operating system reads the status register of the SCI interrupt. Since the button is set to enable the SCI interrupt, the SCI status register of the corresponding PCI link is automatically set to 1 and only takes effect under the operating system. The operating system that supports OSPM triggers the hot removal function of the PCI device of the corresponding PCI link, realizing the functional design of hot-unplugging the PCI device under the system.

[0094] The Differentiated System Description Table (DSDT), which can also be understood as a system configuration file, defines the location of the CPU and the port corresponding to the PCI slot number. For hot removal, when an SCI interrupt is triggered, OSPM calls the EJ0 control method to immediately remove the PCI device associated with the PCI link that caused the SCI interrupt. After calling EJ0, OSPM verifies that the device no longer exists and determines whether the hot removal was successful.

[0095] It should be noted that after the status information of the status register of the SCI interrupt is read by calling the DSDT table of the ACPI protocol, the target slot position where the target PCI device is located is determined according to the status information of the read status register.

[0096] That is to say, because the SCI interrupt trigger will call the function setting of the ACPI DSDT table, it can support the hot removal function of the PCI device under the operating system, wherein the ACPI protocol code includes but is not limited to the following: Figure 5 and Figure 6 shown.

[0097] like Figure 5 As shown, each PCI device is assigned a relative offset address (ADR). For example, the offset address is calculated relative to the address of the instruction following the current instruction. Using the ADR instruction, you can load the address of a label into a register. This instruction is useful when you need to reference data or other instruction addresses, such as when setting up jump tables, referencing static data, or initializing function pointers.

[0098] pass Figure 5 and Figure 6It can be seen that since the button is set to enable the SCI status register of the corresponding PCI link when the SCI interrupt is enabled, after the button is triggered, according to the status value (0 or 1) of the queried status register (for example, EJ0), it is possible to determine which PCI link on the CPU side is the target PCI link, and determine the target slot position of the target PCI device connected to the PCI link.

[0099] By adding an interrupt status register, the interrupt status during the hot-swap process can be more accurately recorded and managed, providing powerful data support for device troubleshooting and performance optimization. This also allows electronic devices to achieve a higher level of hot-swap functionality, providing users with a safer, more efficient, and user-friendly environment.

[0100] In an exemplary embodiment, determining the target slot location of the target PCI device connected to the target PCI link based on the status information of the status register of the system interrupt signal corresponding to each PCI link includes:

[0101] Determine target state information of a target state register corresponding to the target PCI link from the state information of the state register;

[0102] In a case where the target status information indicates that the target status register corresponding to the target PCI link is set, determining a target PCI slot where the target PCI device is located from a plurality of PCI slots included in the target PCI link based on the target status information;

[0103] The slot position where the target PCI slot is located is determined as the target slot position.

[0104] In an embodiment of the present application, after entering the operating system through server startup, a physical connection is made through the high and low level states of the GPIO output signals corresponding to the buttons on the control panel. After entering the operating system, the enable bit control of the SCI interrupt of the PCI link is realized, thereby triggering the status register update of the SCI interrupt under the operating system.

[0105] The OSPM of the operating system actively polls and determines which specific PCI link the register of the SCI interrupt comes from, thereby realizing the device hot removal function of the PCI link under the system.

[0106] The technical solution of this application is applicable to operating systems that support the OSPM function and has universal applicability. Its core lies in controlling the high and low level status signals of the GPIO of the physical connection that enables the SCI interrupt of the PCI link. By pressing the button of the control panel, it is connected to the high output state of the GPIO of the GPIO chip, and then the state value of the GPIO pin corresponding to the SCI interrupt is high, thereby triggering the enablement of the SCI interrupt.

[0107] OSPM controls the hot removal of the corresponding PCI link by changing the SCI interrupt status register. This is achieved by entering an OSPM-enabled operating system during server startup and physically connecting the PCI link's SCI interrupt enable signal to a high-output GPIO pin on a physically linkable GPIO chip using a button on the physical control panel. This allows hot removal of PCI peripheral devices that support the PCI interface under the operating system.

[0108] It should be noted that this application uses a physical method to introduce the buttons of the control panel, and physically connects the GPIO pins of the GPIO chip in the control panel with the SCI interrupt enable signal of the PCI link. After the server starts and enters the operating system, the SCI interrupt enable signal of the corresponding PCI link is physically connected with the high and low level states of the GPIO signal through the button to realize the enable setting of the SCI interrupt.

[0109] Use an OSPM-capable operating system to poll the SCI interrupt status register of each PCI link to see if it has been used, that is, if it is set to 1 (for example, Figure 6 If EJ0 is 1, the PCI device of the corresponding PCI link is hot-plugged; if it is 0, the PCI device of the PCI link can continue to be used.

[0110] At the same time, if you need to adjust the hot removal function of other PCI devices, you need to restart the server and press the same button again on the control panel, that is, set the SCI interrupt enable to a low level or reload a PCI device, you need to restart and press the button of the SCI interrupt connection of the corresponding PCI link again.

[0111] Through the above method, the hot removal or hot insertion function of the PCI link can be realized without powering off and disassembling the server's hardware devices. At the same time, the hot plugging of PCI devices under the system can be realized without restarting the server. It also supports the hot plugging function of other PCI devices except traditional hard disk devices and OCP network card devices.

[0112] The embodiment of the present application adopts an operating system that supports the OSPM function, and detects and responds to changes in the SCI interrupt status register on the PCI link through the ACPI protocol to control the hot plugging of PCI devices. Through the operating system's support for hot plugging operations, intelligent management of PCI devices can be achieved, thereby improving the system's resource utilization and operating efficiency.

[0113] In an exemplary embodiment, after the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1 in response to the target component entering the activated state, the method further includes:

[0114] In response to the interrupt status bit of the target system interrupt signal of the target PCI link being set to 1, the system configuration file of the ACPI protocol is triggered to be called.

[0115] In order to understand the control method of the above PCI device more clearly, the following Figure 8 The overall flow chart shown further explains it.

[0116] S802, the server is powered on but not started;

[0117] At this time, each button on the control panel is physically connected to the SCI interrupt signal of a PCI link. For details, please refer to Figure 3 shown.

[0118] S804, start the server;

[0119] After starting the server, enter the server's operating system.

[0120] S806, determining whether the key connected to the PCI link SCI interrupt signal is pressed;

[0121] If pressed, execute step S808; otherwise, execute step S812.

[0122] S808, the PCI link SCI interrupt enable bit is set to a high level;

[0123] If the SCI interrupt enable bit is high, it determines that the SCI interrupt is triggered.

[0124] S810, the PCI link SCI interrupt status bit is set to 1;

[0125] S812, the PCI link SCI interrupt enable bit is set to 0 and the SCI status bit remains 0;

[0126] S814, by calling the DSDT table of ACPI, determine whether the interrupt status register in the SCI corresponding to each PCI link is set;

[0127] If it is set, execute step S816; otherwise, execute step S818.

[0128] Among them, it is possible but not limited to using the operating system's OSPM to actively poll and determine whether the SCI interrupt register is updated. If updated, determine which PCI link the SCI interrupt register comes from, and then implement the device hot removal function of the PCI link under the system, such as step S816.

[0129] S816, using the EJ0 method of OSPM of the operating system to perform a hot removal operation on the PCI device corresponding to the PCI link;

[0130] S818, if the SCI interrupt register penguin PCI link is not set, it will continue to be used normally;

[0131] S820, the operating system continues normally as a PCI device that is not hot-removed;

[0132] S822, determining whether there are other cases pressed on the control surface;

[0133] If yes, execute step S826; otherwise, the server continues to run.

[0134] S824, determining whether the same button on the control panel is pressed twice;

[0135] If yes, execute step S826; otherwise, the server continues to run.

[0136] S826, the SCI signal corresponding to the PCI link is pulled low, i.e. the enable signal is turned off;

[0137] S828, the server is restarted;

[0138] S830 supports hot-swapping of PCI devices in the system.

[0139] In an exemplary embodiment, the method further includes:

[0140] In a case where the target PCI device connected to the target PCI link includes a first PCI device and a second PCI device, at least one of the following is performed:

[0141] In response to a second triggering operation on a first component on the control panel, the first component enters an activated state, wherein the first component is connected to a first system interrupt signal of the first PCI link;

[0142] In response to the first component entering the activated state, the interrupt status bit of the first system interrupt signal is set to 1;

[0143] Determine a first slot position where a first PCI device connected to the first PCI link is located by searching a system configuration file of the operating system, and perform a hot removal operation on the first PCI device based on the first slot position; or

[0144] In response to a third trigger operation on a second component on the control panel, the second component enters an activated state, wherein the second component is connected to a second system interrupt signal of a second PCI link;

[0145] In response to the second component entering the activated state, the interrupt status bit of the second system interrupt signal is set to 1;

[0146] Determine the second slot location of the second PCI device connected to the second PCI link by searching a system configuration file, and perform a hot removal operation on the second PCI device based on the second slot location; or

[0147] In response to a fourth triggering operation on the first component and a fifth triggering operation on the second component, the first component and the second component enter an activated state;

[0148] In response to the first component and the second component entering the activated state, the interrupt status bit of the first system interrupt signal and the interrupt status bit of the second system interrupt signal are both set to 1;

[0149] By searching the system configuration file, the first slot position where the first PCI device is located and the second slot position where the second PCI device is located are determined, and based on the first slot position and the second slot position, hot removal operations are performed on the first PCI device and the second PCI device.

[0150] Combined with the description in the above embodiments, it can be seen that a PCI link may be split into multiple slots (multiple PCI slots), and a CPI device is usually inserted into a PCI slot. A component (or button) is set for each PCI device on the control panel. By performing a trigger operation on the component, the component enters an activated state, for example, a button is pressed.

[0151] In response to the component entering the activated state, the interrupt status bit of the SCI interrupt signal of the corresponding PCI link is set to 1, and then by calling the ACPI DSDT table, it is determined whether the SCI interrupt status register corresponding to each PCI link is set. If the status register is set, it is determined that the slot corresponding to the set status register is the slot position of the target PCI device.

[0152] In actual applications, trigger operations may be performed on one or more components on the control panel in sequence, causing one or more components to enter an activated state. For example, assuming that there is a first component (a first button) and a second component (a second button) on the control panel, if only the first button is pressed, the corresponding interrupt enable bit is set to 1. Then, by calling the DSDT table of the ACPI protocol, it is determined whether the SCI interrupt status register corresponding to each PCI link is set. The PCI link corresponding to the set SCI interrupt status register is then determined as the target PCI link.

[0153] On the contrary, if only the second button is pressed, the corresponding interrupt enable bit is set to 1, and then the DSDT table of the ACPI protocol is called to determine whether the SCI interrupt status register corresponding to each PCI link is set, and then the PCI link corresponding to the set SCI interrupt status register is determined as the target PCI link.

[0154] For another example, assuming that the first and second buttons are pressed sequentially, the corresponding two interrupt enable bits are set to 1 respectively. Then, by calling the DSDT table of the ACPI protocol, it is determined whether the SCI interrupt status register corresponding to each PCI link is set. Then, the two PCI links corresponding to the two set SCI interrupt status registers are determined as target PCI links. Alternatively, the two PCI devices in the two slots of the two PCI links corresponding to the two set SCI interrupt status registers are determined as devices that can be hot-removed.

[0155] That is to say, the operating system of the target server runs on the processor, supports the OSPM function, detects and responds to changes in the SCI interrupt status register on the PCI link through the ACPI protocol to control the hot plugging of PCI devices. Through the operating system's support for hot plugging operations, intelligent management of PCI devices can be achieved, thereby improving the system's resource utilization and operating efficiency.

[0156] In an exemplary embodiment, the method further includes:

[0157] When the target server is running and the target component is not in an active state, in response to two consecutive trigger operations on the target component, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 0;

[0158] In response to the interrupt status bit of the target system interrupt signal being set to 0, the target server is restarted.

[0159] The core of the technical solution of this application is to physically connect the GPIO signal with the SCI interrupt of the PCI device link, add a control panel at the front end of the server, and physically connect the buttons of the control panel with the SCI enable interrupt information of the slot of each PCI link.

[0160] However, in the control panel, the GPIO pins of the GPIO chip are connected to the buttons. The GPIO pins of the GPIO chip are in output state and high level by default. The buttons of the control panel are similar to the power-on function of lighting a lamp. When pressed, they are physically connected to the GPIO pins of the GPIO chip and the output is high level, which triggers the SCI interrupt. When the button is pressed again, the physical connection of the GPIO signal is disconnected and the SCI interrupt of the PCI link is grounded, which is a low level at this time.

[0161] Since the SCI interrupt of the PCI link is enabled, the value of the SCI interrupt status register will be synchronously updated to 1 under the system. At the same time, after the server starts and enters the operating system, the OSPM driver under the system actively identifies whether the SCI interrupt of the PCI link has occurred. If the SCI status register is set to 1, it means that the SCI interrupt hot plug mode of the corresponding PCI link has been triggered, and the PCI device hot plug function of the corresponding PCI link is implemented.

[0162] Therefore, the control method of the above-mentioned PCI device mainly realizes the setting of the SCI interrupt enable bit by operating the GPIO pins of the GPIO chip through the buttons of the control panel, thereby triggering the generation of the SCI interrupt. OSPM sets the value of the status register of the SCI interrupt to 1, thereby triggering the device hot plug function of the PCI link.

[0163] In addition, the hot-plug function of the PCI device in the system can be realized by pressing the same button twice under the system, but the system needs to be restarted, or the hot-plug function of the PCI device in the system can be realized by pressing the same button twice when the server is shut down and then starting the server to enter the system. In other words, the hot-plug function of the PCI device in the embodiment of the present application requires that the high state of the GPIO pin be disconnected by pressing the same button on the control panel twice under the system or when the system is shut down, and the hot-plug function of the PCI device in the system can be realized when the system is restarted again.

[0164] In addition, if the server is not started or in the operating system, the key of the GPIO signal of the SCI interrupt of the corresponding PCI link is popped up through the control panel, that is, the SCI interrupt corresponding to the PCI link is not enabled or turned off, the hot-plug function of the PCI device can be realized after restarting and entering the operating system.

[0165] In the embodiment of the present application, the effectiveness of the SCI interrupt of the PCI link can only be realized under a system that supports OSPM. If it is set under an operating system other than the operating system, the hot removal action of the PCI device cannot be realized. Therefore, in the embodiment of the present application, only the hot unplugging of the PCI device under the system is guaranteed, and the hot plugging function under the system is not supported. If the hot plugging function needs to be realized, it is necessary to set the GPIO button of the control panel of the corresponding PCI link that controls the SCI interrupt signal to a low level before restarting or after shutting down. At this time, the server can realize the hot plugging function of the PCI device under the system by starting the computer and entering the operating system. Because the SCI interrupt trigger will call the function setting of the DSDT table of ACPI to support the hot removal function of the PCI device under the system.

[0166] In order to more clearly understand the process of implementing the above-mentioned PCI device control method through the interaction between the server, operating system and control panel, the following Figure 9 The overall schematic diagram shown is further explained.

[0167] S902, the server is powered on but not started;

[0168] After the server is started and enters the operating system, step S904 is executed.

[0169] S904, determining whether the PCI link SCI interrupt signal is connected to a key on the control panel and whether the key is pressed;

[0170] If pressed, execute step S906; otherwise, execute step S918.

[0171] S906, in response to the key being pressed, the PCI link SCI interrupt enable bit is set to a high level;

[0172] That is, the SCI interrupt enable bit is enabled, and then step S908 is executed.

[0173] S908, by calling the DSDT table of the ACPI protocol, determining whether the SCI interrupt status register corresponding to each link is set;

[0174] If yes, execute step S910; otherwise, execute step S912.

[0175] S910, hot-remove the PCI device corresponding to the PCI link using the DEJ0 method of OSPM;

[0176] S912: The PCI link for which the SCI interrupt register is not set continues to operate normally.

[0177] S914, the operating system is using the PCI device normally without hot removal;

[0178] S916, while running the operating system using the device that has not been hot-removed, determining whether any other key is pressed;

[0179] If other keys are pressed, jump to step S904; otherwise, the server continues to run.

[0180] While the server continues to run, it determines whether the same button is pressed twice. If so, the SCI signal of the corresponding PCI link is set to a low level, that is, the enable signal is turned off, and the server is restarted. At this time, the hot insertion function of the PCI device under the system is supported; if it is not pressed twice, the server continues to run.

[0181] S918, the PCI link SCI interrupt enable bit is set to 0, and the SCI status bit remains 0.

[0182] This design solution can also achieve the purpose of controlling the power consumption of the entire server by hot-removing PCI devices, that is, reducing the functional requirements of the entire server, saving operation and application costs, and has a wide range of applications. It is highly innovative, improves the hot-swappable capability of PCIE devices, saves manpower and operation and maintenance costs, and is convenient for operation and maintenance personnel to locate the location information of each PCI device. They only need to confirm that they need to hot-unplug the PCI device of a specific slot and press the corresponding button on the control panel to achieve it. It has the advantages of being quick and convenient.

[0183] In addition, the technical solution of the present application has strong replicability and scalability. Specifically, it is controlled by the buttons on the front-end control panel of the server after the server enters the operating system. The SCI interrupt signal of the PCI link connected to the GPIO pin of the GPIO chip is effectively physically connected and controlled by the buttons. Then, the SCI interrupt status register of each PCI link is polled using an operating system that supports OSPM. If the SCI interrupt status register is set to 1, the PCI device of the corresponding PCI link is hot removed under the operating system; if it is not set to 1, it is used normally in the server system.

[0184] If you need to restore the normal use of the hot-removed device under the system, you need to press the control panel button a second time before restarting the server or when the server is shut down to shut down the PCI link through the SCI interrupt. Then you can use the PCI device normally when you enter the operating system again. This solution ensures that when the PCI device is not needed or the PCI device is isolated, the dynamic management hot removal function under the system can be realized without manual physical disassembly. It not only reduces the operation and maintenance costs of the server in the data center, but also improves the energy efficiency of PCI device management. It realizes the hot-plug function of other PCI devices except the traditional Hotplug function that supports the NVME hot-plug function, and has extremely high practicality. At the same time, it also improves the work efficiency of users and ensures the reliability of the server. It provides great benefits to the stability and security of the server, the operation and maintenance of the data center and the service life of the entire server.

[0185] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0186] This embodiment also provides a PCI device control device for implementing the above-mentioned embodiments and preferred implementations. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the modules described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0187] Figure 10 1 is a block diagram of a control device for a PCI device according to an embodiment of the present application, the device comprising:

[0188] A first processing unit 1002 is configured to, in response to a first triggering operation on a target component on a control panel of a target server, cause the target component to enter an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link, and the target system interrupt signal is used to control and notify an operating system of the target server of an event status of a PCI device hot removal event;

[0189] The second processing unit 1004 is configured to set an interrupt status bit of a target system interrupt signal of a target PCI link to 1 in response to the target component entering an activated state;

[0190] a search unit 1006 configured to determine a target slot location of a target PCI device connected to a target PCI link by searching a system configuration file of an operating system, wherein the system configuration file is used to describe CPU location information of a target server, the CPU location information including configuration information of a PCI link connected to the CPU, the PCI link configuration information including a slot number of each PCI slot in the PCI link and device information of a PCI device inserted into each slot numbered PCI slot, and each PCI slot corresponds to a system interrupt signal;

[0191] The hot removal unit 1008 is configured to perform a hot removal operation on a target PCI device based on a target slot location.

[0192] In an exemplary embodiment, the second processing unit 1004 includes:

[0193] A first processing module is configured to, in response to the target component entering an activated state, set a general input / output signal on the control panel to a high level;

[0194] The first control module is configured to control an interrupt status bit of a target system interrupt signal of a target PCI link to be set to 1 in response to the general input / output signal being set to a high level.

[0195] In an exemplary embodiment, the search unit 1006 includes:

[0196] a calling module, configured to call a system configuration file of an ACPI protocol in response to an interrupt status bit of a system interrupt signal of a target PCI link being set to 1, wherein the ACPI protocol is used by an operating system to automatically configure hardware and provide a power management function;

[0197] An acquisition module is used to obtain status information of a status register of a system interrupt signal corresponding to each PCI link by searching a system configuration file;

[0198] The second processing module is configured to determine a target slot position where a target PCI device connected to the target PCI link is located based on status information of a status register of a system interrupt signal corresponding to each PCI link.

[0199] In an exemplary embodiment, the second processing module includes:

[0200] A first processing submodule is configured to determine target state information of a target state register corresponding to a target PCI link from state information of the state register;

[0201] a second processing submodule, configured to determine, based on the target status information, a target PCI slot where the target PCI device is located from a plurality of PCI slots included in the target PCI link, when the target status information indicates that the target status register corresponding to the target PCI link is set;

[0202] The third processing submodule is configured to determine the slot position where the target PCI slot is located as the target slot position.

[0203] In an exemplary embodiment, the apparatus further comprises:

[0204] The third processing unit is configured to trigger calling a system configuration file of the ACPI protocol in response to an interrupt status bit of a target system interrupt signal of a target PCI link being set to 1.

[0205] In an exemplary embodiment, the apparatus further comprises:

[0206] The fourth processing unit is configured to, when the target PCI device connected to the target PCI link includes the first PCI device and the second PCI device, perform at least one of the following:

[0207] In response to a second triggering operation on a first component on the control panel, the first component enters an activated state, wherein the first component is connected to a first system interrupt signal of the first PCI link;

[0208] In response to the first component entering the activated state, the interrupt status bit of the first system interrupt signal is set to 1;

[0209] Determine a first slot position where a first PCI device connected to the first PCI link is located by searching a system configuration file of the operating system, and perform a hot removal operation on the first PCI device based on the first slot position; or

[0210] In response to a third trigger operation on a second component on the control panel, the second component enters an activated state, wherein the second component is connected to a second system interrupt signal of a second PCI link;

[0211] In response to the second component entering the activated state, the interrupt status bit of the second system interrupt signal is set to 1;

[0212] Determine the second slot location of the second PCI device connected to the second PCI link by searching a system configuration file, and perform a hot removal operation on the second PCI device based on the second slot location; or

[0213] In response to a fourth triggering operation on the first component and a fifth triggering operation on the second component, the first component and the second component enter an activated state;

[0214] In response to the first component and the second component entering the activated state, the interrupt status bit of the first system interrupt signal and the interrupt status bit of the second system interrupt signal are both set to 1;

[0215] By searching the system configuration file, the first slot position where the first PCI device is located and the second slot position where the second PCI device is located are determined, and based on the first slot position and the second slot position, hot removal operations are performed on the first PCI device and the second PCI device.

[0216] In an exemplary embodiment, the apparatus further comprises:

[0217] a fifth processing unit, configured to, in response to two consecutive triggering operations on the target component while the target server is running and the target component is not in an activated state, set an interrupt status bit of a target system interrupt signal of a target PCI link to 0;

[0218] The restart unit is configured to restart the target server in response to the interrupt status bit of the target system interrupt signal being set to 0.

[0219] The above-mentioned device indicates that by adding an operable target component to the control panel of the target server, and after the server is started and enters the operating system, the SCI interrupt signal of the corresponding PCI link is enabled by triggering the target component, and then by searching the system configuration file of the operating system, the target slot position of the target PCI device connected to the target PCI link is determined, so as to perform a hot removal operation on the target PCI device at the target slot position. In other words, the embodiment of the present application adopts the method of physically introducing the target component into the control panel, and by physically connecting the target component with the SCI interrupt signal of the PCI link, the hot removal function of each device connected to the PCI link is controlled, which not only improves the accuracy of the hot removal operation of the PCI device, but also enhances the flexibility of the control of the PCI device.

[0220] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0221] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0222] Optionally, in this embodiment, the computer program may be configured to perform the following steps:

[0223] S1, in response to a first triggering operation on a target component on a control panel of a target server, the target component enters an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link, and the target system interrupt signal is used to control and notify an operating system of the target server of an event status of a PCI device hot removal event;

[0224] S2, in response to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1;

[0225] S3, determining a target slot location of a target PCI device connected to a target PCI link by searching a system configuration file of the operating system, wherein the system configuration file is used to describe CPU location information of the target server, the CPU location information includes configuration information of a PCI link connected to the CPU, the PCI link configuration information includes the slot number of each PCI slot in the PCI link and device information of a PCI device inserted into each PCI slot with the slot number, and each PCI slot corresponds to a system interrupt signal;

[0226] S4: Based on the target slot location, perform a hot removal operation on the target PCI device.

[0227] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0228] The embodiment of the present application also provides an electronic device, such as Figure 11 As shown, the electronic device includes a memory 1102 and a processor 1104. The memory 1102 stores a computer program, and the processor 1104 is configured to execute the steps in any of the above method embodiments through the computer program.

[0229] Optionally, in this embodiment, the processor 1104 may be configured to execute the following steps through a computer program:

[0230] S1, in response to a first triggering operation on a target component on a control panel of a target server, the target component enters an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link, and the target system interrupt signal is used to control and notify an operating system of the target server of an event status of a PCI device hot removal event;

[0231] S2, in response to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1;

[0232] S3, determining a target slot location of a target PCI device connected to a target PCI link by searching a system configuration file of the operating system, wherein the system configuration file is used to describe CPU location information of the target server, the CPU location information includes configuration information of a PCI link connected to the CPU, the PCI link configuration information includes the slot number of each PCI slot in the PCI link and device information of a PCI device inserted into each PCI slot with the slot number, and each PCI slot corresponds to a system interrupt signal;

[0233] S4: Based on the target slot location, perform a hot removal operation on the target PCI device.

[0234] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0235] Alternatively, those skilled in the art will appreciate that Figure 11 The structure shown is for illustration only. Figure 11 The structure of the electronic device is not limited. For example, the electronic device may also include Figure 11 More or fewer components (such as network interfaces, etc.) as shown in, or with Figure 11 Different configurations shown.

[0236] Among them, the memory 1102 can be used to store software programs and modules, such as the program instructions / modules corresponding to the control method of the PCI device and the control device of the PCI device in the embodiment of the present application. The processor 1104 executes various functional applications and data processing by running the software programs and modules stored in the memory 1102, that is, realizes the control method of the above-mentioned PCI device. The memory 1102 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1102 may further include a memory remotely located relative to the processor 1104, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof. Among them, the memory 1102 can be used to store information such as target system interrupt signals, system configuration files, and target slot locations, but is not limited to. As an example, if Figure 11As shown, the memory 1102 may include, but is not limited to, the first processing unit 1002, the second processing unit 1004, the search unit 1006, and the hot removal unit 1008 in the control device for the PCI device. In addition, it may also include, but is not limited to, other module units in the control device for PCI hot standby, which will not be described in detail in this example.

[0237] Optionally, the transmission device 1106 is configured to receive or send data via a network. Specific examples of the network may include a wired network and a wireless network. In one embodiment, the transmission device 1106 includes a network interface controller (NIC), which can be connected to other network devices and a router via a network cable to communicate with the Internet or a local area network. In one embodiment, the transmission device 1106 is a radio frequency (RF) module, which is configured to communicate with the Internet wirelessly.

[0238] In addition, the electronic device further includes: a display 1108; and a connection bus 1110 for connecting various module components in the electronic device.

[0239] In other embodiments, the electronic device may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting multiple nodes via network communication. The nodes may form a peer-to-peer network, and any computing device, such as a server, terminal, or other electronic device, may become a node in the blockchain system by joining the peer-to-peer network.

[0240] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0241] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above method embodiments are implemented.

[0242] An embodiment of the present application also provides a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any of the above method embodiments.

[0243] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0244] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for controlling a PCI device, characterized in that: include: In response to a first triggering operation on a target component on a control panel of a target server, the target component enters an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link, and the target system interrupt signal is used to control and notify an operating system of the target server of an event status of a PCI device hot removal event; In response to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1; Determining a target slot location of a target PCI device connected to the target PCI link by searching a system configuration file of the operating system, wherein the system configuration file is used to describe CPU location information of the target server, the CPU location information includes configuration information of a PCI link connected to the CPU, the PCI link configuration information includes a slot number of each PCI slot in the PCI link and device information of a PCI device inserted into each PCI slot with the slot number, and each PCI slot corresponds to a target system interrupt signal; Based on the target slot location, a hot removal operation is performed on the target PCI device.

2. The method according to claim 1, characterized in that In response to the target component entering the activated state, the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1, comprising: In response to the target component entering an activated state, the general input / output signal on the control panel is set to a high level; In response to the general purpose input output signal being set to a high level, an interrupt status bit of the target system interrupt signal controlling the target PCI link is set to 1.

3. The method according to claim 1, characterized in that The step of determining the target slot position of the target PCI device connected to the target PCI link by searching the system configuration file of the operating system includes: In response to an interrupt status bit of a target system interrupt signal of the target PCI link being set to 1, calling the system configuration file of the ACPI protocol, wherein the ACPI protocol is used by the operating system to automatically configure hardware and provide a power management function; By searching the system configuration file, the status information of the status register of the target system interrupt signal corresponding to each PCI link is obtained; Based on the status information of the status register of the target system interrupt signal corresponding to each PCI link, a target slot position of the target PCI device connected to the target PCI link is determined.

4. The method according to claim 3, characterized in that The determining, based on status information of a status register of a target system interrupt signal corresponding to each PCI link, a target slot position of a target PCI device connected to the target PCI link, includes: Determine target state information of a target state register corresponding to the target PCI link from the state information of the state register; In a case where the target status information indicates that the target status register corresponding to the target PCI link is set, determining, based on the target status information, a target PCI slot where the target PCI device is located from a plurality of PCI slots included in the target PCI link; The slot position where the target PCI slot is located is determined as the target slot position.

5. The method according to claim 1, wherein After the interrupt status bit of the target system interrupt signal of the target PCI link is set to 1 in response to the target component entering the activated state, the method further includes: In response to the interrupt status bit of the target system interrupt signal of the target PCI link being set to 1, the system configuration file of the ACPI protocol is triggered to be called.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: In a case where the target PCI device connected to the target PCI link includes a first PCI device and a second PCI device, performing at least one of the following: In response to a second triggering operation on a first component on the control panel, the first component enters an activated state, wherein the first component is connected to a first system interrupt signal of a first PCI link; In response to the first component entering the activated state, the interrupt status bit of the first system interrupt signal is set to 1; Determine a first slot position where the first PCI device connected to the first PCI link is located by searching a system configuration file of the operating system, and perform a hot removal operation on the first PCI device based on the first slot position; or In response to a third trigger operation on a second component on the control panel, the second component enters an activated state, wherein the second component is connected to a second system interrupt signal of a second PCI link; In response to the second component entering the activated state, the interrupt status bit of the second system interrupt signal is set to 1; Determine the second slot position of the second PCI device connected to the second PCI link by searching the system configuration file, and perform a hot removal operation on the second PCI device based on the second slot position; or In response to a fourth triggering operation on the first component and a fifth triggering operation on the second component, the first component and the second component enter an activated state; In response to the first component and the second component entering an activated state, the interrupt status bit of the first system interrupt signal and the interrupt status bit of the second system interrupt signal are both set to 1; The first slot position where the first PCI device is located and the second slot position where the second PCI device is located are determined by searching the system configuration file, and hot removal operations are performed on the first PCI device and the second PCI device based on the first slot position and the second slot position.

7. The method according to any one of claims 1 to 5, characterized in that The method further comprises: When the target server is running and the target component is not in an active state, in response to two consecutive triggering operations on the target component, an interrupt status bit of a target system interrupt signal of the target PCI link is set to 0; In response to the interrupt status bit of the target system interrupt signal being set to 0, the target server is restarted.

8. A control device for a PCI device, characterized in that: include: a first processing unit, configured to, in response to a first triggering operation on a target component on a control panel of a target server, cause the target component to enter an activated state, wherein the target component is connected to a target system interrupt signal of a target PCI link, and the target system interrupt signal is used to control and notify an operating system of the target server of an event status of a PCI device hot removal event; a second processing unit, configured to, in response to the target component entering an activated state, set an interrupt status bit of a target system interrupt signal of the target PCI link to 1; a search unit, configured to determine a target slot location of a target PCI device connected to the target PCI link by searching a system configuration file of the operating system, wherein the system configuration file is used to describe CPU location information of the target server, the CPU location information includes configuration information of a PCI link connected to the CPU, the PCI link configuration information includes a slot number of each PCI slot in the PCI link and device information of a PCI device inserted into each PCI slot with a slot number, and each PCI slot corresponds to a target system interrupt signal; A hot removal unit is configured to perform a hot removal operation on the target PCI device based on the target slot position.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

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