Expansion card circuit and communication method capable of being inserted into external device

Abstract

The present invention discloses an expansion card circuit and communication method that can be inserted into an external device. The circuit includes an expansion card, a slot board, and a mainboard. The mainboard includes a processor, a baseboard management controller, a new bus protocol chip, and at least one connector. The baseboard management controller establishes a first channel between the chip circuit on the expansion card through at least one connector, and the first channel is used to transmit a first high-speed signal of the integrated circuit bus protocol between the mainboard and the expansion card, and establishes a second channel between the external device inserted into the slot board through at least one connector, and the second channel is used to transmit a second high-speed signal of the new bus protocol between the mainboard and the external device. The hardware circuit of the expansion card circuit provided by the present invention meets the CEM Riser card requirements of the PCIe6.0 protocol. At the same time, the circuit retains the communication capability with the I2C high-speed signal, achieving transmission compatibility with the I2C and I3C bus communication protocols.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to an expansion card circuit and a communication method that can be inserted into an external device. Background Art

[0002] With the rise of data-intensive applications such as big data analytics and video rendering, and the widespread adoption of heterogeneous computing architectures, data exchange between CPUs and GPUs (Graphics Processing Units), and between CPUs (Central Processing Units) and DPUs (Data Processing Units), is becoming increasingly frequent, placing increasing demands on data transfer rates and bandwidth. The emergence of PCIe 6.0 (PCI Express, Generation 6, a PCI Express interface standard) technology addresses this demand for high-performance data transfer and provides a more efficient and reliable solution for data exchange within heterogeneous computing architectures.

[0003] Currently, PCIe6.0 technology has introduced the I3C (Improved Inter-Integrated Circuit, a new sensor bus) protocol in the management communication protocol. This has compatibility issues with the I2C (Inter-Integrated Circuit, integrated circuit bus) management link of the general CEM (PCI Express Card Electromechanical Specification, a PCIe electrical mechanical specification) Riser card in the hardware line. The existing CEM Riser design is not compatible with PCIe cards or PCIe devices that support Gen6 rates. Summary of the Invention

[0004] In view of this, the present invention provides an expansion card circuit and communication method that can be inserted into an external device to meet the communication requirements of the new CEM Riser card on the server hardware line with PCIe Gen6 rate, and provides a corresponding solution to the chassis silk screen problem under this technical scheme.

[0005] In a first aspect, the present invention provides an expansion card circuit that can be inserted into an external device, the expansion card circuit comprising an expansion card, a slot board, and a main board, wherein the expansion card is connected to the main board via the slot board, and the slot board is provided with a slot for inserting an external device;

[0006] The mainboard includes a processor, a baseboard management controller, a new bus protocol chip and at least one connector;

[0007] The processor is connected to the new bus protocol chip and the at least one connector, and the baseboard management controller is connected to the new bus protocol chip and the at least one connector;

[0008] The baseboard management controller establishes a first channel between the at least one connector and the chip circuit on the expansion card, wherein the first channel is used to transmit a first high-speed signal of an integrated circuit bus protocol between the mainboard and the expansion card, wherein the first high-speed signal carries address information and asset information of the expansion card;

[0009] The baseboard management controller establishes a second channel between the at least one connector and the external device inserted into the slot board. The second channel is used to transmit a second high-speed signal of the new bus protocol between the mainboard and the external device. The second high-speed signal carries device information of the external device.

[0010] In conjunction with the first aspect, in one possible implementation, the processor includes a basic input / output system; the mainboard further includes at least one arbitration chip, and the basic input / output system is connected to the at least one arbitration chip via the at least one arbitration chip;

[0011] The basic input and output system is used to transmit the first high-speed signal to the chip circuit of the expansion card after transparently transmitting the first high-speed signal through the slot board via the at least one arbitration chip and the at least one connector.

[0012] In conjunction with the first aspect, in another possible implementation, the expansion card includes a microprocessor, at least one chip circuit, and a communication interface; the communication interface is connected to the slot board, and the microprocessor is connected to the at least one chip circuit;

[0013] The basic input and output system is further used to transmit the first high-speed signal to the microprocessor through the slot board and the communication interface;

[0014] The microprocessor is configured to receive the first high-speed signal sent from the basic input / output system module, parse the first high-speed signal, and write the address information into a target chip, which is one of the at least one chip circuit.

[0015] In combination with the first aspect, in another possible implementation, the basic input and output system is further configured to send a notification message to the baseboard management controller after writing the address information to the target chip;

[0016] The baseboard management controller is further configured to receive, through the first channel, a first high-speed signal carrying the address information and asset information and sent by the microprocessor after receiving the notification message.

[0017] In combination with the first aspect, in another possible implementation, the expansion card further includes a field replaceable unit, and the field replaceable unit is connected to the microprocessor MCU and the at least one chip circuit via a bus;

[0018] The baseboard management controller is further configured to scan the field replaceable unit (FRU) on the expansion card and the target chip to obtain the asset information and the address information, and search a truth table for the processor port number corresponding to the external device based on the address information and the asset information;

[0019] The truth table includes at least one corresponding relationship, each corresponding relationship includes a corresponding relationship between a processor port number and a truth value, and each truth value is a character string used to represent the address information and / or the asset information.

[0020] In combination with the first aspect, in another possible implementation, the novel bus protocol chip includes a first pin and a plurality of second pins, the first pin is connected to a port of the baseboard management controller, and the plurality of second pins are connected to the at least one connector;

[0021] The novel bus protocol chip is used for switching transmission modes according to the first pin and the plurality of second pins, and the transmission modes include: a transmission mode of an integrated circuit bus protocol and a transmission mode of a novel bus protocol.

[0022] In combination with the first aspect, in another possible implementation, the baseboard management controller is further used to determine the expansion card type based on the information of the external device obtained by the second channel and the second pin of the new bus protocol chip currently communicating.

[0023] In a second aspect, the present invention provides a communication method, which is applied to the expansion card circuit as described in the first aspect or any embodiment of the first aspect, and the method includes:

[0024] The baseboard management controller establishes a first channel with the chip circuit on the expansion card through at least one connector, and obtains a first high-speed signal of the integrated circuit bus protocol through the first channel;

[0025] The baseboard management controller establishes a second channel with the external device inserted into the slot board through the at least one connector, and transmits a second high-speed signal of the new bus protocol through the second channel;

[0026] The baseboard management controller determines the address information and asset information of the expansion card according to the first high-speed signal, and obtains the device information of the external device according to the second high-speed signal.

[0027] With reference to the second aspect, in a possible implementation, obtaining the first high-speed signal of the integrated circuit bus protocol through the first channel includes:

[0028] The baseboard management controller detects whether a notification message is received when the basic input and output system is initialized, wherein the notification message is used to inform the basic input and output system that address information has been written to the target chip of the expansion card;

[0029] If the notification message is received, the first high-speed signal is obtained from the expansion card through the first channel.

[0030] In combination with the second aspect, in another possible implementation, after obtaining the device information of the external device according to the second high-speed signal, it also includes: the baseboard management controller determines the expansion card type according to the device information and the current communication pin of the new bus protocol chip.

[0031] In the third aspect, the present invention provides a baseboard management controller, comprising a memory and a processor, wherein the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the communication method described in the second aspect or any embodiment of the second aspect by executing the computer instructions.

[0032] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, wherein the computer instructions are used to enable a computer to execute the communication method based on a PCIe device as described in the second aspect or any embodiment of the second aspect.

[0033] In addition, the present invention provides a computer program product, including computer instructions, which are used to enable a computer to execute the communication method described in the second aspect or any embodiment of the second aspect.

[0034] The present invention provides an expansion card circuit and communication method for inserting an external device. The expansion card circuit is designed on a motherboard that includes: a processor, a baseboard management controller (BMC), a novel bus protocol chip, and at least one connector. The novel bus protocol chip on the motherboard is a newly added chip that establishes multiple channels between the BMC and the at least one connector. These channels include a first channel that can be used to transmit a first high-speed signal to the BMC, thereby implementing I2C signal communication in hardware. The first high-speed signal carries device asset information and related address information.

[0035] In addition, the new bus protocol chip also establishes a second channel between at least one connector of the motherboard and the slot of the slot board. When an external device is inserted into the slot, the second channel can be used to access and obtain information about the external device. Because I3C communication is supported on the second channel, the present invention provides an expansion card circuit for emerging PCIe devices that support the I3C protocol. The hardware circuit of the expansion card circuit meets the CEMRiser card requirements of the PCIe6.0 protocol, and realizes effective communication between the baseboard management controller BMC of the motherboard and the PCIe device. At the same time, the circuit retains the communication capability with the I2C high-speed signal, and can achieve compatibility with the I2C / I3C communication protocol.

[0036] Furthermore, the communication method provided in this embodiment can, for a baseboard management controller, not only retrieve address information and asset information from the expansion card's target chip via a first channel upon detecting that the basic input / output system module has written address information to the expansion card's target chip, but also determine the device's processor port number based on this address and asset information, thereby acquiring a new chassis silkscreen. Simultaneously, it can also utilize a second channel to retrieve external device information; based on this external device information and the current communication connection pins of the new bus protocol chip, it can determine the expansion card, thereby supporting existing functions.

[0037] The expansion card circuit of the present invention is rationally designed, and the connections between the components are tight and stable. By introducing an arbitration chip and a new bus protocol chip, the conflicts and error rates during data transmission are effectively reduced, and the overall stability and reliability of the system are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 is a schematic diagram of a system topology structure according to an embodiment of the present invention;

[0040] Figure 2a This is a schematic diagram of the internal structure of a riser card according to an embodiment of the present invention;

[0041] Figure 2b This is a structural diagram of a mainboard and a slot board connected according to an embodiment of the present invention;

[0042] Figure 3ais a circuit structure diagram of a mainboard according to an embodiment of the present invention;

[0043] Figure 3b is a schematic diagram of a connection between a riser card and a slot board according to an embodiment of the present invention;

[0044] Figure 4 This is a schematic structural diagram of an expansion card circuit based on a PCIe device according to an embodiment of the present invention;

[0045] Figure 5a According to an embodiment of the present invention, Figure 4 A partially enlarged circuit structure diagram of the structure;

[0046] Figure 5b According to an embodiment of the present invention, Figure 4 Structure A circuit diagram of a riser card;

[0047] Figure 6a is a circuit structure diagram of another mainboard according to an embodiment of the present invention;

[0048] Figure 6b According to an embodiment of the present invention, Figure 4 Another partially enlarged circuit diagram of the structure;

[0049] Figure 7 is a flow chart of a communication method according to an embodiment of the present invention;

[0050] Figure 8 is a flow chart of another communication method according to an embodiment of the present invention;

[0051] Figure 9 2 is a schematic structural diagram of a baseboard management controller according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0053] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0054] In addition, the terms “first” and “second” are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0055] The technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0056] The technical solution provided by the embodiment of the present invention is applied to the field of server technology, especially to the design of a server motherboard, which is based on the current CEM (a PCIE electrical mechanical specification) Riser design solution.

[0057] like Figure 1 As shown, the CEM riser motherboard design consists of two modules: the riser control board (also known as the riser card) and the slot board (English: slot board). The riser control board houses the riser card's IC chips, while the slot board includes PCIe slots (abbreviated as PCIe slots) for connecting PCIe devices. PCIe high-speed signals are transmitted directly to the PCIe device via a cable from at least one connector on the motherboard. I2C (Inter-Integrated Circuit) management signals and power (English: POWER) are obtained by the riser control board through a connector connected to the motherboard and then transmitted to the PCIe device via the slot board.

[0058] Specifically, if Figure 2a and Figure 2b As shown, based on Figure 1 A partially enlarged circuit diagram. First, the motherboard needs to have an MCIO (Modular Connector Input Output) connector, a Power connector, and an I2C bus connector (I2CHeader) to meet the basic design of the CEM Riser. The PCIe signal, clock signal (Clock, CLK), VPPADDR signal, and CPUADDR (referring to the CPU address bus) signal are transmitted through the MCIO connector, and the above signals are transmitted to the slot board and PCIe slot respectively through the Y-type cable. For details on the specific transmitted signals, see Figure 2a and Figure 2b .

[0059] The MCIO connector standard defines a highly reliable, high-density electronic connector interface, which is usually used for cable connections inside electronic devices and can be used for different applications such as data transmission, signal transmission, and power supply. Figure 2b As shown, the motherboard is provided with two or more MCIO connectors for connecting to the sideband connectors (Sideband Connect) on the slot board. Optionally, the number of the sideband connectors can be one or more, and each sideband connector includes 12 pins.

[0060] The I2C bus connector or connector is part of the I2C communication protocol and is used to implement low-speed data transmission between different integrated circuits (ICs). The I2C protocol is a bus network used to provide a low-speed data transmission method for two or more programmable devices. It allows device connections between multiple wired interfaces and supports a simple master / slave communication mode. In this embodiment, the motherboard acts as the master device and connects to the slave device, i.e., the PCIe device, via the I2C bus connector. The master device is responsible for initiating communication, sending data, receiving data, and controlling the termination of communication.

[0061] Signals such as the VPP ADDR and CPU ADDR from the motherboard are transparently transmitted through the slot board and then transmitted to the CA9*** chip on the riser control board. These signals are then read by the baseboard management controller (BMC) and basic input / output system (BIOS) modules on the motherboard to create the chassis silkscreen solution.

[0062] A method for obtaining a chassis silk screen on a BMC module's web page includes the following steps:

[0063] Step 1: Scan and enumerate the PCIe bus during BIOS initialization to obtain the BDF code of each PCIe device;

[0064] Step 2: The BMC communicates with the CA9555 of the riser control board to obtain the VPP / CPUADDR corresponding to MCIO X8, and determines the CPU PORT corresponding to the hard disk based on the truth table (since MCIO and CPU PORT are bound on the hardware circuit, the truth table is VPP / CPUADDR and CPU PORT);

[0065] Step 3: The BMC communicates with the PCIE device to obtain hard disk related information; and communicates with the FRU to obtain asset information.

[0066] In step 4, the BIOS reports the BDF information corresponding to each CPU port through the eSPI bus. In summary, the BMC summarizes the CPU port, hard disk information, BDF (Bus, Device, Function), asset information, etc. and displays it on the BMC page.

[0067] Based on the above system architecture, in terms of I2C high-speed signal transmission and management design, such as Figure 3a and Figure 3b As shown, the I2C link of the riser control board passes through the I2C switch chip, using channels 1 to 3 to mount IC and PCIe devices respectively. The BMC and BIOS can access the devices in the CEM riser through the I2C arbitration chip 1 or I2C arbitration chip 2 respectively.

[0068] Currently, motherboard BMCs primarily rely on the I2C bus to communicate with PCIe cards and obtain necessary information. However, with the advent of PCIe cards supporting the I3C protocol (PCI Express, the sixth-generation transmission bus protocol), existing circuit designs are no longer sufficient due to incompatibility between I2C and I3C levels. Furthermore, existing chassis silkscreen designs are also based on the I2C bus. To achieve compatibility, hardware circuit modifications require a completely new chassis silkscreen design, which is costly and difficult to implement.

[0069] To address the aforementioned technical issues, the present invention provides a new hardware circuit for emerging PCIe devices supporting the I3C protocol, a CEM Riser that complies with the PCIe 6.0 protocol. This enables effective communication between the BMC and PCIe cards, while retaining I2C communication capabilities and achieving compatibility with the I2C / I3C communication protocols. Furthermore, a new chassis silkscreen implementation solution is proposed within the new hardware circuit design.

[0070] The technical solutions provided by the embodiments of the present invention are described in detail below.

[0071] An embodiment of the present invention provides an expansion card circuit that can be inserted into an external device. The expansion card circuit is suitable for a CEM riser card design solution for a PCIe device with a Gen6 rate. The specific technical solution is as follows:

[0072] like Figure 4 As shown, the expansion card circuit includes: an expansion card (Riser card), a slot board (SLOT) and a mainboard (MB). The expansion card is connected to the mainboard via the slot board, and the slot board is provided with a PCIe slot for inserting an external device. Optionally, the external device is a PCIe device.

[0073] The mainboard includes: a processor, a baseboard management controller (BMC), at least one arbitration chip (Arbitrate), a new bus protocol chip (I3C HUB) and at least one connector.

[0074] Specifically, the connection relationship is as follows Figure 4 As shown, at least one arbitration chip includes arbitration chip 1 and arbitration chip 2, wherein the processor is connected to at least one connector through at least one arbitration chip, and the processor is used to transmit address information to the expansion card through at least one connector.

[0075] Optionally, the at least one connector may be an MCIO connector, such as MCIO 1 and MCIO 2. The processor may be a CPU.

[0076] In this embodiment, the processor is connected to arbitration chip 1 and arbitration chip 2 respectively through a switching circuit. The switching chip is used to select and switch which arbitration chip is connected to the CPU. Arbitration chip 1 is connected to MCIO 1, and arbitration chip 2 is connected to MCIO 2.

[0077] The baseboard management controller is connected to a new bus protocol chip (I3C hub), arbitration chip 1, and arbitration chip 2. The new bus protocol chip (I3C hub) and each arbitration chip include multiple pins for establishing multiple channels between the baseboard management controller and at least one MCIO connector.

[0078] Furthermore, the baseboard management controller establishes a first channel between at least one MCIO connector and the chip circuit on the expansion card. This first channel is used to transmit a first high-speed signal of the Integrated Circuit Bus Protocol (I2C) between the motherboard and the expansion card. This first high-speed signal carries the address information and asset information of the transmission expansion card, so that the baseboard management controller can determine the processor port number (such as CPU port) of the external PCIe device based on the address information and asset information. The processor CPU includes multiple ports, and the first high-speed signal is used to determine which port of the CPU the current PCIe device is connected to.

[0079] In addition, the baseboard management controller establishes a second channel between the external device (such as a PCIe device) inserted into the slot board through at least one MCIO connector. The second channel is used to transmit a second high-speed signal of the new bus protocol (I3C) between the motherboard and the external device. The second high-speed signal carries the device information of the external device. In other words, this information can help the BMC determine that the selected I3C HUB channel is different, that is, it can distinguish which CEM riser card it comes from.

[0080] See also Figure 5a and Figure 5b As shown, based on Figure 4 The expansion card circuit provided by the embodiment of the present invention is in the original CEM Riser design solution (such as Figure 2a and Figure 2b The main improvements include: modifying the MCIO connector pin definition, deleting the original solution's CPUADDR0 / 1 / 2, VPPADDR0 / 1 / 2 / 3, a total of 7 pins, and changing them to pins for transmitting I2C_SDA / SCL signals, I3C_SDA / SCL signals, and Throttle signals.

[0081] In addition, the I2C header connectors on the motherboard and the original riser card have been deleted. The transmission link for the original PCIe high-speed signal and CLK signal is still directly connected to the PCIe card slot via a Y-type cable; the newly added I3C signal is transmitted to the PCIe slot via the sideband connector (Sideband) of the slot board (slot board), participating in the I3C communication between the BMC and the PCIe device. The I2C signal is modified to be transmitted to the riser card after passing through the slot board, and the I2C switching circuit (Switch) is deleted from the original I2C hardware line, and an MCU (microprocessor) chip is added to the riser card side. The power supply solution remains the same as the original design.

[0082] Among them, the I2C_SDA / SCL signal and the I3C_SDA / SCL signal represent signals in the I2C (Inter-Integrated Circuit, integrated circuit bus protocol) and I3C (Improved Inter-Integrated Circuit, new bus protocol) bus systems, respectively, corresponding to the aforementioned first high-speed signal and second high-speed signal.

[0083] Specifically, in the I2C_SDA / SCL signal, SDA (Serial Data): SDA is the serial data line of the I2C bus, responsible for transmitting serial data between devices. It is bidirectional, meaning that data can be transmitted in both directions. During data transmission, the data on the SDA line must be stable during the high period of the clock; the level on the data line SDA is allowed to change only when the clock line SCL is low. SCL (Serial Clock): SCL is the serial clock line of the I2C bus, generated and controlled by the master device. It is used to synchronize data transmission, ensuring that all devices can receive and send data at the same rate. At the beginning of data transmission, when SCL is high, a high-to-low transition of SDA indicates a start signal. At the end of data transmission, when SCL is high, a low-to-high transition of SDA indicates a stop signal.

[0084] In the I3C_SDA / SCL signal, SDA (Serial Data): In the I3C bus, SDA is also used as a serial data line, but compared to I2C, I3C's SDA line may support higher data transmission rates and more complex communication protocols. In addition, I3C's SDA line also supports an in-band interrupt function, and the device can actively trigger an interrupt to communicate with the host controller. SCL (Serial Clock): I3C's SCL line serves as a serial clock line for synchronous data transmission. Unlike I2C, I3C's SCL line may support clock stretching to adapt to the data transmission rate requirements of different devices. However, in push-pull mode, I3C's SCL line does not support the clock stretching of the I2C protocol.

[0085] In addition, the new bus protocol chip (I3C HUB) can be called an "I3C hub" or "I3C hub". It is a chip based on the I3C (Improved Inter-Integrated Circuit) bus protocol. It is designed to improve the traditional I2C bus, providing higher speed, better power management and other advanced features while maintaining backward compatibility. Specifically, the functions and features of I3CHUB include the following:

[0086] (1) High-speed transmission: I3C HUB supports high-speed data transmission and can meet the high data transmission rate requirements of modern electronic devices. (2) Dynamic address allocation: I3C HUB supports a dynamic address allocation mechanism, which can solve the problem of address duplication and enable devices on the bus to be configured and managed more flexibly. (3) Power management: I3C HUB provides advanced power management functions, including sleep mode, which helps reduce device power consumption and extend battery life. (4) Multi-host support: I3CHUB supports multiple host devices connected to the bus at the same time, improving the flexibility and scalability of the system. (5) Hot plug function: I3C HUB allows slave devices to connect to the bus after the host completes initialization, and can then assign them a dynamic address. This mechanism allows slave devices to enter a low-power state and wake up only when needed.

[0087] In this embodiment, the I3C HUB is set on the motherboard and can be connected to the BMC, CPU (including BIOS), and at least one MCIO connector. It can serve as a channel selection chip to select arbitration chip 1 or arbitration chip 2 to connect to the BIOS or BMC, thereby realizing switching control of the BIOS and BMC modules.

[0088] In a specific implementation of this embodiment, Figure 6a and Figure 6bAs shown, the BIOS and BMC transmit at least one high-speed signal to the expansion card through at least two channels, such as the first channel, which passes through at least one arbitration chip and then connects to at least one MCIO connector. The at least one high-speed signal includes the I2C_SDA / SCL signal, i.e., the first high-speed signal.

[0089] like Figure 5b As shown, the expansion card includes a microcontroller unit (MCU), at least one chip circuit (such as chip circuit 1 and chip circuit 2) and a communication interface; the communication interface is connected to the slot board, and the microprocessor is connected to at least one chip circuit. In addition, other circuits or modules such as a power connection port (Power conn) are also included, which are not limited in this embodiment. In addition, the power connection port is used to transmit electrical energy to the power supply and I2C bus interface connector, such as transmitting P12V_PCIE, P3V3 or P3V3_STBY to the power supply and I2C bus interface connector.

[0090] Optionally, the communication interface is a power supply and I2C bus interface connector (PWR&I2C Conn1), which is connected to the Gold Finger connector on the slot board. Figure 5a As shown, the gold finger connector is connected to the sideband connector to receive and transmit I2C_SDA / SCL signals, SLOT_PRSNT_N signals, etc.

[0091] It should be understood that in addition to transmitting the I2C_SDA / SCL signal, the power supply and I2C bus interface connector also transmits other signals, such as the SLOT1_PRSNT_N or SLOT0_PRSNT_N signal to the chip circuit 1, indicating the presence signal from the slot board 0 or the slot board 1.

[0092] The riser card also includes a field replaceable unit (FRU) and a temperature sensor. The FRU and temperature sensor are connected to the microprocessor (MCU) and at least one chip circuit via a bus. A FRU is a circuit board, device component, or assembly designed to be quickly replaced in the field by users or technicians.

[0093] In this embodiment, at least one chip circuit includes chip circuit 1 and chip circuit 2. The structures and models of chip circuit 1 and chip circuit 2 can be the same, for example, both are CA9*** model chip circuits, and both are connected to the MCU through a bus. The MCU is connected to the power supply and I2C bus interface connector, and is used to receive I2C_SDA / SCL signals from the power supply and I2C bus interface connector.

[0094] The BIOS is also used to transmit address information to the MCU via a slot board (such as SLOT B) and a communication interface when the server is powered on. The MCU is used to receive a first high-speed signal from the communication interface, parse the first high-speed signal to obtain address information, and write the address information into a target chip, which is one of the at least one chip circuit.

[0095] Combined with the above Figure 5b The BIOS first transmits address information, such as CPUADDR 0 / 1 / 2 and VPPADDR 0 / 1 / 2 / 3, to MCIO connector x8 via I2C_SDA / SCL signals. MCIO connector x8 then transmits the address information to the sideband connector of the slot board. The sideband connector transmits the address information to the power supply and I2C bus interface connector of the riser card via a gold finger connector, and then to the MCU. Finally, the MCU parses the I2C_SDA / SCL signals and writes CPUADDR 0 / 1 / 2 and VPPADDR 0 / 1 / 2 / 3 to chip circuit 2. The chip circuit to which the MCU writes is predefined by software. In this embodiment, chip circuit 2 is the target chip to which the address information is written. Alternatively, the target chip can be defined as chip circuit 1, but this embodiment does not limit this.

[0096] The address information mentioned above, CPUADDR, stands for CPU address. In circuits, ADDR is often used as an abbreviation for address, which can point to a specific location, such as a storage unit in memory or a device in an I / O port. When the CPU needs to read or write data, it needs to know the corresponding address to find the correct storage unit or device. Generally, CPUADDR is used to identify the address used by the CPU when accessing memory or I / O devices. These addresses can be physical addresses or virtual addresses. In most cases, CPUADDR is used for addressing because it can point to a specific location and allow the CPU to read or write data.

[0097] VPPADDR can represent the address associated with the Voltage Programming Pin (VPP). In some cases, VPPADDR may refer to a configuration or data address associated with VPP. For example, in VPP source code or related configuration files, ADDR may be used to specify the storage location of a configuration parameter or data item.

[0098] In addition, the BIOS is also used to send a notification message to the BMC after writing the address information to the target chip; the BMC is also used to receive the first high-speed signal carrying address information and asset information sent by the MCU through the first channel between the MCU and the expansion card after receiving the notification message, thereby obtaining the address information and asset information, namely CPUADDR, VPPADDR and FRU burning asset information, through the first high-speed signal.

[0099] The BMC is also used to scan the field replaceable units and target chips on the expansion card, obtain asset information and address information, and search the processor port number corresponding to the PCIe device in the truth table based on the address information and asset information; wherein the truth table includes at least one corresponding relationship, each corresponding relationship includes a corresponding relationship between a processor port number and a truth value, and each truth value is a string used to represent address information and / or asset information.

[0100] The circuit provided in this embodiment can transmit I2C signals and I3C signals at the same time. The management design scheme is as follows Figure 6a and Figure 6b As shown:

[0101] On the management link of I2C signal transmission, for example, the I2C_SDA / SCL signal is transmitted through the first channel: the I2C signals of the BIOS and BMC chips are connected to the MCIO x8 connector after passing through the I2C arbitration chip, and are transmitted to the riser card after being transparently transmitted through the CEM Rsier slot board. The BMC and BIOS can communicate with the IC chip of the riser control board through the I2C arbitration chip respectively.

[0102] For the I3C signal transmission management link, an I3C hub chip is added to the motherboard. This I3C hub is connected upstream to a port on the BMC, such as the I3C High-Voltage Mode Bus port. For example, an I3C hub chip has eight channels, with two channels connected to an MCIO X8 connector. For the CEM riser card, since there is only one PCIe device downstream, only I3C0 needs to be connected to that PCIe device.

[0103] In one embodiment, a new bus protocol chip (I3C HUB chip) includes a first pin and multiple second pins, wherein the first pin is connected to a port of a baseboard management controller, such as a high-voltage mode port, and the multiple second pins are connected to at least one MCIO connector. The new bus protocol chip is configured to switch transmission modes based on the first pin and the multiple second pins. The transmission modes include: an integrated circuit bus protocol transmission mode (i.e., an I2C signal transmission mode) and a new bus protocol transmission mode (i.e., a new bus protocol signal transmission mode). The first pin and the multiple second pins are configured to switch between the two modes.

[0104] Specifically, the I3C HUB chip provided in this embodiment can support two communication modes, Open_Drain and Push-Pull, corresponding to the aforementioned first mode (such as Open_Drain) and the second mode (such as Push-Pull), and can dynamically switch between the two. Among them, the status of the IO pin is determined by the I2C&I3C protocol. The working state of the IO (input / output) pin of the I3C HUB chip (such as output high level, low level or high impedance state) is determined by the specific requirements of the I2C or I3C protocol. This means that the chip will configure its IO pins according to the provisions of the current communication protocol. Dynamic switching of Open_Drain / Push-Pull mode is achieved by configuring the parameters in the VIOM_LDO_Voltag register:

[0105] In Open_Drain mode, when the IO pin outputs a low level, it is connected to the power supply (usually VDDIN, here the voltage is 3.3V) through an external pull-up resistor. In this mode, the high level state of the IO pin is determined by the external pull-up resistor and the power supply voltage, usually 3.3V, which can be used to transmit I2C high-speed signals.

[0106] In push-pull mode, the chip may include an internal LDO (low-dropout linear regulator) to adjust the pull-up voltage of the IO pin. By configuring the voltage of the VIOS pin (typically 1.8V here), the IO pin's high state in push-pull mode can be set. This configuration allows the chip to lower its output voltage when communicating with low-voltage devices. This voltage is used to transmit I3C signals.

[0107] In addition, the I3C protocol assigns device addresses (such as PCIe cards) by the host, such as the BMC, using dynamic address allocation. The same I3C device can be assigned different addresses. In the I2C protocol, the device address is determined by hardware pull-up and pull-down circuits. Hard drives of the same model have the same I2C address.

[0108] To avoid I2C address conflicts, each hard drive connected to the I3C hub communicates with the host through a different channel. This ensures I2C compatibility in scenarios where the line supports I3C communication. For devices compatible with both I3C and I2C, the I3C hub allows for flexible switching of bus operating modes, achieving I2C and I3C compatibility.

[0109] The above is the hardware circuit design involved in the solution of the present invention. Based on this solution, the original chassis silk screen printing method of the BMC page is also improved. Based on this design solution, the BMC chassis silk screen printing method can be summarized as follows:

[0110] Step 1: When the server is powered on, the BIOS seizes control of the I2C bus through the I2C arbitration chip and communicates with the MCU in the CEMRsier riser card.

[0111] At this time, the BIOS will send the CPUADDR and VPPADDR (i.e., address information) corresponding to the MCIO connector to the MCU of the riser card according to the correspondence between the I2C switch chip and the MCIO connector. After the MCU chip parses the CPUADDR and VPPADDR in the address information, it will be sent to the target chip, i.e., written into the register of the target chip.

[0112] Step 2: During BIOS initialization, the BIOS scans and enumerates the PCIe bus to obtain the BDF code of each PCIe device.

[0113] In one possible implementation, the BIOS obtains the BDF code of the hard disk through the PCIe bus.

[0114] Step 3: After the BIOS sends CPUADDR and VPPADDR, that is, writes the address information to the target chip, the BIOS notifies the BMC through the eSPI signal.

[0115] Among them, eSPI (Enhanced Serial Peripheral Interface) is an enhanced SPI bus, which is a serial peripheral interface used to connect the processor and various peripherals. The BIOS and BMC communicate through eSPI signals. For example, the eSPI signal is equivalent to the notification message in the above embodiment. After receiving the eSPI signal, the BMC begins to seize the control of the I2C link of the CEM Riser. For example Figure 6a As shown, when the interface M0 of the arbitration chip 1 is turned on and the interface M1 is turned off, it is determined that the BMC has taken over the control of the link. Among them, the interface M0 is used to connect the channel between the MCIO connector and the BMC, and the interface M1 is used to connect the channel between the MCIO connector and the CPU.

[0116] In addition, the above method further comprises:

[0117] Step 4: The BMC scans the FRU and target chip in the riser card to obtain asset information as well as CPUADDR and VPPADDR information (address information). Then, based on the truth table, it determines the CPU port number corresponding to the current PCIe device. This is because the MCIO connector has a fixed correspondence with the CPU port on the hardware circuit. The truth table is developed based on this correspondence. Therefore, when obtaining a true value (such as a binary string) in the truth table, the BMC can determine the CPU port number of the current PCIe device based on the correspondence between the binary string and the CPU port number.

[0118] In another embodiment of this example, the above method also includes: in the transmission mode of the new bus protocol signal, the BMC is also used to determine the expansion card based on the PCIe device information obtained by the second channel and the second pin currently communicating with the new bus protocol chip.

[0119] Among them, the new bus protocol signal transmitted on the second channel is an I3C signal, which is used to carry information of the PCIe device; the I2C signal transmitted on the first channel is used to carry the above-mentioned address information and asset information.

[0120] Step 5: The BMC accesses the PCIe card through I3C to obtain information about the PCIe card. Since each MCIO connector has a fixed binding relationship with the I3C HUB channel in the hardware link, the BMC can identify which CEM Riser it comes from based on the selected I3C HUB channel.

[0121] Optionally, the above method further includes:

[0122] Step 6: The BIOS communicates with the BMC through eSPI signals, notifying the BMC of the BDF code obtained after PCIe scanning and enumeration. The BMC then displays the BDF code, CPUADDR, VPPADDR, FRU asset information, PCIe card asset information, and other information synchronously on the BMC Web.

[0123] This method proposes a new chassis silk screen scheme based on hardware circuit changes to support existing functions.

[0124] This embodiment provides an expansion card circuit. The motherboard includes a processor, a baseboard management controller (BMC), a new bus protocol chip, and at least one connector. The new bus protocol chip on the motherboard is a newly added chip that establishes multiple channels between the BMC and the at least one connector. These channels include a first channel that can be used to transmit a first high-speed signal to the BMC, thereby implementing I2C signal communication in hardware. The first high-speed signal carries device asset information and related address information.

[0125] In addition, the new bus protocol chip also establishes a second channel between at least one MCIO connector of the motherboard and the slot of the slot board. When an external device is inserted into the slot, the second channel can be used to access and obtain information about the external device. Because I3C communication is supported on the second channel, the present invention provides an expansion card circuit for emerging PCIe devices that support the I3C protocol. The hardware circuit of the expansion card circuit meets the CEM Riser card requirements of the PCIe6.0 protocol, realizing effective communication between the baseboard management controller BMC of the motherboard and the PCIe device. At the same time, the circuit retains the communication capability with the I2C high-speed signal, and can achieve compatibility with the I2C / I3C communication protocol.

[0126] Furthermore, the communication method provided in this embodiment allows the baseboard management controller to detect that the basic input / output system module has written address information to the target chip of the expansion card. This method can obtain a first high-speed signal carrying address information and asset information from the target chip of the expansion card via a first channel, and determine the processor port number of the external device based on this address information and asset information, thereby obtaining a new chassis silkscreen. Simultaneously, the method can obtain a second high-speed signal via a second channel to obtain information about the external device. Furthermore, the method can determine the expansion card based on the device information and the current communication connection pins of the new bus protocol chip, thereby supporting existing functions.

[0127] The expansion card circuit of the present invention is rationally designed, and the connections between the components are tight and stable. By introducing an arbitration chip and a new bus protocol chip, the conflicts and error rates during data transmission are effectively reduced, and the overall stability and reliability of the system are improved.

[0128] In another embodiment, based on the design of the above-mentioned software and hardware structure, an embodiment of the present invention also provides a communication method embodiment. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0129] In this embodiment, a communication method is provided, which can be used for the above-mentioned baseboard management controller (BMC). Figure 7 is a flow chart of a communication method according to an embodiment of the present invention. Figure 7 As shown, the method includes:

[0130] Step S101: a baseboard management controller establishes a first channel with a chip circuit on an expansion card through at least one connector, and obtains a first high-speed signal of an integrated circuit bus protocol through the first channel.

[0131] Step S102: the baseboard management controller establishes a second channel with an external device inserted into the slot board through at least one connector, and transmits a second high-speed signal of the new bus protocol through the second channel.

[0132] Step S103: the baseboard management controller determines the address information and asset information of the expansion card according to the first high-speed signal, and obtains the device information of the external device according to the second high-speed signal.

[0133] Specifically, in a possible implementation of this embodiment, step S101 specifically includes:

[0134] When the BIOS is initialized, the BMC detects whether a notification message has been received. The notification message is used to inform the BIOS that the address information has been written to the target chip of the expansion card. The notification message can be an eSPI signal / message, corresponding to the above step 3.

[0135] If yes, that is, the notification message is received, a first high-speed signal, such as an I2C_SDA / SCL signal, is obtained from the target chip of the expansion card through the first channel, and address information and asset information are obtained according to the I2C_SDA / SCL signal.

[0136] The specific process can be found in "Step 2" to "Step 4" of the aforementioned embodiment, which will not be repeated here in this embodiment.

[0137] In addition, after the above step S103, if Figure 8 As shown, the method further includes:

[0138] Step S104: the baseboard management controller determines the expansion card type according to the device information and the current communication pin of the new bus protocol chip.

[0139] Specifically, when an external PCIe device is inserted into a PCIe slot on a slot board, the BMC obtains PCIe device information, such as the PCIe device's BDF code, via the second channel. The BMC determines the expansion card type based on the PCIe device information and the pin currently communicating with the new bus protocol chip. This pin is a pin connected to the MCIO connector.

[0140] The specific process is the same as the aforementioned "Step 5", please refer to the description of "Step 5" in the aforementioned embodiment, and will not be repeated here.

[0141] The method provided in this embodiment is based on the hardware design of the CEM riser card that supports I3C communication. It is not only compatible with I2C communication, but also can obtain a new chassis silk screen based on hardware circuit changes, thereby realizing the acquisition of server chassis silk screen information.

[0142] The present invention also provides a baseboard management controller. Figure 9 , is a schematic structural diagram of a baseboard management controller provided by an optional embodiment of the present invention, the baseboard management controller includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common motherboard or in other ways as needed. The processor can process instructions executed within the BMC, including instructions stored in or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface).

[0143] In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple storages if desired. Similarly, multiple devices can be connected, with each device providing part of the necessary operations (e.g., as a server array, a group of blade servers, or a multi-processor system). Figure 9 A processor 10 is taken as an example.

[0144] The processor 10 may be a processing module or a processing circuit. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0145] The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to implement the communication method shown in the above embodiment.

[0146] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the BMC, etc. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transient memory, such as at least one disk storage device, flash memory device, or other non-transient solid-state memory device. In some optional embodiments, the memory 20 may include a memory remotely located relative to the processor 10, and these remote memories may be connected to the BMC via a network. Examples of the aforementioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0147] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0148] Optionally, the BMC also includes an input device and an output device ( Figure 9 (not shown). The processor 10, the memory 20, the input device and the output device can be connected via a bus or other means. Specifically, the input device can receive input digital or character information, and generate key signal input related to the user settings and function control of the BMC, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device may be a touch screen.

[0149] In addition, the baseboard management controller further includes at least one communication interface 30 for the BMC to communicate with other devices or a communication network.

[0150] It should be understood that in this embodiment Figure 9 The hardware structure shown can also be applied to modules such as CPU, MCU, etc. In other words, the structure of the above-mentioned devices or circuits such as CPU, MCU, BMC can be used with Figure 9 The hardware structure shown is the same, and is used to execute the communication method based on PCIe devices described in the above embodiments, meeting the communication requirements of the new CEMRiser card on the server hardware line with PCIe Gen6 rate.

[0151] An embodiment of the present invention also provides a computer-readable storage medium, and the above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded on a storage medium, or downloaded via a network and originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware.

[0152] The storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium may include a combination of the aforementioned types of memory. It is understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the communication method shown in the above embodiment is implemented.

[0153] The embodiments of the present application may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the above method. The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present disclosure, wherein the programming languages ​​include object-oriented programming languages ​​such as Java, C++, etc., and also include conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0154] The above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the embodiments of the present invention have been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An expansion card circuit that can be inserted into an external device, characterized in that: The circuit includes an expansion card, a slot board and a main board, wherein the expansion card is connected to the main board via the slot board, and the slot board is provided with a slot for inserting an external device; the main board includes a processor, a baseboard management controller, a new bus protocol chip and at least one connector; The processor is connected to the new bus protocol chip and the at least one connector, and the baseboard management controller is connected to the new bus protocol chip and the at least one connector; The baseboard management controller establishes a first channel between the at least one connector and the chip circuit on the expansion card, wherein the first channel is used to transmit a first high-speed signal of an integrated circuit bus protocol between the mainboard and the expansion card, wherein the first high-speed signal carries address information and asset information of the expansion card; The baseboard management controller establishes a second channel between the at least one connector and the external device inserted into the slot board. The second channel is used to transmit a second high-speed signal of the new bus protocol between the mainboard and the external device. The second high-speed signal carries device information of the external device.

2. The expansion card circuit according to claim 1, characterized in that: The processor includes a basic input and output system, the mainboard further includes at least one arbitration chip, and the basic input and output system is connected to the at least one arbitration chip via the at least one arbitration chip; The basic input and output system is used to transmit the first high-speed signal to the chip circuit of the expansion card after transparently transmitting through the slot board via the at least one arbitration chip and the at least one connector.

3. The expansion card circuit according to claim 2, characterized in that: The expansion card includes a microprocessor, at least one chip circuit and a communication interface; the communication interface is connected to the slot board, and the microprocessor is connected to the at least one chip circuit; The basic input and output system is further used to transmit the first high-speed signal to the microprocessor through the slot board and the communication interface; The microprocessor is configured to receive the first high-speed signal sent from the basic input / output system module, parse the first high-speed signal, and write the address information into a target chip, which is one of the at least one chip circuit.

4. The expansion card circuit according to claim 3, characterized in that: The basic input and output system is further configured to send a notification message to the baseboard management controller after writing the address information into the target chip; The baseboard management controller is further configured to receive, through the first channel, a first high-speed signal carrying the address information and asset information and sent by the microprocessor after receiving the notification message.

5. The expansion card circuit according to claim 4, characterized in that: The expansion card further includes a field replaceable unit, and the field replaceable unit is connected to the microprocessor and the at least one chip circuit via a bus; The baseboard management controller is further configured to scan the field replaceable unit (FRU) on the expansion card and the target chip to obtain asset information and address information, and to search a truth table for the processor port number corresponding to the external device based on the address information and the asset information; The truth table includes at least one corresponding relationship, each corresponding relationship includes a corresponding relationship between a processor port number and a truth value, and each truth value is a character string used to represent the address information and / or the asset information.

6. The expansion card circuit according to any one of claims 1 to 5, characterized in that: The novel bus protocol chip includes a first pin and a plurality of second pins, the first pin is connected to a port of the baseboard management controller, and the plurality of second pins are connected to the at least one connector; The novel bus protocol chip is used for switching transmission modes according to the first pin and the plurality of second pins, and the transmission modes include: a transmission mode of an integrated circuit bus protocol and a transmission mode of a novel bus protocol.

7. The expansion card circuit according to claim 6, characterized in that: The baseboard management controller is further configured to determine the type of the expansion card based on the information of the external device obtained by the second high-speed signal and the second pin currently communicating with the new bus protocol chip.

8. A communication method, characterized in that: The method is applied to an expansion card circuit that can be inserted into an external device according to any one of claims 1 to 7, and the method comprises: The baseboard management controller establishes a first channel with the chip circuit on the expansion card through at least one connector, and obtains a first high-speed signal of the integrated circuit bus protocol through the first channel; The baseboard management controller establishes a second channel with the external device inserted into the slot board through the at least one connector, and transmits a second high-speed signal of the new bus protocol through the second channel; The baseboard management controller determines the address information and asset information of the expansion card according to the first high-speed signal, and obtains the device information of the external device according to the second high-speed signal.

9. The communication method according to claim 8, wherein: Acquiring the first high-speed signal of the integrated circuit bus protocol through the first channel includes: The baseboard management controller detects whether a notification message is received when the basic input and output system is initialized, wherein the notification message is used to inform the basic input and output system that address information has been written to the target chip of the expansion card; If the notification message is received, the first high-speed signal is obtained from the expansion card through the first channel.

10. The communication method according to claim 8, wherein: After acquiring the device information of the external device according to the second high-speed signal, the method further includes: The baseboard management controller determines the expansion card type according to the device information and the pin currently communicating with the new bus protocol chip.

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