FPGA (Field Programmable Gate Array) coding method based on System Generator
By using the System Generator tool and the Mcode module in the Xilinx Blockset library, Matlab code is converted into Verilog code, which solves the problem that developers need to master multiple languages at the same time in the traditional FPGA development process, and realizes an efficient and simplified FPGA encoding process.
Patent Information
- Application Number
- CN202411742324.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-04-11
AI Technical Summary
In aircraft control and management, in the traditional FPGA development process, developers need to master the abstract Matlab language and the hardware-based Verilog language at the same time, resulting in the development process being time-consuming, error-prone and numerous steps.
Using the FPGA encoding method based on System Generator, the Matlab code is directly converted into Verilog code through the System Generator tool and the Mcode module in the Xilinx Blockset library, simplifying the development process.
This method simplifies the development process, reduces the types of languages that developers need to master, reduces error rates and development time, and achieves efficient coding from Matlab to Verilog.
Smart Images
Figure CN119808676A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of aircraft control management algorithm embedded control, and specifically relates to an FPGA coding method based on SystemGenerator. Background Art
[0002] With the improvement of algorithm efficiency and the advancement of hardware platforms, advanced control algorithms combined with real-time embedded systems such as FPGA can be used as control units in more high-sampling rate, high-frequency and fast systems in aircraft control management.
[0003] In the traditional FPGA development process, Matlab is generally used to describe each functional module and then establish a system-level model, while the FPGA's Verilog hardware development language is used to describe each module at the register transfer level. This development and design method has many disadvantages.
[0004] First of all, developers need to master not only the relatively abstract Matlab language, but also the Verilog language for hardware bottom-level development. The process of converting abstract models into hardware bottom-level descriptions requires a lot of time and effort, and it is also easy to make mistakes.
[0005] Secondly, after the abstract model described in languages such as Matlab is converted into a model described in hardware language, the hardware language model code will become the focus of the design, and the abstract model that the design developers have worked hard to build will no longer be used.
[0006] Thirdly, different stages of design require the use of different test platforms. For example, the test platform required for the model established by Matlab language cannot be directly converted into the test platform required for the model described by hardware language code.
[0007] Moreover, for large-scale, highly complex systems, the traditional development process is too slow. It requires step-by-step verification of intermediate and final results, and frequent switching between the Matlab working environment and FPGA development tools. It is difficult to achieve unified development requirements and performance in the simulation and implementation stages, and it is difficult to meet the consistency requirements of the verification results.
[0008] This application is proposed to address the problem that codes written in Matlab high-level language are difficult to quickly implement on FPGA hardware. Summary of the invention
[0009] The purpose of this application is to provide an FPGA coding method based on System Generator to solve the technical problems in the related art that the code written in Matlab high-level language is time-consuming, error-prone, and has many steps to implement on FPGA hardware.
[0010] The technical solution of this application is:
[0011] A System Generator-based FPGA coding method, comprising:
[0012] Step 1: Install System Generator and configure the Matlab version:
[0013] S11. Open Vivado software, click Add Design Tools or Devices under Help, and log in to your XILINX account to download and install.
[0014] S12. After the installation is complete, open System Generator MATLAB Configurator, configure the Matlab version, click the corresponding version-apply to complete the configuration;
[0015] Step 2: FPGA code generation: convert Matlab code into Verilog code through Mcode module:
[0016] S21. Add Xilinx Blockset module:
[0017] Add GatewayIn, GatewayOut, MCode, and System GeneratorToken modules from the Xilinx Blockset library, and add input modules such as Stair Generator and Scope modules. The Stair Generator, GatewayIn, MCode, GatewayOut, and Scope modules are connected in sequence, and the Stair Generator is connected to the Scope module.
[0018] S22. Set the Xilinx Blockset module parameters:
[0019] Double-click the System Generator Token module to open the Property Editor, select the Clocking tab, and configure the FPGA clock period and Simulink system period;
[0020] Double-click to open the MCode module, click Edit M-File, change the function name, and edit the corresponding Matlab function;
[0021] S23, Simulink simulation verification:
[0022] Run Simulink simulation to check whether the simulation results meet the requirements. If so, proceed to S24; if not, proceed to S22 to edit the corresponding Matlab function.
[0023] S24, System Generator icon parameter configuration:
[0024] Double-click the System Generator Token block to open the Property Editor, select the Clocking tab, select Post Synthesis in the Perform analysis menu, select Resource in the Analyzer type menu, and select the Compilation tab. Select the compilation target as IP catalog in the "Compilation" menu, select the FPGA device in the "Part" menu, and select Verilog as the language in the "Hardware description language" menu.
[0025] S25, Automatically generate FPGA code:
[0026] Click Generate to compile the design into hardware.
[0027] According to at least one embodiment of the present application, in the above-mentioned FPGA encoding method based on System Generator, in S11, after entering the installation interface, check System Generator for DSP, click NEXT, then Install, and wait for the installation to complete.
[0028] According to at least one embodiment of the present application, in the above-mentioned System Generator-based FPGA encoding method, in S22, the floating-point data is converted into the Xilinx fixed-point format through the xfix function.
[0029] According to at least one embodiment of the present application, the above-mentioned FPGA encoding method based on System Generator further includes:
[0030] Step 3: Check the compilation effect.
[0031] According to at least one embodiment of the present application, in the above-mentioned System Generator-based FPGA encoding method, step three includes:
[0032] S31. Open Vivado, create a new project, click Create Block Design in the process navigator, right-click in the Diagram window and select IP Settings, select "IP→Repository" under project settings, click the "Add Repository" button to add a repository, and in the "IP Repository" dialog box, locate the directory where the design IP is located, select the folder IP, and click Select to create a new repository.
[0033] S32. Click the ADDIP button in the Diagram interface, enter zynq in the search bar, double-click "ZYNQ7Processing System", add the CPU, and click Run Block Automation; right-click anywhere in the block diagram and select Add IP, enter the name of the IP core in the "Search" dialog box, and double-click to add the IP to the design; click Run Connection Automation to connect the IP to the rest of the design;
[0034] S33. Use the "Validate Design toolbar" button to confirm that there are no errors in the design, and use the xpr file in the generated ip_catalog folder to perform simulation tests.
[0035] This application has at least the following beneficial technical effects:
[0036] The present invention provides an FPGA coding method based on System Generator, which is easy to operate and does not require repeated switching between the Matlab working environment and the FPGA development tool. The unified development requirements and performance can be easily achieved in the simulation stage and the implementation stage. Developers do not need to fully master both high-level languages such as Matlab and low-level hardware description languages such as Verilog. The development process has fewer steps and consumes less time. The coding problem from Matlab high-level language to hardware description languages such as Verilog that can be used for FPGA can be solved. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 It is a schematic diagram of an FPGA encoding method based on System Generator provided in an embodiment of the present application;
[0038] Figure 2 is a schematic diagram of the System Generator installation interface provided in an embodiment of the present application;
[0039] Figure 3It is a schematic diagram of the System Generator MATLAB Configurator interface provided in the embodiment of the present application;
[0040] Figure 4 It is a schematic diagram of configuring the Matlab version provided in the embodiment of the present application;
[0041] Figure 5 It is a schematic diagram of opening MATLAB from System Generator provided in an embodiment of the present application;
[0042] Figure 6 is a schematic diagram of the Xilinx Blockset toolbox provided in an embodiment of the present application;
[0043] Figure 7 is a schematic diagram of a System Generator interface provided in an embodiment of the present application;
[0044] Figure 8 is a schematic diagram of a System Generator module property editor provided in an embodiment of the present application;
[0045] Fig. 9 It is a schematic diagram of the final connection diagram of the IP core provided in the embodiment of the present application;
[0046] Fig.10 It is a schematic diagram of the simulation results of the code provided in the embodiment of the present application in Simulink;
[0047] Fig.11 It is a schematic diagram of the simulation results of the code provided in the embodiment of the present application in Vivado.
[0048] In order to better illustrate the present embodiment, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product. In addition, the drawings are only used for illustrative purposes and should not be construed as limitations on the present application. DETAILED DESCRIPTION
[0049] In order to make the technical solution and advantages of the present application clearer, the technical solution of the present application will be described in further detail in detail and in detail with reference to the accompanying drawings. It can be understood that the specific embodiments described here are only partial embodiments of the present application, which are only used to explain the present application, not to limit the present application. It should be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, and other related parts can refer to the general design.
[0050] In addition, unless otherwise defined, the technical terms or scientific terms used in the description of this application shall have the usual meanings understood by those of ordinary skill in the art to which this application belongs. The words used in the description of this application to indicate orientation are only used to indicate relative directions or positional relationships. When the absolute position of the described object changes, its relative positional relationship may also change accordingly. The word "include" used in the description of this application indicates that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, but does not exclude other elements or objects.
[0051] In addition, it should be noted that, unless otherwise clearly specified and limited, the words "installation", "connection" and similar terms used in the description of this application should be understood in a broad sense. For example, the connection can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Technical personnel in the field can understand its specific meaning in this application according to the specific circumstances.
[0052] The present application provides an FPGA coding method based on System Generator, which adopts the System Generator tool and uses the Mcode module in the Xilinx Blockset library to directly convert the Matlab code in the module into Verilog code with equivalent behavior.
[0053] The FPGA coding method based on System Generator provided in this application needs to establish a Simulink project after completing the installation of System Generator and the configuration of the Matlab version, drag in basic modules such as System Generator Token, Gateway In, Gateway Out, and other modules required in Xilinx Blockset, and configure the module parameters, and then verify whether the built modules meet the requirements in the Simulink environment, and then select the appropriate hardware property configuration through the SystemGenerator Token module, such as compilation type, device model on the development board, hardware description language selection, system clock cycle, etc., and finally click the "System Generator" button to automatically generate code.
[0054] The FPGA coding method based on System Generator provided in this application is as follows: Figure 1 shown.
[0055] First, complete the installation of System Generator and the configuration of the Matlab version. Then, for a specific Matlab code, convert it into Verilog code through the Mcode module.
[0056] 1) Install System Generator and configure the Matlab version:
[0057] Open the Vivado software, click Add Design Tools or Devices under Help, and log in to your XILINX account to download and install.
[0058] After entering the installation interface, check System Generator for DSP, click NEXT, then Install, and wait for the installation to complete. Figure 2 shown.
[0059] After the installation is complete, open the System Generator MATLAB Configurator, such as Figure 3 As shown, configure the Matlab version, click the corresponding version-apply to complete the configuration, such as Figure 4 shown.
[0060] 2) FPGA code generation, converting Matlab code into Verilog code through the Mcode module:
[0061] After completing the installation and configuration of System Generator, perform FPGA code generation on a specific Matlab code.
[0062] Running System Generator will automatically open Matlab, such as Figure 5 Open Matlab-Simulink and you can see that there is an additional Xilinx Blockset toolbox in the simulation library, as shown in the figure below. Figure 6 shown.
[0063] Xilinx Blockset toolbox contains a variety of functional modules. Here we introduce how to use Mcode, which is used to execute MATLAB functions in the Simulink environment. When exporting the System Generator design to FPGA, the software will convert the MATLAB code into the corresponding HDL model, thereby converting the controller's MATLAB code into Verilog code for FPGA. The specific process is as follows:
[0064] (1) Add Xilinx Blockset module:
[0065] In order to generate the controller's MATLAB code into Verilog code, add GatewayIn, GatewayOut, MCode, and System Generator Token modules from the Xilinx Blockset library, and add input modules such as StairGenerator and Scope modules. Among them, Stair Generator, GatewayIn, MCode, GatewayOut, and Scope modules are connected in sequence, and Stair Generator is connected to the Scope module, such as Figure 7 shown.
[0066] By setting Figure 7 The model shown can be used to simulate and verify the running effect of the MATLAB code in the Simulink environment before code generation, and the code in the Mcode module can be generated into a hardware description language through the System Generator Token module, so that it can be implemented on the FPGA.
[0067] (2) Set the Xilinx Blockset module parameters:
[0068] Double-click the System Generator Token module to open the Property Editor, select the Clocking tab, and configure the FPGA clock period and Simulink system period.
[0069] Double-click to open the MCode module, click Edit M-File, change the function name, and edit the corresponding Matlab function. Note that you need to use the xfix function to convert floating-point data into the Xilinx fixed-point format supported by the MCode module. After editing, save the Matlab code file.
[0070] (3) Simulink simulation verification:
[0071] Run the Simulink simulation to check whether the simulation results meet the requirements. If so, proceed to (4); if not, proceed to (2) to edit the corresponding Matlab function.
[0072] (4) System Generator icon parameter configuration:
[0073] Double-click the System Generator Token block to open the Property Editor, select the Clocking tab, select Post Synthesis in the Perform analysis menu, select Resource in the Analyzer type menu, which provides detailed information about resource usage after completion, and select the Compilation tab. In the Compilation menu, select IP catalog as the compilation target to ensure that the output is in the IP catalog format, such as Figure 8 As shown, in addition, select the FPGA device in the "Part" menu and select Verilog as the language in the "Hardware description language" menu.
[0074] (5) Automatically generate FPGA code:
[0075] After configuration is complete, click Generate to compile the design into hardware.
[0076] 3) Check the compilation effect:
[0077] After the compilation is completed, the output of the design compilation process will be written to the set directory (netlist by default). The ip subdirectory under this directory contains the design IP, which needs to be imported into Vivado below.
[0078] (1) Open Vivado, create a new project, click Create Block Design in the process navigator, right-click in the Diagram window and select IP Settings, select "IP→Repository" under Project Settings, click the "Add Repository" button to add a repository, and in the "IP Repository" dialog box, locate the directory where the design IP is located, select the folder IP, and click Select to create a new repository.
[0079] (2) After the library is created, click the ADDIP button in the Diagram interface, enter zynq in the search bar, double-click "ZYNQ7 Processing System", add the CPU, and click Run Block Automation; right-click anywhere in the block diagram and select Add IP, enter the name of the IP core in the "Search" dialog box, and double-click to add the IP to the design; click Run Connection Automation to connect the IP to the rest of the design. The connection diagram is shown below. Fig. 9 shown.
[0080] (3) Once the connection is complete, use the "Validate Design toolbar" toolbar button to confirm that the design has no errors. At this point, the design from System Generator has been successfully integrated into the IP Integrator design. The IP in the repository can be used in any Vivado project by simply adding the repository to the project.
[0081] The generated ip_catalog folder contains xpr files that can be used directly for simulation. Simulate them and compare the test results with the simulation results in Matlab, the simulation results in Simulink, and the simulation results in Vivado, such as Figure 10-11 shown.
[0082] Depend on Fig.10 and Fig.11 It can be seen that the simulation results of the code in Vivado are basically consistent with the simulation results in Matlab, so it is verified that the hardware code obtained by System Generator encoding can meet the requirements.
[0083] The FPGA coding method based on System Generator disclosed in the above embodiment is easy to operate and has fewer development process steps. Developers do not need to fully master both high-level languages such as Matlab and low-level hardware description languages such as Verilog. This can reduce a lot of time and energy consumption in the conversion process between the two languages, and also avoid repeated testing and switching between the two languages under their respective test platforms caused by errors during language conversion. This makes it easy to achieve unified development requirements and performance in the simulation stage and the implementation stage, and is less time-consuming. This can solve the coding problem from Matlab high-level language to hardware description languages such as Verilog that can be used for FPGA.
[0084] So far, the technical solution of the present application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. Those skilled in the art should understand that the scope of protection of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the scope of protection of the present application.
Claims
1. A System Generator-based FPGA encoding method, characterized in that: include: Step 1: Install System Generator and configure the Matlab version: S11. Open Vivado software, click Add Design Tools or Devices under Help, and log in to your XILINX account to download and install. S12. After the installation is complete, open System Generator MATLAB Configurator, configure the Matlab version, click the corresponding version-apply to complete the configuration; Step 2: FPGA code generation: convert Matlab code into Verilog code through Mcode module: S21. Add Xilinx Blockset module: Add GatewayIn, GatewayOut, MCode, and System GeneratorToken modules from the Xilinx Blockset library, and add input modules such as Stair Generator and Scope modules. The Stair Generator, GatewayIn, MCode, GatewayOut, and Scope modules are connected in sequence, and the Stair Generator is connected to the Scope module. S22. Set the Xilinx Blockset module parameters: Double-click the System Generator Token module to open the Property Editor, select the Clocking tab, and configure the FPGA clock period and Simulink system period; Double-click to open the MCode module, click Edit M-File, change the function name, and edit the corresponding Matlab function; S23, Simulink simulation verification: Run Simulink simulation to check whether the simulation results meet the requirements. If so, proceed to S24; if not, proceed to S22 to edit the corresponding Matlab function. S24, System Generator icon parameter configuration: Double-click the System Generator Token block to open the Property Editor, select the Clocking tab, select Post Synthesis in the Perform analysis menu, select Resource in the Analyzer type menu, and select the Compilation tab. Select the compilation target as IP catalog in the "Compilation" menu, select the FPGA device in the "Part" menu, and select Verilog as the language in the "Hardware description language" menu. S25, Automatically generate FPGA code: Click Generate to compile the design into hardware.
2. The FPGA encoding method based on System Generator according to claim 1, characterized in that: In S11, after entering the installation interface, check System Generator for DSP, click NEXT, then Install, and wait for the installation to complete.
3. The FPGA encoding method based on System Generator according to claim 1, characterized in that: In S22, the floating-point data is converted to the Xilinx fixed-point format through the xfix function.
4. The FPGA encoding method based on System Generator according to claim 1, characterized in that: Also includes: Step 3: Check the compilation effect.
5. The FPGA encoding method based on System Generator according to claim 1, characterized in that: Step three includes: S31. Open Vivado, create a new project, click Create Block Design in the process navigator, right-click in the Diagram window and select IP Settings, select "IP→Repository" under project settings, click the "AddRepository" button to add a repository, and in the "IP Repository" dialog box, locate the directory where the design IP is located, select the folder IP, and click Select to create a new repository. S32. Click the ADDIP button in the Diagram interface, enter zynq in the search bar, double-click "ZYNQ7 ProcessingSystem", add the CPU, and click Run Block Automation; right-click anywhere in the block diagram and select AddIP, enter the name of the IP core in the "Search" dialog box, and double-click to add the IP to the design; click Run ConnectionAutomation to connect the IP to the rest of the design; S33. Use the "Validate Design toolbar" button to confirm that there are no errors in the design, and use the xpr file in the generated ip_catalog folder to perform simulation tests.