Function security verification optimization method and system, readable storage medium and product

Abstract

The invention provides a function security verification optimization method and system, a readable storage medium and a product, and belongs to the technical field of integrated circuits. The method comprises the following steps: performing redundancy isolation violation check on a plurality of functional security modules in the chip layout; if the redundancy isolation violation exists, adjusting the module position in the chip layout according to the redundancy isolation violation, the design rule, the function safety requirement, the chip data flow information and the time sequence priority information, and obtaining the adjusted chip layout; and evaluating the adjusted chip layout, and determining a target chip layout. Through the function security verification optimization method provided by the invention, physical isolation check of redundant design of the function security module is realized, the deficiency of physical isolation check of redundant design in the traditional technology is made up, feedback information of a verification process is increased, and a chip layout with a higher optimization degree can be obtained.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and in particular, relates to a functional safety verification optimization method, system, readable storage medium and product. Background Art

[0002] In safety-critical fields such as modern automobiles and aerospace, integrated circuits need to have a high degree of fault tolerance and fault detection mechanisms to ensure that they can maintain normal operation in the face of hardware failures. Standards such as ISO26262 put forward functional safety requirements for chip design, which not only involves redundancy mechanisms in front-end design, but also includes physical implementation, timing verification, power consumption, and electrical integrity in the back-end process.

[0003] However, in traditional verification optimization methods, when dealing with functional safety (FUSA) design, they only focus on the verification optimization of design rules, resulting in less verification feedback information and thus low optimization of chip layout. Summary of the invention

[0004] The purpose of this application is to provide a functional safety verification optimization method, system, readable storage medium and product, aiming to solve the problem of low optimization degree caused by insufficient verification feedback information in the verification optimization method.

[0005] A first aspect of an embodiment of the present application provides a functional safety verification optimization method, comprising:

[0006] Placing multiple modules in an initial layout structure according to design rules, functional safety requirements, chip data flow information, and timing priority information to obtain a chip layout; wherein the multiple modules include multiple functional safety modules;

[0007] Performing a redundant isolation violation check on the plurality of functional safety modules in the chip layout;

[0008] If there is a redundant isolation violation, adjusting the module position in the chip layout according to the redundant isolation violation and the first information to obtain an adjusted chip layout; the first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information;

[0009] Evaluating the adjusted chip layout to obtain an evaluation result;

[0010] According to the evaluation results, the target chip layout is determined.

[0011] A second aspect of the embodiment of the present application provides a functional safety verification optimization method, comprising:

[0012] Obtain chip layout at the engineering change order stage;

[0013] Performing redundant isolation violation checks and / or interpenetration violation checks on multiple functional safety modules after wiring in the chip layout at the engineering change order stage;

[0014] If there is a redundant isolation violation and / or a wiring interpenetration violation, adjusting the module position and the wiring in the chip layout according to the redundant isolation violation and / or the wiring interpenetration violation and the first information to obtain an adjusted chip layout; wherein the first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information;

[0015] Evaluating the adjusted chip layout to obtain an evaluation result;

[0016] According to the evaluation results, the target chip layout is determined.

[0017] A third aspect of the embodiment of the present application provides a functional safety verification optimization system, including:

[0018] A layout acquisition module, used to place multiple modules in an initial layout structure according to design rules, functional safety requirements, chip data flow information, and timing priority information to obtain a chip layout; wherein the multiple modules include multiple functional safety modules;

[0019] A redundant isolation violation checking module, used for performing redundant isolation violation checking on the plurality of functional safety modules in the chip layout;

[0020] A layout adjustment module, configured to adjust the module position in the chip layout according to the redundant isolation violation and first information to obtain an adjusted chip layout if there is a redundant isolation violation; the first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information;

[0021] An evaluation module, used to evaluate the adjusted chip layout to obtain an evaluation result;

[0022] The determination module is used to determine the target chip layout according to the evaluation result.

[0023] A fourth aspect of the embodiments of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of the above embodiments are implemented.

[0024] A fifth aspect of the embodiments of the present application provides a computer program product, including a computer program. When the computer program is executed by a computer, the steps of the method described in any one of the above embodiments are implemented.

[0025] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0026] In the functional safety verification optimization method provided by the present application, a redundant isolation violation check is performed on multiple functional safety modules in the chip layout. If there is a redundant isolation violation, the position of the module in the chip layout is adjusted according to the redundant isolation violation to obtain the adjusted chip layout. Through the functional safety verification optimization method provided by the present application, the physical isolation check of the redundant design of the functional safety module is realized, which makes up for the lack of physical isolation check of the redundant design in the traditional technology, and increases the feedback information of the verification process for the functional safety design, making the optimization direction clearer and improving the accuracy of the design verification. Thus, according to the redundant isolation violations, design rules, functional safety requirements, chip data flow information and timing priority information of the verification feedback, the chip layout is adjusted and optimized, and a more optimized chip layout can be obtained, which increases the accuracy of the chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic flow chart of the steps of verifying and optimizing chip layout using a functional safety verification optimization method in some embodiments provided in the present application.

[0028] Figure 2 A schematic flow chart of the steps of verifying and optimizing the chip layout at the engineering change instruction stage using a functional safety verification optimization method in some embodiments provided in the present application.

[0029] Figure 3 A schematic diagram of the structure of a functional safety verification optimization system in some embodiments provided in this application.

[0030] Figure 4 A schematic diagram of the structure of a functional safety verification optimization system for chip layout at the engineering change order stage in some embodiments provided in the present application. DETAILED DESCRIPTION

[0031] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0032] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0033] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0034] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0035] See also Figure 1 , the present application provides a functional safety verification optimization method, comprising:

[0036] Step S110, placing multiple modules in an initial layout structure according to design rules, functional safety requirements, chip data flow information, and timing priority information to obtain a chip layout; wherein the multiple modules include multiple functional safety modules.

[0037] In step S110, the initial floorplan structure can be understood as the floorplan structure obtained after initializing the floorplan data structure. The initial floorplan structure can be used to describe the position, shape, size and relationship between multiple required modules on the chip, and provide a blueprint for the subsequent placement and wiring of multiple modules. The initial floorplan structure includes simulated layout structures such as polygonal area division and position division, which can provide space for multiple modules. Each module includes multiple cells, which can realize different functions in the chip.

[0038] Among them, the functional safety modules include the main core module (MAIN) and shadow core module (SHADOW) based on the dual core lock step (DCLS) safety architecture, and multiple modules based on the triple modular redundancy (TMR) and dual modular redundancy (DMR) safety architecture.

[0039] The main core module (MAIN) and the shadow core module (SHADOW) are processing core modules with the same function and structure. For example: microprocessor core module, digital signal processor core module, graphics processing unit core module, etc. In the DCLS architecture, the main core module (MAIN) and the shadow core module (SHADOW) both implement error detection and fault tolerance by synchronously executing the same operation and comparing the results. The shadow core module (SHADOW) is a backup module of the main core module (MAIN). They are two independently running modules that are not affected by each other.

[0040] Triple Module Redundancy (TMR) is a commonly used fault-tolerant technology used to improve system reliability and safety. The TMR structure detects and corrects errors by tripling key components and performing a voting mechanism. The TMR safety architecture includes triple modules, a voter based on a voting mechanism, and an error detection and correction circuit. Triple modules can be understood as three independent redundant modules that perform the same functions as each other, and the three independent redundant modules operate independently to ensure that the failure of a single redundant module does not affect other modules. The voter is the core component of the triple module redundancy (TMR) architecture, which is used to receive and compare the outputs of the three independent redundant modules. If two or more of the three outputs are consistent, the voter uses the consistent output as the final output. If a redundant module fails, the voter can cover up the failure through majority voting to ensure continued normal operation. At the same time, the error detection and correction circuit can detect inconsistencies between the three independent redundant modules and identify the faulty module, so as to isolate or restart the faulty module to restore its function.

[0041] The main core module (MAIN) and shadow core module (SHADOW) based on the dual core lockstep (DCLS) safety architecture need to meet the physical location isolation requirements and the clock isolation requirements, etc. The multiple modules based on the multiple module redundancy (TMR or DMR) safety architecture also need to meet the physical location isolation requirements and the clock isolation requirements, etc., to ensure the effectiveness of mutual backup in the functional safety module.

[0042] In the design of the chip front end, the flow path and method of data between the various functional modules of the chip, including the input, processing, storage and output of data, forms the chip data flow information in step S10. The chip data flow information includes data information between multiple functional safety modules and other modules. The chip data flow information containing multiple functional safety modules can constrain the placement, connection and mobility of multiple modules in subsequent steps to realize various functions in the front-end design.

[0043] Timing priority information can be understood as the priority of the timing path, or as the relative importance ranking given to different data paths, operations or events when considering the time sequence and precedence of data transmission. Through the timing priority information, it can be determined which timing paths are most critical to the overall timing performance and need to be given priority in the design optimization process. The timing path can be understood as a combination of multiple modules and interconnects that the data signal passes through from the starting point to the end point. Each timing path has a corresponding start clock and end clock, as well as related timing constraints. Therefore, the timing priority information can be used as a basis for placing multiple modules in the initial layout structure, fully considering the timing requirements of multiple functional safety modules and ensuring the timing consistency of multiple functional safety modules.

[0044] Design rules cover multiple dimensions of chip design, including rules that need to be met in functional design, timing design, physical design, etc. Design rules can be understood as rules formulated based on manufacturing processes and performance optimization, which are standardized and universal. Functional safety requirements can be understood as requirements for safety-related modules in the automotive electronics field, aerospace field, etc., such as the layout requirements of functional safety modules such as the main core module (MAIN), shadow core module (SHADOW), and multiple modules. Functional safety requirements can be understood as starting from a safety perspective, focusing on the chip's tolerance to faults, and ensuring that the chip can still maintain a safe state under various possible fault conditions. Through the design of functional safety requirements, it can be ensured that the chip can still operate safely in the face of hardware failures, software errors, external interference, etc. Based on the design rules, functional safety requirements, chip data flow information, and timing priority information, multiple modules are placed in the initial layout structure to obtain the chip layout to ensure that each layout requirement is met.

[0045] Step S120 , performing a redundant isolation violation check on multiple functional safety modules in the chip layout.

[0046] In step S120, the chip layout includes multiple functional safety modules and other modules required by the chip. Redundant isolation violation check can be understood as a physical isolation check for the redundant design of the functional safety module. By performing redundant isolation violation checks on multiple functional safety modules in the chip layout, the mutual independence between the main core module and the shadow core module based on the dual-core lock-step structure can be ensured, and the mutual independence between the multiple modules can be ensured, avoiding problems such as physical close-proximity failures, physical interference, and common mode failures.

[0047] Step S130, if there is a redundant isolation violation, adjust the module position in the chip layout according to the redundant isolation violation and the first information to obtain an adjusted chip layout; the first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information.

[0048] It can be understood that when adjusting the module position in the chip layout, one or more of the design rules, functional safety requirements, chip data flow information, and timing priority information can be used as the basis for adjustment and optimization, so that the adjusted chip layout can meet one or more of the following information: design rules, functional safety requirements, chip data flow information, and timing priority information.

[0049] Redundant isolation violations can reflect errors in the physical isolation of the redundant design of the functional safety module, and can adjust the position of the module in the chip layout in a more targeted manner.

[0050] Step S140, evaluating the adjusted chip layout to obtain an evaluation result.

[0051] While adjusting the position of the module in the chip layout according to the redundant isolation violation, the chip data flow information and timing priority information are used as the basis for adjustment and optimization, which can ensure that multiple functional safety modules can realize data flow arrangement under the premise of meeting the timing requirements, and ensure the physical isolation of the redundant design of the functional safety module. Among them, when adjusting the position of the module in the chip layout, the adjustment can be made around the functional safety module with redundant isolation violation, and it is not limited to adjusting only the functional safety module with redundant isolation violation, and the position of other modules associated with the functional safety module can also be adjusted.

[0052] The evaluation of the adjusted chip layout can be understood as evaluating the adjusted chip layout by deducting points or scoring the adjusted chip layout.

[0053] Step S150, determining the target chip layout according to the evaluation result.

[0054] The evaluation result can be understood as the score after deduction calculation or the score after scoring calculation. By evaluating the adjusted chip layout, it can be known whether the adjusted chip layout meets the design rules, functional safety requirements, chip data flow information, and timing priority requirements. The evaluation result can reflect the optimization of the adjusted chip layout. Furthermore, it is determined whether the adjusted chip layout can be used as the target chip layout based on the evaluation result.

[0055] Thus, in the functional safety verification optimization method provided by the present application, a redundant isolation violation check is performed on multiple functional safety modules in the chip layout. If there is a redundant isolation violation, the position of the module in the chip layout is adjusted according to the redundant isolation violation to obtain the adjusted chip layout. Through the functional safety verification optimization method provided by the present application, the physical isolation check of the redundant design of the functional safety module is realized, which makes up for the lack of physical isolation check of redundant design in traditional technology, increases the feedback information of the verification process, makes the optimization direction clearer, and improves the accuracy of design verification. Thus, according to the redundant isolation violations, design rules, functional safety requirements, chip data flow information and timing priority information of the verification feedback, the chip layout is adjusted and optimized, and a more optimized chip layout can be obtained, which increases the accuracy of the chip design.

[0056] In one embodiment, before step S110, the functional safety verification optimization method further includes:

[0057] Step S101, obtaining an initial layout structure, chip data flow information and timing priority information of a plurality of functional safety modules in a chip front end.

[0058] In this embodiment, the chip data flow information can be obtained from the chip front-end design. Obtain the design constraint file (Synopsys Design Constraints, SDC). According to the design constraint file, parse the clock tree, and calculate the clock weight according to the clock tree. According to the clock weight and timing convergence information, the timing path is weighted and ranked to obtain the timing weight ranking information. According to the weight ranking information, determine the timing priority information of multiple modules in the data flow information.

[0059] SDC files are standard files used to describe constraints in integrated circuit design. SDC files include constraint information for various clock signals, input and output delays, timing exceptions, etc. in the design. Information such as clock definition, clock frequency, relationship between clocks, and other constraints related to timing can be obtained from SDC files, which can provide the required data for parsing clock trees and timing analysis in subsequent steps.

[0060] By parsing the clock tree, we can get information about the clock signal, such as the connection relationship between each clock node, the propagation path, delay, etc. Based on the data provided by the clock tree, the functional criticality of the reference clock domain, the data flow size, the participation of the clock signal on the critical path, etc., a corresponding weight value is assigned to each clock signal, that is, the clock weight is obtained.

[0061] Timing convergence information can be understood as the degree of influence of different clock signals and timing paths on timing convergence. Timing convergence information includes the difficulty of timing convergence. The difficulty of timing convergence is high, which can be understood as the difficulty of completing all timing constraints for the timing path driven by the clock signal due to complex logic structure or transmission delay. The difficulty of timing convergence is low, which can be understood as the difficulty of completing all timing constraints for the timing path driven by the clock signal. Through the clock weight and timing convergence information, different weights can be assigned to the timing path to obtain the timing weight ranking information. Then, the timing priority information is determined according to the timing weight ranking information.

[0062] In one embodiment, in step S110, the step of placing multiple modules in an initial layout structure according to design rules, functional safety requirements, chip data flow information, and timing priority information to obtain a chip layout includes:

[0063] Step S111, placing multiple modules in the initial layout structure according to the timing priority information;

[0064] Step S112, if the position of the module meets the design rules, functional safety requirements and chip data flow information, then maintain the current position;

[0065] Step S113: if the position of each module does not comply with the design rules, functional safety requirements and chip data flow information, the layout adjusts the position of the module.

[0066] In this embodiment, the timing priority information is derived from the design constraint file (SDC file), which enables the timing requirements of multiple functional safety modules to be fully considered when laying out the chip layout, and the clock jitter and delay of the voting logic in the multiplexed module and the lock-step logic of the main core module and the shadow core module to be comprehensively considered. Based on the design rules, functional safety requirements, chip data flow information and timing priority information, the obtained chip layout can ensure that the chip realizes the predetermined functions, the collaborative work between modules, the timing accuracy, signal integrity, reliability, stability and cost controllability, etc., and meet the needs of modern automobiles, aerospace and other safety fields.

[0067] In one embodiment, step S140, evaluating the adjusted chip layout to obtain an evaluation result, includes:

[0068] Step S141, performing a deduction calculation on the chip layout after the first adjustment to obtain a first deduction result, and continuing to perform steps S120 and S130 to obtain the chip layout after the second adjustment;

[0069] Step S142, performing a deduction calculation on the chip layout after the second adjustment to obtain a second deduction result, and continuing to perform steps S120 and S130 to obtain the chip layout after the third adjustment;

[0070] Step S143, performing a deduction calculation on the chip layout after the third adjustment to obtain a third deduction result.

[0071] In one embodiment, step S150, determining the target chip layout according to the evaluation result, includes:

[0072] Step S151, determining the deduction result with the least deduction according to the first deduction result, the second deduction result and the third deduction result, and obtaining the corresponding chip layout as the target chip layout according to the deduction result with the least deduction.

[0073] In this embodiment, the deduction calculation includes the deduction calculation of the number of module units in the chip layout, the timing deduction calculation, the power distribution deduction calculation, the pin density deduction calculation, etc., which do not meet the design rules, functional safety requirements, and chip data flow information. Through steps S141 to S142, steps S120 and S130 are repeatedly iterated to find the chip layout with the least deduction as the target chip layout. The number of repeated iterations is not limited in this application and can be set according to actual conditions to ensure that no new violations are generated in the target chip layout. Through the method provided in this application, the chip layout is iteratively optimized for multiple times, and more refined adjustments can be achieved until the chip layout with the least deduction is obtained, which can ensure that the functional safety module can realize the arrangement of data flow under the premise of meeting the timing requirements, realize the timing consistency of the functional safety module, and ensure the physical isolation of the redundant design of the functional safety module.

[0074] In one embodiment, after step S110 and before step S120, the functional safety verification optimization method further includes:

[0075] Step S114, checking the number of cells in the plurality of modules of the chip layout;

[0076] Step S115, if the number of cells is greater than the design number upper limit threshold or less than the design number lower limit threshold, then step S110 is executed to adjust the number and position of cells in the multiple modules placed in the initial layout structure. The design number upper limit threshold or less than the design number lower limit threshold can be set according to actual design requirements.

[0077] In this embodiment, each unit in the chip layout has different functions. The number of units is greater than the lower limit threshold of the design number, which can ensure that the basic functions of the chip can be realized. The number of units is less than the upper limit threshold of the design number, which can avoid problems such as waste of resources or excessive power consumption, and effectively control the cost of the chip. Furthermore, the number of units is greater than the lower limit threshold of the design number and less than the upper limit threshold of the design number, which can avoid problems such as waste of resources or excessive power consumption while meeting the chip performance requirements.

[0078] Therefore, when the number of units is greater than the upper limit threshold of the design number or less than the lower limit threshold of the design number, it is necessary to adjust the number and position of units in multiple modules to meet the requirement that the number of units is greater than the lower limit threshold of the design number and less than the upper limit threshold of the design number, so as to ensure the functional integrity of the chip and control the chip cost.

[0079] In one embodiment, after step S150, the functional safety verification optimization method further includes:

[0080] Step S160: adjusting the main core module and the shadow core module in the target chip layout according to a genetic algorithm or a simulated annealing algorithm.

[0081] In this embodiment, based on the layout of the target chip, the positions of the main core module and the shadow core module are fine-tuned so that when a fault occurs in the main core module, the shadow core module can detect the fault signal of the main core module more quickly and complete the state switching in a short time, seamlessly taking over the tasks of the main core module, ensuring that the functions of the chip are not affected and improving the fault tolerance of the chip.

[0082] In one embodiment, step S120, the step of performing redundant isolation violation checks on multiple functional safety modules in the chip layout, includes:

[0083] Step S121, setting a checkpoint for each group of functional safety modules in a plurality of functional safety modules according to design rules and functional safety requirements; wherein each group of functional safety modules includes at least two functional safety modules that are independent of each other and have the same functions;

[0084] Step S122 : checking physical position violations between the functional safety modules in each group of functional safety modules according to the checkpoints.

[0085] In this embodiment, in step S121, the chip layout defines the physical locations of all module units. Initialize the checkpoints in step S122. According to the design rules and functional safety requirements, checkpoints are set to identify the physical location requirements, clock isolation requirements, and boundary isolation requirements of the target area for inspection. Redundant isolation violation checks are performed using a checkpoint-to-checkpoint inspection method. Point-to-point can be one module to another module, or one functional unit to another functional unit, or one interface to another interface, etc.

[0086] Through design rules, the boundaries of multiple functional safety modules can be checked to avoid crossing the boundaries between each functional safety module in each group of functional safety modules, ensure that the boundaries between each functional safety module in each group of functional safety modules are clear, and achieve logical isolation. Through functional safety requirements, the hierarchical constraints, physical distances, and clock isolation between each functional safety module in each group of functional safety modules can be checked to ensure the physical isolation of the redundant design between each functional safety module in each group of functional safety modules. Each group of functional safety modules can include two independent and functionally identical functional safety modules, namely the main core module (MAIN) and the shadow core module (SHADOW) based on the dual-core lockstep (DCLS) safety architecture. Each group of functional safety modules can also include a dualized module or a triple module based on a multiple module redundancy (TMR or DMR) safety architecture.

[0087] In step S122, the physical position violation can be understood as the situation of the physical isolation position of the redundant design of the functional safety module in the design rules and functional safety requirements that occurs during the verification process. Through steps S121 and S122, checkpoints for the functional safety module can be set in the chip layout, and based on the checkpoints, the physical positions between each functional safety module in each group of functional safety modules can be checked and verified. By checking and verifying the physical positions between each functional safety module in each group of functional safety modules, physical position violations for functional safety requirements can be found in a timely manner, so that the module position of the chip layout can be adjusted in a timely manner based on the physical position violation, and iterative optimization can be completed.

[0088] In one embodiment, step S122, the step of checking physical position violations between functional safety modules in each group of functional safety modules, includes:

[0089] Step S1221, checking the hierarchical constraint information between each functional safety module in each group of functional safety modules;

[0090] Step S1222: If the hierarchical constraint information does not exist between any two functional safety modules, it is determined that a hierarchical constraint violation exists between any two functional safety modules.

[0091] In this embodiment, the hierarchical constraint information can be understood as the relevant information for regulating and managing the multiple levels divided in the chip design structure. Under normal circumstances, the functional safety modules in each group of functional safety modules need to be designed to have a relationship with hierarchical constraint information. However, in abnormal circumstances, during the adjustment and optimization process, the hierarchical constraint information will be removed and lost. By checking the hierarchical constraint information between each functional safety module in each group of functional safety modules in each network in step S1221 in this embodiment, it can be ensured that the hierarchical constraint information between each functional safety module is not lost.

[0092] In step S1222, if the hierarchical constraint information is missing, it indicates that the hierarchical constraint information that should normally exist is lost, which is an abnormal situation, and it is considered that there is a hierarchical constraint violation. Then, according to the hierarchical constraint violation, the hierarchical constraint information between each functional safety module in the chip layout is adjusted and supplemented in time to ensure the correctness, manufacturability and performance optimization of the chip design.

[0093] In one embodiment, in step S1221, each functional safety module in each group of functional safety modules may be a duplex module or a triplex module. Through step S1221 and step S1222, it is possible to check whether there is hierarchical constraint information in the duplex module or the triplex module, so as to ensure that the redundant logic of the duplex module or the triplex module is not lost, thereby protecting the integrity of the redundant structure of the duplex module or the triplex module, so that the mutual independence between them is not destroyed.

[0094] In one embodiment, step S122, the step of checking physical position violations between functional safety modules in each group of functional safety modules, includes:

[0095] Step S1223, checking a first physical distance between two identical functional units in a main core module and a shadow core module of each group of functional safety modules;

[0096] Step S1224: If the first physical distance is less than or equal to the first distance threshold, a physical distance violation occurs.

[0097] In this embodiment, in step S1223, the first physical distance can be calculated by a geometric distance formula. The shadow core module (SHADOW) is a backup module of the main core module (MAIN), and is two independently running modules. Each unit in the shadow core module corresponds to each unit in the main core module one by one. The functions of each pair of units are the same.

[0098] In step S1224, the first physical distance is compared with the first distance threshold. The first distance threshold can be determined by the maximum value of the minimum spacing value of the process node, the spacing requirement value based on the automotive safety integrity level (ASIL), the thermal effect isolation distance value, the crosstalk limit distance value, and the failure mode and effect analysis (FMEA) failure propagation range value. When the first physical distance is less than the first distance threshold, there is a physical distance violation. When the first physical distance is equal to or greater than the first distance threshold, there is no physical distance violation. By checking whether there is a physical distance violation in step S1223 and step S1224 in this embodiment, the isolation of the functional safety module in the chip layout can be checked. If there is a physical distance violation, the chip layout is adjusted in time to ensure that the physical implementation of the redundant design between the shadow core module (SHADOW) and the main core module (MAIN) based on the dual-core lock-step structure meets the physical isolation requirements, avoids common mode failures, and ensures the effectiveness of mutual backup.

[0099] In one embodiment, step S122, the step of checking physical position violations between the functional safety modules in each group of functional safety modules, includes:

[0100] Step S1225, checking the second physical distance between the multiple identical functional units in the multiplexed modules of each group of functional safety modules;

[0101] Step S1226: If the second physical distance is less than or equal to the second distance threshold, a physical distance violation occurs.

[0102] In this embodiment, in step S1225, the multiplex module can be a triplex module or a duplex module. The multiplex module includes a plurality of independent redundant modules. Each unit in each redundant module (e.g., a voter logic gate, an AND logic gate, an OR logic gate, and a buffer logic gate, etc.) corresponds one-to-one with each unit in other redundant modules. The functions of each pair of units are the same. The second physical distance can be represented by the row spacing in the chip layout.

[0103] In step S1226, the second physical distance is compared with the second distance threshold. The second distance threshold can be determined by the maximum value of the minimum spacing value of the process node, the spacing requirement value based on the automotive safety integrity level (ASIL), the thermal effect isolation distance value, the crosstalk limit distance value, and the failure mode and effect analysis (FMEA) failure propagation range value. If the second physical distance is less than the second distance threshold, there is a physical distance violation. If the second physical distance is equal to or greater than the second distance threshold, there is no physical distance violation. By checking whether there is a physical distance violation in steps S1225 and S1226 in this embodiment, the isolation of the functional safety module in the chip layout can be checked. If there is a physical distance violation, the chip layout is adjusted in time to ensure that the physical implementation of the redundant design between the multiple modules meets the physical isolation requirements, avoid common mode failures (such as thermal failure or electrical interference), and ensure the effectiveness of mutual backup.

[0104] In one embodiment, step S122, the step of checking physical position violations between the functional safety modules in each group of functional safety modules, further includes:

[0105] Step S1227, checking a third physical distance between the comparison module and each group of functional safety modules in the chip layout;

[0106] Step S1228: If the third physical distance is less than or equal to the third distance threshold, a physical distance violation occurs.

[0107] In this embodiment, in step S1227, the comparison module is used to execute the comparison logic, and the outputs between each functional safety module in each group of functional safety modules can be compared. In step S1228, the third physical distance is less than the third distance threshold for comparison. The third distance threshold can be determined by the maximum value of the minimum spacing value of the process node, the spacing requirement value based on the automotive safety integrity level (ASIL), the thermal effect isolation distance value, the crosstalk limit distance value, and the failure mode and effect analysis (FMEA) failure propagation range value. If the third physical distance is less than the third distance threshold, there is a physical distance violation. If the third physical distance is equal to or greater than the third distance threshold, there is no physical distance violation. By checking whether there is a physical distance violation in steps S1227 and S1228 in this embodiment, it is possible to check the isolation between the comparison module and each group of functional safety modules in the chip layout. If there is a physical distance violation, the chip layout should be adjusted in time to ensure that the physical implementation of the redundant design between the comparison module and each group of functional safety modules meets the physical isolation requirements, avoid the possibility of physical close-range failures in the same circuit, and prevent each functional safety module in each group of functional safety modules from being physically interfered with at the same time, resulting in system errors.

[0108] In one embodiment, step S120, the step of performing redundant isolation violation checks on multiple functional safety modules in the chip layout, further includes:

[0109] Step S123, determining the number of fan-out ports in each clock domain containing a functional safety module in the chip layout;

[0110] Step S124: If the number of fan-out ports is greater than or equal to the fan-out port threshold, a clock isolation violation occurs.

[0111] In this embodiment, in step S123, the clock domain can be understood as a group of logic modules driven by the same clock source or a clock signal with a fixed phase relationship. In a clock domain, there are functional safety modules and multiple other non-functional safety modules. By analyzing the number of fan-out ports of the clock signal in a clock domain, the number of downstream input ports driven by a clock signal output port can be known. The fan-out port can also be understood as an output port with a fan-out function, which can be connected to and drive multiple other input ports. Furthermore, in each clock domain, all fan-out ports are traversed to determine the number of fan-out ports, and the modules that have a clock signal relationship with the functional safety module can be known.

[0112] In step S124, the fan-out port threshold is the number of fan-out ports required in a clock domain. If the number of fan-out ports is greater than the fan-out port threshold, it indicates that there are redundant fan-out ports in the clock domain, which are abnormal fan-out ports, further indicating that there is an erroneous clock distribution, thereby indicating that there is a clock isolation violation, which will cause timing problems. The fan-out port threshold can be set according to actual design requirements. In one embodiment, the fan-out port threshold can be 10 fan-out ports. By checking whether there is a clock isolation violation in steps S123 and S124 in this embodiment, the clock isolation of multiple functional safety modules in the chip layout can be checked. If there is a clock isolation violation, the chip layout is adjusted in time to ensure the correct isolation of the clock signal and the effectiveness of mutual backup.

[0113] In one embodiment, in each clock domain, all fan-out ports are traversed to determine the number of fan-out ports, and the modules with clock signal relationships with the functional safety module can be learned, and the shadow core module (SHADOW) and the main core module (MAIN) are searched to verify whether there is a clock isolation violation between the shadow core module (SHADOW) and the main core module (MAIN). If there is a clock signal relationship between the fan-out port of the shadow core module (SHADOW) and the fan-out port of the main core module (MAIN), it indicates that there is a clock isolation violation between the shadow core module (SHADOW) and the main core module (MAIN), and it is necessary to adjust the chip layout in time to ensure the clock isolation of the shadow core module (SHADOW) and the main core module (MAIN), and to ensure that there is no random penetration between the clocks of all shadow core modules (SHADOW) belonging to the main core module (MAIN). If the fan-out port of the shadow core module (SHADOW) and the fan-out port of the main core module (MAIN) are isolated and independent from each other, it indicates that there is no clock isolation violation between the shadow core module (SHADOW) and the main core module (MAIN), ensuring the independent timing of the two modules, avoiding problems such as timing errors and performance degradation.

[0114] In one embodiment, step S120, the step of performing redundant isolation violation checks on multiple functional safety modules in the chip layout, further includes:

[0115] Step S125 , checking whether there is a power domain isolation violation in each power domain containing a functional safety module in the chip layout.

[0116] In this embodiment, a power domain can be understood as an area in a chip with an independent power supply, which can meet the different power requirements of different modules, such as operating voltage, power consumption requirements, etc. Checking whether there is a power domain isolation violation can ensure whether each power domain has correctly implemented power shutdown or power isolation measures, so that when a fault occurs in one power domain, it will not affect other power domains, thereby ensuring that the chip can still work normally. By checking whether there is a power domain isolation violation in step S250, the conduction of power noise and the spread of faults can be reduced.

[0117] In one embodiment, in step S125, when checking whether there is a power domain isolation violation, a violation check can be performed based on the physical location of the power domain to determine whether a physical isolation zone is set between the power domains, such as using insulating materials or maintaining a physical distance.

[0118] In one embodiment, before the step S140 of evaluating the adjusted chip layout and obtaining the evaluation result, the functional safety verification optimization method further includes:

[0119] Step S131, performing interface violation check on each functional unit in each functional safety module;

[0120] Step S132, if there is an interface violation, the module position in the chip layout is adjusted according to the interface violation, design rules, functional safety requirements, chip data flow information and timing priority information to obtain an adjusted chip layout.

[0121] In this embodiment, in step S131, the interface unit can be understood as a test access port (Test Access Port) unit, which is a special circuit unit for implementing the design for testability (DFT). Check whether there is a corresponding interface unit for each functional safety module (for example: voter logic gate, AND logic gate, OR logic gate, and buffer logic gate, etc.). In step S132, if there is a corresponding interface unit, there is no interface violation. If there is no corresponding interface unit, there is an interface violation, and the module position in the chip layout needs to be adjusted according to the interface violation, and the interface unit is placed around the functional safety module, and at the same time, the design rules, functional safety requirements, chip data flow information, and timing priority information are met.

[0122] Through step S131 and step S132, it is checked whether there is an interface violation, and the interface unit corresponding to the functional unit in each functional safety module in the chip layout can be checked. If there is an interface violation, the chip layout is adjusted in time, and the corresponding interface unit is added, so that the functional unit can be connected to the external verification device through the interface unit, so that the input, output and internal state of each logic gate can be independently controlled and monitored during the verification stage to prevent the generation of latch-up. When the chip works in a high radiation environment, through step S131 and step S132, if there is an interface violation, the chip layout can be adjusted in time, the corresponding interface unit can be added, the metastable problem can be eliminated, and the chip reliability and stability can be improved.

[0123] Furthermore, through step S131 and step S132, if there is an interface violation, the chip layout can be adjusted in time, and the corresponding interface unit can be added, so that the power supply and ground of the logic gate in the functional safety module can be isolated and controlled to avoid the formation of an abnormal current path between the power supply and the ground, thereby reducing the triggering probability of the latch effect.

[0124] In one embodiment, before the step S140 of evaluating the adjusted chip layout and obtaining the evaluation result, the functional safety verification optimization method further includes:

[0125] Step S133, performing a distribution uniformity violation check on the functional units in the plurality of functional safety modules in the chip layout;

[0126] Step S134, if there is a distribution uniformity violation, the module position in the chip layout is adjusted according to the distribution uniformity violation, design rules, functional safety requirements, chip data flow information and timing priority information to obtain an adjusted chip layout.

[0127] In this embodiment, in step S133, distribution uniformity can be understood as the physical space distribution of each functional unit in the chip layout. In step S134, if the functional units in the multiple modules of the chip layout are evenly distributed, there is no distribution uniformity violation. If the functional units in the multiple modules of the chip layout are unevenly distributed, there is a distribution uniformity violation, and it is necessary to adjust the position of each functional unit in the chip layout according to the distribution uniformity violation to meet the distribution uniformity. In addition, while the functional units in the multiple modules of the chip layout meet the distribution uniformity, they also meet the design rules, functional safety requirements, chip data flow information and timing priority information to obtain the adjusted chip layout.

[0128] By checking whether there is a distribution uniformity violation through step S133 and step S134, it is possible to avoid the situation where the functional units in some areas are too densely crowded while other areas are sparse, so as to improve the physical robustness of the design. When the functional units in multiple modules of the chip layout are evenly distributed, the signal interference problem caused by the over-dense functional units can be avoided, and it is helpful for the chip to dissipate heat evenly, thereby improving the performance and reliability of the chip.

[0129] In one embodiment, in step S133, the distribution of functional units in the chip layout is calculated according to the principal component analysis method (PCA), the positions of the functional units are analyzed, and the principal components of the position information are extracted to ensure the uniformity of the distribution of the functional units.

[0130] See also Figure 2 , the present application provides a functional safety verification optimization method, comprising:

[0131] Step S210, obtaining the chip layout at the engineering change order stage;

[0132] Step S220, performing a redundant isolation violation check and / or a winding interpenetration violation check on a plurality of functional safety modules after the wiring in the chip layout at the engineering change order stage;

[0133] Step S230, if there is a redundant isolation violation and / or a wiring interpenetration violation, adjusting the module position and the wiring in the chip layout according to the redundant isolation violation and / or the wiring interpenetration violation and the first information, to obtain an adjusted chip layout; wherein the first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information;

[0134] Step S240, evaluating the adjusted chip layout to obtain an evaluation result;

[0135] Step S250, determining the target chip layout according to the evaluation result.

[0136] In step S210, the Engineering Change Order (ECO) stage can be understood as the stage after the chip design such as step S110 to step S150 and winding is basically completed, and before the final manufacturing, the design that has been basically completed is finally modified and optimized to ensure that the chip can meet all design requirements and work normally. The engineering change order stage is the stage after the winding is performed on the basis of the target chip layout obtained after step S140 and step S150. The chip layout layout in the engineering change order stage can be understood as the target chip layout layout after winding based on the network connection table (netlist). The network connection table (netlist) can be obtained through logic synthesis tools (such as Synopsys Design Compiler, Cadence Genus, etc.) in the chip front-end design. The network connection table contains the connection information between all module units. The network (net) can be understood as a network composed of metal wires or wires connecting the functional units in each module, which is responsible for transmitting electrical signals between the functional units of different modules to realize data transmission, clock distribution and various logic functions. During the engineering change order stage, small-scale modifications are made to the chip layout layout of the engineering change order stage, targeting the chip layout after routing.

[0137] The description of the redundant isolation violation check in step S220 can refer to the description of the redundant isolation violation check in step S120 in the above embodiment. The redundant isolation violation check includes one or more of the physical location violation check, the hierarchical constraint violation check, the physical distance violation check, and the clock isolation violation check. For the description of the physical location violation check, the hierarchical constraint violation check, the physical distance violation check, and the clock isolation violation check, refer to the description of each embodiment in the above embodiment.

[0138] In step S220, after the layout and winding, there may be situations where multiple functional safety modules are destroyed. For example, the DCLS network may interpenetrate (which can also be understood as winding interpenetration caused by cross-module wiring), affecting functional safety. Therefore, in step S220, redundant isolation violation checks and winding interpenetration violation checks are added to the multiple functional safety modules after winding, and multiple functional safety modules after winding of each network (net) in the chip layout layout of the engineering change instruction stage are traversed to detect whether there are redundant isolation violations and winding interpenetration violation checks. For the redundant isolation violation check, please refer to the relevant description in the above embodiment. The winding interpenetration violation check can identify the windings that cannot be interpenetrated across modules (which can also be understood as interpenetration across regions) by analyzing the winding paths between the functional safety modules in the layout winding. The module positions and windings in the chip layout layout of the engineering change instruction stage are adjusted, and the layout windings are readjusted to avoid destroying the functional safety characteristics of multiple functional safety modules, and obtain the adjusted chip layout layout.

[0139] For the description of adjusting the chip layout layout in the engineering change instruction stage in step S230, reference may be made to the description of step S130 in the above embodiment. For the description of evaluating and determining the adjusted chip layout layout in steps S240 and 250, reference may be made to the description of steps S140 and S150 in the above embodiment. When adjusting the module position and winding in the chip layout layout in the engineering change instruction stage, it is also necessary to meet the requirements of design rules, functional safety requirements, chip data flow information, and timing priority information. Thus, through steps S210 to S250, while optimizing the module position and winding in the chip layout layout in the engineering change instruction stage, the isolation of the redundant design can be ensured, and the problem of winding interpenetration between multiple functional safety modules is solved, ensuring that the functional safety of the redundant design is not destroyed while correcting the timing, and ensuring the correctness and functional safety of the data flow.

[0140] In one embodiment, through steps S210 to S250, the problem of random penetration between the main core module (MAIN) and the shadow core module (SHADOW) in the DCLS architecture is solved. Through step S70, it is checked whether the winding of the main core module (MAIN) is mistakenly penetrated into the area of ​​the shadow core module (SHADOW). If there is a winding mistakenly penetrated between the main core module (MAIN) and the shadow core module (SHADOW), it is considered that there is a winding interpenetration violation. The existence of the winding interpenetration violation will destroy the logical isolation between the main core module (MAIN) and the shadow core module (SHADOW) and introduce potential functional safety issues. Through steps S210 to S250, the winding interpenetration violation can be checked in time, and the module winding in the chip layout layout in the engineering change instruction stage can be adjusted in time according to the winding interpenetration violation, design rules, functional safety requirements, chip data flow information and timing priority information to ensure that all windings are laid out according to the design specifications to avoid interference with the data and signals between the main core module (MAIN) and the shadow core module (SHADOW).

[0141] In one embodiment, a point-to-point check is used to perform redundant isolation violation checks and winding interpenetration violation checks. Point-to-point can be one module to another module, or one functional unit to another functional unit, or one interface to another interface, etc. For example: through a point-to-point check, check whether the winding of the main core module (MAIN) passes through the polygonal area formed by the shadow core module (SHADOW). Through the point-to-point check, it is possible to implement physical distance checks between functional units, physical distance checks between winding lines, and physical distance checks between clock lines to see if there is any intersection.

[0142] In one embodiment, in step S230, the step of adjusting the module position and the routing in the chip layout in the engineering change order stage to obtain the adjusted chip layout includes:

[0143] Step S231 , using an independent component analysis algorithm to adjust the positions and wirings of the functional units in the plurality of functional safety modules to obtain an adjusted chip layout.

[0144] In this embodiment, independent component analysis (ICA) can be used to extract independent components from the distribution of functional units in multiple functional safety modules with redundant isolation violations or / and interpenetrating wiring violations, identify the causes of the violations, and adjust the positions and wiring to reduce the mutual interference between functional units in multiple functional safety modules, thereby avoiding violations. When the independent component analysis algorithm is used to adjust the positions and wiring of functional units in multiple functional safety modules, it is necessary to meet the redundant isolation violations or / and interpenetrating wiring violations, design rules, functional safety requirements, chip data flow information, and timing priority information to obtain the adjusted chip layout.

[0145] In one embodiment, in step S230, the step of adjusting the module position and the routing in the chip layout in the engineering change order stage to obtain the adjusted chip layout includes:

[0146] Step S232: using a genetic algorithm or a simulated annealing algorithm, adjusting the positions and wirings of the functional units in the plurality of functional safety modules to obtain an adjusted chip layout.

[0147] In this embodiment, the simulated annealing algorithm randomly exchanges the positions of functional units in multiple functional safety modules and gradually reduces the temperature to explore different layout possibilities, thereby adjusting the placement and winding of functional units in multiple functional safety modules to obtain an adjusted chip layout. Furthermore, through steps S240 and S250, the adjusted chip layout is iteratively evaluated to obtain an evaluation result, and based on the evaluation result, the optimal solution is selected to determine whether it is the target chip layout, thereby finding the optimal solution. When using a genetic algorithm or a simulated annealing algorithm to adjust the positions and windings of functional units in multiple functional safety modules, it is necessary to meet redundant isolation violations and / or winding interpenetration violations, design rules, functional safety requirements, chip data flow information, and timing priority information to obtain an adjusted chip layout.

[0148] In one embodiment, before step S120 and before step S220, the functional safety verification optimization method further includes analyzing multiple functional safety modules in the chip layout according to failure mode and effect analysis, determining the failure mode and cause of each functional safety module, and implementing risk assessment and measure formulation, so that subsequent steps S120, step S130, step S220 and step S230 are more targeted and purposeful when optimizing the chip back-end verification, so as to obtain a more accurate chip layout.

[0149] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0150] See also Figure 3 , the present application provides a functional safety verification optimization system 100. The functional safety verification optimization system 100 includes a layout acquisition module 110, a redundant isolation violation check module 120, a layout adjustment module 130, an evaluation module 140 and a determination module 150. The layout acquisition module 110 is used to place multiple modules in an initial layout structure according to design rules, functional safety requirements, chip data flow information and timing priority information to obtain a chip layout; wherein the multiple modules include multiple functional safety modules. The redundant isolation violation check module 120 is used to perform redundant isolation violation checks on multiple functional safety modules in the chip layout.

[0151] The layout adjustment module 130 is used to adjust the module position in the chip layout according to the redundant isolation violation and the first information if there is a redundant isolation violation, and obtain the adjusted chip layout. The first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information. The evaluation module 140 is used to evaluate the adjusted chip layout and obtain an evaluation result. The determination module 150 is used to determine the target chip layout according to the evaluation result.

[0152] In this embodiment, the relevant description of the layout acquisition module 110 can refer to the relevant description of step S110 in the above embodiment. The relevant description of the redundant isolation violation checking module 120 can refer to the relevant description of step S120 in the above embodiment. The relevant description of the layout adjustment module 130 can refer to the relevant description of step S130 in the above embodiment. The relevant description of the evaluation module 140 can refer to the relevant description of step S140 in the above embodiment. The relevant description of the determination module 150 can refer to the relevant description of step S150 in the above embodiment.

[0153] See also Figure 4 The present application provides a functional safety verification optimization system 100, including a change phase layout acquisition module 210, a change phase violation check module 220, a change phase adjustment module 230, a change phase evaluation module 240, and a change phase determination module 250. The change phase layout acquisition module 210 is used to acquire the chip layout layout of the engineering change instruction stage. The change phase violation check module 220 is used to perform redundant isolation violation checks and / or wiring interpenetration violation checks on multiple functional safety modules after wiring in the chip layout of the engineering change instruction stage.

[0154] The change phase adjustment module 230 is used to adjust the module position and the routing in the chip layout according to the redundant isolation violation and / or the routing interpenetration violation and the first information if there are redundant isolation violations and / or routing interpenetration violations, so as to obtain the adjusted chip layout. The first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information. The change phase evaluation module 240 is used to evaluate the adjusted chip layout and obtain an evaluation result. The change phase determination module 250 is used to determine the target chip layout according to the evaluation result.

[0155] In this embodiment, the description of the change phase layout acquisition module 210 can refer to the description of step S210 in the above embodiment. The description of the change phase violation check module 220 can refer to the description of step S220 in the above embodiment. The description of the change phase adjustment module 230 can refer to the description of step S230 in the above embodiment. The description of the change phase assessment module 240 can refer to the description of step S240 in the above embodiment. The description of the change phase determination module 250 can refer to the description of step S250 in the above embodiment.

[0156] The present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the method in any of the above embodiments are implemented. The present application provides a computer program product, including a computer program. When the computer program is executed by a computer, the steps of the method in any of the above embodiments are implemented.

[0157] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0158] In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments. Those of ordinary skill in the art can appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0159] In the embodiments provided in the present application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0160] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware or in the form of software functional units.

[0161] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0162] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A functional safety verification optimization method, characterized in that: include: Placing multiple modules in an initial layout structure according to design rules, functional safety requirements, chip data flow information, and timing priority information to obtain a chip layout; wherein the multiple modules include multiple functional safety modules; Performing a redundant isolation violation check on the plurality of functional safety modules in the chip layout; If there is a redundant isolation violation, adjusting the module position in the chip layout according to the redundant isolation violation and the first information to obtain an adjusted chip layout; the first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information; Evaluating the adjusted chip layout to obtain an evaluation result; According to the evaluation results, the target chip layout is determined.

2. The functional safety verification optimization method according to claim 1, characterized in that: The performing redundant isolation violation check on the plurality of functional safety modules in the chip layout comprises: Determine, according to the design rules and the functional safety requirements, the checkpoints of each group of functional safety modules in the multiple functional safety modules; wherein each group of functional safety modules includes at least two functional safety modules that are independent of each other and have the same functions; According to the check point, physical position violations between the functional safety modules in each group of functional safety modules are checked.

3. The functional safety verification optimization method according to claim 2, characterized in that: The checking for physical position violations between the functional safety modules in each group of functional safety modules comprises: Checking the hierarchical constraint information between the functional safety modules in each group of functional safety modules; If the hierarchical constraint information does not exist between any two of the functional safety modules, it is determined that a hierarchical constraint violation exists between any two of the functional safety modules.

4. The functional safety verification optimization method according to claim 2, characterized in that: The checking for physical position violations between the functional safety modules in each group of functional safety modules comprises: Checking a first physical distance between two identical functional units in a main core module and a shadow core module of each group of functional safety modules; If the first physical distance is less than or equal to a first distance threshold, a physical distance violation occurs.

5. The functional safety verification optimization method according to claim 2, characterized in that: The checking for physical position violations between the functional safety modules in each group of functional safety modules comprises: Checking a second physical distance between a plurality of identical functional units in the multiplexed modules of each group of functional safety modules; If the second physical distance is less than or equal to a second distance threshold, a physical distance violation occurs.

6. The functional safety verification optimization method according to claim 1, characterized in that: The performing redundant isolation violation check on the plurality of functional safety modules in the chip layout comprises: Determining the number of fan-out ports in each clock domain containing the functional safety module in the chip layout; If the number of fan-out ports is greater than or equal to the fan-out port threshold, a clock isolation violation exists.

7. The functional safety verification optimization method according to any one of claims 1 to 6, characterized in that: Before evaluating the adjusted chip layout and obtaining the evaluation result, the method further includes: Performing interface violation checks on the functional units in each of the functional safety modules; If there is an interface violation, the module position in the chip layout is adjusted according to the interface violation and the first information to obtain an adjusted chip layout.

8. The functional safety verification optimization method according to any one of claims 1 to 6, characterized in that: Before evaluating the adjusted chip layout and obtaining the evaluation result, the method further includes: Performing a distribution uniformity violation check on the functional units in the plurality of functional safety modules in the chip layout; If there is a distribution uniformity violation, the module position in the chip layout is adjusted according to the distribution uniformity violation and the first information to obtain an adjusted chip layout.

9. A functional safety verification optimization method, characterized in that: include: Obtain chip layout at the engineering change order stage; Performing redundant isolation violation checks and / or interpenetration violation checks on multiple functional safety modules after wiring in the chip layout at the engineering change order stage; If there is a redundant isolation violation and / or a wiring interpenetration violation, adjusting the module position and the wiring in the chip layout according to the redundant isolation violation and / or the wiring interpenetration violation and the first information to obtain an adjusted chip layout; wherein the first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information; Evaluating the adjusted chip layout to obtain an evaluation result; According to the evaluation results, the target chip layout is determined.

10. The functional safety verification optimization method according to claim 9, characterized in that: The redundant isolation violation check and the winding interpenetration violation check are performed on the multiple functional safety modules after the wiring in the chip layout in the engineering change order stage, including: Performing the redundant isolation violation check on the plurality of functional safety modules after the wiring in the chip layout at the engineering change instruction stage; wherein the redundant isolation violation check includes one or more of a physical location violation check, a hierarchical constraint violation check, a physical distance violation check, and a clock isolation violation check; The step of adjusting the module position and the wiring in the chip layout according to the redundant isolation violation and / or the wiring interpenetration violation and the first information to obtain the adjusted chip layout includes: An independent component analysis algorithm, a genetic algorithm, or a simulated annealing algorithm is used to adjust the positions and wirings of the functional units in the multiple functional safety modules to obtain the adjusted chip layout.

11. A functional safety verification optimization system, characterized in that: include: A layout acquisition module, used to place multiple modules in an initial layout structure according to design rules, functional safety requirements, chip data flow information, and timing priority information to obtain a chip layout; wherein the multiple modules include multiple functional safety modules; A redundant isolation violation checking module, used for performing redundant isolation violation checking on the plurality of functional safety modules in the chip layout; A layout adjustment module, configured to adjust the module position in the chip layout according to the redundant isolation violation and first information to obtain an adjusted chip layout if there is a redundant isolation violation; the first information includes one or more of the following: design rules, functional safety requirements, chip data flow information, and timing priority information; An evaluation module, used to evaluate the adjusted chip layout to obtain an evaluation result; The determination module is used to determine the target chip layout according to the evaluation result.

12. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a computer, the steps of the method according to any one of claims 1 to 10 are implemented.

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