Source driving integrated circuit and display device including same

Abstract

The invention relates to a source driving integrated circuit and a display device including the same. A source driving integrated circuit (IC) includes: one or more digital circuit sections configured to receive a digital signal; a plurality of signal leads connected to the digital circuit section and configured to transmit a digital signal to the digital circuit section; and a clock lead connected to the digital circuit section and configured to transmit a clock to the digital circuit section. Each of the signal lead and the clock lead includes: an input lead located at a center in a length direction of the digital circuit portion; and a branch lead branching toward both sides of the input lead in the longitudinal direction of the digital circuit unit.

Description

Technical Field

[0001] The present disclosure relates to a source driver integrated circuit (IC) and a display device including the same. Background Art

[0002] Various flat panel displays are known, including electroluminescent displays (ELDs) such as liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays, field emission displays (FEDs), plasma display panels (PDPs), and electrophoretic displays (EPDs).

[0003] The display device includes: a display panel in which pixels displaying an input image are arranged; and a display panel driving circuit that writes data to the pixels in the display panel. The display panel driving circuit includes a data driver that supplies data signals to data lines on the display panel. The data driver is integrated into a source driver integrated circuit (IC) and electrically connected to the data lines on the display panel. The leads, digital circuit parts, analog circuit parts, etc. that transmit data signals are integrated in the source driver IC with high density.

[0004] Due to the thin and long leads transmitting the digital signals in the source driver IC, a voltage drop of the digital signals may occur. When the voltage of the digital signals input to the source driver IC undergoes a transition, the voltage drop may become larger. Summary of the invention

[0005] The present disclosure provides a source driver IC capable of reducing a voltage drop of a digital signal and a display device including the same.

[0006] A source driver integrated circuit (IC) according to one or more example embodiments of the present disclosure includes: one or more digital circuit units, which are configured to receive digital signals; a plurality of signal leads, which are connected to the digital circuit units and configured to transmit digital signals to the digital circuit units; and a clock lead, which is connected to the digital circuit units and configured to transmit a clock to the digital circuit units.

[0007] Each of the signal lead and the clock lead includes: an input lead located at the center in the length direction of the digital circuit portion; and branch leads branched to both sides of the input lead along the length direction of the digital circuit portion.

[0008] The source driver IC may further include a plurality of buffers connected in series to each of the signal lead and the clock lead at equal intervals.

[0009] The buffers may be arranged on the branch leads in bilateral symmetry based on the input leads.

[0010] The source driver IC may further include: a plurality of flip-flops connected to the respective signal leads; and a delay circuit connected to a clock terminal of at least one flip-flop.

[0011] The source driver IC may further include a buffer connected between the flip-flops.

[0012] The source driver IC may further include: a first trigger connected to the first signal lead; a first delay circuit connected to a clock terminal of the first trigger; a second trigger connected to the second signal lead; and a second delay circuit connected to the clock terminal of the second trigger. The delay value of the first delay circuit may be different from the delay value of the second delay circuit.

[0013] A display device according to one or more example embodiments of the present disclosure includes a source driver IC.

[0014] According to the present disclosure, by arranging buffers at equal intervals on leads transmitting digital signals and clocks in a source driver IC chip, a voltage drop of a digital signal can be reduced.

[0015] According to the present disclosure, by connecting an input lead for inputting a digital signal and a clock to the center of a digital circuit section in a source driver IC chip, a voltage drop of a digital signal can be reduced.

[0016] According to the present disclosure, by dispersing the transition or switching timing of digital signals input to the respective digital circuit sections in the source driver IC on the time axis, the voltage drop of the digital signal can be further reduced.

[0017] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0019] Figure 1 is a block diagram showing a display device according to one embodiment of the present disclosure;

[0020] Figure 2 is a plan view schematically showing a source driver IC chip;

[0021] Figure 3 It is shown Figure 2 A block diagram of an example of a source block is shown;

[0022] Figure 4A and Figure 4Bis a diagram showing an input port of a source driver IC chip according to an embodiment of the present disclosure;

[0023] Figure 5 is a diagram schematically showing an example of a buffer clustered on a digital signal transmission path of a source driver IC chip;

[0024] Fig. 6A and Figure 6B is a diagram showing an input port of a source driver IC chip according to another embodiment of the present disclosure;

[0025] Fig. 7A is shown connected to Fig. 6A and Figure 6B A diagram of a buffer for a signal lead on a first digital circuit portion shown;

[0026] Figure 7B is shown connected to Fig. 6A and Figure 6B A diagram of a buffer for a signal lead on a second digital circuit portion shown;

[0027] Figure 8 is a diagram showing digital signals and clocks input to a digital circuit portion through leads to which a buffer is connected;

[0028] Fig. 9 is a waveform diagram showing an example of a digital signal and a clock input to a digital circuit portion;

[0029] Fig.10 and Fig.11 is a diagram showing an equidistant arrangement of buffers in a source driver IC chip;

[0030] Fig.12 and Fig.13 is a circuit diagram showing one example of a method of delaying a signal input to a digital circuit portion; and

[0031] Fig.14 and Fig.15 is a waveform diagram showing an example in which some signals input to a digital circuit unit are delayed. DETAILED DESCRIPTION

[0032] The advantages and features of the present disclosure and methods for implementing the same will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various forms. On the contrary, the present embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0033] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0034] Terms such as “include,” “comprising,” and “having” used herein are generally intended to allow the addition of other components unless these terms are used with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0035] Even if not explicitly stated, components are interpreted as including ordinary margins of error.

[0036] The terms “first”, “second”, etc. may be used to distinguish elements from each other, but the function or structure of a component is not limited by an ordinal number preceding the component or the component name.

[0037] The following embodiments may be partially or completely joined or combined with each other, and may be technically linked and operated in various ways. These embodiments may be implemented independently of each other or in association with each other.

[0038] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 is a block diagram showing a display device according to one embodiment of the present disclosure.

[0040] Reference Figure 1 , a display device according to an embodiment of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels in the display panel 100 .

[0041] The substrate of the display panel 100 may be (but not limited to) a plastic substrate, a thin glass substrate or a metal substrate. The display panel 100 may be (but not limited to) a panel having a rectangular structure having a length in a first direction, a width in a second direction and a thickness in a third direction. Figure 1 X, Y, and Z in the diagram may be a first direction, a second direction, and a third direction, respectively. At least a portion of the display panel 100 may have a curved periphery.

[0042] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual object in the background is visible. The display panel 100 may be made into a flexible display panel.

[0043] In the case of a liquid crystal display device, a backlight unit (BLU) may be disposed under the display panel 100. In the case of a self-emissive display device such as an electroluminescent display device, a separate light source such as a backlight unit is not required.

[0044] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102 , a plurality of gate lines 103 crossing the data lines 102 , and pixels 101 connected to the data lines 102 and the gate lines 103 .

[0045] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel and a blue sub-pixel for color realization. Each pixel may also include a white sub-pixel. In a liquid crystal display device, a pixel includes a liquid crystal cell. In an electroluminescent display, each pixel includes a light-emitting element such as an OLED, an inorganic LED, etc. and a pixel circuit that drives the light-emitting element. Each pixel circuit is connected to a data line, a gate line and a power line. In the following, a "pixel" may be interpreted as a "sub-pixel".

[0046] The display panel driving circuit writes pixel data of an input image to pixels in the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0047] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. In a mobile device or a wearable device, the timing controller 130, the data driver 110, the touch sensor driver, etc. may be integrated into one driving IC.

[0048] The data driver 110 receives pixel data of an input image provided as a digital signal from the timing controller 130 and outputs a data voltage of the pixel data. The data driver 110 converts the pixel data of the input image into a gamma compensation voltage using a digital-to-analog converter (DAC) to output the data voltage. The gamma reference voltage is divided into gamma compensation voltages of respective grayscales by a voltage divider circuit in the data driver 110 and supplied to the DAC. The DAC generates the data voltage as a gamma compensation voltage corresponding to the grayscale value of the pixel data. The data voltage output from the DAC is output to the data line 102 through an output buffer in each data output channel of the data driver 110. Figure 2 As shown, the data driver 110 may be integrated into a driving integrated circuit (IC) chip.

[0049] The gate driver 120 circuit may be disposed in the non-display area NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed in the display area AA. The gate driver 120 may be integrated into a separate gate drive IC and electrically connected to the gate line 103 on the display panel 100.

[0050] The gate driver 120 sequentially outputs pulses of a gate signal to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply pulses of the gate signal to the gate lines 103 by shifting the pulses of the gate signal using a shift register.

[0051] The timing controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from an external host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a master clock. The vertical period and the horizontal period can be known by counting the data enable signal DE, so the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The vertical synchronization signal Vsync has a cycle of one frame period. The horizontal synchronization signal Hsync and the data enable signal DE have a cycle of one horizontal period (1H).

[0052] The timing controller 130 controls operation timings of the display panel driving circuits 110 and 120 based on timing signals such as Vsync, Hsync, and DE received from the host system 200 .

[0053] The host system 200 may scale the image signal from the video source to match the resolution of the display panel 100, and may send it to the timing controller 130 together with the timing control signal. In a mobile system, the host system 200 may be implemented by an application processor (AP). The host system 200 may send pixel data of the input image to the driver IC via a mobile industrial processor interface (MIPI). The host system 200 may be electrically connected to the driver IC via a flexible printed circuit (e.g., a flexible printed circuit (FPC)). The driver IC may be bonded to the display panel 100 in a COG (chip on glass) process. The driver IC may be a chip on film (COF) mounted on a flexible circuit film. The COF may be bonded to a data pad disposed on a non-display area of ​​the display panel 100 in a bonding process and electrically connected to a data line on the display panel 100.

[0054] Figure 2 is a plan view schematically showing a source driver IC chip.

[0055] Reference Figure 2 The source driver IC chip SIC has a length (L) in a first direction, a width (W) in a second direction, and a thickness in a third direction.

[0056] The input port may be provided at least one of four sides of the source drive IC chip SIC. The digital signal and the clock transmitted from the timing controller 130 may be received by the source drive IC chip SIC through the input port.

[0057] The source driver IC chip SIC may include a first source block SBL and a second source block SBR. Each of the source blocks SBL and SBR receives a digital signal and a clock, converts them into an analog voltage, and outputs the analog voltage. When viewed from the center C of the length of the source driver IC chip SIC in the first direction, the first source block SBL may be disposed on one side (or the left side) of the source driver IC chip SIC. When viewed from the center C of the length of the source driver IC chip SIC in the first direction, the second source block SBR may be disposed on the other side (or the right side) of the source driver IC chip SIC. The first source block SBL and the second source block SBR may be spaced a predetermined distance from each other.

[0058] Each of the first source block SBL and the second source block SBR includes a digital circuit portion DCB that receives and latches a digital signal and Figure 3 The analog circuit part ACB converts the digital signal received from the digital circuit part DCB into an analog voltage to output a data voltage. The source driver IC chip SIC may further include a memory disposed near the first source block SBL and the second source block SBR. The memory may be, but is not limited to, a frame memory that stores data in an amount of one frame.

[0059] Figure 3 It is shown Figure 2 A block diagram of an example of a source block is shown.

[0060] Reference Figure 3 , the digital circuit part DCB of each of the source blocks SBL and SBR may include a first latch LAT1 and a second latch LAT2.

[0061] The first latch LAT1 samples and sequentially latches the digital signal received in series from the timing controller 130 at a clock timing synchronized with the digital signal and transmits it to the second latch LAT2. The second latch LAT2 simultaneously outputs the digital signal received from the first latch LAT1 in response to the output enable clock. The first latch LAT1 and the second latch LAT2 convert the pixel data received in series into pixel data of a parallel scheme by sequentially latching the digital signal. Each of the source blocks SBL and SBR may also include a shift register connected to the input terminal of the first latch LAT1.

[0062] The analog circuit part ACB of each of the source blocks SBL and SBR includes a DAC and an output buffer OBUF connected to the output terminal of the second latch LAT2. The DAC converts the pixel data received from the second latch LAT2 into a gamma compensation voltage and outputs a data voltage of the pixel data. The data voltage output from the DAC can be output through the output buffer OBUF in each channel of the source driver IC chip SIC and fed to the data line 102 on the display panel 100.

[0063] Figure 4A and Figure 4B is a diagram showing an input port of a source driver IC chip according to one embodiment of the present disclosure.

[0064] Reference Figure 4A , the source driver IC chip SIC may include a first input port IPL and a second input port IPR arranged on both surfaces in the second direction Y. The signal lead 91 and the clock lead 92 may be connected to the first digital circuit portion DCB1 and the second digital circuit portion DCB2 through the input ports IPL and IPR of the source driver chip SIC. The digital signal is transmitted through the signal lead 91, and the clock is transmitted through the clock lead 92. In order to synchronize the first digital circuit portion DCB1 and the second digital circuit portion DCB2 with each other, the clock lead 92 may be connected to the digital circuit portions DCB1 and DCB2 through a common lead, but is not limited thereto.

[0065] In the first source block SBL, the first digital circuit portion DCB1 starts to sequentially receive the first digital signal DATA_L and the clock from the left end unit in the first digital circuit portion DCB1 through the first input port IPL located on the left side of the source driver IC chip SIC, so as to receive the first digital signal DATA_L and the clock to the right end unit in the first digital circuit portion DCB1. In the second source block SBR, the second digital circuit portion DCB2 starts to sequentially receive the second digital signal DATA_R and the clock from the right end unit in the second digital circuit portion DCB2 through the second input port IPR located on the right side of the source driver IC chip SIC, so as to receive the second digital signal DATA_R and the clock to the left end unit in the second digital circuit portion DCB2.

[0066] The input port of the source driver IC chip SIC is not limited to Figure 4A As an example, Figure 4B As shown, the input port of the source driver IC chip SIC may be arranged on at least one side of the source driver IC chip SIC in the first direction X.

[0067] Reference Figure 4B, the source driver IC chip SIC may include an input port IPC located at the center of the length in the first direction X. The signal lead 91 and the clock lead 92 may be connected to the first digital circuit part DCB1 and the second digital circuit part DCB2 through the input port IPC of the source driver chip SIC.

[0068] In the first source block SBL, the first digital circuit portion DCB1 starts to sequentially receive the first digital signal DATA_L and the clock from the right end unit in the first digital circuit portion DCB1 through the input port IPC to receive the first digital signal DATA_L and the clock to the left end unit of the first digital circuit portion DCB1. In the second source block SBR, the second digital circuit portion DCB2 starts to sequentially receive the second digital signal DATA_R and the clock from the left end unit in the second digital circuit portion DCB2 through the input port IPC to receive the second digital signal DATA_R and the clock to the right end unit of the digital circuit portion DCB2.

[0069] Due to the structure of the source driver IC chip SIC, the digital circuit portion DCB may have a very long length L in the first direction X relative to the width W in the second direction Y. This results in an increase in the resistance of the leads transmitting digital signals in the source driver IC chip SIC, and an increase in the voltage drop of the digital signal input to the digital circuit portion DCB as the leads are further away from the input port of the source driver IC chip SIC. Figure 4A and Figure 4B As shown, in a structure where the transmission path of digital signals in the source driver IC chip SIC is extended, the resistance of the wires transmitting the digital signals may increase. The voltage drop of the digital signal to be input to the digital circuit part DCB may cause a sampling error of the pixel data in the digital circuit part DCB.

[0070] In the source driver IC chip SIC, digital signals may be received through a plurality of signal leads and transmitted to the digital circuit portion DCB. In this case, if the digital signals transmitted to the signal leads within the source driver IC chip SIC undergo simultaneous transitions, for example, if the logic values ​​of the digital signals are simultaneously inverted from "L" (or "0") to "H" (or "1") or from "H" (or "1") to "L" (or "0"), the amount of current in the signal leads may increase, resulting in a large voltage drop of the digital signal.

[0071] In order to reduce the transmission loss of digital signals within the source driver IC, a buffer may be placed on the leads transmitting the digital signals. Each buffer may be implemented as any known digital signal buffer. Even if multiple buffers are connected to the corresponding leads transmitting digital signals, when the digital signals applied to the leads undergo simultaneous transitions, the amount of current flowing through the leads increases, which increases the voltage drop of the digital signals. In buffers such as Figure 5In the case of the cluster arrangement shown in the figure, when a transition of a digital signal occurs, a large voltage drop occurs each time the digital signal passes through a plurality of cluster buffers BFS. This voltage drop increases as the lead moves away from the input port of the source driver IC chip SIC, thereby causing the maximum voltage drop at the end unit of the digital circuit part DCB that is further away from the input port.

[0072] In order to reduce the voltage drop of the digital signal in the source driver IC chip SIC, such as Fig. 6A and Figure 6B As shown, a digital signal may be input to the center of each of the source blocks SBL and SBR.

[0073] Fig. 6A and Figure 6B is a diagram showing an input port of a source driver IC chip according to another embodiment of the present disclosure.

[0074] Reference Fig. 6A The source driver IC chip SIC may include a first input port IPL and a second input port IPR disposed on both sides thereof. The signal lead 91 and the clock lead 92 may be connected to the center of the length direction (or the first direction) of the first digital circuit portion DCB1 and the second digital circuit portion DCB2 through the input ports IPL and IPR of the source driver chip SIC.

[0075] The first digital signal DATA_L and the clock are input to the center cell in the first digital circuit part DCB1 located at the center of the first source block SBL in the length direction through the first input port IPL, so that the first digital signal DATA_L and the clock are sequentially transferred to the left end cell in the first digital circuit part DCB1 while being sequentially transferred to the right end cell in the first digital circuit part DCB1. The second digital signal DATA_R and the clock are input to the center cell in the second digital circuit part DCB2 located at the center of the second source block SBR in the length direction through the second input port IPR, so that the second digital signal DATA_R and the clock are sequentially transferred to the left end cell in the second digital circuit part DCB2 while being sequentially transferred to the right end cell in the second digital circuit part DCB2. Therefore, the transmission path of the digital signals DATA_L and DATA_R and the clock received by the digital circuit parts DCB1 and DCB2 in each of the first source block SBL and the second source block SBR can be shortened to reduce the lead resistance by that amount, and the driving strength of the buffer can be reduced, resulting in a reduction in the voltage drop of the digital signals transmitted to the digital circuit parts DCB1 and DCB2.

[0076] Reference Figure 6B, the source driver IC chip SIC may include an input port IPC located at the center of the length in the first direction X. The signal lead 91 and the clock lead 92 may be connected to the center of the length direction (or the first direction) of each of the first digital circuit part DCB1 and the second digital circuit part DCB2 through the input port IPC of the source driver chip SIC.

[0077] The first digital signal DATA_L and the clock are input to the center cell in the first digital circuit part DCB1 located at the center of the first source block SBL in the length direction through the input port IPC, so that the first digital signal DATA_L and the clock are sequentially transferred to the left end cell in the first digital circuit part DCB1 while being sequentially transferred to the right end cell in the first digital circuit part DCB1. The second digital signal DATA_R and the clock are input to the center cell in the second digital circuit part DCB2 located at the center of the second source block SBR in the length direction through the input port IPC, so that the second digital signal DATA_R and the clock are sequentially transferred to the left end cell in the second digital circuit part DCB2 while being sequentially transferred to the right end cell in the second digital circuit part DCB2. Therefore, the transmission path of the digital signals DATA_L and DATA_R and the clock received by the digital circuit parts DCB1 and DCB2 in each of the first source block SBL and the second source block SBR can be shortened to reduce the lead resistance by the amount, and the driving strength of the buffer can be reduced, resulting in a reduction in the voltage drop of the digital signal transmitted to the digital circuit part.

[0078] Fig. 7A is shown connected to Fig. 6A and Figure 6B A diagram of a buffer of the signal pins of the first digital circuit part DCB1 is shown. Figure 7B is shown connected to Fig. 6A and Figure 6B FIG. 1 is a diagram of a buffer of a signal lead of the second digital circuit portion DCB2. Fig. 7A and Figure 7B In , "D" represents a unit that receives a bit of a digital signal in the first digital circuit portion DCB1 and the second digital circuit portion DCB2. Fig. 7A and Figure 7B The clock leads are omitted.

[0079] The signal leads and the clock leads of the source drive IC chip SIC each include branch leads branched from the center in the length direction of the source blocks SBL and SBR to opposite sides.

[0080] Reference Fig. 7A, the first digital circuit portion DCB1 includes a plurality of cells 1011, 1012, 1021, and 1022 that receive a digital signal DATA_L and a clock through leads L11 to L2n and buffers BUF1 and BUF2. The cells 1011, 1012, 1021, and 1022 include center cells 1011 and 1021, a left end cell 1012, and a right end cell 1022 located at the center of the first digital circuit portion DCB1.

[0081] The leads L11 to L2n include a first left lead L11 branched to the left along the first direction X from the first input lead LI11, ..., an (n)th left lead L1n branched to the left along the first direction X from the (n)th input lead LI1n (where n is a natural number greater than or equal to 2), a first right lead L21 branched to the right along the first direction X from the first input lead LI11, ..., and a second right lead L2n branched to the right along the first direction X from the (n)th input lead LI1n. The first buffer BUF1 may be arranged to be spaced apart from each other at equal intervals on the left side of the input leads LI11 to LI1n to be connected in series to the left leads L11 to L1n. The input terminal and the output terminal of the first buffer BUF1 are connected to the left leads L11 to L1n so that the digital signal can be transmitted from right to left. The second buffer BUF2 may be arranged to be spaced apart from each other at equal intervals on the right side of the input leads LI11 to LI1n to be connected in series to the right leads L21 to L2n. The input terminal and the output terminal of the second buffer BUF2 are connected to the right leads L21 to L2n so that the digital signal can be transmitted from left to right. The first buffer BUF1 and the second buffer BUF2 may be arranged in a bilaterally symmetrical structure with the input leads LI11 and LI1n interposed therebetween.

[0082] The digital signal DATA_L and the clock CLK may be received into the plurality of cells 1011 to 1012 through left leads L11 to L1n between adjacent first buffers BUF1 in the first direction X. The digital signal DATA_L and the clock CLK may be received into the plurality of cells 1021 to 1022 through right leads L21 to L2n between adjacent second buffers BUF2 in the first direction X. The leads L11 to L2n may be connected to different cells in the first digital circuit portion DCB1.

[0083] Reference Figure 7BThe second digital circuit portion DCB2 includes a plurality of cells 1031, 1032, 1041, and 1042, and the digital signal DATA_R and the clock are received into the plurality of cells 1031, 1032, 1041, and 1042 through the leads L31 to L4n and the buffers BUF3 and BUF4. The cells 1031, 1032, 1041, and 1042 include center cells 1031 and 1041, a left end cell 1032, and a right end cell 1042 located at the center of the second digital circuit portion DCB2.

[0084] Leads L31 to L4n include a first left lead L31 branched to the left along a first direction X from a first input lead LI21, ..., a (n) left lead L3n branched to the left along a first direction X from an (n) input lead LI2n, a first right lead L41 branched to the right along a first direction X from a first input lead LI21, ..., and a (n) right lead L4n branched to the right along a first direction X from an (n) input lead LI2n. The third buffer BUF3 may be arranged to be spaced apart from each other at equal intervals on the left side of the input leads LI31 to LI3n to be connected in series to the left leads L31 to L3n. The input terminals and output terminals of the third buffer BUF3 are connected to the left leads L31 to L3n so that digital signals can be transmitted from right to left. The fourth buffer BUF4 may be arranged to be spaced apart from each other at equal intervals on the right side of the input leads LI21 to LI2n to be connected in series to the right leads L41 to L4n. The input terminal and output terminal of the fourth buffer BUF4 are connected to the right leads L41 to L4n so that the digital signal can be transmitted from left to right. The third buffer BUF3 and the fourth buffer BUF4 may be arranged in a bilaterally symmetrical structure with the input leads LI21 to LI2n interposed therebetween.

[0085] The digital signal DATA_R and the clock CLK may be received into the plurality of cells 1031 to 1032 through left leads L31 to L3n between adjacent third buffers BUF3 in the first direction X. The digital signal DATA_R and the clock CLK may be received into the plurality of cells 1041 to 1042 through right leads L41 to 42n between adjacent fourth buffers BUF4 in the first direction X. The leads L31 to L4n may be connected to different cells in the second digital circuit portion DCB2.

[0086] Reference Figure 8 and Fig. 9 , the source driver IC chip SIC includes leads 91 and 92 that are provided in the digital circuit portion DCB and connected to the cells D in the digital circuit portion DCB.

[0087] The leads 91 and 92 include a plurality of signal leads 91 transmitting digital signals DATA[0] to DATA[n-1] and a clock lead 92 transmitting a clock CLK. In order to reduce a voltage drop caused by the cluster of buffers BUF, buffers BUF may be connected to each of the leads 91 and 92 at equal intervals L01.

[0088] When the clock is at a specific logic value, each unit D in the digital circuit portion DCB can sample and latch the digital signals DATA[0] to DATA[n-1]. For example, the unit D can sample and latch the bits of the digital signals DATA[0] to DATA[n-1] input through the signal lead 91 at the rising edge of the clock CLK. After the clock has risen to a high logic value (H), the unit D can sample the digital signals DATA[0] to DATA[n-1] during the time period in which the clock CLK maintains the high logic value (H).

[0089] Fig.10 and Fig.11 is a diagram showing an equidistant arrangement of buffers in a source driver IC chip.

[0090] Reference Fig.10 , digital signals DATA[0] to DATA[n-1] are input to the digital circuit portion DCB of the source driver IC chip through signal leads 911 to 91n-1. The clock CLK is provided to the digital circuit portion DCB of the source driver IC chip through a clock lead 92. The buffer BUF is connected to the leads 911 to 91n-1 and 92 so that they are spaced apart at equal intervals L01.

[0091] Reference Fig.11 , the separation distance between the buffers BUF connected in series to each of the adjacent leads 911 to 914 and 92 is equal to the interval I1. In the source driver IC chip SIC, the buffers BUF may be arranged to satisfy the condition L01>l1. In other words, in each lead (911 to 914, 92), the distance (l1) between the buffers (BUF) connected to the adjacent leads (911 to 914, 92) is smaller than the distance (L01) between the buffers (BUF) connected in series to one lead.

[0092] In the source driver IC chip SIC, the buffer BUF connected to the leads 911 to 914 and 92 can be as shown in FIG. Fig.11 As shown, the buffer unit block BUG is arranged in a repeated form.

[0093] When the digital signals DATA[0] to DATA[n-1] applied to the leads 911 to 914 and 92 connected to the digital circuit portion DCB undergo simultaneous transitions, the voltage drop increases. If the transition or switching timing of the digital signals DATA[0] to DATA[n-1] is spread out on the time axis, the amount of voltage drop can be reduced because the fewer the number of buffers BUF driven simultaneously, the smaller the dynamic IR drop.

[0094] Fig.12 and Fig.13 is a circuit diagram showing an example of a method of delaying a signal input to a digital circuit portion.

[0095] Reference Fig.12 and Fig.13 The source driver IC chip SIC may further include a plurality of triggers FF1 to FF6 connected to the signal leads 911 to 91n-1 and delay circuits DLY, DLY1 and DLY2 connected to the clock terminal of at least one trigger FF4. One or more buffers may be connected to the leads between adjacent triggers FF1 to FF6.

[0096] The flip-flops FF1 to FF6 and the delay circuits DLY, DLY1 and DLY2 may be arranged in the digital circuit portion DCB or outside the digital circuit portion DCB. The flip-flops FF1 to FF6 are connected to the leads 911 to 91n-1 to receive the digital signals DATA[0] to DATA[n-1] and the clock CLK input through the leads 911 to 91n-1. The clock CLK is commonly input to the clock terminals of the flip-flops FF1 to FF6. Each of the flip-flops FF1 to FF6 outputs the digital signals DATA[0] to DATA[n-1] latched at the rising edge of the clock inversion to a high logic value.

[0097] The delay circuits DLY, DLY2, and DLY1 are connected between the clock terminals of the flip-flops FF4 and FF6 and the clock lead 92 to delay the clock CLK, thereby causing clock skew. The delay circuit may be implemented as an RC delay circuit, but is not limited thereto. Therefore, the flip-flops FF4 and FF6 connected to the delay circuits DLY, DLY2, and DLY1 output digital signals DATA[n-1] and DATA[x] in response to the delayed clock CLK. As a result, as shown in FIG. Fig.14 and Fig.15 As shown, the timing of transition or switching of the digital signals DATA[0] to DATA[n-1] transmitted through the leads 911 to 91n-1 may be spread out on the time axis. Fig.14 and Fig.15 In the figure, "Δt", "Δt1" and "Δt2" are delay times.

[0098] like Fig.13As shown, the delay circuits DLY1 and DLY2 can be connected to a plurality of flip-flops FF6 and FF4. The delay circuits DLY1 and DLY2 can be set to different delay values. For example, the delay value of the second delay circuit DLY2 can be greater than the delay value of the first delay circuit DLY1. In this case, Fig.15 As shown, the delay time Δt2 of the digital signal DATA[n-1] delayed by the second delay circuit DLY2 may be greater than the delay time Δt1 of the digital signal DATA[x] delayed by the first delay circuit DLY1. Fig.15 As shown, the maximum delay should be within the high logic period (H) of the clock CLK within one cycle T of the clock CLK.

[0099] The above-mentioned objects to be achieved by the present disclosure, means for achieving these objects and effects of the present disclosure do not indicate the essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0100] Although the embodiments of the present disclosure are described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be specifically implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and are not intended to limit the present disclosure.

[0101] CROSS-REFERENCE TO RELATED APPLICATIONS

[0102] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0134239, filed on October 10, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A source driver integrated circuit IC, the source driver IC comprising: one or more digital circuit sections configured to receive a digital signal; a plurality of signal leads connected to the digital circuit section and configured to transmit the digital signal to the digital circuit section; as well as a clock lead connected to the digital circuit portion and configured to transmit a clock to the digital circuit portion, Wherein, each of the signal lead and the clock lead comprises: an input lead located at the center of the digital circuit portion in the length direction; and A branch lead is branched toward both sides of the input lead along the length direction of the digital circuit portion.

2. The source driver IC according to claim 1, further comprising: A plurality of buffers are connected in series to each of the signal lead and the clock lead at equal intervals.

3. The source driver IC according to claim 2, wherein: The buffers are arranged on the branch leads in bilateral symmetry with respect to the input leads.

4. The source driver IC according to any one of claims 1 to 3, further comprising: A plurality of triggers, wherein the plurality of triggers are connected to each of the signal leads; as well as A delay circuit is connected to a clock terminal of at least one of the flip-flops.

5. The source driver IC according to claim 4, further comprising: A buffer is connected between the flip-flops.

6. The source driver IC according to any one of claims 1 to 3, further comprising: a first trigger connected to a first signal lead; a first delay circuit connected to a clock terminal of the first flip-flop; a second trigger connected to a second signal lead; as well as a second delay circuit connected to a clock terminal of the second flip-flop, The delay value of the first delay circuit is different from the delay value of the second delay circuit.

7. A display device, comprising: A display panel, on which a plurality of data lines and a plurality of pixels are arranged; as well as a source driver integrated circuit IC, the source driver IC being configured to supply a data voltage to the data line, Wherein, the source driver IC comprises: a digital circuit portion configured to receive a digital signal; a plurality of signal leads connected to the digital circuit section and configured to transmit the digital signal to the digital circuit section; and a clock lead connected to the digital circuit portion and configured to transmit a clock to the digital circuit portion, and Wherein, each of the signal lead and the clock lead comprises: an input lead located at the center of the digital circuit portion in the length direction; and A branch lead is branched toward both sides of the input lead along the length direction of the digital circuit portion.

8. The display device according to claim 7, wherein: The source driver IC further includes a plurality of buffers connected in series at equal intervals to each of the signal lead and the clock lead; and The buffers are arranged on the branch leads in bilateral symmetry with respect to the input leads.

9. The display device according to claim 7 or 8, wherein: The source driver IC also includes: a plurality of triggers connected to each of the signal leads; and A delay circuit is connected to a clock terminal of at least one of the flip-flops.

10. The display device according to claim 9, further comprising: A buffer is connected between the flip-flops.

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