Gamma circuit and control method thereof, display driving circuit and display device

Abstract

The embodiment of the invention provides a gamma circuit, relates to the technical field of display, and is used for improving the crosstalk problem. The gamma circuit includes a plurality of gate sub-circuits including a first gate sub-circuit and a second gate sub-circuit. The gating sub-circuit comprises a plurality of switches, the first ends of the plurality of switches are used for receiving gamma signals respectively, and the second ends of the plurality of switches are connected to the output end of the gating sub-circuit. The gating sub-circuit is configured to turn on one of the plurality of switches to output a gray scale data signal according to one of the plurality of gamma signals. Under the condition that a first gating sub-circuit needs to output a first gray scale data signal in the scanning time period of the Nth row of sub-pixels and the scanning time period of the (N + 1) th row of sub-pixels, a second gating sub-circuit needs to output a second gray scale data signal in the scanning time period of the Nth row of sub-pixels, and the first gray scale data signal needs to be output in the scanning time period of the (N + 1) th row of sub-pixels. A switch, used for outputting a first gray scale data signal, of the first gating sub-circuit is configured to be turned off firstly and then turned on.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a gamma circuit and a control method thereof, a display driving circuit, and a display device. Background Art

[0002] Liquid Crystal Display (LCD), as an important display technology, has been widely used in various electronic devices due to its advantages such as light weight, low power consumption and no radiation.

[0003] However, in the display process of LCD display devices, crosstalk is inevitable, which means that the grayscale brightness of a certain area in the display screen is affected by the grayscale brightness of the adjacent area, resulting in unexpected brightness deviation, color distortion or image blur. Crosstalk can significantly reduce the image quality of LCD display devices, affect the viewing experience, and even cause visual fatigue.

[0004] Therefore, an improved gamma circuit and control method thereof, a display driving circuit, and a display device are expected to solve the above problems. Summary of the invention

[0005] The purpose of the embodiments of the present disclosure is to provide a gamma circuit and a control method thereof, a display driving circuit, and a display device, so as to improve the crosstalk problem and enhance the display effect of the display device.

[0006] On the one hand, a gamma circuit is provided, comprising a plurality of gating subcircuits, wherein the plurality of gating subcircuits include a first gating subcircuits and a second gating subcircuits. The gating subcircuits include a plurality of switches, wherein the first ends of the plurality of switches are used to receive gamma signals respectively, and the second ends of the plurality of switches are connected to the output end of the gating subcircuits. The gating subcircuits are configured to turn on one of the plurality of switches to output a grayscale data signal according to one of the plurality of gamma signals. When the first gating subcircuits need to output a first grayscale data signal during the scanning period of the Nth row of subpixels and the N+1th row of subpixels, and the second gating subcircuits need to output a second grayscale data signal during the scanning period of the Nth row of subpixels, and when the first grayscale data signal needs to be output during the scanning period of the N+1th row of subpixels, in the first gating subcircuits, the switches for outputting the first grayscale data signal are configured to be turned off first and then turned on. N is an integer greater than or equal to 1.

[0007] In the scanning period of the Nth row of sub-pixels, the capacitor in the first selection sub-circuit is charged to the voltage of the first grayscale data signal, and the capacitor in the second selection sub-circuit is charged to the voltage of the second grayscale data signal. In the process of switching from the scanning period of the Nth row of sub-pixels to the scanning period of the N+1th row of sub-pixels, the switch of the second selection sub-circuit for outputting the second grayscale data signal is disconnected, and the switch for outputting the first grayscale data signal is turned on, and the switch of the first selection sub-circuit for outputting the first grayscale data signal is configured to be disconnected first and then turned on, and the voltage of the capacitor in the second selection sub-circuit is released during this process. Before the switch for outputting the first grayscale data signal in the first selection sub-circuit is closed, the residual charge in the second selection sub-circuit is released, and the influence of gamma charge sharing on the first selection sub-circuit is reduced or eliminated, thereby weakening or even eliminating the crosstalk problem.

[0008] In some feasible embodiments, when the second selection sub-circuit needs to output the second grayscale data signal during the scanning period of the Nth row of sub-pixels and needs to output the first grayscale data signal during the scanning period of the N+1th row of sub-pixels, in the second selection sub-circuit, the switch for outputting the second grayscale data signal is configured to be turned off, and the switch for outputting the first grayscale data signal is configured to be turned on.

[0009] In some feasible embodiments, the switch in the first gating subcircuit for outputting the first grayscale data signal is configured to be turned off before the switch in the second gating subcircuit for outputting the second grayscale data signal is turned off; or, the switch in the first gating subcircuit for outputting the first grayscale data signal is configured to be turned off when the switch in the second gating subcircuit for outputting the second grayscale data signal is turned off.

[0010] The switch for outputting the first grayscale data signal in the first gating subcircuit is configured to be turned off before or at the same time as the switch for outputting the second grayscale data signal in the second gating subcircuit is turned off, which can ensure that the residual charge in the second gating subcircuit can be effectively released before the switch for outputting the first grayscale data signal in the first gating subcircuit is turned on. On the other hand, it can ensure that the time for the switch for outputting the first grayscale data signal in the first gating subcircuit to be turned on again after being turned off is small in magnitude, and will not affect the normal display of the display device.

[0011] In some feasible embodiments, the switch in the first gating subcircuit for outputting the first grayscale data signal is configured to be turned on when the switch in the second gating subcircuit for outputting the first grayscale data signal is turned on.

[0012] According to another aspect of the present invention, a display driving circuit is provided, and the display driving circuit comprises: the above-mentioned gamma circuit.

[0013] In some feasible embodiments, the display driving circuit further includes a synchronization signal generating circuit and a gate driving circuit. The synchronization signal generating circuit is configured to provide a horizontal synchronization signal. The gate driving circuit is configured to provide a clock signal, and the start time of the clock signal is delayed by a first preset time compared to the start time of the horizontal synchronization signal.

[0014] The clock signal is delayed, so that when the clock signal ends, the abnormal fluctuation of the grayscale data signal ends and stabilizes, thereby effectively reducing the fluctuation amplitude of the grayscale data signal provided to the data line.

[0015] In some feasible embodiments, the gamma circuit is further configured to receive a source output enable signal and provide a grayscale data signal according to the source output enable signal; the start time of the source output enable signal is delayed by a second preset time compared to the end time of the horizontal synchronization signal.

[0016] The delay of the end time of the source output enable signal prolongs the time when the source output enable signal is at the working voltage, thereby effectively reducing the fluctuation amplitude of the grayscale data signal.

[0017] In some feasible embodiments, the difference between the end time of the clock signal and the start time of the grayscale data signal is greater than or equal to 0.8 microseconds; and / or, the difference between the end time of the grayscale data signal and the end time of the clock signal is greater than or equal to 0.8 microseconds.

[0018] Ensuring sufficient charging time and / or gate opening time of the grayscale data signal allows the sub-pixel to obtain sufficient charging time, thereby avoiding display abnormality caused by too short charging time.

[0019] In some feasible embodiments, the display driving circuit further includes a bias circuit configured to provide a bias current to the gamma circuit to reduce the thrust of the grayscale data signal.

[0020] Reducing the thrust of the grayscale data signal can slow down the rising and falling edges of the grayscale data signal, that is, prolonging the rising time and falling time of the grayscale data signal to weaken the influence of gamma charge sharing and reduce the fluctuation amplitude of the grayscale data signal. At the end of the clock signal, the fluctuation of the grayscale data signal has returned to stability, thereby improving the crosstalk problem.

[0021] According to another aspect of the present invention, there is provided a display device, comprising: a display panel, the display panel comprising a plurality of sub-pixels arranged in an array, and a plurality of data lines, one data line being connected to at least one column of sub-pixels; and the above-mentioned display driving circuit, wherein a gamma circuit in the display driving circuit is connected to the plurality of data lines.

[0022] According to another aspect of the present invention, a control method for a gamma circuit is provided, and the control method is applied to the above-mentioned gamma circuit. During scanning from the Nth row of sub-pixels to the N+1th row of sub-pixels, the control method comprises: turning off a switch for outputting a second grayscale data signal in a second selection sub-circuit in the gamma circuit, and turning on a switch for outputting a first grayscale data signal in the second selection sub-circuit, so that the output of the second selection sub-circuit is switched from the second grayscale data signal to the first grayscale data signal; turning off a switch for outputting the first grayscale data signal in a first selection sub-circuit in the gamma circuit, and turning on the switch for outputting the first grayscale data signal in the first selection sub-circuit again.

[0023] The control method of the gamma circuit, the display driving circuit and the display device have the same structure and beneficial technical effects as the gamma circuits provided in some of the above embodiments, which will not be described in detail herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0025] Figure 1 is a structural diagram of a display panel according to some embodiments;

[0026] Figure 2 is a circuit module diagram of a display device according to some embodiments;

[0027] Figure 3 A gray screen of a display device according to some embodiments;

[0028] Figure 4 A gray-black screen of a display device according to some embodiments;

[0029] Figure 5 A crosstalk picture of a display device according to some embodiments;

[0030] Figures 6 to 8 is another crosstalk picture of a display device according to some embodiments;

[0031] Fig. 9 is a waveform diagram of a grayscale data signal of a display device according to some embodiments;

[0032] Fig.10 for Figure 5 A partial enlarged view of the middle C area;

[0033] Fig.11 is a signal timing diagram of a display device according to some embodiments;

[0034] Fig.12 is a circuit structure diagram of a gamma circuit according to some embodiments;

[0035] Fig.13 is a working principle diagram of a gamma circuit according to some embodiments;

[0036] Fig.14 is a gamma signal timing diagram and a grayscale data signal timing diagram according to some embodiments;

[0037] Fig.15 is a flow chart of a method for controlling a gamma circuit according to some embodiments;

[0038] Fig.16 is a working principle diagram of another gamma circuit according to some embodiments;

[0039] Fig.17 is another signal timing diagram of a display device according to some embodiments. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0043] When describing some embodiments, the expression "connection" and its derivatives may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0044] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0045] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0046] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices being configured to perform additional tasks or steps.

[0047] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0048] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0049] Figure 1 FIG. 1 is a structural diagram of a display device according to some embodiments. Figure 1 As shown, an embodiment of the present disclosure provides a display device 1000, which is a product with an image display function. Exemplarily, the display device 1000 can be any device that displays either motion (e.g., video) or fixed (e.g., still image) and whether text or image.

[0050] For example, the display device 1000 may be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle display, a flight display, or any other product or component having a display function. For example, Figure 1 As shown, the display device 1000 may be a mobile phone.

[0051] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be a liquid crystal display (LCD) display device, an organic light-emitting diode (OLED) display device, or a quantum dot light emitting diode (QLED) display device. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular.

[0052] In the following, some embodiments of the present disclosure are schematically described by taking the display device 1000 as a rectangular and planar liquid crystal display device as an example, but the implementation of the present disclosure is not limited to this, and any other display device can also be considered as long as the same technical concept is applied.

[0053] Figure 2 FIG. 1 is a circuit module diagram of a display device according to some embodiments. Figure 2As shown, the display device 1000 includes a display panel 100 and a display driving circuit 300. Exemplarily, the display device 1000 may include one or more display driving circuits 300, such as one, two or three display driving circuits 300.

[0054] The display panel 100 includes a plurality of sub-pixels (not shown) arranged in an array, and a plurality of data lines.

[0055] The display driving circuit 300 includes a gate driving circuit 310, a synchronization signal generating circuit 320, a bias circuit 330, and a gamma circuit 340. The gate driving circuit 310 is configured to provide a clock signal CLK to the display panel 100. Exemplarily, the gate driving circuit 310 may provide one or more clock signals CLK to the display panel 100, for example, the gate driving circuit 310 provides one clock signal CLK, two clock signals CLK, or three clock signals CLK to the display panel 100. When the gate driving circuit 310 provides multiple clock signals CLK, the timings of the multiple clock signals CLK may be the same or different.

[0056] The synchronization signal generating circuit 320 is configured to provide a horizontal synchronization signal Hsync, which, for example, marks the end of a row of sub-pixels and the beginning of the next row of sub-pixels to ensure that each row of sub-pixels of the display panel 100 can be displayed in sequence and aligned. Exemplarily, the horizontal synchronization signal Hsync can also be used as a time reference for other control signals.

[0057] The gamma circuit 340 is connected to the display panel 100 through a plurality of data lines. The gamma circuit 340 is configured to receive a source output enable signal SOP enable, and provide a plurality of grayscale data signals S corresponding to the number of the plurality of data lines according to the source output enable signal SOP enable, and provide the plurality of grayscale data signals S to the selected sub-pixels, thereby enabling the display device 1000 to display an image.

[0058] In some feasible embodiments, the display driving circuit 300 further includes a bias circuit 330, which is configured to provide a bias current Ib. The gamma circuit 340 receives the bias current Ib and adjusts the thrust of the grayscale data signal S provided by the gamma circuit 340 according to the bias current Ib.

[0059] In some feasible embodiments, the display driving circuit 300 may be a touch and display driver integration (TDDI) circuit.

[0060] In some feasible embodiments, the gate driving circuit 310 may be integrated with the display panel 100 on the same substrate to form a gate driver on array (GOA).

[0061] In some exemplary screens, such as Figure 3 As shown, it shows the screen displayed by the display device 1000 in an ideal state. Figure 3 A gray screen of a display device according to some embodiments. Figure 3 Only the display panel 100 and the display driving circuit 300 are shown, and other components are not shown. Figure 3 In the example, the first color display area 105 displays gray, and the second color display area 106 displays white. Figure 3 In the figure, the boundary between the first color display area 105 and the second color display area 106 is clear, and there is no display abnormality.

[0062] Figure 4 The gray-black screen of the display device according to some embodiments, wherein the first color display area 105 displays gray, the third color display area 107 displays black, Figure 4 In the figure, the first color display area 105 and the third color display area 107 also have clear boundaries, and there is no display abnormality.

[0063] However, in actual application scenarios, the display device 1000 has a crosstalk problem. For example, during the display process of the display device 1000, other colors of the screen appearing on the solid color background cause the brightness of the adjacent area to change, resulting in abnormal display of the screen, such as Figure 5 shown. Figure 5 A crosstalk picture of a display device according to some embodiments. Figure 5 Only the display panel 100 and the display driving circuit 300 are shown, and other components are not shown.

[0064] The display panel 100 includes a first sub-area 101, a second sub-area 102, a third sub-area 103 and a fourth sub-area 104. It can be seen that the second color display area 106 displaying white is located in the second sub-area 102 and the third sub-area 103. There is an obvious crosstalk problem at one end of the second color display area 106 close to the display driving circuit 300, and the crosstalk is located in the second sub-area 102 and the third sub-area 103.

[0065] In some possible embodiments, such as Figures 6 to 8 As shown, Figures 6 to 8 is another crosstalk picture of a display device according to some embodiments. Figure 6In the embodiment, the second color display area 106 displaying white is located in the first sub-area 101, and a section of the second color display area 106 close to the display driving circuit 300 has a crosstalk problem, and the crosstalk is located in the first sub-area 101. Figure 7 In the embodiment, the second color display area 106 displaying white is located in the second sub-area 102. The second color display area 106 close to the display driving circuit 300 has a crosstalk problem, and the crosstalk is located in the second sub-area 102. Figure 8 In the embodiment, the second color display area 106 displaying white is located in the first sub-area 101. The second color display area 106 near the end of the display driving circuit 300 has a crosstalk problem, and the crosstalk is located in the first sub-area 101. Figures 5 to 8 It is easy to see that the crosstalk problem is regional.

[0066] To solve the above crosstalk problem, the waveform of the grayscale data signal S at different positions is measured, and the following is obtained: Fig. 9 The waveform shown in the figure, Fig. 9 1 is a waveform diagram of a grayscale data signal S of a display device according to some embodiments, which includes, from top to bottom, a start pulse signal, a signal of data line S2, a signal of data line S1, a partial enlarged diagram of the signal of data line S2 in region A, and a partial enlarged diagram of data line S1 in region A. Fig.10 for Figure 5 A partial enlarged view of the middle C area. Fig.10 In the scanning period of the Nth row of sub-pixels, the data line S1 provides the first grayscale data signal SS1, and the data line S2 provides the second grayscale data signal SS2. In the scanning period of the N+1th row of sub-pixels, the data line S1 provides the first grayscale data signal SS1, and the data line S2 provides the first grayscale data signal SS1. Fig. 9 At time t0, the scanning period is switched to the N+1th row of sub-pixels, where N is an integer greater than or equal to 1.

[0067] Fig. 9 In the figure, at time t0 in area B, the data line S2 switches from providing the second grayscale data signal SS2 to providing the first grayscale data signal SS1, and the first grayscale data signal SS1 provided by the data line S1 has an abnormal pulse. It is easy to know that one of the reasons why the display device 1000 has a crosstalk problem is that when the data line S1 outputs the first grayscale data signal SS1 during the scanning period of the Nth row of sub-pixels and the N+1th row of sub-pixels, the data line S2 provides the second grayscale data signal SS2 during the scanning period of the Nth row of sub-pixels, and provides the first grayscale data signal SS1 during the scanning period of the N+1th row of sub-pixels. This switching process will cause the first grayscale data signal SS1 provided by the data line S1 to generate an abnormal pulse, thereby causing the display device 1000 to have a display abnormality.

[0068] In view of this, some embodiments of the present application reduce abnormal pulses by adjusting the signal timing, such as Fig.11 As shown, Fig.11 1 is a signal timing diagram of a display device according to some embodiments, which respectively represents the horizontal synchronization signal Hsync, the clock signal CLK, the source output enable signal SOP enable, and the first grayscale data signal SS1 in the first embodiment, and the clock signal CLK, the source output enable signal SOP enable, and the first grayscale data signal SS1 in the second embodiment. The time period t1-t4 is the scanning period of the Nth row of sub-pixels, and the time period t4-t8 is the scanning period of the N+1th row of sub-pixels.

[0069] In the first embodiment, t1 is the starting time of the horizontal synchronization signal Hsync, the clock signal CLK and the source output enable signal SOPenable, t2 is the starting time of the source output signal, and t3 is the ending time of the clock signal CLK. It can be seen that in the first embodiment, the fluctuation amplitude of the first grayscale data signal SS1 is large, and when the clock signal CLK ends at time t3, the first grayscale data signal SS1 is still in an abnormal fluctuation state, so that the display device 1000 has display abnormalities such as crosstalk problems.

[0070] In the second embodiment, t4 is the starting time of the horizontal synchronization signal Hsync, t5 is the starting time of the clock signal CLK, t6 is the starting time of the source output enable signal SOP enable, and t7 is the end time of the clock signal CLK. That is, the starting time t5 of the clock signal CLK is delayed by the first preset time compared to the starting time t4 of the horizontal synchronization signal Hsync, and its end time t7 is also delayed by the first preset time, that is, the clock signal CLK is shifted back as a whole, ensuring the duty cycle of the clock signal CLK. Exemplarily, the duty cycle of the clock signal CLK is 35%. In different application scenarios, the duty cycle of the clock signal CLK can be adjusted according to actual needs, and the present application does not limit this. The starting time t6 of the source output enable signal SOP enable is delayed by the second preset time compared to the end time of the horizontal synchronization signal Hsync. It can be seen that the source output enable signal starts at time t6 and the clock signal CLK ends at time t7. The delay of the clock signal CLK and the delay of the start time of the source output enable signal SOP enable can effectively increase the time for the first grayscale data signal SS1 to return to a steady state, while reducing gamma charge sharing (Gamma charge sharing), thereby effectively reducing the fluctuation amplitude of the first grayscale data signal SS1.

[0071] In some feasible embodiments, when adjusting the start time and / or end time of the clock signal CLK and the source output enable signal SOPenable in the second embodiment, the charging time of the grayscale data signal S of the display device 1000 must also be ensured. Exemplarily, the difference between the end time of the clock signal CLK and the start time of the grayscale data signal S is greater than or equal to 0.8 microseconds.

[0072] In some feasible embodiments, when adjusting the start and / or end time of the clock signal CLK and the source output enable signal SOPenable in the second embodiment, the gate-on time (GOE time, Gate On Enable) of the display device 1000 must also be ensured. For example, the difference between the end time of the grayscale data signal S and the end time of the clock signal CLK is greater than or equal to 0.8 microseconds.

[0073] The first preset time and / or the second preset time are adjusted according to the requirements of the actual application scenario to ensure sufficient charging time of the grayscale data signal S and / or gate opening time, so that the sub-pixel obtains sufficient charging time to avoid display abnormalities caused by too short charging time.

[0074] The present application also provides another embodiment for improving or solving the crosstalk problem. Fig.12 , Fig.13 as well as Fig.14 . Fig.12 3 is a circuit structure diagram of a gamma circuit according to some embodiments. The gamma circuit 340 includes a plurality of gating sub-circuits 350 and a gamma voltage generating circuit 360 .

[0075] The gamma voltage generating circuit 360 is configured to provide multiple gamma signals. Exemplarily, the display device 1000 is an eight-bit grayscale display device. In this case, the multiple gamma signals provided by the gamma voltage generating circuit 360 include gamma signal 0 to gamma signal 255, totaling 256 grayscale levels.

[0076] The gating subcircuit 350 includes a plurality of switches K, the number of switches K included in the gating subcircuit 350 corresponds to the number of gamma signals, a first end of each switch K is connected to the gamma voltage generating circuit 360 to receive the plurality of gamma signals, and a second end of each switch K is connected to the output end of the gating subcircuit 350. The gating subcircuit 350 is configured to turn on one of the plurality of switches K to output the grayscale data signal S according to one of the plurality of gamma signals. Exemplarily, the gating subcircuit 350 further includes a capacitor Vdac, a first end of the capacitor Vdac is connected to the first end of the gating subcircuit 350, and a second end is grounded.

[0077] In some feasible embodiments, the gamma circuit 340 further includes a plurality of amplifiers SOP, and the number of the amplifiers SOP corresponds to the number of the gating sub-circuit 350. The input end of the amplifier SOP is connected to the gating sub-circuit 350 to receive the grayscale data signal S provided by the gating sub-circuit 350, and the output end of the amplifier SOP is connected to the data line to provide the adjusted grayscale data signal S to the corresponding data line.

[0078] Specifically, see Fig.13 and Fig.14 , Fig.13 is a working principle diagram of a gamma circuit according to some embodiments, Fig.14 is a timing diagram of a gamma signal and a timing diagram of a grayscale data signal S according to some embodiments, Fig.14 In FIG. 1 , from top to bottom, they are respectively the gamma signal 255, the gamma signal 127, the grayscale data signal S of the data line S2, and the grayscale data signal S of the data line S1, wherein the dotted line Vdacs2 is the capacitor Vdac voltage of the second selection sub-circuit 352. Fig.10 , Figure 12 to Figure 14 The operating principle of the display device 1000 is described.

[0079] Fig.13 In the figure, the left side is the scanning period of the Nth row of sub-pixels, and the right side is the scanning period of the N+1th row of sub-pixels. In the scanning period of the Nth row of sub-pixels, the first selection sub-circuit 351 turns on one of the multiple switches K to provide the gamma signal 127 to the capacitor Vdac. The first selection sub-circuit 351 outputs the first grayscale data signal SS1 according to the gamma signal 127, so that the corresponding sub-pixel of the display device 1000 displays gray. The second selection sub-circuit 352 turns on one of the multiple switches K to provide the gamma signal 255 to the capacitor Vdac. The second selection sub-circuit 352 outputs the second grayscale data signal SS2 according to the gamma signal 255, so that the corresponding sub-pixel of the display device 1000 displays white. Fig.14 Before time t9, the first selection sub-circuit 351 outputs the first grayscale data signal SS1 to the data line S1, and the second selection sub-circuit 352 outputs the second grayscale data signal SS2 to the data line S2.

[0080] During the scanning period of the N+1th row of sub-pixels, the switch K for outputting the first grayscale data signal SS1 in the first selection sub-circuit 351 remains turned on, and the first selection sub-circuit 351 continues to output the first grayscale data signal SS1. The switch K for outputting the second grayscale data signal SS2 in the second selection sub-circuit 352 is turned off, and the switch K for outputting the first grayscale data signal SS1 is turned on, and the second selection sub-circuit 352 outputs the first grayscale data signal SS1 according to the gamma signal 127. Fig.14After the moment t9 in the figure, the first selection subcircuit 351 outputs the first grayscale data signal SS1 to the data line S1, and the second selection subcircuit 352 outputs the first grayscale data signal SS1 to the data line S2. It can be seen that the first selection subcircuit 351 outputs the first grayscale data signal SS1 in the scanning period of the Nth row of sub-pixels and the N+1th row of sub-pixels, and the second selection subcircuit 352 outputs the second grayscale data signal SS2 in the scanning period of the Nth row of sub-pixels, and outputs the first grayscale data signal SS1 in the scanning period of the N+1th row of sub-pixels. The path of the second selection subcircuit 352 is switched from the gamma signal 255 to the gamma signal 127, and the capacitor Vdac still has the voltage of the gamma signal 255. Since the first selection subcircuit 351 and the second selection subcircuit 352 are connected to the same gamma voltage generating circuit 360, gamma charge sharing is generated during switching, resulting in abnormal pulses in the gamma signal 127. The first selection subcircuit 351 keeps the path of the gamma signal 127 unchanged, but the switching change of the second selection subcircuit 352 affects the voltage of the gamma signal 127. Therefore, the first grayscale data signal SS1 provided by the first selection subcircuit 351 according to the gamma signal 127 is affected, generating an abnormal pulse.

[0081] Therefore, the present application provides a gamma circuit and a control method thereof to solve the above problems. Fig.15 3 is a flow chart of a method for controlling a gamma circuit according to some embodiments. In the process of scanning from the Nth row of sub-pixels to the N+1th row of sub-pixels, the method for controlling the gamma circuit 340 includes step S1 and step S2.

[0082] In step S1, the switch K for outputting the second grayscale data signal SS2 in the second selection subcircuit 352 in the gamma circuit 340 is turned off, and the switch K for outputting the first grayscale data signal SS1 in the second selection subcircuit 352 is turned on, so that the output of the second selection subcircuit 352 is switched from the second grayscale data signal SS2 to the first grayscale data signal SS1.

[0083] In step S2 , the switch K in the first gating subcircuit 351 in the gamma circuit 340 for outputting the first grayscale data signal SS1 is turned off, and the switch K in the first gating subcircuit 351 for outputting the first grayscale data signal SS1 is turned on again.

[0084] There is no strict order between step S1 and step S2. It is not necessary to execute all the steps in step S1 first and then execute all the steps in step S2. The two steps can be performed synchronously or alternately.

[0085] In some feasible embodiments, before the switch K for outputting the second grayscale data signal SS2 in the second selection subcircuit 352 is turned off in step S1 , the switch K for outputting the first grayscale data signal SS1 in the first selection subcircuit 351 is turned off in step S2 .

[0086] In some feasible embodiments, when the switch K for outputting the second grayscale data signal SS2 in the second selection subcircuit 352 is turned off in step S1 , the switch K for outputting the first grayscale data signal SS1 in the first selection subcircuit 351 is turned off in step S2 .

[0087] The following combination Fig.16 The above control method is explained. Fig.16 FIG. 4 is a working principle diagram of another gamma circuit according to some embodiments.

[0088] The left side is the scanning period of the Nth row of sub-pixels, the middle is the switching period of the Nth row of sub-pixels and the N+1th row of sub-pixels, and the right side is the scanning period of the N+1th row of sub-pixels. During the scanning period of the Nth row of sub-pixels, the switch K for outputting the first grayscale data signal SS1 in the first selection sub-circuit 351 is turned on to provide the gamma signal 127 to the capacitor Vdac. The first selection sub-circuit 351 outputs the first grayscale data signal SS1 according to the gamma signal 127, so that the corresponding sub-pixel of the display device 1000 displays gray. The switch K for providing the second grayscale data signal SS2 in the second selection sub-circuit 352 is turned on to provide the gamma signal 255 to the capacitor Vdac. The second selection sub-circuit 352 outputs the second grayscale data signal SS2 according to the gamma signal 255, so that the corresponding sub-pixel of the display device 1000 displays white. Corresponding Fig.14 Before time t9, the first selection sub-circuit 351 outputs the first grayscale data signal SS1 to the data line S1, and the second selection sub-circuit 352 outputs the second grayscale data signal SS2 to the data line S2.

[0089] During the switching period between the Nth row of sub-pixels and the N+1th row of sub-pixels, the switch K for outputting the second grayscale data signal SS2 in the second selection sub-circuit 352 is disconnected, and the switch K for outputting the first grayscale data signal SS1 in the first selection sub-circuit 351 is also disconnected, so that the capacitor Vdac in the second selection sub-circuit 352 releases the residual charge.

[0090] During the scanning period of the N+1th row of sub-pixels, the switch K for outputting the first grayscale data signal SS1 in the first selection sub-circuit 351 is turned on to provide the gamma signal 127 to the capacitor Vdac, and the first selection sub-circuit 351 outputs the first grayscale data signal SS1 according to the gamma signal 127, so that the corresponding sub-pixel of the display device 1000 displays gray. The switch K for providing the first grayscale data signal SS1 in the second selection sub-circuit 352 is turned on to provide the gamma signal 127 to the capacitor Vdac, and the second selection sub-circuit 352 outputs the first grayscale data signal SS1 according to the gamma signal 127.

[0091] In the scanning period of the Nth row of sub-pixels, the capacitor Vdac in the first selection sub-circuit 351 is charged to the voltage of the gamma signal 127, and the capacitor Vdac in the second selection sub-circuit 352 is charged to the voltage of the gamma signal 255. In the process of switching from the scanning period of the Nth row of sub-pixels to the scanning period of the N+1th row of sub-pixels, the switch K of the second selection sub-circuit 352 for outputting the second grayscale data signal SS2 is disconnected, and the switch K for outputting the first grayscale data signal SS1 is turned on, the switch K of the first selection sub-circuit 351 for outputting the first grayscale data signal SS1 is configured to be disconnected first and then turned on, and the voltage of the capacitor Vdac in the second selection sub-circuit 352 is released in this process. Before the switch for outputting the first grayscale data signal SS1 in the first selection sub-circuit 351 is closed, the residual charge in the second selection sub-circuit 352 is released, and the influence of the gamma charge sharing on the first selection sub-circuit 351 is reduced or eliminated, thereby weakening or even eliminating the crosstalk problem.

[0092] Before or when the switch K for outputting the second grayscale data signal SS2 in the second selection sub-circuit 352 is disconnected, the switch K for outputting the first grayscale data signal SS1 in the first selection sub-circuit 351 is disconnected, so as to ensure that when the second selection sub-circuit 352 releases its residual charge, it will not affect the first selection sub-circuit 351, thereby further reducing or eliminating the crosstalk problem.

[0093] In some feasible embodiments, the switch K in the first gating subcircuit 351 for outputting the first grayscale data signal SS1 is configured to be turned off before the switch K in the second gating subcircuit 352 for outputting the second grayscale data signal SS2 is turned off.

[0094] In some feasible embodiments, the switch K in the first gating subcircuit 351 for outputting the first grayscale data signal SS1 is configured to be turned off when the switch K in the second gating subcircuit 352 for outputting the second grayscale data signal SS2 is turned off.

[0095] The switch K for outputting the first grayscale data signal SS1 in the first gating subcircuit 351 is configured to be turned off before or at the same time as the switch K for outputting the second grayscale data signal SS2 in the second gating subcircuit 352 is turned off, which can ensure that the residual charge in the second gating subcircuit 352 can be effectively released before the switch K for outputting the first grayscale data signal SS1 in the first gating subcircuit 351 is turned on. On the other hand, it can ensure that the time magnitude of the switch K for outputting the first grayscale data signal SS1 in the first gating subcircuit 351 being turned on again after being turned off is small, and will not affect the normal display of the display device 1000.

[0096] In this embodiment, the first gating subcircuit 351 is affected by the second gating subcircuit 352, resulting in the crosstalk problem. In some feasible embodiments, the gamma circuit 340 may further include more gating subcircuits 350 similar to the first gating subcircuit 351 and affected by the second gating subcircuit 352. For example, the gamma circuit 340 further includes a third gating subcircuit, which is similar to the first gating subcircuit 351 and is affected by the residual charge of the capacitor Vdac in the second gating subcircuit 352. Therefore, the third gating subcircuit has the same circuit structure and configuration as the first gating subcircuit 351 and is applicable to the same control method, thereby avoiding the gamma charge sharing of the second gating subcircuit 352 affecting the first gating subcircuit 351 and the third gating subcircuit, and reducing or even eliminating the crosstalk problem.

[0097] In some feasible embodiments, in order to reduce the crosstalk problem caused by gamma charge sharing, the thrust of the grayscale data signal S may be reduced without affecting the normal display of the display device 1000. Fig.17 As shown, Fig.17 FIG. 1 is another signal timing diagram of a display device according to some embodiments, which respectively shows the horizontal synchronization signal Hsync, the clock signal CLK, the source output enable signal SOP enable, and the first grayscale data signal SS1 in the first embodiment, and the clock signal CLK, the source output enable signal SOP enable, and the first grayscale data signal SS1 in the third embodiment. Figure 2 Provide further explanation.

[0098] The bias circuit 330 provides a bias current Ib, and the gamma circuit 340 outputs grayscale data signals S with different thrusts according to the bias current Ib. By adjusting the bias current Ib provided by the bias circuit 330, the thrust of the first grayscale data signal SS1 is reduced, and the influence of gamma charge sharing can be weakened. The thrust refers to the driving force required for the grayscale data signal S to climb from a low level to a high level. When the thrust is high, the time required for the grayscale data signal S to rise from a low level to a high level is short, that is, the switching rate from a low level to a high level is fast.

[0099] See also Fig.17 , when the horizontal synchronization signal Hsync, the clock signal CLK and the source output enable signal SOP enable are basically consistent, the fluctuation amplitude of the first grayscale data signal SS1 at time t10 in the first embodiment is relatively large. After reducing the thrust, the fluctuation amplitude of the first grayscale data signal SS1 at time t10 in the third embodiment is significantly reduced. Reducing the thrust of the first grayscale data signal SS1 can slow down the rising edge and falling edge of the first grayscale data signal SS1, that is, extend the rising time and falling time of the first grayscale data signal SS1, so as to weaken the influence of gamma charge sharing and reduce the fluctuation amplitude of the first grayscale data signal SS1. At the end of the clock signal CLK, the fluctuation of the first grayscale data signal SS1 has returned to stability, thereby improving the crosstalk problem.

[0100] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A gamma circuit, characterized in that: The gating subcircuit comprises a plurality of gating subcircuits, wherein the gating subcircuit comprises a plurality of switches, wherein first ends of the plurality of switches are used to receive gamma signals respectively, and second ends of the plurality of switches are connected to output ends of the gating subcircuit; The gating subcircuit is configured to turn on one of the plurality of switches to output a grayscale data signal according to one of the plurality of gamma signals; The multiple selection sub-circuits include a first selection sub-circuit and a second selection sub-circuit. The first selection sub-circuit needs to output a first grayscale data signal during the scanning period of the Nth row of sub-pixels and the N+1th row of sub-pixels, and the second selection sub-circuit needs to output a second grayscale data signal during the scanning period of the Nth row of sub-pixels. When the first grayscale data signal needs to be output during the scanning period of the N+1th row of sub-pixels, in the first selection sub-circuit, a switch for outputting the first grayscale data signal is configured to be first turned off and then turned on; N is an integer greater than or equal to 1.

2. The gamma circuit according to claim 1, characterized in that: When the second selection sub-circuit needs to output the second grayscale data signal during the scanning period of the sub-pixels in the Nth row, and needs to output the first grayscale data signal during the scanning period of the sub-pixels in the N+1th row, in the second selection sub-circuit, the switch for outputting the second grayscale data signal is configured to be turned off, and the switch for outputting the first grayscale data signal is configured to be turned on.

3. The gamma circuit according to claim 2, characterized in that: The switch in the first gating subcircuit for outputting the first grayscale data signal is configured to be turned off before the switch in the second gating subcircuit for outputting the second grayscale data signal is turned off; or, The switch in the first gating subcircuit for outputting the first grayscale data signal is configured to be turned off when the switch in the second gating subcircuit for outputting the second grayscale data signal is turned off.

4. The gamma circuit according to claim 3, characterized in that: The switch in the first gating subcircuit for outputting the first grayscale data signal is configured to be turned on when the switch in the second gating subcircuit for outputting the first grayscale data signal is turned on.

5. A display driving circuit, characterized in that: The display driving circuit comprises: a gamma circuit as claimed in any one of claims 1 to 4.

6. The display driving circuit according to claim 5, characterized in that: Also includes: A synchronization signal generating circuit configured to provide a horizontal synchronization signal; The gate driving circuit is configured to provide a clock signal, wherein a starting time of the clock signal is delayed by a first preset time compared to a starting time of the horizontal synchronization signal.

7. The display driving circuit according to claim 6, characterized in that: The gamma circuit is further configured to receive a source output enable signal and provide a grayscale data signal according to the source output enable signal; The starting time of the source output enable signal is delayed by a second preset time compared to the ending time of the horizontal synchronization signal.

8. The display driving circuit according to claim 7, characterized in that: The difference between the end time of the clock signal and the start time of the grayscale data signal is greater than or equal to 0.8 microseconds; and / or, The difference between the end time of the grayscale data signal and the end time of the clock signal is greater than or equal to 0.8 microseconds.

9. The display driving circuit according to any one of claims 5 to 8, characterized in that: Also includes: The bias circuit is configured to provide a bias current to the gamma circuit to output grayscale data signals with different thrusts.

10. A display device, characterized in that: include: A display panel, the display panel comprising a plurality of sub-pixels arranged in an array, and a plurality of data lines, one data line being connected to at least one column of sub-pixels; The display driving circuit according to any one of claims 5 to 9, wherein a gamma circuit in the display driving circuit is connected to a plurality of the data lines.

11. A method for controlling a gamma circuit, characterized in that: The control method is applied to the gamma circuit according to any one of claims 1 to 4, and in the process of scanning from the Nth row of sub-pixels to the N+1th row of sub-pixels, the control method comprises: Turning off a switch in a second gating subcircuit in the gamma circuit for outputting a second grayscale data signal, and turning on a switch in the second gating subcircuit for outputting a first grayscale data signal, so that the output of the second gating subcircuit is switched from the second grayscale data signal to the first grayscale data signal; A switch in a first gating subcircuit in the gamma circuit for outputting the first grayscale data signal is turned off, and a switch in the first gating subcircuit for outputting the first grayscale data signal is turned on again.

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