Anti-side-channel-attack NTT circuit facing lattice-based cryptographic algorithm

Abstract

The invention discloses a lattice-based cryptographic algorithm-oriented side channel attack-resistant NTT circuit, which comprises a control unit, which is mainly used for controlling the enabling of a bottom layer component in the structure and the data flow direction among modules; the storage unit is used for storing the coefficient, the random twiddle factor address and the twiddle factor; the address generation unit is used for calculating and generating a storage RAM (Random Access Memory) address of a twiddle factor participating in operation and a read address required by the coefficient storage unit; and the coefficient transposing unit is used for realizing coefficient reading meeting the index distance among all NTT stages. According to the side channel attack resisting NTT circuit oriented to the lattice-based cryptographic algorithm, when a low delay base-4CT / GS butterfly unit is masked, the increment of modular multiplication resources is reduced, and the resource consumption is remarkably reduced while high security is kept.

Description

Technical Field

[0001] The present invention relates to the technical field of information security and cryptographic hardware circuits, and in particular to an NTT circuit resistant to side channel attacks for a lattice cryptographic algorithm. Background Art

[0002] The rapid development of quantum computers poses a severe challenge to modern encryption systems. Shor's algorithm significantly weakens the security of encryption systems built on algorithms such as RSA and ECC. In response to future changes in information security, NIST launched the Post-Quantum Cryptography (PQC) standardization process in 2016 and announced four PQC standard algorithms including CRYSTALS-Dilithium in 2023. However, while pursuing high mathematical security in lattice cryptographic schemes, the threat of side channel attacks (SCA) cannot be ignored. Attackers may use side channel information such as the time and power consumption of the system when executing core operators to obtain sensitive information, which brings new challenges to the security of lattice cryptographic systems.

[0003] In the cryptographic system based on RLWE, the key consists of a polynomial in a finite ring, and encryption and decryption involve multiplication operations with the key polynomial, which is an ideal target for SCA. As a common method to accelerate polynomial multiplication, NTT currently faces one of the main attack methods, which is single-trace attacks (SA). Soft analysis side channel attack (SASCA) was first proposed by Veyrat-Charvillon et al. in 2015. It is a type of attack that combines trace information and information about the algorithm itself. This attack combines the algebraic side channel attack (ASCA) with optimal data complexity and the noise tolerance (DPA) based on divide-and-conquer differential power analysis, with low time and space complexity. The attacker uses the sparsity of information of the intermediate variables of the actual leakage trace to effectively recover the key. Primas et al. first applied this method to the side channel attack on NTT, and realized SA by using the leakage during the execution of NTT. First, INTT was selected as the attack target, then the factor graph was constructed according to the NTT algorithm, and finally the private key was solved by lattice decoding, but this attack requires about 1 million templates. Pessl et al. reduced the number of templates required for SA to only 213, successfully performed full key recovery for constant-time Kyber implemented on an ARM Cortex-M4 microcontroller, and proposed protecting NTT from the above SA through shuffling or randomized butterfly operations.

[0004] Ravi et al. proposed two schemes, Shuffling and randomization, for the SA attack on NTT, and evaluated their performance on the ARM Cortex-M4 microcontroller. In the randomization scheme, the power of the sum of the rotation factors is used to replace the random number as a mask, thereby avoiding the complex modular inverse operation and realizing the security design of the underlying CT butterfly unit. On this basis, by updating the random rotation factors used by NTT at different stages, three randomized NTT schemes with different granularities were proposed, which increased the complexity of the NTT calculation process and thus increased the difficulty of SA. However, this method is limited to the software level and has not been implemented at the hardware level.

[0005] In 2023, Rodriguez et al. built on this foundation and realized the hardware implementation of the base-2NTT side-channel mask protection scheme, but the hardware overhead was as high as about 2.3 to 5.4 times.

[0006] In CHES 2024, Rodriguez et al. proposed an NTT hardware implementation that configures the above-mentioned shuffling and randomization countermeasures in a flexible manner, and conducted a security analysis of the masking scheme, but the hardware overhead was also more than 2 times. Summary of the invention

[0007] In order to solve the technical problems existing in the background technology, the present invention proposes an NTT circuit resistant to side channel attacks for a lattice cryptographic algorithm.

[0008] The present invention proposes a side channel attack resistant NTT circuit for a lattice cryptographic algorithm, comprising:

[0009] The control unit mainly controls the enabling of the underlying components in the structure and the data flow between modules;

[0010] A storage unit for storing coefficients, random rotation factor addresses and rotation factors;

[0011] An address generation unit, used for calculating and generating the storage RAM address of the rotation factor involved in the operation and the read address required by the coefficient storage unit;

[0012] The coefficient transposition unit realizes the coefficient reading that satisfies the index distance between all NTT stages;

[0013] The calculation unit is used to obtain the operation mode of the polynomial, and perform polynomial operation according to the operation mode, rotation factors and coefficients to obtain the operation result corresponding to the polynomial, and write the operation result back to the coefficient memory.

[0014] Preferably, the output end of the controller is electrically connected to the storage unit, the input end of the storage unit is electrically connected to the output end of the coefficient transposition unit, the output end of the storage unit is electrically connected to the input end of the coefficient transposition unit, the output end of the storage unit is electrically connected to the input of the address generation unit, the input end of the storage unit is electrically connected to the output end of the address generation unit, the output end of the address generation unit is electrically connected to the input end of the rotation factor storage RAM, the rotation factor storage RAM and the rotation factor preprocessing unit are communicatively connected to each other, the rotation factor preprocessing unit and the calculation unit are communicatively connected to each other, the calculation unit and the coefficient transposition unit are communicatively connected to each other, and the storage unit and the coefficient transposition unit are communicatively connected to each other.

[0015] Preferably, the computing unit includes a low-latency radix-4 CT butterfly unit and a low-latency radix-4 GS butterfly unit; the output end of the low-latency radix-4 CT butterfly unit is electrically connected to the input end of the low-latency radix-4 GS butterfly unit, the low-latency radix-4 CT butterfly unit includes 6 first modular multipliers, 4 first modular adders and 4 first modular subtractors, and the low-latency radix-4 GS butterfly unit includes 6 second modular multipliers, 4 second modular adders and 4 second modular subtractors.

[0016] Preferably, the low-latency radix-4 CT butterfly unit is used to divide the polynomial into 4 sub-formulas and perform operations on the 4 sub-formulas one by one.

[0017] Preferably, the low-latency radix-4 CT butterfly unit includes 4 input ends and 4 output ends, the low-latency radix-4 GS butterfly unit includes 4 input ends and 4 output ends, and the 4 output ends of the low-latency radix-4 CT butterfly unit are electrically connected to the 4 input ends of the low-latency radix-4 GS butterfly unit in a one-to-one correspondence.

[0018] Preferably, in the address generation unit, the read address of the rotation factor RAM is calculated by adding and subtracting the rotation factor address, the previous round random rotation factor address and the current round random rotation factor address.

[0019] Preferably, the operation mode includes NTT operation and INTT operation; the control unit is also used to generate an operation control signal, and the operation control signal determines the current operation mode of the calculation unit.

[0020] Preferably, the coefficient transposition unit is composed of a 4×4 array consisting of 16 registers and 9 MUXs.

[0021] In the present invention, the proposed side-channel attack-resistant NTT circuit for lattice-based cryptographic algorithms extends the radix-2Cooley-Tukey (CT) butterfly unit structure with random rotation factors as masks to low-latency radix-4CT butterfly units. When masking the low-latency radix-4 CT / GS butterfly units, the increase in modular multiplication resources is reduced, thereby achieving a significant reduction in resource consumption while maintaining high security. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the hardware structure of the polynomial operation component of the NTT circuit for the lattice cryptographic algorithm against side channel attacks of the present invention;

[0023] Figure 2 The circuit structure diagram of the existing low-latency base-4 CT butterfly unit is shown below;

[0024] Figure 3 The circuit structure diagram of the existing low-latency base-4 GS butterfly unit is shown below;

[0025] Figure 4 This is the structure diagram of the low-delay base-4MDISO_BF CT of the NTT circuit for the lattice cryptographic algorithm against side channel attacks of the present invention;

[0026] Figure 5 The low-delay base-4MDISO_BFGS structure diagram of the NTT circuit for the lattice cryptographic algorithm of the present invention against side channel attacks;

[0027] Figure 6 It is a transposition unit movement sequence diagram of the NTT circuit in the NTT mode for the lattice cryptographic algorithm against side channel attacks of the present invention;

[0028] Figure 7 The present invention is a transposition unit movement sequence diagram in the INTT mode of the NTT circuit that resists side channel attacks for the lattice cryptographic algorithm. DETAILED DESCRIPTION

[0029] Reference Figure 1-7 The present invention proposes a side-channel attack-resistant NTT circuit for lattice cryptographic algorithms.

[0030] include:

[0031] The control unit mainly controls the enabling of the underlying components in the structure and the data flow between modules.

[0032] In this embodiment, the operation mode includes NTT operation and INTT operation; the control unit is also used to generate an operation control signal, and the operation control signal determines the current operation mode of the calculation unit.

[0033] Specifically, the control unit mainly controls the enabling of the underlying components in the structure and the data flow between the modules. It contains a state machine inside, which can complete the state control of the complete polynomial operation. The mode control signal Mode is used as the chip select signal of the selector to realize different data flows under different polynomial operation modes. The RAM chip select signal can control the connection between the RAM output and the coefficient transposition unit and the reconfigurable low-latency base-4CT / GS unit. The control unit also controls the enabling and read-write control of the RAM unit.

[0034] A storage unit is used to store coefficients, random rotation factor addresses, and rotation factors.

[0035] The address generation unit is used to calculate and generate the storage RAM address of the rotation factor involved in the operation and the read address required by the coefficient storage unit.

[0036] Specifically, when performing polynomial operations, the address generation unit is used to generate the read addresses required by the rotation factor storage RAM and the polynomial coefficient storage RAM, wherein the rotation factor storage RAM read address is calculated by adding and subtracting the butterfly algorithm rotation factor address, the previous round random rotation factor address and the current round random rotation factor address. Since the polynomial operation component contains two modes: NTT and INTT, it is crucial to effectively complete the reading of coefficients in different modes. There are two methods for address generation: dynamic generation and static generation. Static generation requires writing the reading rules to the ROM in advance for storage, and then directly reading the ROM in sequence during operation to obtain the address, and reading the coefficients in the RAM with the address. This paper adopts the dynamic generation method to generate the RAM read address in real time. Compared with the static generation method, the dynamic generation method avoids the use of additional ROM resources. In addition, in different modes, the address distribution has obvious rules, and a simple hardware circuit can be used to implement this function. In this paper, the rotation factor RAM read address generation method, the rotation factor address is calculated by adding and subtracting the butterfly algorithm rotation factor address, the previous round random rotation factor address and the current round random rotation factor address. The address of the previous round of random rotation factors is stored in the BRAM together with the coefficient data through the coefficient transposition unit.

[0037] In this embodiment, the read address of the rotation factor RAM in the address generation unit is calculated by adding and subtracting the rotation factor address, the previous round random rotation factor address and the current round random rotation factor address.

[0038] The calculation unit is used to obtain the operation mode of the polynomial, and perform polynomial operation according to the operation mode, rotation factors and coefficients to obtain the operation result corresponding to the polynomial, and write the operation result back to the coefficient memory.

[0039] In this embodiment, the computing unit includes a low-latency radix-4 CT butterfly unit and a low-latency radix-4 GS butterfly unit; the output end of the low-latency radix-4 CT butterfly unit is electrically connected to the input end of the low-latency radix-4 GS butterfly unit, the low-latency radix-4 CT butterfly unit includes 6 first modular multipliers, 4 first modular adders and 4 first modular subtractors, and the low-latency radix-4 GS butterfly unit includes 6 second modular multipliers, 4 second modular adders and 4 second modular subtractors.

[0040] In this embodiment, the low-latency radix-4 CT butterfly unit is used to divide the polynomial into 4 sub-formulas and perform operations on the 4 sub-formulas one by one.

[0041] In this embodiment, the low-latency radix-4 CT butterfly unit includes 4 input terminals and 4 output terminals, the low-latency radix-4 GS butterfly unit includes 4 input terminals and 4 output terminals, and the 4 output terminals of the low-latency radix-4 CT butterfly unit are electrically connected to the 4 input terminals of the low-latency radix-4 GS butterfly unit in a one-to-one correspondence.

[0042] In this embodiment, the butterfly unit of NTT for the lattice cryptographic algorithm against side channel attacks:

[0043] The NWC calculation process is as follows

[0044]

[0045] Based on the above formula, the preprocessing and NTT are written together, and the rotation factor is used The properties of

[0046]

[0047] According to the index partition, the sum of the above formula is 4 residual congruence groups of length , and the rotation factor is used The elimination properties Simplify, use variable X 0 , X 1 , X 2 , X 3 Replace Using the periodicity of the rotation factors as well as The polynomial can be divided into four parts for representation, as shown in the following formula, where i = 0, 1, ..., N / 4-1;

[0048]

[0049] If the above formula is decomposed into two-level operations, the number of modular multiplication, modular addition and modular subtraction operations can be effectively reduced. However, the two-layer modular multiplication unit means that the number of pipeline stages required is doubled, which may cause memory conflict problems when performing NTT transformation. The root cause of memory conflict is analyzed in detail and the following are given: The limit is expressed as the cardinality of NTT. We seek a decomposition solution with higher parallelism for modular multiplication from the perspective of reducing the number of pipeline stages, as shown in the following formula:

[0050]

[0051] Figure 2 The circuit structure corresponding to the above equation is shown. Compared with the low computational complexity radix-4 CT butterfly unit, this structure only adds one modular multiplication element, but can realize the parallel operation of all modular multiplication operations. In the case of large multiplication delay, the critical delay path is significantly improved, while avoiding the problem of doubling the depth of the modular multiplication pipeline. We call it Figure 2 The structure is a low-latency radix-4CT butterfly unit. The low-computational complexity radix-4 GS butterfly unit is optimized similarly, which we call Figure 3 The structure is a low-latency base-4 GS butterfly unit.

[0052] According to the MDISO_BF principle, the first-level operation of the above formula is masked, where the input is X 0 , X 1 , X 2 , X 3 The random rotation factor Masked X′ 0 , X′ 1 , X′ 2 , X′ 3 , the first stage output Y 0 , Y 1 By the new random rotation factor Mask, Y 2 , Y 3 By the new random rotation factor Mask. Then, use a random rotation factor and The second-level operation of the above formula is blinded to obtain the following formula:

[0053]

[0054] From the above formula, we can see that the low-latency radix-4 CT butterfly unit after masking requires a total of 12 modular multiplication operation resources, and the requirement for random numbers is 4. Compared with the low-latency radix-4 CT butterfly structure, the radix-4 MDISO_BF adds 7 modular multiplication operation resources, which is also a non-negligible overhead in hardware implementation. In order to further compress the number of modular multiplication operation resources, assume that the output of the first-level operation is masked by the same random rotation factor, and the input of the second-level operation is masked by the same random rotation factor, that is, r 4 =r 5 =r 6 =r 7 , the modular multiplication operation of the second level can be directly avoided, and the above formula can be simplified to:

[0055]

[0056] The requirement for random numbers in the above formula is reduced to 1, and the modular multiplication operation resources are reduced to 6. Compared with the low-latency base-4CT butterfly unit, only one modular multiplication operation resource is added, and the modular multiplication operation can also be implemented in parallel without affecting the overall hardware timing. The circuit structure is as follows Figure 4 The mask of the low-latency radix-4 GS butterfly unit is similar, which we call Figure 5 The structure is a low-latency base-4 MDISO_BF GS structure.

[0057] The coefficient transposition unit realizes the coefficient reading that satisfies the index distance between all NTT stages.

[0058] In this embodiment, the coefficient transposition unit is composed of a 4×4 array of 16 registers and 9 MUXs.

[0059] In this embodiment, a single-address multi-coefficient storage method is used for coefficient storage, so it is impossible to read four coefficients that meet the NTT index distance in parallel within a single clock cycle like multi-Bank storage. Instead, the coefficients that meet the NTT index distance are stored at different addresses of the RAM. Therefore, 4 clock cycles are required to complete the reading of the 4×4 coefficient matrix. Each column of the coefficient matrix serves as the input of the NTT, and the remaining data needs to be synchronized using an additional linear shift register to ensure that the remaining data is not lost. In the case where NTT adopts a pipeline design, the above reading method may cause discontinuity of the pipeline input data, thereby affecting the pipeline from being 100% utilized, resulting in increased computing time costs and decreased overall system performance. Therefore, achieving coefficient reading that meets the index distance between all NTT stages is a design difficulty.

[0060] The coefficient transposition unit is responsible for synchronizing and transposing the 4×4 matrix composed of intermediate data. The circuit structure is as follows Figure 6As shown. The internal circuit of the coefficient transposition unit consists of a 4×4 array of 16 registers and 9 MUXs. The red arrows and blue arrows in the figure show two data movement modes. The two movement modes use 4 clocks as one cycle and are interleaved with each other. Data can be stored in rows (columns) and read in columns (rows), completing the synchronization and reordering of input data in the form of a pipeline. In addition, the coefficient transposition operation must be performed before the data enters the butterfly unit in NTT and after exiting the butterfly unit in INTT. The coefficient transposition unit in this paper supports both of the above situations. Figure 6 and Figure 7 The data flow of the improved coefficient transposition unit when performing data reordering in the first 8 clock cycles of the first stage in NTT / INTT mode is given.

[0061] Specifically, the hardware implementation resource consumption of the current NTT side channel mask protection solution is more than 2 times, while this design consumes 1.56 times the resources of the mask while ensuring security, which is much less than other design solutions.

[0062] In this embodiment, the output end of the controller is electrically connected to the storage unit, the input end of the storage unit is electrically connected to the output end of the coefficient transposition unit, the output end of the storage unit is electrically connected to the input end of the coefficient transposition unit, the output end of the storage unit is electrically connected to the input of the address generation unit, the input end of the storage unit is electrically connected to the output end of the address generation unit, the output end of the address generation unit is electrically connected to the input end of the rotation factor storage RAM, the rotation factor storage RAM and the rotation factor preprocessing unit are communicatively connected to each other, the rotation factor preprocessing unit and the calculation unit are communicatively connected to each other, the calculation unit and the coefficient transposition unit are communicatively connected to each other, and the storage unit and the coefficient transposition unit are communicatively connected to each other.

[0063] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A side-channel attack-resistant NTT circuit for a lattice cryptographic algorithm, characterized in that: include: The control unit mainly controls the enabling of the underlying components in the structure and the data flow between modules; A storage unit for storing coefficients, random rotation factor addresses and rotation factors; An address generation unit, used for calculating and generating the storage RAM address of the rotation factor involved in the operation and the read address required by the coefficient storage unit; The coefficient transposition unit realizes the coefficient reading that satisfies the index distance between all NTT stages; The calculation unit is used to obtain the operation mode of the polynomial, and perform polynomial operation according to the operation mode, rotation factors and coefficients to obtain the operation result corresponding to the polynomial, and write the operation result back to the coefficient memory.

2. The side-channel attack-resistant NTT circuit for the lattice cryptographic algorithm according to claim 1, characterized in that: The output end of the controller is electrically connected to the storage unit, the input end of the storage unit is electrically connected to the output end of the coefficient transposition unit, the output end of the storage unit is electrically connected to the input end of the coefficient transposition unit, the output end of the storage unit is electrically connected to the input of the address generation unit, the input end of the storage unit is electrically connected to the output end of the address generation unit, the output end of the address generation unit is electrically connected to the input end of the rotation factor storage RAM, the rotation factor storage RAM and the rotation factor preprocessing unit are communicatively connected to each other, the rotation factor preprocessing unit and the calculation unit are communicatively connected to each other, the calculation unit and the coefficient transposition unit are communicatively connected to each other, and the storage unit and the coefficient transposition unit are communicatively connected to each other.

3. The side-channel attack-resistant NTT circuit for the lattice cryptographic algorithm according to claim 1, characterized in that: The computing unit includes a low-latency base-4CT butterfly unit and a low-latency base-4GS butterfly unit; the output end of the low-latency base-4CT butterfly unit is electrically connected to the input end of the low-latency base-4GS butterfly unit, the low-latency base-4CT butterfly unit includes 6 first modular multipliers, 4 first modular adders and 4 first modular subtractors, and the low-latency base-4GS butterfly unit includes 6 second modular multipliers, 4 second modular adders and 4 second modular subtractors.

4. The side-channel attack-resistant NTT circuit for the lattice cryptographic algorithm according to claim 3, characterized in that: The low-latency radix-4CT butterfly unit is used to divide the polynomial into 4 sub-formulas and perform operations on the 4 sub-formulas one by one.

5. According to the side-channel attack-resistant NTT circuit for the lattice-based cryptographic algorithm of claim 4, the low-delay base-4CT butterfly unit includes 4 input terminals and 4 output terminals, the low-delay base-4GS butterfly unit includes 4 input terminals and 4 output terminals, and the 4 output terminals of the low-delay base-4CT butterfly unit are electrically connected to the 4 input terminals of the low-delay base-4GS butterfly unit in a one-to-one correspondence.

6. The side-channel attack-resistant NTT circuit for the lattice cryptographic algorithm according to claim 1, characterized in that: In the address generation unit, the read address of the rotation factor RAM is calculated by adding and subtracting the rotation factor address, the previous round random rotation factor address and the current round random rotation factor address.

7. The side-channel attack-resistant NTT circuit for the lattice cryptographic algorithm according to claim 1, characterized in that: The operation mode includes NTT operation and INTT operation; the control unit is also used to generate an operation control signal, and the operation control signal determines the current operation mode of the calculation unit.

8. The side-channel attack-resistant NTT circuit for the lattice cryptographic algorithm according to claim 1, characterized in that: The coefficient transposition unit is composed of a 4×4 array of 16 registers and 9 MUXs.

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