A data transmission method and device for high-speed time-triggered bus

Abstract

The present invention discloses a data transmission method and device for a high-speed time-triggered bus, which relates to the technical field of communication networks. The method comprises: a TTP protocol layer encapsulates data according to a pre-configured data frame format to obtain parallel data, and sends the parallel data to a coding and decoding layer; the coding and decoding layer performs coding processing and parallel-to-serial conversion processing on the parallel data sent by the TTP protocol layer to obtain serial data, and sends the serial data to a physical layer for transmission; the physical layer uploads the serial data to the coding and decoding layer to perform sampling of multiple phase points to obtain multi-channel sampling data; the coding and decoding layer performs decoding processing and serial-to-parallel conversion processing on the multi-channel sampling data to obtain multi-channel parallel data, and uploads the multi-channel parallel data to the TTP protocol layer; wherein one channel of sampling data corresponds to one channel of parallel data; the TTP protocol layer performs data verification on each channel of parallel data, and after the verification passes, the corresponding channel of parallel data transmission is correct.

Description

Technical Field

[0001] The present invention relates to the technical field of communication networks, and more particularly to a data transmission method and device for a high-speed time-triggered bus. Background Art

[0002] Aircraft management systems are a key component of modern aircraft. With the increasing functionality of onboard systems, aircraft management systems are gradually transitioning from a centralized to a distributed architecture. In a distributed architecture, subsystems communicate with each other via a network or bus, placing higher demands on the real-time, deterministic, and secure nature of network or bus communications.

[0003] The Time Triggered Protocol (TTP), based on the Time Triggered Architecture (TTA), has been proposed. This protocol achieves safety-critical and hard real-time characteristics through time-division multiplexing, time synchronization, member confirmation, fault detection, and redundancy. TTP has been widely adopted in a variety of aerospace systems, such as the digital engine control systems of the F-16 and M-346, the cabin pressure control system of the A380, and the environmental control system of the Boeing 787.

[0004] The current 5–25 Mbps transmission rate supported by TTP is no longer sufficient for high-performance sensors. When using MLVDS chips for high-speed data transmission, the following issues may arise, affecting the correct transmission and reception of data: 1. During high-speed data transmission, frequency deviations in the crystal oscillators between different nodes can cause irregular phase shifts between nodes. Interference from the transmission medium can also cause signal attenuation or distortion, ultimately affecting accurate data reception. 2. The current TTP coding layer primarily uses Manchester encoding, which has an actual data transmission rate of only half the link rate. To achieve data transmission rates of 100 Mbps or higher, the required clock frequency may exceed the upper limit of the MLVDS chip's clock frequency. 3. Currently, the commonly used data sampling methods include clock extraction, time domain oversampling, and spatial oversampling. For clock extraction, due to the non-ideal node frequency, frequency deviation and drift are present. Therefore, the clock received by data frames aligned with the preamble will drift after a certain period of time. For the time domain oversampling technology, if 125Mhz data is oversampled 5 times in the time domain, the required frequency will reach 625Mhz, which is beyond the FPGA's capability. Summary of the Invention

[0005] The purpose of the present invention is to provide a data transmission method and device for a high-speed time-triggered bus, which solves the problems of transmission rate and accuracy in the data transmission process in the related art.

[0006] A first aspect of the present invention provides a data transmission method for a high-speed time-triggered bus, which is applied to a data transmission architecture, wherein the data transmission architecture includes a TTP protocol layer, a codec layer, and a physical layer, and the method includes:

[0007] The TTP protocol layer encapsulates the data according to the pre-configured data frame format, obtains parallel data, and sends the parallel data to the encoding and decoding layer;

[0008] The codec layer encodes and serializes the parallel data sent by the TTP protocol layer to obtain serial data, and sends the serial data to the physical layer for transmission;

[0009] The physical layer uploads the serial data to the codec layer for sampling at multiple phase points to obtain multiple channels of sampled data; wherein one phase point corresponds to one channel of sampled data;

[0010] The encoding and decoding layer performs decoding and serial-to-parallel conversion on the multiple sampling data to obtain multiple parallel data, and uploads the multiple parallel data to the TTP protocol layer; wherein one channel of sampling data corresponds to one channel of parallel data;

[0011] The TTP protocol layer performs data verification on each channel of parallel data. When the verification passes, the corresponding channel of parallel data is transmitted correctly.

[0012] In one implementation, the data frame format includes a preamble, a frame header, a TTP frame, and a frame trailer.

[0013] In one implementation, the codec layer performs encoding and parallel-to-serial conversion on the parallel data sent by the TTP protocol layer to obtain serial data, specifically:

[0014] Encoding the parallel data using a first encoding method to obtain first encoded data;

[0015] Performing parallel-to-serial conversion on the first coded data to obtain serial data corresponding to the first coded data;

[0016] The serial data corresponding to the first coded data is coded using a second coding method to obtain serial data.

[0017] In one implementation, the first encoding method is 4B5B encoding, and the second encoding method is NRZI encoding.

[0018] In one implementation, the serial data is uploaded to the codec layer for sampling at multiple phase points to obtain multi-channel sampling data, specifically:

[0019] Configure a first sampling clock signal without phase offset and a second sampling clock signal with a 90-degree phase offset;

[0020] Adjusting the number of phase offsets of the serial data according to the number of phase points, and adjusting the phase offset value during the oversampling process according to the number of phase offsets and the number of phase points;

[0021] Phase-shifting the serial data based on the phase offset value to obtain phase-shifted data;

[0022] The serial data and the phase-shifted data are sampled using the rising edge and the falling edge of the first sampling clock signal and the second sampling clock signal to obtain multi-channel sampling data.

[0023] In one implementation, the expression for adjusting the number of phase offsets of serial data is: Where N represents the number of phase shifts, and k represents the number of phase points;

[0024] The expression for adjusting the phase offset value during the oversampling process is:

[0025] In one implementation, the codec layer performs decoding and serial-to-parallel conversion on the multi-channel sampled data to obtain multi-channel parallel data, specifically:

[0026] Decoding the multiple channels of sampled data using a second decoding method to obtain multiple channels of first decoded data;

[0027] Performing serial-to-parallel conversion on the multiple channels of first decoded data to obtain serial data corresponding to the multiple channels of first decoded data;

[0028] The first decoding method is used to decode the serial data corresponding to the multiple channels of first decoded data to obtain multiple channels of parallel data.

[0029] In one implementation, the first decoding method is 4B5B decoding, and the second decoding method is NRZI decoding.

[0030] In one implementation, the data verification method is CRC verification.

[0031] A second aspect of the present invention provides a data transmission device for a high-speed time-triggered bus, which is applied to a data transmission architecture. The data transmission architecture includes a TTP protocol layer, a codec layer, and a physical layer. The device includes:

[0032] A first data processing module is used for the TTP protocol layer to encapsulate data according to a pre-configured data frame format, obtain parallel data, and send the parallel data to the encoding and decoding layer;

[0033] The second data processing module is used for the codec layer to encode and serialize the parallel data sent by the TTP protocol layer to obtain serial data, and send the serial data to the physical layer for transmission;

[0034] A third data processing module is configured to cause the physical layer to upload the serial data to the codec layer for sampling at multiple phase points to obtain multiple channels of sampled data; wherein one phase point corresponds to one channel of sampled data;

[0035] A fourth data processing module is configured to perform decoding and serial-to-parallel conversion on the multi-channel sampling data at the encoding and decoding layer to obtain multi-channel parallel data, and upload the multi-channel parallel data to the TTP protocol layer; wherein one channel of sampling data corresponds to one channel of parallel data;

[0036] The fifth data processing module is used for the TTP protocol layer to perform data verification on each channel of parallel data. When the verification passes, the corresponding channel of parallel data is transmitted correctly.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] First, the present invention introduces coding technologies with higher link rate utilization, namely 4B5B and NRZI coding, in the encoding process, which increases data transmission rates and effectively reduces bandwidth waste. Second, it uses multi-phase point sampling technology and cross-layer redundancy checking to reduce the impact of frequency and phase offsets between nodes on node synchronization. This increases the TTP bus data rate from the traditional 5-25Mbps to 100Mbps, meeting the demand for high-speed data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0040] Figure 1 A schematic diagram of the structure of a data transmission architecture provided by an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of a data frame format provided by an embodiment of the present invention;

[0042] Figure 3 A flow chart of a data transmission method for a high-speed time-triggered bus provided by an embodiment of the present invention;

[0043] Figure 4 A sampling schematic diagram of eight-phase point sampling provided by an embodiment of the present invention;

[0044] Figure 5A principle block diagram of a data transmission device for a high-speed time-triggered bus provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0046] It should be noted that the terms "include" or "may include" used in various embodiments of the present application indicate the presence of the claimed function, operation or element, and do not limit the addition of one or more functions, operations or elements. In addition, as used in various embodiments of the present application, the terms "include", "have" and their cognates are only intended to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0047] In various embodiments of the present application, the expression "or" or "at least one of B or / and C" includes any or all combinations of the words listed simultaneously. For example, the expression "B or C" or "at least one of B or / and C" may include B, may include C, or may include both B and C.

[0048] It should be understood that terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0049] Please refer to Figure 3 , Figure 3 A flow chart of a data transmission method for a high-speed time-triggered bus provided by an embodiment of the present invention is provided. The method is applied to a data transmission architecture. The composition of the data transmission architecture is shown in FIG. Figure 1 , Figure 1This is a schematic diagram of the data transmission architecture provided in an embodiment of the present invention. The data transmission architecture includes a TTP protocol layer, a codec layer, and a physical layer, and is composed of the following components: a sampling module, an encoding module, and a cross-layer redundancy check module. The cross-layer redundancy check module further includes a decoding module and a CRC check module. The method includes the following processes: 1. Transmitting process: From the TTP protocol layer to the physical layer, passing through the encoding module; 2. Receiving process: From the physical layer to the TTP protocol layer, passing through the sampling module, decoding module, and cross-layer redundancy check module.

[0050] For the sampling module, encoding module, cross-layer redundancy check module, ① Sampling module, the sampling technology of this module is specifically multi-phase oversampling technology, which is a technology used to improve data sampling accuracy. Its main function is to sample the input data signal with no phase shift and phase shift through the rising and falling edges of the sampling clock with no phase shift and phase shift.

[0051] ②The specific implementation of the encoding module is as follows:

[0052] 1.4B5B encoding: 4B5B encoding converts every four bits of data into five bits and ensures that every four bits of data has at least one 1-bit change, eliminating long periods of 0 or 1.

[0053] 2. Serial-to-parallel conversion: Convert parallel data into serial data bit by bit.

[0054] 3. NRZI encoding: NRZI code is non-return-to-zero inversion code, which represents logical values ​​by whether the level is flipped. In the present invention, logic "1" is represented by level flipping, while logic "0" remains unchanged.

[0055] The decoding module is implemented as follows:

[0056] 1. NRZI decoding: By detecting the change of level inversion, the received NRZI encoded data is correctly decoded and restored to the original bit data.

[0057] 2. Serial-to-parallel conversion: The data after NRZI decoding is still serial, so it needs to be converted into parallel data through serial-to-parallel conversion.

[0058] 3.4B5B Decoding: The 4B5B decoding module reversely decodes the serial-to-parallel converted data, restoring it from 5 bits to 4 bits.

[0059] ③ Cross-layer redundancy check module. The cross-layer redundancy check module is divided into two parts: the decoding module and the CRC check module. The following explains the work flow of these two parts respectively.

[0060] The encoding module is specifically implemented as follows:

[0061] 1. NRZI decoding: After the multi-channel sampled data reaches the decoding module, the received NRZI encoded data is correctly decoded and restored to the original bit data by detecting the change of level inversion.

[0062] 2. Serial-to-parallel conversion: The data after NRZI decoding is still serial, so it needs to be converted into parallel data through serial-to-parallel conversion.

[0063] 3.4B5B Decoding: The 4B5B decoding module reverse-decodes the serial-to-parallel converted data, restoring it from 5 bits to 4 bits, and uploads the multiplexed data to the CRC check module of the protocol layer.

[0064] The CRC check module is implemented as follows: After multiple data streams arrive at the cross-layer redundancy check module, the parallel data undergoes CRC checking and data FIFO buffering. Finally, among the multiple data streams with correct CRC results, the data stream with the earliest phase is preferentially output from the FIFO. In other words, the TTP protocol layer performs CRC checking on the 4B data received from the codec layer, parses it, performs CRC checking on it, eliminates data with CRC errors, and finally selects and outputs reliable data with correct CRC results.

[0065] like Figure 3 As shown, the method includes: S301, the TTP protocol layer encapsulates data according to a pre-configured data frame format, obtains parallel data, and sends the parallel data to the encoding and decoding layer.

[0066] In this embodiment, the data frame format is as follows: Figure 2 As shown in the figure, the data frame format includes a preamble, a frame header, a TTP frame, and a frame trailer. The preamble consists of 30 bits of "10" data, the frame header consists of 60 bits of "11000_10001", and TTP frames can be I, X, or N frames, with the user selecting the frame type. The frame trailer consists of "01101". It is understood that encapsulation is common knowledge in the art and will not be further described in this embodiment. The TTP protocol layer encapsulates 4B of parallel data.

[0067] S302: The codec layer encodes and performs parallel-to-serial conversion on the parallel data sent by the TTP protocol layer to obtain serial data, and sends the serial data to the physical layer for transmission.

[0068] In this embodiment, the encoding processing and parallel-to-serial conversion processing are specifically as follows: using a first encoding method to encode parallel data to obtain first encoded data; performing parallel-to-serial conversion on the first encoded data to obtain serial data corresponding to the first encoded data; and using a second encoding method to encode the serial data corresponding to the first encoded data to obtain serial data.

[0069] Specifically, the first encoding method is 4B5B encoding, and the second encoding method is NRZI encoding. It should be noted that 4B5B encoding encodes 4B parallel data into 5B data, and the parallel-to-serial conversion process is a conversion process performed on the 5B data, and then NRZI encoding is performed.

[0070] S303 , the physical layer uploads the serial data to the codec layer for sampling at multiple phase points to obtain multiple channels of sampled data; wherein one phase point corresponds to one channel of sampled data.

[0071] In this embodiment, the way in which the physical layer receives and sends data is achieved through corresponding time slot conditions. This is common knowledge in the technical field and will not be described in detail in this embodiment.

[0072] The physical layers of other nodes in the receiving state upload the serial data to the codec layer for sampling at multiple phase points to obtain multiple channels of sampled data; one phase point corresponds to one channel of sampled data.

[0073] The multiple phase point sampling technology is a technology used to improve data sampling accuracy. Its main function is to sample serial data with or without phase shift by using the rising and falling edges of the sampling clock with or without phase shift.

[0074] The sampling process is as follows: configuring a first sampling clock signal without phase offset and a second sampling clock signal with a 90-degree phase offset; adjusting the number of phase offsets of serial data according to the number of phase points, and adjusting the phase offset value in the oversampling process according to the number of phase offsets and the number of phase points; phase-shifting the serial data based on the phase offset value to obtain phase-shifted data; and sampling the serial data and phase-shifted data using the rising and falling edges of the first sampling clock signal and the second sampling clock signal to obtain multi-channel sampled data.

[0075] Specifically, step 1: the sampling clock selects a zero-offset clock and a 90°-offset clock, ie, a first sampling clock signal and a second sampling clock signal.

[0076] Step 2: Adjust the number of phase points, k, as needed, so that the interval between each phase point is 2π / k. Increasing k allows for more precise signal sampling, capturing subtler phase changes and achieving higher sampling accuracy. However, increasing the number of sampling phases also increases chip hardware resources.

[0077] Step 3: Adjust the phase shift times N and the phase shift value θ of the data signal according to the number of phase points k. N , the calculation formula is as follows:

[0078] Step 4: Use the rising and falling edges of the offset-free sampling clock and the 90° phase-shifted sampling clock to sample the offset-free and phase-shifted hand data. The phases of the obtained k-channel sampling data are: 0°, 2π / k, 4π / k, ..., (k-1)*2π / k; where k is equal to 2 to the power of m, and m is greater than or equal to 2.

[0079] The following takes the sampling of eight phase points as an example, that is, k is 8, then the number of phase shifts N of the data signal is 1, and the phase shift values ​​are 0° and 45° respectively. Figure 4 As shown, the phases of the k-channel sampling data are: 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° respectively;

[0080] S304, the codec layer performs decoding and serial-to-parallel conversion on the multiple sampling data to obtain multiple parallel data, and uploads the multiple parallel data to the TTP protocol layer; wherein one channel of sampling data corresponds to one channel of parallel data.

[0081] In this embodiment, the decoding process and serial-to-parallel conversion process specifically include: decoding multiple channels of sampled data using a second decoding method to obtain multiple channels of first decoded data; performing serial-to-parallel conversion on the multiple channels of first decoded data to obtain serial data corresponding to the multiple channels of first decoded data; and decoding the serial data corresponding to the multiple channels of first decoded data using a first decoding method to obtain multiple channels of parallel data. The first decoding method is 4B5B decoding, and the second decoding method is NRZI decoding.

[0082] Specifically, encoding and decoding are in one-to-one correspondence, so this embodiment does not make redundant descriptions of the decoding process.

[0083] S305: The TTP protocol layer performs data verification on the multi-channel data. When the verification passes, the data transmission is completed.

[0084] In this embodiment, the data verification method is CRC verification. The specific process of CRC verification is common knowledge and will not be described in detail in this embodiment.

[0085] The following uses the example of two TTP bus nodes transmitting data using 254 bytes of random data as TTP frames under the condition that the chip's system clock is 125MHz to illustrate the detailed data transmission process of the codec layer when TTP nodes send and receive data.

[0086] The TTP protocol layer encapsulates data, which includes: a 30-bit preamble "10", a 60-bit SOF "11000_10001", 254 bytes of random data, and a 5-bit frame tail "01101". The protocol layer sends the encapsulated parallel data to the coding layer.

[0087] At the codec layer, the parallel data is first 4B5B encoded, and the data is encoded according to the 4B5B encoding table. For example, "1010" will be encoded as "01011" according to the 4B5B encoding table.

[0088] The data passes through the parallel-to-serial conversion module, and the parallel data is converted into serial data.

[0089] The serial data is counted. When the count reaches 90, that is, the TTP frame is reached, the TTP frame is NRZI encoded. The initial value of the NRZI code is specified to be 1. Data "1" will cause the level to flip, and "0" will keep the level unchanged. The data is flipped according to the NRZI encoding rules.

[0090] The NRZI-encoded serial data is sent to the receiving end of node 2 through the physical layer of node 1.

[0091] At the receiving end of node 2, the data first enters the eight-phase oversampling module, which samples the input data signal with no offset and 45° phase shift by the rising and falling edges of the 125MHz clock with no offset and 90° phase shift, obtaining eight channels of sampled data with different phases.

[0092] The eight-channel sampled data is NRZI decoded, and the level in the TTP frame is flipped and restored to the previous data through the reverse operation.

[0093] The data then enters the serial-to-parallel conversion module, which converts the serial data into parallel data. The data continues to flow through the 4B5B decoding module and is finally restored to the original 4B data.

[0094] After CRC verification, the data is checked for redundancy. After the CRC verification passes, the data is uploaded to the TTP protocol layer for subsequent processing.

[0095] Please refer to Figure 5 , Figure 5 A block diagram of a data transmission device for a high-speed time-triggered bus provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the device is applied to a data transmission architecture, which includes a TTP protocol layer, a codec layer, and a physical layer. The device includes:

[0096] The first data processing module 510 is used for the TTP protocol layer to encapsulate data according to a pre-configured data frame format, obtain parallel data, and send the parallel data to the codec layer;

[0097] The second data processing module 520 is used for the codec layer to encode and convert the parallel data sent by the TTP protocol layer to obtain serial data, and send the serial data to the physical layer for transmission;

[0098] The third data processing module 530 is used for the physical layer to upload the serial data to the codec layer for sampling at multiple phase points to obtain multiple channels of sampled data; wherein one phase point corresponds to one channel of sampled data;

[0099] The fourth data processing module 540 is used for the codec layer to decode and serial-to-parallel convert the multiple channels of sampled data to obtain multiple channels of parallel data, and upload the multiple channels of parallel data to the TTP protocol layer; wherein one channel of sampled data corresponds to one channel of parallel data;

[0100] The fifth data processing module 550 is used for the TTP protocol layer to perform data verification on each channel of parallel data. If the verification passes, the corresponding channel of parallel data is transmitted correctly.

[0101] As can be seen, in the data transmission device for a high-speed time-triggered bus provided in this embodiment, first, the encoding portion introduces coding technologies that utilize the link rate more efficiently, namely 4B5B and NRZI encoding, which improves the data transmission rate and effectively reduces bandwidth waste. Second, the use of multi-phase point sampling technology and cross-layer redundancy check reduces the impact of frequency deviation and phase offset between nodes on node synchronization. This increases the TTP bus data rate from the traditional 5-25Mbps to 100Mbps, meeting the requirements of high-speed data transmission.

[0102] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A data transmission method for a high-speed time-triggered bus, characterized in that: Applied to a data transmission architecture, the data transmission architecture includes a TTP protocol layer, a codec layer, and a physical layer, the method includes: The TTP protocol layer encapsulates the data according to the pre-configured data frame format, obtains parallel data, and sends the parallel data to the encoding and decoding layer; The codec layer encodes and serializes the parallel data sent by the TTP protocol layer to obtain serial data, and sends the serial data to the physical layer for transmission; The physical layer uploads the serial data to the codec layer for sampling at multiple phase points to obtain multi-channel sampled data; wherein one phase point corresponds to one channel of sampled data; wherein, uploading the serial data to the codec layer for sampling at multiple phase points to obtain multi-channel sampled data specifically comprises: configuring a first sampling clock signal without phase offset and a second sampling clock signal with a 90-degree phase offset; adjusting the number of phase offsets of the serial data according to the number of phase points, and adjusting the phase offset value during the oversampling process according to the number of phase offsets and the number of phase points; phase-shifting the received serial data based on the phase offset value to obtain phase-shifted data; and sampling the serial data and the phase-shifted data using the rising and falling edges of the first sampling clock signal and the second sampling clock signal to obtain multi-channel sampled data; The encoding and decoding layer performs decoding and serial-to-parallel conversion on the multiple sampling data to obtain multiple parallel data, and uploads the multiple parallel data to the TTP protocol layer; wherein one channel of sampling data corresponds to one channel of parallel data; The TTP protocol layer performs data verification on each channel of parallel data. When the verification passes, the corresponding channel of parallel data is transmitted correctly.

2. The method according to claim 1, wherein The data frame format includes a preamble, a frame header, a TTP frame and a frame trailer.

3. The method according to claim 1, characterized in that The encoding and decoding layer performs encoding and parallel-to-serial conversion on the parallel data sent by the TTP protocol layer to obtain serial data, specifically: Encoding the parallel data using a first encoding method to obtain first encoded data; Performing parallel-to-serial conversion on the first coded data to obtain serial data corresponding to the first coded data; The serial data corresponding to the first coded data is coded using a second coding method to obtain serial data.

4. The method according to claim 3, characterized in that The first encoding method is 4B5B encoding, and the second encoding method is NRZI encoding.

5. The method according to claim 1, wherein The expression for adjusting the number of phase offsets of serial data is: ; Where N represents the number of phase shifts and k represents the number of phase points; The expression for adjusting the phase offset value during the oversampling process is: , n=0,1,…,N.

6. The method according to claim 1, characterized in that The codec layer performs decoding and serial-to-parallel conversion on the multi-channel sampled data to obtain multi-channel parallel data, specifically: Decoding the multiple channels of sampled data using a second decoding method to obtain multiple channels of first decoded data; Performing serial-to-parallel conversion on the multiple channels of first decoded data to obtain serial data corresponding to the multiple channels of first decoded data; The first decoding method is used to decode the serial data corresponding to the multiple channels of first decoded data to obtain multiple channels of parallel data.

7. The method according to claim 6, characterized in that The first decoding mode is 4B5B decoding, and the second decoding mode is NRZI decoding.

8. The method according to claim 1, characterized in that The data verification method is CRC verification.

9. A data transmission device for a high-speed time-triggered bus, characterized in that: Applied to a data transmission architecture, the data transmission architecture includes a TTP protocol layer, a codec layer, and a physical layer, and the device includes: A first data processing module is used for the TTP protocol layer to encapsulate data according to a pre-configured data frame format, obtain parallel data, and send the parallel data to the encoding and decoding layer; The second data processing module is used for the codec layer to encode and serialize the parallel data sent by the TTP protocol layer to obtain serial data, and send the serial data to the physical layer for transmission; a third data processing module, configured for the physical layer to upload the serial data to the codec layer for sampling at multiple phase points to obtain multiple channels of sampled data; wherein one phase point corresponds to one channel of sampled data; wherein uploading the serial data to the codec layer for sampling at multiple phase points to obtain multiple channels of sampled data comprises: configuring a first sampling clock signal without phase offset and a second sampling clock signal with a 90-degree phase offset; adjusting the number of phase offsets of the serial data according to the number of phase points, and adjusting the phase offset value during the oversampling process according to the number of phase offsets and the number of phase points; phase-shifting the received serial data based on the phase offset value to obtain phase-shifted data; and sampling the serial data and the phase-shifted data using the rising and falling edges of the first and second sampling clock signals to obtain the multiple channels of sampled data; A fourth data processing module is configured to perform decoding and serial-to-parallel conversion on the multi-channel sampling data at the encoding and decoding layer to obtain multi-channel parallel data, and upload the multi-channel parallel data to the TTP protocol layer; wherein one channel of sampling data corresponds to one channel of parallel data; The fifth data processing module is used for the TTP protocol layer to perform data verification on each channel of parallel data. When the verification passes, the corresponding channel of parallel data is transmitted correctly.

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