Communication system with pluggable optical modules

Abstract

The present application provides an apparatus comprising a housing mountable in a rack, and a vertically oriented switch card. The vertically oriented switch card includes one or more vertically oriented application specific integrated circuits (ASICs) mounted on the vertically oriented switch card. The switch card comprises a two-dimensional arrangement of a plurality of plug ports; each plug port is configured to receive a pluggable optical module. The switch card further comprises a two-dimensional arrangement of a plurality of channel inlets, each channel inlet being located adjacent to at least one plug port in the two-dimensional arrangement of the plurality of plug ports, each channel inlet receiving air and directing the received air towards an interior of the housing mountable in the rack.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 337,582, filed May 2, 2022, U.S. Provisional Patent Application No. 63 / 407,581, filed September 16, 2022, U.S. Provisional Patent Application No. 63 / 416,902, filed October 17, 2022, and U.S. Provisional Patent Application No. 63 / 431,610, filed December 9, 2022. The entire disclosures of the above applications are hereby incorporated herein by reference. Technical Field

[0003] This document describes a communication system with pluggable optical modules. Background Art

[0004] This section introduces various aspects that may be helpful in better understanding the present disclosure. Therefore, the statements in this section should be read in this light and should not be understood as an admission that what is included or not included in the prior art.

[0005] For example, a data center may include multiple switches mounted in a rack, each switch including one or more data processors mounted on a circuit board housed in a housing. Each switch includes one or more optical communication modules for converting input optical signals received from an optical fiber cable into input electrical signals provided to the one or more data processors, and converting output electrical signals from the one or more data processors into output optical signals output to the optical fiber cable. Summary of the Invention

[0006] In one overall aspect, an apparatus includes a housing capable of being mounted in a rack, and a vertically oriented switch card. The vertically oriented switch card includes one or more vertically oriented application-specific integrated circuits (ASICs) mounted on the vertically oriented switch card. The switch card also includes a two-dimensional arrangement of a plurality of plug ports. Each plug port is configured to receive a pluggable optical module. The switch card also includes a two-dimensional arrangement of a plurality of channel inlets. Each channel inlet is located adjacent to at least one plug port in the two-dimensional arrangement of the plurality of plug ports. Each channel inlet receives air and directs the received air toward an interior of the housing capable of being mounted in the rack.

[0007] Embodiments may include one or more of the following features. Each channel entrance may be connected to a channel that extends into the interior of the housing that can be mounted in a rack. The at least one channel may extend through a cutout of the vertically oriented switch card. The at least one channel may include one or more structures that are used for thermal regulation in the housing. The one or more structures may extend to the entire length of the channel. The one or more structures may extend to a portion of the length of the channel. Each channel may include one or more structures that are used for one or more structures for thermal regulation of the device. Each of the one or more structures may include a heat sink geometry. Two ASICs may be mounted in the housing. Each plug port may be configured to receive a small form factor pluggable. Each plug port may be configured to receive at least one of the following: (i) a small form factor pluggable, (ii) an eight-channel small form factor pluggable, or (iii) an ultra-small form factor pluggable (OSFP).

[0008] In some examples, each of the channels includes one or more structures configured to thermally regulate the device. The device may further include a structural support member configured to provide mechanical rigidity to facilitate insertion and removal of the pluggable optical module from the corresponding plug port. A structure in the one or more structures configured to thermally regulate the device may include a first end having a first width and a second end having a second width, the second width being less than the first width.

[0009] In one overall aspect, a device includes a housing capable of being mounted in a rack, and a vertically oriented switch card. The vertically oriented switch card includes one or more vertically oriented application-specific integrated circuits (ASICs) mounted on the vertically oriented switch card, a two-dimensional arrangement of multiple plug ports, each plug port being configured to receive a pluggable optical module. The vertically oriented switch card includes a two-dimensional arrangement of multiple channel inlets. Each channel inlet is located adjacent to at least one plug port in the two-dimensional arrangement of the multiple plug ports, each channel inlet receiving air and directing the received air toward an interior of the housing capable of being mounted in a rack. The vertically oriented switch card includes a first radiator air inlet located above the one or more vertically oriented application-specific integrated circuits, and a second radiator air inlet located below the one or more vertically oriented application-specific integrated circuits.

[0010] Embodiments may include one or more of the following features. The apparatus may include at least one of the following: (i) a first radiator air dam proximate to the first radiator air inlet and configured to receive air and direct the air toward the first radiator air inlet; or (ii) a second radiator air dam proximate to the second radiator air inlet and configured to receive air and direct the air toward the second radiator air inlet. The first radiator air inlet is configured to direct air to a first set of fins, with the first set of fins extending from the first radiator air inlet. The second radiator air inlet is configured to direct air to a second set of fins, with the second set of fins extending from the second radiator air inlet. The vertically oriented switch card includes a pair of connectors, each connector in the pair of connectors being configured to connect the vertically oriented switch card to a horizontal backside line card. The vertically oriented switch card includes an input / output module coupled to one or both connectors in the pair of connectors. In some examples, at least one channel inlet in the two-dimensional arrangement of the plurality of channel inlets includes a first end of the at least one channel inlet having a first width and a second end of the at least one channel inlet having a second width, the first end being positioned adjacent to the at least one plug port and the second end being located within the interior of the housing, the second width being greater than the first width.

[0011] Particular embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages: The data processing system has high power efficiency, low construction cost, low operation cost, and high flexibility in reconfiguring optical network connections.

[0012] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the invention will be apparent from the description, drawings, and claims.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by one of ordinary skill in the art to which this invention belongs. In the event of a conflict with a patent application or patent application publication incorporated herein by reference, the present specification, including definitions, will control. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to common practice, the various features of the drawings are not drawn to scale. The dimensions of the various features may be arbitrarily expanded or reduced for clarity.

[0015] Figure 1is a block diagram of an exemplary optical communication system.

[0016] Figure 2 is a schematic side view of an exemplary data processing system.

[0017] Figure 3 is a schematic side view of an exemplary integrated optical device.

[0018] Figure 4 is a schematic side view of an exemplary data processing system.

[0019] Figure 5 is a schematic side view of an exemplary integrated optical device.

[0020] Figure 6 and 7 is a schematic side view of an example of a data processing system.

[0021] Figure 8 It is an exploded perspective view of an integrated optical communication device.

[0022] Figure 9 and 10 is a schematic diagram of an exemplary layout pattern of optical terminals and electrical terminals of an integrated optical device.

[0023] Figure 11 、 12 , 13 and 14 are schematic side views of examples of data processing systems.

[0024] Figure 15 and 16 is a bottom view of an example of an integrated light device.

[0025] Figure 17 is a schematic diagram of various integrated optical communication devices that can be used in data processing systems.

[0026] Figure 18 is a schematic diagram of an exemplary octal serializer / deserializer block.

[0027] Figure 19 is a schematic diagram of an exemplary electronic communications integrated circuit.

[0028] Figure 20 is a functional block diagram of an exemplary data processing system.

[0029] Figure 21 is a schematic diagram of an exemplary rackmount data processing system.

[0030] Figure 22 、 23 , 24, 25, 26A, 26B, 26C, 27, 28A, and 28B are top views of examples of rack-mounted data processing systems incorporating optical interconnect modules.

[0031] Figure 29A and 29B is a schematic diagram of an exemplary rack-mounted data processing system incorporating multiple optical interconnect modules.

[0032] Figure 30 and 31 is a block diagram of an exemplary data processing system.

[0033] Figure 32 is a schematic side view of an exemplary data processing system.

[0034] Figure 33 is a schematic diagram of an exemplary electronic communications integrated circuit including an octal serializer / deserializer block.

[0035] Figure 34 is a flow chart of an exemplary process for processing optical and electrical signals using a data processing system.

[0036] Figure 35A It is a schematic diagram of an optical communication system.

[0037] Figure 35B and 35C is a schematic diagram of a co-packaged optical interconnect module.

[0038] Figure 36 and 37 is a schematic diagram of an example of an optical communication system.

[0039] Figure 38 and 39 is a schematic diagram of an example of a serializer / deserializer block.

[0040] Figure 40A 、 40B , 41A, 41B, and 42 are diagrams of examples of bus processing units.

[0041] Figure 43 is an exploded view of an example of a front-end module of a data processing system.

[0042] Figure 44 This is an exploded view of an example of the internal structure of an optical module.

[0043] Figure 45 This is an assembly diagram of the internal structure of the optical module.

[0044] Figure 46 This is an exploded view of the optical module.

[0045] Figure 47 This is the assembly diagram of the optical module.

[0046] Figure 48 It is a schematic diagram of a grid structure and part of a circuit board.

[0047] Figure 49 is a schematic diagram of the lower mechanical components before insertion into the grid structure.

[0048] Figure 50 is a schematic diagram of an example of a partially populated front view of an assembled system.

[0049] Figure 51A This is a front view of an example module installation.

[0050] Figure 51B This is a side view of an example module installation.

[0051] Figure 52A is a front view of an example of a mechanical connector structure and optical modules installed within a mesh structure.

[0052] Figure 52B is a side view of an example of a mechanical connector structure and optical modules installed within a grid structure.

[0053] Figure 53 and 54 is a schematic diagram of an example of an assembly including a fiber optic cable, a fiber optic connector, a mechanical connector module, and a mesh structure.

[0054] Figure 55A and 55B Before inserting the fiber optic connector into the mechanical connector structure Figure 53 and 54 A perspective view of the mechanism shown.

[0055] Figure 56 is a perspective view showing the insertion of optical modules and mechanical connector structures into the mesh structure.

[0056] Figure 57 It is a perspective view showing the cooperation between the optical fiber connector and the mechanical connector structure.

[0057] Figure 58A 、 58B , 58C, and 58D are schematic diagrams of exemplary light modules including latch mechanisms.

[0058] Figure 59 is a schematic diagram of an alternative example of an optical module.

[0059] Figure 60A and 60B is a schematic diagram of an exemplary embodiment of a lever and latch mechanism in a light module having a connector.

[0060] Figure 61 is a cross-sectional view from the front of a module installed in an assembly with a connector.

[0061] Figure 62 、 63 , 64 and 65 are schematic diagrams showing cross-sectional views of examples of fiber optic cable connection designs.

[0062] Figure 66 is a diagram of the electrical contact pads.

[0063] Figure 67 is a top view of an example of a rack-mounted server.

[0064] Figure 68A is a top view of an example of a rack-mounted server.

[0065] Figure 68B The diagram is a diagram showing an example of a front panel of a rack-mounted server.

[0066] Figure 68C is a perspective view of an example of a heat sink.

[0067] Figure 69A is a top view of an example of a rack-mounted server.

[0068] Figure 69B The diagram is a diagram showing an example of a front panel of a rack-mounted server.

[0069] Figure 70 is a top view of an example of a rack-mounted server.

[0070] Figure 71A is a top view of an example of a rack-mounted server.

[0071] Figure 71B This is the front view of a rack-mount server.

[0072] Figure 72 is a top view of an example of a rack-mounted server.

[0073] Figure 73A is a top view of an example of a rack-mounted server.

[0074] Figure 73B This is the front view of a rack-mount server.

[0075] Figure 74A is a top view of an example of a rack-mounted server.

[0076] Figure 74B This is the front view of a rack-mount server.

[0077] Figure 75A is a top view of an example of a rack-mounted server.

[0078] Figure 75B This is the front view of a rack-mount server.

[0079] Figure 75CFigure 1 is a schematic diagram of the airflow in a rack-mounted server.

[0080] Figure 76 is a diagram of a network rack that includes multiple rack-mounted servers.

[0081] Figure 77A is a side view of an example of a rack-mount server.

[0082] Figure 77B This is a top view of a rack server.

[0083] Figure 78 is a top view of an example of a rack-mounted server.

[0084] Figure 79 is a block diagram of an example of an optical communication system.

[0085] Figure 80A is a schematic diagram of an example of an optical communication system.

[0086] Figure 80B yes Figure 80A Schematic diagram of an example of a fiber optic cable assembly used in an optical communication system.

[0087] Figure 80C yes Figure 80B A magnified view of the fiber optic cable assembly.

[0088] Figure 80D yes Figure 80B An enlarged view of the upper portion of the fiber optic cable assembly.

[0089] Figure 80E yes Figure 80B An enlarged view of the lower portion of the fiber optic cable assembly.

[0090] Figure 80F yes Figure 80D An enlarged view of the schematic diagram of .

[0091] Figure 80G yes Figure 80E An enlarged view of the schematic diagram of .

[0092] Figure 81 is a block diagram of an example of an optical communication system.

[0093] Figure 82A is a schematic diagram of an example of an optical communication system.

[0094] Figure 82B is a schematic diagram of an example of a fiber optic cable assembly.

[0095] Figure 82C yes Figure 82B A magnified view of the fiber optic cable assembly.

[0096] Figure 82D yes Figure 82B An enlarged view of the upper portion of the fiber optic cable assembly.

[0097] Figure 82E yes Figure 82B An enlarged view of the lower portion of the fiber optic cable assembly.

[0098] Figure 82F yes Figure 82A An enlarged view of a portion of a schematic diagram.

[0099] Figure 82G yes Figure 82D An enlarged view of the schematic diagram of .

[0100] Figure 82H yes Figure 82E An enlarged view of the schematic diagram of .

[0101] Figure 83 is a block diagram of an example of an optical communication system.

[0102] Figure 84A is a schematic diagram of an example of an optical communication system.

[0103] Figure 84B is a schematic diagram of an example of a fiber optic cable assembly.

[0104] Figure 84C yes Figure 84B A magnified view of the fiber optic cable assembly.

[0105] Figure 85 、 86 , 87A, and 87B are schematic diagrams of examples of data processing systems.

[0106] Figure 88 is a schematic diagram of an example of a connector port mapping for a fiber optic interconnect cable.

[0107] Figure 89 and 90 is a schematic diagram of an example of a fiber optic port mapping for a fiber optic interconnect cable.

[0108] Figure 91 and 92 is a schematic diagram of an example of a possible port mapping of optical fiber connectors of a universal optical fiber interconnect cable.

[0109] Figure 93 is a diagram illustrating an example of port mapping of a fiber optic connector that is not applicable to a universal fiber optic interconnect cable.

[0110] Figure 94 and 95 is a schematic diagram of an example of a possible port mapping of optical fiber connectors of a universal optical fiber interconnect cable.

[0111] Figure 96 is a top view of an example of a rack-mounted server.

[0112] Figure 97A yes Figure 96 A perspective view of a rack server.

[0113] Figure 97B yes Figure 96 A perspective view of a rack server with the top panel removed.

[0114] Figure 98 yes Figure 96 Schematic diagram of the front portion of a rack server.

[0115] Figure 99 include Figure 96 Perspective front and rear views of the front panel of a rack server.

[0116] Figure 100 is a top view of an example of a rack-mounted server.

[0117] Figure 101 、 102 , 103A, and 103B are schematic diagrams of examples of optical fiber connectors.

[0118] Figure 104 and 105 1 and 2 are top and front views, respectively, of an example of rack-mount equipment including a vertical printed circuit board on which co-packaged optical modules are mounted.

[0119] Figure 106 is a schematic diagram of an example of a fiber optic cable assembly.

[0120] Figure 107 is a front view of a rack-mount device with a fiber optic cable assembly.

[0121] Figure 108 is a top view of an example of a rack-mount device including a vertical printed circuit board on which co-packaged optical modules are mounted.

[0122] Figure 109 is a front view of a rack-mount device with a fiber optic cable assembly.

[0123] Figure 110 and 111 They are top and front views of an example of a rack-mounted device.

[0124] Figure 112 is a schematic diagram of an example of rack-mounted equipment with exemplary parameter values.

[0125] Figure 113 and 114Another example of rack-mounted equipment with exemplary parameter values ​​is shown.

[0126] Figure 115 and 116 They are top and front views of an example of a rack-mounted device.

[0127] Figure 117 、 118 , 119 , 120 , 121 , and 122 are schematic diagrams of examples of systems including co-packaged optical modules.

[0128] Figure 123 is a schematic diagram of an example of a vertically mounted processor blade.

[0129] Figure 124 is a top view of an example of a rack system including several vertically mounted processor blades.

[0130] Figure 125A is a side view of an example of a rack server with a hinged front panel.

[0131] Figure 125B is a schematic diagram of an example of a rack-mount server having pluggable modules.

[0132] Figure 126A 、 126B 127 are schematic diagrams of examples of rack-mount servers having pluggable modules.

[0133] Figure 128 is a schematic diagram of an example of a fiber guide including one or more photon suppliers.

[0134] Figure 129 is a schematic diagram of an example of a rack-mount server including rails / cages to facilitate insertion of fiber guides.

[0135] Figure 130 is a side view of an example of a rack-mount server with a hinged-mounted front panel.

[0136] Figure 131 is a top view of an example of a rack-mount server with a hinged-mounted front panel.

[0137] Figure 132 is a schematic diagram of an example of an optical fiber cable.

[0138] Figure 133 Schematic top and side views of a rack-mount server with a hinged front panel are shown.

[0139] Figure 134 Shown are a top view, a vertical application specific integrated circuit (VASIC) plan front view, and a front panel front view of an example of a rack-mount server.

[0140] Figure 135 Shown are a top view, a VASIC plan front view, and a front panel front view of another example of a rack-mounted server.

[0141] Figure 136A is a schematic diagram of an example of a data processing system.

[0142] Figure 136B 、 136C , 136D, 136E, 136F, 136G and 136H are Figure 136A Schematic diagram of parts of a data processing system.

[0143] Figure 137 is a schematic diagram of a fiber optic connector.

[0144] Figure 138 is a schematic diagram of an example of a wavelength division multiplexing (WDM) data processing system.

[0145] Figure 139A is a schematic diagram of an example of a switch rack WDM converter.

[0146] Figure 139B FIG. 1 is a diagram illustrating an example of a 4×4 wavelength / space shuffle matrix.

[0147] Figure 140A is a schematic diagram of an example of a wavelength division multiplexing data processing system.

[0148] Figure 140B 、 140C , 140D, 140E, 140F, 140G and 140H are Figure 140A Schematic diagram of parts of a WDM data processing system.

[0149] Figure 141 is a schematic diagram of a fiber optic connector.

[0150] Figure 142 yes Figure 89 An enlarged view of the schematic diagram of .

[0151] Figure 143 yes Figure 90 An enlarged view of the schematic diagram of .

[0152] Figure 144 Show Figure 91 Schematic diagram of .

[0153] Figure 145 Show Figure 92 Schematic diagram of .

[0154] Figure 146 Show Figure 93 Schematic diagram of .

[0155] Figure 147 、 148 , 149, 150, and 151 are schematic diagrams of examples of systems that can provide large memory banks or memory pools.

[0156] Figure 152A is a schematic diagram of an exemplary pluggable optical module.

[0157] Figure 152B This figure shows a cross-sectional view of a pluggable optical module.

[0158] Figure 153A is a side view of an exemplary pluggable optical module.

[0159] Figure 153B The figure is a perspective view of the rear portion of a pluggable optical module.

[0160] Figure 153C is a side cross-sectional view of a pluggable optical module inserted into a cage.

[0161] Figure 154A is a rear view of an exemplary OSFP optical transceiver module.

[0162] Figure 154B is a rear view of an exemplary OSFP-XD optical transceiver module.

[0163] Figure 154C is a schematic diagram of an exemplary co-packaged optical module that may fit inside the housing of an OSFP module having a vertically oriented substrate or circuit board.

[0164] Figure 154D is a schematic diagram of an exemplary co-packaged optical module that may fit inside a housing of an OSFP-XD module having a vertically oriented substrate or circuit board.

[0165] Figure 154E is a cross-sectional view of an exemplary OSFP pluggable optical module.

[0166] Figure 154F is a cross-sectional view of an exemplary OSFP-XD pluggable optical module.

[0167] Figure 155A is a side cross-sectional view of an exemplary pluggable optical module inserted into a cage.

[0168] Figure 155B is a front view of an exemplary co-packaged optical module.

[0169] Figure 155C is a rear view of an exemplary connector module.

[0170] Figure 155D is a side view of an exemplary co-packaged optical module, flexible RF cable, and connector module.

[0171] Figure 155E is a schematic diagram of an example of fiber port mapping for a fiber optic connector.

[0172] Figure 156A is a side cross-sectional view of an exemplary pluggable optical module inserted into a cage.

[0173] Figure 156B is a front view of an exemplary co-packaged optical module.

[0174] Figure 156C is a rear view of an exemplary connector module.

[0175] Figure 156D This is a side view of the co-packaged optical module and connector module.

[0176] Figure 157A is a side cross-sectional view of an exemplary pluggable optical module inserted into a cage.

[0177] Figure 157B This figure shows a top-down cross-sectional view of a pluggable optical module.

[0178] Figure 157C This is a side view of a pluggable optical module.

[0179] Figure 157D is a schematic diagram of an exemplary fiber port mapping for a fiber optic connector.

[0180] Figure 158 Shows an example of an OSFP module pinout configuration.

[0181] Figure 159A is a perspective view of an exemplary 1×1 cage mounted on a circuit board.

[0182] Figure 159B is a perspective view of an exemplary 1×4 cage mounted on a circuit board.

[0183] Figure 159C is a perspective view of an exemplary OSFP module inserted into a 1x1 cage.

[0184] Figure 160 is a top cross-sectional view of an exemplary pluggable optical module.

[0185] Figure 161 is a side cross-sectional view of an exemplary pluggable optical module.

[0186] Figure 162 is a schematic diagram of an exemplary co-packaged optical module.

[0187] Figure 163A 、 163B , 164A, and 164B are perspective views of exemplary co-packaged optical modules.

[0188] Figure 165 is a top view of an exemplary placement of an electrical integrated circuit on a photonic integrated circuit.

[0189] Figure 166A 、 166B , 166C, and 166D are schematic diagrams of examples of photonic integrated circuit and optical fiber connections.

[0190] Figure 167 is a view of the front panel of a housing for a rack-mount switch.

[0191] Figure 168 This is a schematic diagram of the vertical front line card layout.

[0192] Figure 169 is a front view of the vertical front line card with plug ports and channel entrances.

[0193] Figure 169A is an exemplary front view of a vertical front line card with plug ports and channel entrances.

[0194] Figure 170 FIG. 1 is the left half of a front view of a vertical front line card with plug ports and channel entrances.

[0195] Figure 171 、 172 , 173, 174 and 175 are through including Figure 169 Partial view of the vertical front line card showing the design features.

[0196] Figure 176 FIG. 1 is the left half of a front view of a vertical dual ASIC front line card with plug ports and channel inlets.

[0197] Figure 177 is through including Figure 176 Partial view of the vertical front line card housing showing the design features of the .

[0198] Figure 177A is through including Figure 176 Partial view of the vertical front line card housing, featuring additional support structure, which is a design feature of the .

[0199] Figure 178 is through including Figure 176 Partial view of the vertical front line card housing showing the design features of the .

[0200] Figure 179 and 179A is through including Figure 176 Partial view of the vertical front line card housing showing the design features of the .

[0201] Figure 180 and181 is through including Figure 176 Partial view of the vertical front line card housing showing the design features of the .

[0202] Figure 182 This figure shows the layout of the vertical front line cards.

[0203] Figure 183 is a full view of the front of the vertical front line card with header ports and channel entries for a dual ASIC design.

[0204] Figure 184 is a full view of the front of the vertical front line card with header ports and channel entries for a single ASIC design.

[0205] Figure 184A 、 184B , 184C and 184D are full front views of vertical front line cards with alternative plug port and channel entry arrangements.

[0206] Figure 185 This figure shows the layout of the vertical front line cards.

[0207] Figure 186 is a front full view of a vertical front line card with alternative header port and channel entry orientations for a dual ASIC design.

[0208] Figure 187 is a front full view of a vertical front line card with alternative header port and channel entry orientations for a dual ASIC design.

[0209] Figure 188 is a front view of a design with front-mounted ASICs.

[0210] Figure 189 yes Figure 188 Shown in the left side of the front view.

[0211] Figure 190 It passes through Figure 189 A side view of a cross section of the left side of the design is shown in FIG.

[0212] Figure 191 It passes through Figure 189 A side view of a section of the center portion of the left side view is shown.

[0213] Figure 192 It passes through Figure 189 A side view of the cross section of the right side of the design is shown in FIG.

[0214] Figure 193 It passes through Figure 189 A top view of the designed cross section is shown in FIG.

[0215] Figure 194 It passes through Figure 189 Another top view of the cross section showing another vertical position of the design is shown in FIG.

[0216] Figure 195 It passes through Figure 189 Another top view of the cross section showing yet another vertical position of the design is shown in FIG.

[0217] Figure 196 It passes through Figure 189 The center portion of the left side view is shown in a side view with a cross section of an alternative design.

[0218] Figure 197 is a front view of a front-mounted ASIC design with dual air inlets.

[0219] Figure 198 It passes through Figure 197 A side view of a cross section of the left side of the design is shown in FIG.

[0220] Figure 199 It passes through Figure 197 Another side view of the cross section showing the right side of the design.

[0221] Figure 200 This figure shows the layout of the vertical front line cards.

[0222] Figure 201 is a full view of the front of a vertical front line card with alternative header port and channel entry orientations for a dual ASIC design.

[0223] Figure 202 It passes through Figure 201 A side view of a cross section of the left side of the design is shown in FIG.

[0224] Figure 203 It passes through Figure 201 A side view of a section of the center portion of the left side view is shown.

[0225] Figure 204 It passes through Figure 201 A top view of the cross section showing the vertical position of the design is shown in FIG.

[0226] Figure 205 It passes through Figure 201 A side view of a cross section of the central portion of the design is shown in FIG.

[0227] Like reference numbers in the various drawings indicate like elements. DETAILED DESCRIPTION

[0228] This document describes a novel system for high-bandwidth data processing, including a novel input / output interface module for coupling a bundle of optical fibers to a data processing integrated circuit (e.g., a network switch, a central processing unit, a graphics processing unit, a tensor processing unit, a digital signal processor, and / or other application-specific integrated circuit (ASIC)) that processes data transmitted via the optical fibers. In some embodiments, the data processing integrated circuit is mounted on a circuit board (or substrate, or a combination of a circuit board and a substrate) positioned adjacent to the input / output interface module, passing through a relatively short electrical signal path on the circuit board (or substrate, or a combination of a circuit board and a substrate). The input / output interface module includes a first connector that allows a user to conveniently connect or disconnect the input / output interface module to or from the circuit board (or substrate, or a combination of a circuit board and a substrate). The input / output interface module may also include a second connector that allows a user to conveniently connect or disconnect the bundle of optical fibers to or from the input / output interface module. In some embodiments, a rack-mounted system having a front panel is provided, wherein the circuit board (which supports the input / output interface module and the data processing integrated circuit) (or substrate, or a combination of a circuit board and a substrate) is vertically mounted in an orientation generally parallel to and adjacent to the front panel. In some examples, the circuit board (or substrate or a combination of circuit board and substrate) serves as a front panel or a portion of a front panel. The second connector of the input / output interface module faces the front side of the rack-mounted system to allow a user to conveniently connect or disconnect the bundle of optical fibers to the system.

[0229] In some embodiments, a feature of the high-bandwidth data processing system is that, by vertically mounting a circuit board supporting an input / output interface module and a data processing integrated circuit near a front panel, or configuring the circuit board as or as part of the front panel, optical signals can be routed from optical fibers through the input / output interface module to the data processing integrated circuit via a relatively short electrical signal path. This allows the signals transmitted to the data processing integrated circuit to have a high bit rate (e.g., exceeding 50 Gbps) while maintaining low crosstalk, low distortion, and low noise, thereby reducing the power consumption and footprint of the data processing system.

[0230] In some embodiments, a high-bandwidth data processing system can be characterized by lower maintenance and repair costs compared to conventional systems. For example, the input / output interface modules and fiber optic cables are configured to be detachable, allowing a defective input / output interface module to be replaced without disassembling the data processing system and without having to reroute any optical fibers. Another feature of the high-bandwidth data processing system is that because a user can easily connect or disconnect bundles of optical fibers from the input / output interface modules through the front panel of the rack-mounted system, the configuration of high-bit-rate signal routing via optical fiber to various data processing integrated circuits is flexible and easily modifiable. For example, connecting a bundle of hundreds of optical fibers to the optical connector of the rack-mounted system is almost as simple as plugging a Universal Serial Bus (USB) cable into a USB port. Another feature of the high-bandwidth data processing system is that the input / output interface modules can be manufactured using relatively standard, low-cost, and energy-efficient components, resulting in relatively low initial hardware costs and ongoing operating costs for the input / output interface modules compared to conventional systems.

[0231] In some embodiments, an optical interconnect may co-package and / or co-integrate an optical transponder with an electronic processing chip. As is seen in electronic processing chip packaging, transponder solutions that consume relatively low power and are sufficiently robust to withstand significant temperature variations are useful. In some embodiments, a high-speed and / or high-bandwidth data processing system may include a massively spatially parallel optical interconnect solution that multiplexes information onto a relatively small number of wavelengths and uses a relatively large number of parallel spatial paths for chip-to-chip interconnection. For example, a relatively large number of parallel spatial paths may be arranged in a two-dimensional array using connector structures, such as those disclosed in U.S. patent application Ser. No. 16 / 816,171, filed on March 11, 2020, and published as US2021 / 0286140, which is incorporated herein by reference in its entirety.

[0232] Figure 1A block diagram of a communication system 100 is shown, which incorporates one or more novel features described herein. In some embodiments, system 100 includes nodes 101_1 to 101_6 (collectively referred to as 101), and in some embodiments, each node may include one or more of the following: optical communication equipment, electronic and / or optical switching equipment, electronic and / or optical routing equipment, network control equipment, flow control equipment, synchronization equipment, computing equipment, and data storage equipment. Nodes 101_1 to 101_6 can be appropriately interconnected by optical fiber links 102_1 to 102_12 (collectively referred to as 102) to establish communication paths between communication devices within the node. Optical fiber link 102 may include an optical fiber cable described in U.S. Patent No. 11,194,109, entitled "Optical Fiber Cable and Trough Thereof," issued on December 7, 2021, which is incorporated herein by reference in its entirety. The system 100 may also include one or more optical power supply modules 103 that generate one or more optical outputs, each optical output including one or more continuous wave (CW) optical fields and / or one or more optical pulse trains for use in one or more optical communication devices of nodes 101_1 to 101_6. For illustrative purposes, Figure 1 Only one such optical power supply module 103 is shown. Those skilled in the art will appreciate that some embodiments may have more than one optical power supply module 103, appropriately distributed across the system 100, and that such multiple power supply modules may be synchronized, for example, using some of the techniques disclosed in U.S. Patent No. 11,153,670, issued on October 19, 2021, entitled “Communication System Employing Optical Frame Templates,” which is incorporated herein by reference in its entirety.

[0233] Some end-to-end communication paths may pass through the optical power supply module 103 (e.g., see the communication path between nodes 101_2 and 101_6). For example, the communication path between nodes 101_2 and 101_6 may be established by optical fiber links 102_7 and 102_8, whereby light from the optical power supply module 103 is multiplexed onto optical fiber links 102_7 and 102_8.

[0234] Some end-to-end communication paths may pass through one or more optical multiplexing units 104 (e.g., see the communication path between nodes 101_2 and 101_6). For example, the communication path between nodes 101_2 and 101_6 may be established by optical fiber links 102_10 and 102_11. Multiplexing unit 104 is also connected via link 102_9 to receive light from optical power supply module 103, and thus may multiplex the received light onto optical fiber links 102_10 and 102_11.

[0235] Some end-to-end communication paths may pass through one or more optical switching units 105 (e.g., see the communication path between nodes 101_1 and 101_4). For example, the communication path between nodes 101_1 and 101_4 may be established by fiber optic links 102_3 and 102_12, whereby light from fiber optic links 102_3 and 102_4 is statically or dynamically directed to fiber optic link 102_12.

[0236] As used herein, the term "network element" refers to any element that generates, modulates, processes, or receives light for communication within system 100. Exemplary network elements include node 101, optical power supply module 103, optical multiplexing unit 104, and optical switching unit 105.

[0237] Some light distribution paths may pass through one or more network elements. For example, the optical power supply module 103 may provide light to the node 101_4 via the optical fiber links 102_7 , 102_4 , and 102_12 , allowing the light to pass through the network elements 101_2 and 105 .

[0238] Various elements of the communication system 100 may benefit from the use of optical interconnects, which may be co-packaged and / or co-integrated with electronic chips including integrated circuits using photonic integrated circuits including optoelectronic devices.

[0239] As used herein, the term "photonic integrated circuit" (or PIC) should be interpreted to encompass planar lightwave circuits (PLCs), integrated optoelectronic devices, wafer-scale products on substrates, individual photonic chips and dies, and hybrid devices. The substrate may be made of, for example, one or more ceramic materials or organic "high-density build-up" (HDBU). Exemplary material systems that can be used to fabricate various photonic integrated circuits may include, but are not limited to, III-V semiconductor materials, silicon photonic devices, silica-on-silicon products, silica-glass-based planar lightwave circuits, polymer integration platforms, lithium niobates and their derivatives, nonlinear optical materials, and the like. Both packaged devices (e.g., wired and / or encapsulated chips) and unpackaged devices (e.g., dies) may be referred to as planar lightwave circuits.

[0240] Photonic integrated circuits are used in a variety of applications in the fields of telecommunications, instrumentation control, and signal processing. In some embodiments, photonic integrated circuits use optical waveguides to implement and / or interconnect various circuit components, such as optical switches, couplers, routers, splitters, multiplexers / demultiplexers, filters, modulators, phase shifters, lasers, amplifiers, wavelength converters, optical / electrical (O / E) and electrical / optical (E / O) signal converters, and the like. For example, the waveguides in a photonic integrated circuit can be on-chip solid-state photoconductors that can guide light due to the difference in refractive index between the waveguide core and cladding. The photonic integrated circuit can include a planar substrate onto which optoelectronic devices are grown using an additive manufacturing process and / or onto which optoelectronic devices are etched using a subtractive manufacturing process, for example, using a multi-step sequence of photolithographic and chemical processing steps.

[0241] In some embodiments, an "optoelectronic device" can operate on both light and electric current (or voltage) and can include one or more of the following: (i) an electrically driven light source, such as a laser diode; (ii) an optical amplifier; (iii) an optical / electrical converter, such as a photodiode; (iv) an optoelectronic component that can control the propagation and / or certain properties (e.g., amplitude, phase, polarization) of light, such as an optical modulator or switch. A corresponding optoelectronic circuit can additionally include one or more optical elements and / or one or more electronic components that enable the optoelectronic device of the circuit to be used in a manner consistent with the intended function of the circuit. Some optoelectronic devices can be implemented using one or more photonic integrated circuits.

[0242] As used herein, the term "integrated circuit" (IC) should be interpreted as including both non-packaged dies and packaged dies. In a typical integrated circuit manufacturing process, dies (chips) are produced in relatively large batches using silicon wafers or other suitable materials. Electrical and optical circuits can be gradually created on the wafer using a multi-step sequence of photolithography and chemical processing steps. Each wafer is then cut ("diced") into many pieces (chips, dies), each containing a corresponding copy of the circuit being manufactured. Each individual die can be appropriately packaged before being incorporated into a larger circuit, or it may not be packaged.

[0243] The term "hybrid circuit" may refer to a multi-component circuit consisting of multiple monolithic integrated circuits and possibly some discrete circuit components, all of which are attached to each other and can be mounted and electrically connected to a common base, carrier or substrate. A representative hybrid circuit may include (i) one or more packaged or unpackaged tube cores, some or all of which include optical, optoelectronic and / or semiconductor devices, and (ii) one or more optional discrete components, such as connectors, resistors, capacitors and inductors. The electrical connections between the integrated circuits, tube cores and discrete components can be formed, for example, using patterned conductive (e.g., metal) layers, ball grid arrays, solder bumps, wire bonds, etc. The electrical connections are detachable, for example, by using a planar grid array and / or a compression interposer. A separate integrated circuit may include any combination of one or more corresponding substrates, one or more redistribution layers (RDLs), one or more interposers, one or more laminates, etc.

[0244] In some embodiments, multiple individual chips can be stacked. As used herein, the term "stack" refers to an ordered arrangement of packaged or unpackaged dies, wherein the major planes of the stacked dies are substantially parallel to one another. The stack can typically be mounted on a carrier with the major planes of the stacked dies parallel to one another and / or to the major plane of the carrier.

[0245] The "principal plane" of an object, such as a die, photonic integrated circuit, substrate, or integrated circuit, is parallel to its substantially planar surface that has the largest dimension, e.g., length and width, of all the exterior surfaces of the object. This substantially planar surface may be referred to as a major surface. An exterior surface of an object that has one relatively large dimension (e.g., length) and one relatively small dimension (e.g., height) is often referred to as an edge of the object.

[0246] Figure 2 is a schematic cross-sectional view of a data processing system 200 that includes an integrated optical communication device 210 (also referred to as an optical interconnect module), a fiber optic connector assembly 220, a packaging substrate 230, and an electronic processor integrated circuit 240. The data processing system 200 may be used to implement, for example, Figure 1 One or more of devices 101_1 to 101_6. Figure 3 An enlarged cross-sectional view of an integrated optical communication device 210 is shown.

[0247] Reference Figure 2 and 3The integrated optical communication device 210 includes a substrate 211 having a first major surface 211_1 and a second major surface 211_2. The major surfaces 211_1 and 211_2 include arrays of electrical contacts 212_1 and 212_2, respectively. In some embodiments, the minimum spacing d1 between any two contacts within the array of electrical contacts 212_1 is greater than the minimum spacing d2 between any two contacts within the array of electrical contacts 212_2. In some embodiments, the minimum spacing between any two contacts within the array of electrical contacts 212_2 is between 40 and 200 microns. In some embodiments, the minimum spacing between any two contacts within the array of electrical contacts 212_1 is between 200 microns and 1 millimeter. At least some of the contacts 212_1 are electrically connected to at least some of the electrical contacts 212_2 via the substrate 211. In some embodiments, the contacts 212_1 can be permanently attached to corresponding arrays of electrical contacts 232_1 on the packaging substrate 230. In some embodiments, the contacts 212_1 may include a mechanism that allows the device 210 to be removably connected to the package substrate 230, as indicated by the double arrow 233. For example, the system may include a mechanical mechanism (e.g., one or more snap-on or screw-in mechanisms) to hold the various modules in place. In some embodiments, the contacts 212_1, 212_2, and / or 232_1 may include one or more of solder balls, metal pillars, and / or metal pads. In some embodiments, the contacts 212_1 and / or 232_1 may include one or more of a spring-loaded element, a compression interposer, and / or a planar grid array.

[0248] In some embodiments, the integrated optical communication device 210 can be connected to an electronic processor integrated circuit 240 using traces 231 embedded in one or more layers of the package substrate 230. In some embodiments, the processor integrated circuit 240 can include a serializer / deserializer (SerDes) array 247 monolithically embedded therein, the array being electrically coupled to the traces 231. In some embodiments, the processor integrated circuit 240 can include electronic switching circuitry, electronic routing circuitry, network control circuitry, flow control circuitry, computational circuitry, synchronization circuitry, time stamping circuitry, and data storage circuitry. In some embodiments, the processor integrated circuit 240 can be a network switch, a central processing unit, a graphics processor unit, a tensor processing unit, a digital signal processor, or an application-specific integrated circuit (ASIC).

[0249] Because both the electronic processor integrated circuit 240 and the integrated communication device 210 are mounted on the package substrate 230, mounting on the package substrate 230 can result in shorter electrical connectors or traces 231 compared to mounting the electronic processor integrated circuit 240 and the integrated communication device 210 on separate circuit boards. Shorter electrical connectors or traces 231 can transmit signals with higher data rates, lower noise, lower distortion, and / or lower crosstalk.

[0250] In some embodiments, the electrical connectors or traces can be configured as differential pairs of transmission lines, for example, a ground-signal-ground-signal-ground configuration. In some examples, the speed of such a signal link can be 10 Gbps or greater; 56 Gbps or greater; 112 Gbps or greater; or 224 Gbps or greater.

[0251] In some embodiments, the integrated optical communication device 210 further includes a first optical connector component 213 having a first surface 213_1 and a second surface 213_2. The connector component 213 is configured to receive a second optical connector component 223 of the optical fiber connector assembly 220, with the second optical connector component 223 optically coupled to the connector component 213 via the surfaces 213_1 and 223_2. In some embodiments, the connector component 213 is removably attached to the connector component 223, as indicated by a double arrow 234, for example, via a hole 235 in the package substrate 230. In some embodiments, the connector component 213 can be permanently attached to the connector component 223. In some embodiments, the connector components 213 and 223 can be implemented as a single connector element that combines the functionality of both connector components 213 and 223.

[0252] In some embodiments, the optical connector component 223 is attached to an array of optical fibers 226. In some embodiments, the array of optical fibers 226 may include one or more of the following: single-mode optical fibers, multi-mode optical fibers, multi-core optical fibers, polarization-maintaining optical fibers, dispersion-compensating optical fibers, hollow-core optical fibers, or photonic crystal fibers. In some embodiments, the array of optical fibers 226 may be a linear (1D) array. In some other embodiments, the array of optical fibers 226 may be a two-dimensional (2D) array. For example, the array of optical fibers 226 may include 2 or more optical fibers, 4 or more optical fibers, 10 or more optical fibers, 100 or more optical fibers, 500 or more optical fibers, or 1000 or more optical fibers. Each optical fiber may include, for example, 2 or more cores, or 10 or more cores, wherein each core provides a different optical path. Each optical path may include, for example, multiplexing of 2 or more, 4 or more, 8 or more, or 16 or more serial optical signals, for example, by using wavelength division multiplexing channels, polarization multiplexing channels, or coherent orthogonal multiplexing channels. Connector components 213 and 223 are configured to establish optical paths through first major surface 211_1 of substrate 211. For example, array of optical fibers 226 may include n1 optical fibers, each of which may include n2 cores, and connector components 213 and 223 may establish n1×n2 optical paths through first major surface 211_1 of substrate 211. Each optical path may include a multiplex of n3 serial optical signals, resulting in a total of n1×n2×n3 serial optical signals passing through connector components 213 and 223. In some embodiments, connector components 213 and 223 may be implemented, for example, as disclosed in U.S. patent application Ser. No. 16 / 816,171.

[0253] In some embodiments, the integrated optical communication device 210 further includes a photonic integrated circuit 214 having a first major surface 214_1 and a second major surface 214_2. The photonic integrated circuit 214 is optically coupled to a connector component 213 via its first major surface 214_1, for example, as disclosed in U.S. patent application Ser. No. 16 / 816,171. For example, the connector component 213 can be configured to optically couple light to the photonic integrated circuit 214 using an optical coupling interface, such as a vertical grating coupler or a steering mirror. In the above example, a total of n1×n2×n3 serial optical signals can be coupled to the photonic integrated circuit 214 via the connector components 213 and 223. Each serial optical signal is converted into a serial electrical signal by the photonic integrated circuit 214, and each serial electrical signal is transmitted from the photonic integrated circuit 214 to a deserializer unit or a serializer / deserializer unit, as described below.

[0254] In some embodiments, the connector component 213 can be mechanically connected (e.g., glued) to the photonic integrated circuit 214. The photonic integrated circuit 214 can include active and / or passive optical and / or optoelectronic components, including optical modulators, optical detectors, optical phase shifters, optical power splitters, optical wavelength splitters, optical polarization splitters, optical filters, optical waveguides, or lasers. In some embodiments, the photonic integrated circuit 214 can also include monolithically integrated active or passive electronic components, such as resistors, capacitors, inductors, heaters, or transistors.

[0255] In some embodiments, the integrated optical communication device 210 further includes an electronic communication integrated circuit 215 configured to facilitate communication between the array of optical fibers 226 and the electronic processor integrated circuit 240. The first major surface 215_1 of the electronic communication integrated circuit 215 is electrically coupled to the second major surface 214_2 of the photonic integrated circuit 214, for example, via solder bumps, copper pillars, etc. The first major surface 215_1 of the electronic communication integrated circuit 215 is further electrically connected to the second major surface 211_2 of the substrate 211 via an array of electrical contacts 212_2. In some embodiments, the electronic communication integrated circuit 215 may include an electrical preamplifier and / or an electrical driver amplifier electrically coupled to the photodetector and modulator within the photonic integrated circuit 214, respectively (see also Figure 14 ). In some embodiments, the electronic communication integrated circuit 215 may include: a first serializer / deserializer (SerDes) array 216 (also referred to as a serializer / deserializer module), whose serial input / output is electrically connected to the photodetector and modulator of the photonic integrated circuit 214; and a second serializer / deserializer array 217, whose serial input / output is electrically coupled to the electrical contact 212_1 through the substrate 211. The parallel inputs of the serializer / deserializer array 216 can be connected to the parallel outputs of the serializer / deserializer array 217 through the bus processing unit 218, and vice versa. The bus processing unit 218 can be, for example, a parallel bus of electrical channels (lanes), a cross-connect device, or a remapping device (gearbox). For example, the bus processing unit 218 can be configured to enable switching of signals, thereby allowing the routing of signals to be remapped. For example, N×50Gbps electrical channels can be remapped to N / 2×100Gbps electrical channels, where N is a positive even number. An example of a bus processing unit 218 is shown in Figure 40A .

[0256] For example, the electronic communication integrated circuit 215 includes a first serializer / deserializer module including a plurality of serializer units and a plurality of deserializer units, and a second serializer / deserializer module including a plurality of serializer units and a plurality of deserializer units. The first serializer / deserializer module includes a first serializer / deserializer array 216. The second serializer / deserializer module includes a second serializer / deserializer array 217.

[0257] In some embodiments, the first and second serializer / deserializer modules have hardwired functional units such that which units function as serializers and which units function as deserializers are fixed. In some embodiments, the functional units may be configurable. For example, the first serializer / deserializer module may be capable of operating as a serializer unit upon receiving a first control signal and as a deserializer unit upon receiving a second control signal. Similarly, the second serializer / deserializer module may be capable of operating as a serializer unit upon receiving a first control signal and as a deserializer unit upon receiving a second control signal.

[0258] Signals can be transmitted between the optical fiber 226 and the electronic processor integrated circuit 240. For example, signals can be transmitted from the optical fiber 226 to the photonic integrated circuit 214, the first serializer / deserializer array 216, the second serializer / deserializer array 217, and the electronic processor integrated circuit 240. Similarly, signals can be transmitted from the electronic processor integrated circuit 240 to the second serializer / deserializer array 217, the first serializer / deserializer array 216, the photonic integrated circuit 214, and the optical fiber 226.

[0259] In some embodiments, the electronic communication integrated circuit 215 is implemented as a first integrated circuit and a second integrated circuit electrically coupled to each other. For example, the first integrated circuit includes a serializer / deserializer array 216 and the second integrated circuit includes a serializer / deserializer array 217.

[0260] In some embodiments, the integrated optical communication device 210 is configured to receive an optical signal from the array of optical fibers 226, generate an electrical signal based on the optical signal, and transmit the electrical signal to the electronic processor integrated circuit 240 for processing. In some examples, signals can also flow from the electronic processor integrated circuit 240 to the integrated optical communication device 210. For example, the electronic processor integrated circuit 240 can transmit the electronic signal to the integrated optical communication device 210, which generates an optical signal based on the received electrical signal and transmits the optical signal to the array of optical fibers 226.

[0261] In some embodiments, the photodetector of the photonic integrated circuit 214 converts the optical signal transmitted in the optical fiber 226 into an electrical signal. In some examples, the photonic integrated circuit 214 may include a transimpedance amplifier for amplifying the current generated by the photodetector, and a driver for driving the output circuit (e.g., driving the optical modulator). In some examples, the transimpedance amplifier and the driver are integrated with the electronic communication integrated circuit 215. For example, the optical signal in each optical fiber 226 can be converted into one or more serial electrical signals. For example, a single optical fiber can carry multiple signals by using wavelength division multiplexing. The optical signal (and the serial electrical signal) can have a high data rate, such as 50 Gbps, 100 Gbps, or more. The first serializer / deserializer module 216 converts the serial electrical signal into multiple sets of parallel electrical signals. For example, each serial electrical signal can be converted into a set of N parallel electrical signals, where N can be, for example, 2, 4, 8, 16, or more. The first serializer / deserializer module 216 adjusts the serial electrical signal when converting it into multiple sets of parallel electrical signals, where the signal adjustment can include, for example, one or more of clock and data recovery and signal equalization. The first SerDes module 216 sends the multiple parallel electrical signals to the second SerDes module 217 through the bus processing unit 218. The second SerDes module 217 converts the multiple parallel electrical signals into high-speed serial electrical signals, which are output to the electrical contacts 212_2 and 212_1.

[0262] The serializer / deserializer modules (e.g., 216, 217) can perform functions such as fixed or adaptive signal pre-distortion on the serialized signal. In addition, the parallel-to-serial mapping can use a serialization factor M that is different from N. For example, 50 Gbps at the input of the first serializer / deserializer module 216 can become 50×1 Gbps on a parallel bus, and two such parallel buses from two serializer / deserializer modules 216 totaling 100×1 Gbps can be mapped to a single 100 Gbps serial signal by the serializer / deserializer module 217. An example of a bus processing unit 218 for performing such mapping is shown in FIG. Figure 40B . In addition, the high-speed modulation on the serial side can be different, for example, the SerDes module 216 can use 50Gbps non-return-to-zero (NRZ) modulation, while the SerDes module 217 can use 100Gbps pulse-amplitude modulation 4-level (PAM4) modulation. In some embodiments, encoding (line coding or error correction coding) can be performed at the bus processing unit 218. The first and second SerDes modules 216 and 217 can be commercially available high-quality, low-power SerDes that can be purchased in bulk at a low price.

[0263] In some embodiments, the package substrate 230 may include a connector on the bottom side that connects the package substrate 230 to another circuit board, such as a motherboard. The connection may be fixed (e.g., by using a solder connection) or removable (e.g., by using one or more snap-on or screw-on mechanisms). In some examples, another substrate may be provided between the electronic processor integrated circuit 240 and the package substrate 230.

[0264] like Figure 4 As shown, in some embodiments, the data processing system 250 includes an integrated optical communication device 252 (also referred to as an optical interconnect module), a fiber optic connector assembly 220, a packaging substrate 230, and an electronic processor integrated circuit 240. The data processing system 250 can be used to implement, for example Figure 1 The integrated optical communication device 252 is configured to receive an optical signal, generate an electrical signal based on the optical signal, and transmit the electrical signal to the electronic processor integrated circuit 240 for processing. In some examples, signals can also flow from the electronic processor integrated circuit 240 to the integrated optical communication device 252. For example, the electronic processor integrated circuit 240 can transmit the electronic signal to the integrated optical communication device 252, which generates an optical signal based on the received electrical signal and transmits the optical signal to the optical fiber 226 array.

[0265] System 250 is similar to Figure 2 The data processing system 200 is different in that, in the system 250, a portion 254 of the top surface of the photonic integrated circuit 214 is not covered by the first serializer / deserializer module 216 and the second serializer / deserializer module 217 in the cross-sectional direction of the figure. For example, the portion 254 can be used to access the photonic integrated circuit 214 from the bottom (e.g., Figure 4 as shown) or from the top (as Figure 6 ) coupled to other electronic, optical, or electro-optical components. In some examples, the first SerDes module 216 may have a high temperature during operation. The portion 254 is not covered by the first SerDes module 216 and may be less thermally coupled to the first SerDes module 216. In some examples, the photonic integrated circuit 214 may include a modulator that modulates the phase of the optical signal by modifying the temperature of the waveguide and thereby modifying the refractive index of the waveguide. In such a device, the use Figure 4 The design shown in the example allows the modulator to operate in a more thermally stable environment.

[0266] Figure 5An enlarged cross-sectional view of an integrated optical communication device 252 is shown. In some embodiments, substrate 211 includes a first plate 256 and a second plate 258. First plate 256 provides an electrical connector to fan out electrical contacts, and second plate 258 provides a removable connection to package substrate 230. First plate 256 includes a first set of contacts arranged on a top surface and a second set of contacts arranged on a bottom surface, wherein the first set of contacts has a fine pitch and the second set of contacts has a coarse pitch. The minimum distance between contacts in the second set of contacts is greater than the minimum distance between contacts in the first set of contacts. Second plate 258 may include, for example, spring-loaded contacts 259.

[0267] like Figure 6 As shown, in some embodiments, the data processing system 260 includes an integrated optical communication device 262 (also referred to as an optical interconnect module), a fiber optic connector assembly 270, a packaging substrate 230, and an electronic processor integrated circuit 240. The data processing system 260 can be used to implement, for example Figure 1 One or more of the devices 101_1 to 101_6. The integrated optical communication device 262 includes a photonic integrated circuit 264. The photonic integrated circuit 264 may include a device that performs Figures 2 to 5 The integrated optical communication device 262 further includes a first optical connector component 266 configured to receive a second optical connector component 268 of the fiber optic connector assembly 270. For example, a snap-on or screw-on mechanism may be used to hold the first and second optical connector components 266 and 268 together.

[0268] Connector components 266 and 268 may be similar to Figure 4 In some examples, the optical connector assembly 268 is attached to an array of optical fibers 272, which may be similar to Figure 4 Optical fiber 226.

[0269] The photonic integrated circuit 264 has a top major surface and a bottom major surface. The terms "top" and "bottom" refer to the orientation shown in the figures. It is understood that the devices described in this document can be positioned in any orientation, for example, the "top surface" of the device can be facing downward or sideways, and the "bottom surface" of the device can be facing upward or sideways. The photonic integrated circuit 264 and the photonic integrated circuit 214 ( Figure 4 ) is that photonic integrated circuit 264 is optically coupled to connector component 268 via a top major surface, while photonic integrated circuit 214 is optically coupled to connector component 213 via a bottom major surface. For example, connector component 266 can be configured to optically couple light to photonic integrated circuit 214 using an optical coupling interface such as a vertical grating coupler or a turning mirror, in a manner similar to how connector component 213 optically couples light to photonic integrated circuit 214.

[0270] Integrated optical communication device 252 ( Figure 4 ) and 262( Figure 6 ) provides flexibility in the design of the data processing system, allowing the fiber optic connector assembly 220 or 270 to be positioned on either side of the packaging substrate 230.

[0271] like Figure 7 As shown, in some embodiments, the data processing system 280 includes an integrated optical communication device 282 (also referred to as an optical interconnect module), a fiber optic connector assembly 270, a packaging substrate 230, and an electronic processor integrated circuit 240. The data processing system 280 can be used to implement, for example Figure 1 One or more of devices 101_1 to 101_6.

[0272] The integrated optical communication device 282 includes a photonic integrated circuit 284, a circuit board 286, a first serializer / deserializer module 216, a second serializer / deserializer module 217, and a control circuit 287. The photonic integrated circuit 284 may include a processor that performs operations associated with the photonic integrated circuit 214 ( Figures 2 to 5 ) and 264( Figure 6 ) components with similar functions. Control circuitry 287 controls the operation of photonic integrated circuit 284. For example, control circuitry 287 can statically or adaptively control one or more photodetector and / or modulator bias voltages, heater voltages, etc. based on one or more sensor voltages that control circuitry 287 can receive from photonic integrated circuit 284. Integrated optical communication device 282 also includes a first optical connector component 288 configured to receive second optical connector component 268 of fiber optic connector assembly 270. Optical connector component 268 is attached to an array of optical fibers 272.

[0273] The circuit board 286 has a top major surface 290 and a bottom major surface 292. The photonic integrated circuit 284 has a top major surface 294 and a bottom major surface 296. The first and second serializer / deserializer modules 216 and 217 are mounted on the top major surface 290 of the circuit board 286. The top major surface 294 of the photonic integrated circuit 284 has electrical terminals that are electrically connected to corresponding electrical terminals on the bottom major surface 292 of the circuit board 286. In this example, the photonic integrated circuit 284 is mounted on a side of the circuit board 286 that is opposite the side of the circuit board 286 on which the first and second serializer / deserializer modules 216 and 217 are mounted. The photonic integrated circuit 284 is electrically coupled to the first serializer / deserializer 216 via an electrical connector 300 that extends through the thickness of the circuit board 286. In some embodiments, the electrical connector 300 can be implemented as a through-hole.

[0274] The dimensions of connector assembly 288 are configured such that fiber optic connector assembly 270 can be coupled to connector assembly 288 without impinging on other components of integrated optical communication device 282. Connector assembly 288 can be configured to optically couple light to photonic integrated circuit 284 using an optical coupling interface, such as a vertical grating coupler or a turning mirror, in a manner similar to how connector assembly 213 or 266 optically couples light to photonic integrated circuit 214 or 264, respectively.

[0275] When the integrated optical communication device 282 is coupled to the packaging substrate 230, the photonic integrated circuit 284 and the control circuit 287 are located between the circuit board 286 and the packaging substrate 230. The integrated optical communication device 282 includes a contact array 298 disposed on the bottom major surface 292 of the circuit board 286. The contact array 298 is configured such that after the circuit board 286 is coupled to the packaging substrate 230, the contact array 298 maintains a thickness d3 between the circuit board 286 and the packaging substrate 230, wherein the thickness d3 is slightly greater than the thickness of the photonic integrated circuit 284 and the control circuit 287.

[0276] Figure 8 yes Figure 7 16 / 816,171, which is an exploded perspective view of an integrated optical communication device 282. The photonic integrated circuit 284 includes an array of optical coupling components 310, such as vertical grating couplers or turning mirrors as disclosed in U.S. patent application Ser. No. 16 / 816,171, which are configured to optically couple light from the optical connector assembly 288 to the photonic integrated circuit 214. The optical coupling components 310 are densely packed and have a fine pitch, so that optical signals from many optical fibers can be coupled to the photonic integrated circuit 284. For example, the minimum distance between adjacent optical coupling components 310 can be as small as 5 μm, 10 μm, 50 μm, or 100 μm.

[0277] An electrical terminal array 312 disposed on the top major surface 294 of the photonic integrated circuit 284 is electrically coupled to an electrical terminal array 314 disposed on the bottom major surface 292 of the circuit board 286. The electrical terminal arrays 312 and 314 have a fine pitch, wherein the minimum distance between two adjacent electrical terminals can be as small as, for example, 10 μm, 40 μm, or 100 μm. The electrical terminal array 316 disposed on the bottom major surface of the first serializer / deserializer 216 is electrically coupled to an electrical terminal array 318 disposed on the top major surface 290 of the circuit board 286. The electrical terminal array 320 disposed on the bottom major surface of the second serializer / deserializer module 217 is electrically coupled to an electrical terminal array 322 disposed on the top major surface 290 of the circuit board 286.

[0278] For example, the electrical terminal arrays 312, 314, 316, 318, 320, and 322 have a fine pitch (or several fine pitches). Figure 8 In the example of , for each electrical terminal array 312, 314, 316, 318, 320 and 322, the minimum distance between adjacent terminals is d2, which can be in the range of, for example, 10 μm to 200 μm. In some examples, the minimum distance between adjacent terminals can be different for different electrical terminal arrays. For example, the minimum distance between adjacent terminals of the electrical terminal array 314 (which is arranged on the bottom surface of the circuit board 286) can be different from the minimum distance between adjacent terminals of the electrical terminal array 318 arranged on the top surface of the circuit board 286. The minimum distance between adjacent terminals of the electrical terminal array 316 of the first serializer / deserializer 216 can be different from the minimum distance between adjacent terminals of the electrical terminal array 320 of the second serializer / deserializer module 217.

[0279] The electrical terminal array 324 disposed on the bottom main surface of the circuit board 286 is electrically coupled to the contact array 298. The electrical terminal array 324 may have a coarse pitch. For example, the minimum distance between adjacent electrical terminals is d1, which may be in the range of, for example, 200 μm to 1 mm. The contact array 298 may be configured as a module that maintains a distance slightly greater than the distance between the integrated optical communication device 282 and the package substrate 230 after the integrated optical communication device 282 is coupled to the package substrate 230. Figure 8 The contact array 298 may include, for example, a substrate with embedded spring-loaded connectors.

[0280] Figure 9 yes Figure 7 and 8 Schematic diagram of an exemplary layout design of optical and electrical terminals of an integrated optical communication device 282. Figure 9 The layout of the optical and electrical terminals is shown when viewed from the top or bottom side of device 282. In this example, photonic integrated circuit 284 has a width of approximately 5 mm and a length of approximately 2.2 mm to 18 mm. For an example in which the length of photonic integrated circuit 284 is approximately 2.2 mm, the optical signals provided to photonic integrated circuit 284 can have a total bandwidth of approximately 1.6 Tbps. For an example in which the length of photonic integrated circuit is approximately 18 mm, the optical signals provided to photonic integrated circuit can have a total bandwidth of approximately 12.8 Tbps. The width of integrated optical communication device 282 can be approximately 8 mm.

[0281] An array 330 of optical coupling components 310 is provided to allow optical signals to be provided in parallel to the photonic integrated circuit 284. The first serializer / deserializer 216 includes an array 332 of electrical terminals 316 arranged on the bottom surface of the first serializer / deserializer 216. The second serializer / deserializer module 217 includes an array 334 of electrical terminals 320 arranged on the bottom surface of the second serializer / deserializer module 217. The arrays 332 and 334 of electrical terminals 316, 320 have a fine pitch, and the minimum distance between adjacent terminals can be in the range of, for example, 40 μm to 200 μm. An array 336 of electrical terminals 324 is arranged on the bottom major surface of the circuit board 286. The array 336 of electrical terminals 324 has a coarse pitch, and the minimum distance between adjacent terminals can be in the range of, for example, 200 μm to 1 mm. For example, the array 336 of electrical terminals 324 can be part of a compression interposer having a pitch of approximately 400 μm between terminals.

[0282] Figure 10 yes Figure 2 Schematic diagram of an exemplary layout design of optical and electrical terminals of an integrated optical communication device 210. Figure 10 The layout of the optical and electrical terminals is shown when viewed from the top or bottom side of device 210. In this embodiment, photonic integrated circuit 214 is implemented as a single chip. In some embodiments, photonic integrated circuit 214 can be tiled across multiple chips. Similarly, in this embodiment, electronic communication integrated circuit 215 is implemented as a single chip. In some embodiments, electronic communication integrated circuit 215 can be tiled across multiple chips. In this embodiment, the electronic communication integrated circuit 215 is implemented using the following: 16 serializer / deserializer blocks 216_1 to 216_16, which are electrically connected to the photonic integrated circuit 214; and 16 serializer / deserializer blocks 217_1 to 217_16, which are electrically connected to the contact array 212_1 via electrical connectors that pass through the thickness of the substrate 211. The 16 serializer / deserializer blocks 216_1 to 216_16 are electrically coupled to the 16 serializer / deserializer blocks 217_1 to 217_16 via bus processing units 218_1 to 218_16, respectively. In this embodiment, each serializer / deserializer block (216 or 217) is implemented using eight serial differential transmitters (TX) and eight serial differential receivers (RX). To transmit electrical signals from the serializer / deserializer block 217 to the ASIC 240, a total of 8×16×2=256 electrical differential signal contacts 212_1 may be used, in addition to 8×17×2=272 ground (GND) contacts 212_1. As will be appreciated by those skilled in the art, other contact arrangements that beneficially reduce crosstalk may also be used, such as placing a ground contact between each pair of TX and RX contacts. The transmitter contacts are collectively referred to as 340, the receiver contacts are collectively referred to as 342, and the ground contacts are collectively referred to as 344.

[0283] The electrical contacts of the SerDes blocks 216_1 to 216_12 and 217_1 to 217_12 have a fine pitch, and the minimum distance between adjacent terminals may be, for example, in the range of 40 μm to 200 μm. The electrical contacts 212_1 have a coarse pitch, and the minimum distance between adjacent terminals may be, for example, in the range of 200 μm to 1 mm.

[0284] Figure 11 FIG3 is a schematic side view of an exemplary data processing system 350, which includes an integrated optical communication device 374, a package substrate 230, and a host-specific integrated circuit 240. The integrated optical communication device 374 and the host-specific integrated circuit 240 are mounted on the top side of the package substrate 230. The integrated optical communication device 374 includes a first optical connector 356 that allows an optical signal transmitted in an optical fiber to be coupled to the integrated optical communication device 374, wherein a portion of the optical fiber connected to the first optical connector 356 is located in an area facing the bottom side of the package substrate 230.

[0285] The integrated optical communication device 374 includes a photonic integrated circuit 352, a combination of a driver and transimpedance amplifier (D / T) 354, a first serializer / deserializer module 216, a second serializer / deserializer module 217, a first optical connector 356, a control module 358, and a substrate 360. The host-specific integrated circuit 240 includes an embedded third serializer / deserializer module 247.

[0286] In this example, the photonic integrated circuit 352, the driver and transimpedance amplifier 354, the first serializer / deserializer module 216, and the second serializer / deserializer module 217 are mounted on the top side of the substrate 360. In some embodiments, the driver and transimpedance amplifier 354, the first serializer / deserializer module 216, and the second serializer / deserializer module 217 can be monolithically integrated into a single electrical chip. A first optical connector 356 is optically coupled to the bottom side of the photonic integrated circuit 352. A control module 358 is electrically coupled to electrical terminals arranged on the bottom side of the substrate 360, while the photonic integrated circuit 352 is connected to electrical terminals arranged on the top side of the substrate 360. The control module 358 is electrically coupled to the photonic integrated circuit 352 via an electrical connector 362 that passes through the thickness of the substrate 360. In some embodiments, the substrate 360 ​​can be removably connected to the packaging substrate 230, for example, using a compression interposer or a planar grid array.

[0287] The photonic integrated circuit 352 is electrically coupled to the driver and transimpedance amplifier 354 via an electrical connector 364 on or in the substrate 360. The driver and transimpedance amplifier 354 is electrically coupled to the first serializer / deserializer module 216 via an electrical connector 366 on or in the substrate 360. The second serializer / deserializer module 216 has electrical terminals 370 on its bottom side, which are electrically coupled to electrical terminals 366 disposed on the bottom side of the substrate 360 ​​via electrical connectors 368 that pass through the substrate 360 ​​in the thickness direction. The electrical terminals 370 have a fine pitch, while the electrical terminals 366 have a coarse pitch. The electrical terminals 366 are electrically coupled to the third serializer / deserializer module 247 via electrical connectors or traces 372 on or in the packaging substrate 230.

[0288] In some embodiments, the optical signal is converted to an electrical signal by the photonic integrated circuit 352, the electrical signal is conditioned by the first serializer / deserializer module 216 (or the second serializer / deserializer module 217), and processed by the host-specific integrated circuit 240. The host-specific integrated circuit 240 generates the electrical signal that is converted to an optical signal by the photonic integrated circuit 352.

[0289] Figure 12 3 is a schematic side view of an exemplary data processing system 380, which includes an integrated optical communication device 382, ​​a package substrate 230, and a host-specific integrated circuit 240. The integrated optical communication device 382 is similar to the integrated optical communication device 374 ( Figure 11 ), except that the transimpedance amplifier and driver are implemented in a chip 384 that is separate from the chip that houses the serializer / deserializer modules 216 and 217.

[0290] Figure 13FIG3 is a schematic side view of an exemplary data processing system 390, which includes an integrated optical communication device 402, a packaging substrate 230, and a host-specific integrated circuit (ASIC) (not shown). The integrated optical communication device 402 includes a photonic integrated circuit 392, a first serializer / deserializer (SDS) module 394, a second serializer / deserializer (SDS) module 396, a third serializer / deserializer (SDS) module 398, and a fourth serializer / deserializer (SDS) module 400, which are mounted on a substrate 410. The photonic integrated circuit 392 may include a transimpedance amplifier and a driver, or such amplifiers and / or drivers may be included in the serializer / deserializer (SDS) modules 394 and 398. The first serializer / deserializer (SDS) module 394 and the second serializer / deserializer (SDS) module 396 are located to the right of the photonic integrated circuit 392. The third serializer / deserializer (SDS) module 398 and the fourth serializer / deserializer (SDS) module 400 are located to the left of the photonic integrated circuit 392. The terms "left" and "right" herein refer to relative positions as shown in the figure. It will be appreciated that the system 390 can be positioned in any orientation such that the first serializer / deserializer module 394 and the second serializer / deserializer module 396 are not necessarily on the right side of the photonic integrated circuit 392, and the third serializer / deserializer module 398 and the fourth serializer / deserializer module 400 are not necessarily on the left side of the photonic integrated circuit 392.

[0291] The photonic integrated circuit 392 receives an optical signal from the first optical connector 404, generates a serial electrical signal based on the optical signal, and transmits the serial electrical signal to the first and second serializer / deserializer modules 394 and 398. The first and second serializer / deserializer modules 394 and 398 generate parallel electrical signals based on the received serial electrical signal and transmit the parallel electrical signals to the third and fourth serializer / deserializer modules 396 and 400, respectively. The third and fourth serializer / deserializer modules 396 and 400 generate serial electrical signals based on the received parallel electrical signals and transmit the serial electrical signals to electrical terminals 406 and 408, respectively, arranged on the bottom side of the substrate 410.

[0292] The first optical connector 404 is optically coupled to the bottom side of the photonic integrated circuit 392. In some embodiments, the optical connector 404 can also be placed on top of the photonic integrated circuit 392 and couple light to the top side of the photonic integrated circuit 392 (not shown). The first optical connector 404 is optically coupled to the second optical connector, which is in turn optically coupled to a plurality of optical fibers. Figure 13 As shown, the first optical connector 404, the second optical connector, and / or the optical fiber pass through an opening 412 in the packaging substrate 230. The electrical terminal 406 is arranged on the right side of the first optical connector 404, and the electrical terminal 408 is arranged on the left side of the first optical connector 404. The electrical terminals 406 and 408 are configured so that the substrate 410 can be removably coupled to the packaging substrate 230.

[0293] Figure 14 FIG4 is a schematic side view of an exemplary data processing system 420, which includes an integrated optical communication device 428, a packaging substrate 230, and a host-specific integrated circuit (not shown). The integrated optical communication device 428 includes a photonic integrated circuit 422 (which does not include a transimpedance amplifier and driver), a first serializer / deserializer module 394, a second serializer / deserializer module 396, a third serializer / deserializer module 398, and a fourth serializer / deserializer module 400, which are mounted on a substrate 410. The integrated optical communication device 428 includes a first set of transimpedance amplifier and driver circuits 424 located to the right of the photonic integrated circuit 422, and a second set of transimpedance amplifier and driver circuits 426 located to the left of the photonic integrated circuit 422. The first set of transimpedance amplifier and driver circuits 424 are located between the photonic integrated circuit 422 and the first serializer / deserializer module 394. The second set of transimpedance amplifier and driver circuits 424 are located between the photonic integrated circuit 422 and the third serializer / deserializer module 398.

[0294] In some embodiments, the integrated optical communication device 402 (or 408 ) can be modified so that the first optical connector 404 couples the optical signal to the top side of the photonic integrated circuit 392 (or 422 ).

[0295] Figure 32 FIG2 is a schematic side view of an exemplary data processing system 510, which includes an integrated optical communication device 512, a packaging substrate 230, and a host-specific integrated circuit (not shown). The integrated optical communication device 512 includes a substrate 514, which includes a first plate 516 and a second plate 518. The first plate 516 provides an electrical connector to fan out electrical contacts. The first plate 516 includes a first set of contacts arranged on a top surface and a second set of contacts arranged on a bottom surface, wherein the first set of contacts has a fine pitch and the second set of contacts has a coarse pitch. The second plate 518 provides a detachable connection to the packaging substrate 230. A photonic integrated circuit 524 is mounted on the bottom side of the first plate 516. A first optical connector 520 extends through an opening in the substrate 514 and couples optical signals to the top side of the photonic integrated circuit 524.

[0296] The first serializer / deserializer module 394, the second serializer / deserializer module 396, the third serializer / deserializer module 398, and the fourth serializer / deserializer module 400 are mounted on the top side of the first board 516. The photonic integrated circuit 524 is electrically coupled to the first and third serializer / deserializer modules 394 and 398 via an electrical connector 522 that passes through the substrate 514 in the thickness direction. For example, the electrical connector 522 can be implemented as a through-hole. In some examples, the driver and the transimpedance amplifier can be integrated into the photonic integrated circuit 524, or integrated into the serializer / deserializer modules 394 and 398. In some examples, the driver and the transimpedance amplifier can be implemented in a separate chip (not shown) located between the photonic integrated circuit 524 and the serializer / deserializer modules 394 and 398, similar to Figure 14 A control chip (not shown) may be provided to control the operation of the photonic integrated circuit 512.

[0297] Figure 15 yes Figure 14 4. A bottom view of an example of an integrated optical communication device 428. The photonic integrated circuit 422 includes modulator and photodetector blocks on both sides of a center line 432 in the longitudinal direction. The photonic integrated circuit 422 includes a photonic integrated circuit 392 disposed on the bottom side or the top side of the photonic integrated circuit (see FIG. Figure 32 ) of the optical fiber coupling region 430, wherein the optical fiber coupling region 430 includes a plurality of optical coupling elements 310, such as a receiver optical coupling element (RX), a transmitter optical coupling element (TX), and a remote optical power supply (e.g., Figure 1 103) optical coupling element (PS).

[0298] A complementary metal oxide semiconductor (CMOS) transimpedance amplifier and driver block 424 is arranged on the right side of the photonic integrated circuit 424, and a CMOS transimpedance amplifier and driver block 426 is arranged on the left side of the photonic integrated circuit 424. The first serializer / deserializer module 394 and the second serializer / deserializer module 396 are arranged on the right side of the CMOS transimpedance amplifier and driver block 424. The third serializer / deserializer module 398 and the fourth serializer / deserializer module 400 are arranged on the left side of the CMOS transimpedance amplifier and driver block 426.

[0299] In this example, each of the first, second, third, and fourth SerDes modules 394, 396, 398, 400 includes eight serial differential transmitter blocks and eight serial differential receiver blocks. The integrated optical communication device 428 has a width of approximately 3.5 mm and a length slightly greater than approximately 3.6 mm.

[0300] Figure 16 yes Figure 14FIG4 is a bottom view of an example of an integrated optical communication device 428, which also illustrates electrical terminals 406 and 408. As shown, electrical terminals 406 and 408 have a coarse pitch, where the minimum distance between terminals in the array of electrical terminals 406 or 408 is much greater than the minimum distance between terminals in the arrays of electrical terminals of the first, second, third, and fourth serializer / deserializer modules 394, 396, 398, and 400. For example, the array of electrical terminals 406 and 408 may be part of a compressive interposer having a pitch of approximately 400 μm between terminals.

[0301] In some embodiments, the electrical terminals (eg, 406 and 408) may be arranged as follows Figure 66 Configuration shown. Figure 66 A pad map 1020 is shown showing the locations of the various contact pads as viewed from the bottom of the package. The contact pads occupy an area of ​​approximately 9.8 mm x 9.8 mm, with 400 μm pitch pads used.

[0302] The middle rectangle 1022 is the cutout that connects the photonic integrated circuit to the optical device exiting the top of the module. The larger rectangle 1024 represents the photonic integrated circuit. The two gray rectangles 1026a and 1026b represent the circuitry in the serializer / deserializer chip 1028a. The two gray rectangles 1026c and 1026d represent the circuitry in another serializer / deserializer chip 1028b. The serializer / deserializer chip is located at the top of the package, and the photonic integrated circuit is located at the bottom of the package. The overlap between the photonic integrated circuit and the serializer / deserializer chips 1028a and 1028b is designed so that through-holes (not shown) can directly connect these integrated circuits through the package. In some embodiments, the serializer / deserializer chips 1028a, 1028b and / or other electronic integrated circuits can be placed around three or four sides of the optical connector (represented by rectangle 1022).

[0303] exist Figures 2 to 8 In the example of the data processing system shown in Figures 11 to 14 and 32, the integrated optical communication device (e.g., 210, 252, 262, 282, 374, 382, ​​402, 428, 512, which includes a photonic integrated circuit and a serializer / deserializer module) is mounted on the package substrate 230 on the same side (top side in the example shown in the figure) as the electronic processor integrated circuit (or host application-specific integrated circuit) 240. The data processing system can also be modified so that the integrated optical communication device is mounted on the side of the package substrate 230 opposite to the electronic processor integrated circuit (or host application-specific integrated circuit) 240. For example, the electronic processor integrated circuit 240 can be mounted on the top side of the package substrate 230, while the electronic processor integrated circuit 240 is mounted on the top side of the package substrate 230. Figures 2 to 8One or more integrated optical communication devices of the forms disclosed in , 11 to 14 and 32 may be mounted on the bottom side of the package substrate 230 .

[0304] Figure 17 4 is a schematic diagram illustrating four types of integrated optical communication devices that can be used in data processing system 440. In these examples, the integrated optical communication device does not include a serializer / deserializer module. At least some signal conditioning is performed by the serializer / deserializer module in a digital application-specific integrated circuit (ASIC). The integrated optical communication device is mounted on the side of the printed circuit board opposite the side where the digital application-specific integrated circuit is mounted, thereby allowing connector shorting.

[0305] In a first example, a data processing system includes a digital application-specific integrated circuit 444 mounted on the top side of a substrate 442, and an integrated optical communication device 448 mounted on the bottom side of a first circuit board. In some embodiments, the integrated optical communication device 448 includes a photonic integrated circuit 450 and a set of transimpedance amplifiers and drivers 452 mounted on the bottom side of a substrate 454 (e.g., a second circuit board). The top side of the photonic integrated circuit 450 is electrically coupled to the bottom side of the substrate 454. A first optical connector component 456 is optically coupled to the bottom side of the photonic integrated circuit 450. The first optical connector component 456 is configured to optically couple to a second optical connector component 458, which is optically coupled to a plurality of optical fibers (not shown). An electrical terminal array 460 is disposed on the top side of the substrate 454 and is configured to enable the integrated optical communication device 448 to be removably coupled to the substrate 442.

[0306] The optical signal from the optical fiber is processed by a photonic integrated circuit 450, which generates a serial electrical signal based on the optical signal. The serial electrical signal is amplified by a set of transimpedance amplifiers and drivers 452, which drive the output signal. The output signal is transmitted to a serializer / deserializer module 446 embedded in a digital application-specific integrated circuit 444.

[0307] In a second example, an integrated optical communication device 462 can be mounted on the bottom side of the substrate 442 to provide an optical / electrical communication interface between the optical fiber and the digital application specific integrated circuit 444. The integrated optical communication device 462 includes a photonic integrated circuit 464 mounted on the bottom side of the substrate 454 (e.g., a second circuit board). The top side of the photonic integrated circuit 464 is electrically coupled to the bottom side of the substrate 454. The first optical connector component 456 is optically coupled to the bottom side of the photonic integrated circuit 450. An array of electrical terminals 460 is arranged on the top side of the substrate 454 and is configured to enable the integrated optical communication device 462 to be removably coupled to the substrate 442. The integrated optical communication device 462 is similar to the integrated optical communication device 448, except that the photonic integrated circuit 464 or the serializer / deserializer module 446 includes a set of transimpedance amplifiers and driver circuitry. In some examples, the serializer / deserializer module 446 is configured to directly accept electrical signals emerging from the photonic integrated circuit 464, for example, by having a sufficiently high receiver input impedance to convert the photocurrent generated within the photonic integrated circuit 464 into a suitable voltage swing for further electrical processing. For example, the serializer / deserializer module 446 is configured to have a low transmitter output impedance and provide an output voltage swing that allows direct driving of an optical modulator embedded within the photonic integrated circuit 464.

[0308] In a third example, an integrated optical communication device 466 can be mounted on the bottom side of the substrate 442 to provide an optical / electrical communication interface between an optical fiber and the digital application-specific integrated circuit 444. The integrated optical communication device 466 includes a photonic integrated circuit 468 mounted on the top side of a substrate 470 (e.g., a second circuit board). The bottom side of the photonic integrated circuit 468 is electrically coupled to the top side of the substrate 470. The first optical connector component 456 is optically coupled to the bottom side of the photonic integrated circuit 468. An array of electrical terminals 460 is arranged on the top side of the substrate 470 and is configured to enable the integrated optical communication device 466 to be removably coupled to the substrate 442. In some examples, the photonic integrated circuit 468 or the serializer / deserializer module 446 includes a set of transimpedance amplifiers and driver circuitry. In some examples, the serializer / deserializer module 446 is configured to directly accept electrical signals emerging from the photonic integrated circuit 464.

[0309] In a fourth example, an integrated optical communication device 472 can be mounted on the bottom side of the substrate 442 to provide an optical / electrical communication interface between an optical fiber and the digital application specific integrated circuit 444. The integrated optical communication device 472 includes a photonic integrated circuit 474 and a set of transimpedance amplifiers and drivers 476, which are mounted on the top side of the substrate 470 (e.g., a second circuit board). The bottom side of the photonic integrated circuit 474 is electrically coupled to the top side of the substrate 470. The first optical connector component 456 is optically coupled to the bottom side of the photonic integrated circuit 468. An array of electrical terminals 460 is arranged on the top side of the substrate 470 and is configured to enable the integrated optical communication device 466 to be removably coupled to the substrate 442. The integrated optical communication device 472 is similar to the integrated optical communication device 466, except that neither the photonic integrated circuit 464 nor the serializer / deserializer module 446 includes a set of transimpedance amplifiers and driver circuitry, and the set of transimpedance amplifiers and drivers 476 are implemented as separate integrated circuits.

[0310] Figure 18 4 is a schematic diagram of an exemplary octal serializer / deserializer block 480 including eight serial differential transmitters (TX) 482 and eight serial differential receivers (RX) 484. Each serial differential receiver 484 receives a serial differential signal, generates a parallel signal based on the serial differential signal, and provides the parallel signal on a parallel bus 488. Each serial differential transmitter 482 receives a parallel signal from a parallel bus 488, generates a serial differential signal based on the parallel signal, and provides the serial differential signal on an output electrical terminal 490. The serializer / deserializer block 480 outputs and / or receives the parallel signals via a parallel bus interface 492.

[0311] In the above example, for example Figures 2 to 14 In the example shown in , the integrated optical communication device (e.g., 210, 252, 262, 282, 374, 382, ​​402, 428) includes a first serializer / deserializer module (e.g., 216, 394, 398) and a second serializer / deserializer module (e.g., 217, 396, 400). The first serializer / deserializer module is serially interfaced with the photonic integrated circuit, and the second serializer / deserializer module is serially interfaced with the electronic processor integrated circuit or the host application-specific integrated circuit (e.g., 240). In some embodiments, the electronic communication integrated circuit 215 includes a serializer / deserializer array that can be logically divided into a first sub-array of serializers / deserializers and a second sub-array of serializers / deserializers. The first sub-array of SerDes corresponds to a SerDes module (eg, 216, 394, 398), and the second sub-array of SerDes corresponds to a second SerDes module (eg, 217, 396, 400).

[0312] Figure 38is a schematic diagram of an exemplary octal serializer / deserializer block 480 coupled to the bus processing unit 218. The octal serializer / deserializer block 480 includes eight serial differential transmitters (TX1 to TX8) 482 and eight serial differential receivers (RX1 to RX4) 484. In some embodiments, the transmitters and receivers are divided such that transmitters TX1, TX2, TX3, TX4 and receivers RX1, RX2, RX3, RX4 form a first serializer / deserializer module 840, and transmitters TX5, TX6, TX7, TX8 and receivers RX5, RX6, RX7, RX8 form a second serializer / deserializer module 842. Serial electrical signals received at receivers RX1, RX2, RX3, RX4 are converted to parallel electrical signals and routed by the bus processing unit 218 to transmitters TX5, TX6, TX7, TX8, which convert the parallel electrical signals to serial electrical signals. For example, the photonic integrated circuit can send serial electrical signals to receivers RX1, RX2, RX3, and RX4, and the transmitters TX5, TX6, TX7, and TX8 can transmit serial electrical signals to an electronic processor integrated circuit or a host application-specific integrated circuit.

[0313] For example, the bus processing unit 218 may remap signal lanes and encode the signals so that the bit rate and / or modulation format of the serial signals output from transmitters TX5, TX6, TX7, and TX8 may be different from the bit rate and / or modulation format of the serial signals received at receivers RX1, RX2, RX3, and RX4. For example, four 1 Gbps NRZ serial signal lanes received by receivers RX1, RX2, RX3, and RX4 may be re-encoded and routed to transmitters TX5 and TX6 to output two 2×1 Gbps PAM4 serial signal lanes.

[0314] Similarly, the serial electrical signals received at receivers RX5, RX6, RX7, RX8 are converted to parallel electrical signals and routed by bus processing unit 218 to transmitters TX1, TX2, TX3, TX4, which convert the parallel electrical signals to serial electrical signals. For example, an electronic processor integrated circuit or a host application-specific integrated circuit can send the serial electrical signals to receivers RX5, RX6, RX7, RX8, and transmitters TX1, TX2, TX3, TX4 can transmit the serial electrical signals to a photonic integrated circuit.

[0315] For example, the bus processing unit 218 may remap signal lanes and encode the signals so that the bit rate and / or modulation format of the serial signals output from transmitters TX1, TX2, TX3, and TX4 may be different from the bit rate and / or modulation format of the serial signals received at receivers RX5, RX6, RX7, and RX8. For example, two 2×T ​​Gbps PAM4 serial signal lanes received by receivers RX5 and RX6 may be re-encoded and routed to transmitters TX5, TX6, TX7, and TX8 to output four T Gbps NRZ serial signal lanes.

[0316] Figure 39 FIG2 is a schematic diagram of another exemplary octal serializer / deserializer block 480 coupled to the bus processing unit 218, wherein the transmitters and receivers are divided such that transmitters TX1, TX2, TX5, TX6 and receivers RX1, RX2, RX5, RX6 form a first serializer / deserializer module 850, and transmitters TX3, TX4, TX7, TX8 and receivers RX3, RX4, RX7, RX8 form a second serializer / deserializer module 852. Serial electrical signals received at receivers RX1, RX2, RX5, RX6 are converted to parallel electrical signals and routed by the bus processing unit 218 to transmitters TX3, TX4, TX7, TX8, which convert the parallel electrical signals to serial electrical signals. For example, a photonic integrated circuit can transmit the serial electrical signals to receivers RX1, RX2, RX5, RX6, and transmitters TX3, TX4, TX7, TX8 can transmit the serial electrical signals to an electronic processor integrated circuit or a host application-specific integrated circuit.

[0317] Similarly, the serial electrical signals received at receivers RX3, RX4, RX7, and RX8 are converted to parallel electrical signals and routed by bus processing unit 218 to transmitters TX1, TX2, TX5, and TX6, which convert the parallel electrical signals to serial electrical signals. For example, an electronic processor integrated circuit or a host application-specific integrated circuit can send the serial electrical signals to receivers RX3, RX4, RX7, and RX8, while transmitters TX1, TX2, TX5, and TX6 can transmit the serial electrical signals to a photonic integrated circuit.

[0318] In some embodiments, the bus processing unit 218 may remap the channels of the signals and perform encoding on the signals so that the bit rate and / or modulation format of the serial signals output from the transmitters TX3, TX4, TX7, and TX8 may be different from the bit rate and / or modulation format of the serial signals received at the receivers RX1, RX2, RX5, and RX6. Similarly, the bus processing unit 218 may remap the channels of the signals and perform encoding on the signals so that the bit rate and / or modulation format of the serial signals output from the transmitters TX1, TX2, TX5, and TX6 may be different from the bit rate and / or modulation format of the serial signals received at the receivers RX4, RX7, and RX8.

[0319] Figure 38 and 39 Two examples are shown of how the receiver and transmitter can be partitioned to form a first serializer / deserializer module and a second serializer / deserializer module. The partitioning can be determined arbitrarily based on the application and is not limited to Figure 38 and 39 Example shown. The partitioning may be programmable and can be changed dynamically by the system.

[0320] Figure 19 is a schematic diagram of an exemplary electronic communication integrated circuit 480 including a first octal serializer / deserializer block 482 electrically coupled to a second octal serializer / deserializer block 484. For example, the electronic communication integrated circuit 480 may be used as Figure 2 and 3 The electronic communication integrated circuit 215 of the embodiment of the present invention. The first octal serializer / deserializer block 482 can be used as the first serializer / deserializer module 216, and the second octal serializer / deserializer block 484 can be used as the second serializer / deserializer module 217. For example, the first octal serializer / deserializer block 482 can receive 8 serial differential signals through electrical terminals provided on the bottom side of the block, and generate 8 sets of parallel signals based on the 8 serial differential signals, wherein each set of parallel signals is generated based on the corresponding serial differential signals. The first octal serializer / deserializer block 482 can adjust the serial electrical signals when converting them into 8 sets of parallel signals, such as performing clock and data recovery and / or signal equalization. The first octal serializer / deserializer block 482 transmits the 8 sets of parallel signals to the second octal serializer / deserializer block 484 via parallel buses 485 and 486. The second octal serializer / deserializer block 484 can generate eight serial differential signals based on the eight sets of parallel signals, where each serial differential signal is generated according to a corresponding set of parallel signals. The second octal serializer / deserializer block 484 can output the eight serial differential signals through electrical terminals arranged on the bottom side of the block, for example.

[0321] The multiple serializer / deserializer blocks may be electrically coupled to the multiple serializer / deserializer blocks via a bus processing unit, which may be, for example, a parallel bus of electrical channels, a statically or dynamically reconfigurable cross-connect device, or a remapping device (gearbox). Figure 33 is a schematic diagram of an exemplary electronic communication integrated circuit 530, which includes a first octal SerDes block 532 and a second octal SerDes block 534 electrically coupled to a third octal SerDes block 536 via a bus processing unit 538. In this example, the bus processing unit 538 is configured to enable switching of signals, allowing for remapping of signal routing, wherein an 8×50 Gbps serial electrical signal that uses NRZ modulation and is serially interfaced to the first and second octal SerDes blocks 532 and 534 is rerouted or combined into an 8×100 Gbps serial electrical signal that uses PAM4 modulation and is serially interfaced to the third octal SerDes block 536. An example of a bus processing unit 538 is shown in FIG. Figure 41A In some examples, the bus processing unit 538 enables N lanes of T Gbps serial electrical signals to be remapped to N / M lanes of M×T Gbps serial electrical signals, where N and M are positive integers and T is a real value, wherein the N serially interfaced electrical signals can be modulated using a first modulation format and the M serially interfaced electrical signals can be modulated using a second modulation format.

[0322] In some other examples, the bus processing unit 538 can allow for redundancy to increase reliability. For example, the first and second SerDes blocks 532 and 534 can be jointly configured to serially interface to a total of N lanes of T×N / (Nk) Gbps electrical signals, while the third SerDes block 536 can be configured to serially interface to N lanes of T Gbps electrical signals. The bus processing unit 538 can be configured to remap data from Nk lanes of the N lanes serially interfaced to the first and second SerDes blocks 532 and 534 (carrying a total bit rate of (Nk)×T×N / (Nk)=T×N) to the third SerDes block 536. In this way, the bus processing unit 538 allows for k of the N serially interfaced electrical links to the first and second SerDes blocks 532 and 534 to fail while still maintaining the total number of T×N Gbps of data serially interfaced to the third SerDes block 536. The number k is a positive integer. In some embodiments, k may be approximately 1% of N. In some other embodiments, k may be approximately 10% of N. In some embodiments, the bus processing unit 538 may be used to dynamically select Nk of the N serial interfacing electrical links to the first and second serializer / deserializer blocks 532 and 534 for remapping to the third serializer / deserializer block 536, for example, based on signal integrity and signal performance information extracted from the serial interfacing signals by the serializer / deserializer blocks 532 and 534. An example of a bus processing unit 538 is shown in FIG. Figure 41B As shown in FIG, N=16, k=2, and T=50 Gbps.

[0323] In some examples, using the redundancy techniques discussed above, the bus processing unit 538 remaps the N-lane T×N / (Nk) Gbps serial electrical signals to the N / M-lane M×T Gbps serial electrical signals. The bus processing unit 538 tolerates the failure of k of the N serially interfaced electrical links while still maintaining the total number of T×N Gbps of data serially interfaced with the third serializer / deserializer block 536.

[0324] Figure 20 is a functional block diagram of an exemplary data processing system 200, which may be used to implement, for example Figure 1 1 through 101_6. For illustrative purposes, and without limitation, data processing system 200 is shown as part of node 101_1. Data processing system 200 may be part of any other network element of system 100. Data processing system 200 includes an integrated communication device 210, a fiber optic connector assembly 220, a packaging substrate 230, and an electronic processor integrated circuit 240.

[0325] Connector assembly 220 includes connector 223 and optical fiber array 226. Connector 223 may include multiple individual optical fiber connectors 423_i (i belongs to {R1 ... RM; S1 ... SK; T1 ... TN}, where K, M, and N are positive integers). In some embodiments, some or all of the individual connectors 423_i may form a single physical entity. In some embodiments, some or all of the individual connectors 423_i may be separate physical entities. When operating as part of the network element 101_1 of the system 100, (i) connectors 423_S1 to 423_SK can be connected to the optical power supply 103, for example via the optical fiber link 102_6, to receive supply light; (ii) connectors 423_R1 to 423_RM can be connected to the transmitter of the node 101_2, for example via the link 102_1, to receive optical communication signals from the node 101_2; and (iii) connectors 423_T1 to 423_TN can be connected to the receiver of the node 101_2, for example via the link 102_1, to transmit optical communication signals to the node 101_2.

[0326] In some embodiments, the communication device 210 includes an electronic communication integrated circuit 215, a photonic integrated circuit 214, a connector component 213, and a substrate 211. The connector component 213 can include a plurality of individual connectors 413_i (i belonging to {R1 ... RM; S1 ... SK; T1 ... TN}, where K, M, and N are positive integers) to the photonic integrated circuit 214. In some embodiments, some or all of the individual connectors 413_i can form a single physical entity. In some embodiments, some or all of the individual connectors 413_i can be separate physical entities. As disclosed in U.S. patent application Ser. No. 16 / 816,171, the optical connectors 413_i are configured to optically couple light to the photonic integrated circuit 214 via an optical coupling interface 414, such as a vertical grating coupler, a steering mirror, or the like.

[0327] In operation, light entering the photonic integrated circuit 214 from the link 102_6 through the coupling interfaces 414_S1 to 414_SK can be split using an optical splitter 415. The optical splitter 415 can be an optical power splitter, an optical polarization splitter, an optical wavelength demultiplexer, or any combination or series thereof, for example, as disclosed in U.S. Patent No. 11 / 153,670 and U.S. Patent Application No. 16 / 888,890, filed on June 1, 2020 and published as US2021 / 0376950, the entire contents of which are incorporated herein by reference in their entirety. In some embodiments, one or more branching functions of the splitter 415 can be integrated into the optical coupling interface 414 and / or the optical connector 413. For example, in some embodiments, a polarization diversity vertical grating coupler can be configured to function as both a polarization splitter 415 and a portion of the optical coupling interface 414. In some other embodiments, an optical connector including a polarization diversity arrangement may function simultaneously as optical connector 413 and as polarization splitter 415 .

[0328] In some embodiments, a receiver 416 can be used to detect light at one or more outputs of splitter 415 to extract synchronization information as disclosed in U.S. Patent No. 11 / 153,670. In various embodiments, receiver 416 can include one or more pin photodiodes, one or more avalanche photodiodes, one or more auto-coherent receivers, or one or more analog (heterodyne / homodyne) or digital (intradyne) coherent receivers. In some embodiments, one or more electro-optical modulators 417 can be used to modulate data onto light at one or more outputs of splitter 415 for communication with other network elements.

[0329] Before exiting the photonic integrated circuit 214 through the optical coupling interfaces 414_T1 to 414_TN, the modulated light at the output of the modulators 417 can be multiplexed by polarization or wavelength using a multiplexer 418. In some embodiments, the multiplexer 418 is not used, i.e., the output of each modulator 417 can be coupled directly to the corresponding optical coupling interface 414.

[0330] At the receiver end, light entering the photonic integrated circuit 214 from, for example, link 101_2 through coupling interfaces 414_R1 to 414_RM can first be demultiplexed in polarization and / or wavelength using an optical demultiplexer 419. The output of the demultiplexer 419 is then individually detected using a receiver 421. In some embodiments, the demultiplexer 419 is not used, i.e., the output of each coupling interface 414_R1 to 414_RM can be directly coupled to a corresponding receiver 421. In various embodiments, the receiver 421 can include one or more pin photodiodes, one or more avalanche photodiodes, one or more auto-coherent receivers, or one or more analog (heterodyne / homodyne) or digital (intradyne) coherent receivers.

[0331] The photonic integrated circuit 214 is electrically coupled to the integrated circuit 215. In some embodiments, the photonic integrated circuit 214 provides a plurality of serial electrical signals to the first serializer / deserializer module 216; the first serializer / deserializer module 216 generates a plurality of sets of parallel electrical signals based on the serial electrical signals, wherein each set of parallel electrical signals is generated based on the corresponding serial electrical signal. The first serializer / deserializer module 216 conditions the serial electrical signals, demultiplexes them into a plurality of sets of parallel electrical signals, and sends the plurality of sets of parallel electrical signals to the second serializer / deserializer module 217 through the bus processing unit 218. In some embodiments, the bus processing unit 218 implements signal switching and performs line coding and / or error correction coding functions. An example of a bus processing unit 218 is shown in FIG. Figure 42 In display.

[0332] The second serializer / deserializer module 217 generates a plurality of serial electrical signals based on the plurality of sets of parallel electrical signals, wherein each serial electrical signal is generated based on a corresponding set of parallel electrical signals. The second serializer / deserializer module 217 transmits the serial electrical signals to the electrical terminal array 500 arranged on the bottom surface of the substrate 211 via an electrical connector that passes through the substrate 211 in the thickness direction. For example, the electrical terminal array 500 is configured to enable the integrated communication device 210 to be easily coupled to or detached from the packaging substrate 230.

[0333] In some embodiments, the electronic processor integrated circuit 240 includes a data processor 502 and an embedded third serializer / deserializer module 504. The third serializer / deserializer module 504 receives the serial electrical signal from the second serializer / deserializer module 217 and generates a plurality of parallel electrical signals based on the serial electrical signal, wherein each parallel electrical signal is generated based on a corresponding serial electrical signal. The data processor 502 processes the plurality of parallel signals generated by the third serializer / deserializer module 504.

[0334] In some embodiments, the data processor 502 generates multiple sets of parallel electrical signals, and the third serializer / deserializer module 504 generates serial electrical signals based on the multiple sets of parallel electrical signals, wherein each serial electrical signal is generated based on a corresponding set of parallel electrical signals. The serial electrical signals are sent to the second serializer / deserializer module 217, which generates multiple sets of parallel electrical signals based on the serial electrical signals, wherein each set of parallel electrical signals is generated based on a corresponding set of serial electrical signals. The second serializer / deserializer module 217 sends the multiple sets of parallel electrical signals to the first serializer / deserializer module 216 via the bus processing unit 218. The first serializer / deserializer module 216 generates serial electrical signals based on the multiple sets of parallel electrical signals, wherein each serial electrical signal is generated based on a corresponding set of parallel electrical signals. The first serializer / deserializer module 216 sends the serial electrical signals to the photonic integrated circuit 214. The optoelectronic modulator 417 modulates the optical signal based on the serial electrical signal, and the modulated optical signal is output from the photonic integrated circuit 214 through the optical coupling interfaces 414_T1 to 414_TN.

[0335] In some embodiments, the supply light from the optical power supply 103 includes an optical pulse train, and the synchronization information extracted by the receiver 416 can be used by the serializer / deserializer module 216 to align the electrical output signal of the serializer / deserializer module 216 with the corresponding copy of the corresponding optical pulse train at the output of the splitter 415 in the modulator 417. For example, the optical pulse train can be used as an optical power supply at the optical modulator. In some such embodiments, the first serializer / deserializer module 216 can include an interpolator or other electrical phase adjustment element.

[0336] Please refer to Figure 21 In some embodiments, data processing system 540 includes a housing or casing 542 having a front panel 544, a bottom panel 546, side panels 548 and 550, a rear panel 552, and a top panel (not shown). System 540 includes a printed circuit board 558 extending generally parallel to bottom panel 546. Data processing chip 554 is mounted on printed circuit board 558, where chip 554 can be, for example, a network switch, a central processing unit, a graphics processing unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application-specific integrated circuit (ASIC).

[0337] On the front panel 544 is a pluggable input / output interface 556 that allows the data processing chip 554 to communicate with other systems and devices. For example, the input / output interface 556 can receive an optical signal from outside the system 540 and convert the optical signal into an electrical signal for processing by the data processing chip 554. The input / output interface 556 can receive an electrical signal from the data processing chip 554 and convert the electrical signal into an optical signal that is transmitted to other systems or devices. For example, the input / output interface 556 can include one or more small form-factor pluggable (SFP), SFP+, SFP28, QSFP, QSFP28, or QSFP56 transceivers. The electrical signal output from the transceiver is routed to the data processing chip 554 via an electrical connector on or in the printed circuit board 558.

[0338] like Figures 21 to 29B , 69A, 70, 71A, 72, 72A, 74A, 75A, 75C, 76, 77A, 77B, 78, 96 to 98, 100, 110, 112, 113, 115, 117 to 122, 125A to 127, 129 to 131, various embodiments can have various shapes and sizes. For example, in some embodiments, the top and bottom panels 546 can have the largest area; in other embodiments, the side panels 548 and 550 can have the largest area; and in other embodiments, the front panel 544 and the rear panel 552 can have the largest area. In various embodiments, the printed circuit board 558 can be made substantially parallel to the two side panels, for example, as shown in FIG. Figure 21 The data processing system 540 shown can stand on one of its side panels during normal operation (such that the side panel 550 is at the bottom and the bottom panel 546 is at the side). In various embodiments, the data processing system 540 can include two or more printed circuit boards, some of which can be generally parallel to the bottom panel and some of which can be generally parallel to the side panels. For example, vertical circuit boards are used in some computer systems for machine learning / artificial intelligence applications to be inserted into the system. As used herein, the distinction between "front" and "back" is based on where most of the input / output interfaces 556 are located, rather than what a user might think of as the front or back of the data processing system 540.

[0339] Figure 225 is a top view of an exemplary data processing system 560, which includes a housing 562 having side panels 564 and 566 and a rear panel 568. System 560 includes a vertically mounted printed circuit board 570, which also serves as a front panel. The surface of printed circuit board 570 is substantially perpendicular to the bottom panel of housing 562. The term "substantially perpendicular" means that if a first surface is substantially perpendicular to a second surface, the angle between the first surface and the second surface is in the range of 85° to 95°, taking into account manufacturing and assembly tolerances. A data processing chip 572 and an integrated communication device 574 are mounted on printed circuit board 570. In some examples, data processing chip 572 and integrated communication device 574 are mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached (e.g., electrically coupled) to printed circuit board 570. Data processing chip 572 can be, for example, a network switch, a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processor, an artificial intelligence accelerator, a digital signal processor (DSP), a microcontroller, or an application-specific integrated circuit (ASIC). The heat sink 576 is disposed on the data processing chip 572 .

[0340] In some embodiments, the integrated communication device 574 includes a photonic integrated circuit 586 and an electronic communication integrated circuit 588 mounted on a substrate 594. The electronic communication integrated circuit 588 includes a first serializer / deserializer module 590 and a second serializer / deserializer module 592. The printed circuit board 570 can be similar to the package substrate 230 (e.g., Figure 2 、 4 , 11-14), data processing chip 572 can be similar to electronic processor integrated circuit or application-specific integrated circuit 240, and integrated communication device 574 can be similar to integrated communication devices 210, 252, 374, 382, ​​402, 428. In some embodiments, integrated communication device 574 is soldered to printed circuit board 570. In some other embodiments, integrated communication device 574 is removably connected to printed circuit board 570, for example, via a flat grid array or compression interposer. The associated fixing means are not shown in the figure and may include a snap-on or screw-in mechanism.

[0341] In some examples, the integrated communication device 574 includes a photonic integrated circuit without a serializer / deserializer module, and a driver / transimpedance amplifier (TIA) is provided separately. In some examples, the integrated communication device 574 includes a photonic integrated circuit and a driver / transimpedance amplifier, but does not include a serializer / deserializer module.

[0342] The integrated communication device 574 includes a first optical connector 578 configured to receive a second optical connector 580 coupled to a bundle of optical fibers 582. The integrated communication device 574 is electrically coupled to the data processing chip 572 via electrical connectors or traces 584 on or in the printed circuit board 570. Because both the data processing chip 572 and the integrated communication device 574 are mounted on the printed circuit board 570, there is no need to electrically couple the transceiver 556 to the printed circuit board 570. Figure 21 The electrical connector or trace 584 can be made shorter than the electrical connector for the data processing chip 554 in the housing. Using a shorter electrical connector or trace 584 allows for signals with higher data rates, lower noise, lower distortion, and / or lower crosstalk. Mounting the printed circuit board 570 perpendicular to the bottom panel of the housing makes the integrated communication device 574 more accessible, i.e., the integrated communication device 574 can be removed and reconnected, for example, without having to remove the housing from the rack.

[0343] In some examples, the bundle of optical fibers 582 may be securely attached to the photonic integrated circuit 586 without the use of the first and second optical connectors 578 , 580 .

[0344] The printed circuit board 570 can be secured to the side panels 564 and 566 and the bottom and top panels of the housing using, for example, brackets, screws, clips, and / or other types of fastening mechanisms. The surface of the printed circuit board 570 can be oriented perpendicular to the bottom panel of the housing or angled (e.g., between -60° and 60°) relative to the vertical (vertical direction perpendicular to the bottom panel). The printed circuit board 570 can have multiple layers, with the outermost layer (i.e., the layer facing the user) having an aesthetically pleasing exterior surface texture.

[0345] The first optical connector 578, the second optical connector 580 and the bundle 582 of optical fibers may be connected to Figure 2 、 4 and similarly for 11 through 16. As described above, the bundle of optical fibers 582 can include 10 or more optical fibers, 100 or more optical fibers, 500 or more optical fibers, or 1000 or more optical fibers. The optical signals provided to the photonic integrated circuit 586 can have a high total bandwidth, for example, about 1.6 Tbps or about 12.8 Tbps or more.

[0346] Although Figure 22 One integrated communication device 574 is shown, but additional integrated communication devices 574 may be present, electrically coupled to the data processing chip 572. The data processing system 560 may include a second printed circuit board (not shown) parallel to the bottom panel of the housing 562. The second printed circuit board may support other optical and / or electronic devices, such as storage devices, memory chips, controllers, power modules, fans, and other cooling devices.

[0347] In the data processing system 540 (such as Figure 21 In some examples (such as those shown in FIG5 ), the transceiver 556 may include a circuit system (such as an integrated circuit) that performs some type of processing on the signal and / or the data contained in the signal. The signal output from the transceiver 556 needs to be routed to the data processing chip 554 through a longer signal path, thereby limiting the data rate. In some data processing systems, the data processing chip 554 outputs processed data, which is routed to a transceiver and transmitted to another system or device. Similarly, the signal output from the data processing chip 554 needs to be routed to the transceiver 556 through a longer signal path, thereby limiting the data rate. In contrast, in a data processing system 560 (such as FIG5 Figure 22 As shown in FIG, the signal path for electrical signal transmission between the integrated communication device 574 and the data processing chip 572 is shorter, thereby supporting a higher data rate.

[0348] Figure 23 FIG6 is a top view of an exemplary data processing system 600, which includes a housing 602 having side panels 604 and 606 and a rear panel 608. System 600 includes a vertically mounted printed circuit board 610 serving as a front panel. The surface of printed circuit board 610 is generally perpendicular to the bottom panel of housing 602. Data processing chip 572 is mounted on the inside of printed circuit board 610, and integrated communication device 612 is mounted on the outside of printed circuit board 610. In some examples, data processing chip 572 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to printed circuit board 610. In some embodiments, integrated communication device 612 is soldered to printed circuit board 610. In some other embodiments, integrated communication device 612 is removably connected to printed circuit board 610, for example, via a flat grid array or a compression interposer. The associated fixing means, which may include a snap-on or screw-in mechanism, are not shown. A heat sink 576 is disposed on data processing chip 572.

[0349] In some embodiments, the integrated communication device 612 includes a photonic integrated circuit 614 and an electronic communication integrated circuit 588 mounted on a substrate 618. The electronic communication integrated circuit 588 includes a first serializer / deserializer module 590 and a second serializer / deserializer module 592. The integrated communication device 612 includes a first optical connector 578 configured to receive a second optical connector 580 coupled to an optical fiber 582. The integrated communication device 612 is electrically coupled to the data processing chip 572 via an electrical connector or trace 616 that passes through the thickness of the printed circuit board 610. Because both the data processing chip 572 and the integrated communication device 612 are mounted on the printed circuit board 610, the electrical connector or trace 616 can be made shorter, thereby resulting in a signal with a higher data rate, lower noise, lower distortion, and / or lower crosstalk. Mounting the integrated communication device 612 on the exterior of the printed circuit board 610 perpendicular to the housing bottom panel makes it accessible from outside the housing, making the integrated communication device 612 easier to access, such as remove and reconnect, without removing the housing from the rack.

[0350] In some examples, the photonic integrated circuit of the integrated communication device 612 does not include a serializer / deserializer module, and the driver and transimpedance amplifier (TIA) are provided separately. In some examples, the integrated communication device 612 includes a photonic integrated circuit and a driver / transimpedance amplifier, but no serializer / deserializer module. In some examples, the bundle of optical fibers 582 can be securely attached to the photonic integrated circuit 614 without using the first and second optical connectors 578, 580.

[0351] In some examples, the data processing chip 572 is mounted on the back side of the substrate, while the integrated communication device 612 is removably attached to the front side of the substrate, where the substrate provides a high-speed connection between the data processing chip 572 and the integrated communication device 612. For example, the substrate can be attached to the front side of a printed circuit board, where the printed circuit board includes an opening that allows the data processing chip 572 to be mounted on the back side of the substrate. The printed circuit board can provide power from the motherboard to the substrate (and thus to the data processing chip 572 and the integrated communication device 612), and allows the data processing chip 572 and the integrated communication device 612 to connect to the motherboard using a low-speed electrical link.

[0352] The printed circuit board 610 can be secured to the side panels 604 and 606 and the bottom and top panels of the housing using, for example, brackets, screws, clips, and / or other types of fastening mechanisms. The surface of the printed circuit board 610 can be perpendicular to the bottom panel of the housing or angled (e.g., between -60° and 60°) relative to the vertical direction (vertical direction perpendicular to the bottom panel). The printed circuit board 610 can have multiple layers, with the outermost layer (i.e., the user-facing layer) not covered by the integrated communication device 612 having an aesthetically pleasing outer surface texture.

[0353] the following Figures 24 to 27 Four general designs are described in which the data processing chip is located near the input / output communication interface. Figure 24 6 is a top view of an exemplary data processing system 630, in which a data processing chip 640 is mounted near an optical / electrical communication interface 644 to enable a high-bandwidth data path (e.g., 1, 10, or more gigabits per second per data path) between the data processing chip 640 and the optical / electrical communication interface 644. In this example, the data processing chip 640 and the optical / electrical communication interface 644 are mounted on a circuit board 642, which serves as a front panel of a housing 632 in the system 630, thereby allowing optical fibers to be easily coupled to the optical / electrical communication interface 644. In some examples, the data processing chip 640 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board 642.

[0354] Housing 632 has side panels 634 and 636, a rear panel 638, a top panel, and a bottom panel. In some examples, circuit board 642 is perpendicular to the bottom panel. In some examples, the angle of circuit board 642 relative to the vertical direction of the bottom panel is in a range of -60° to 60°. The side of circuit board 642 facing the user has an aesthetically pleasing exterior surface.

[0355] The optical / electrical communication interface 644 is electrically coupled to the data processing chip 640 via electrical connectors or traces 646 on or in the circuit board 642. The circuit board 642 may be a printed circuit board having one or more layers. The electrical connectors or traces 646 may be signal lines printed on one or more layers of the printed circuit board 642 and implement a high-bandwidth data path (e.g., one or more gigabits per second per data path) between the data processing chip 640 and the optical / electrical communication interface 644.

[0356] In the first example, the data processing chip 640 receives electrical signals from the optical / electrical communication interface 644 but does not transmit electrical signals to the optical / electrical communication interface 644. In the second example, the data processing chip 640 receives electrical signals from the optical / electrical communication interface 644 and transmits electrical signals to the optical / electrical communication interface 644. In the first example, the optical / electrical communication interface 644 receives an optical signal from an optical fiber, generates an electrical signal based on the optical signal, and transmits the electrical signal to the data processing chip 640. In the second example, the optical / electrical communication interface 644 also receives an electrical signal from the data processing chip, generates an optical signal based on the electrical signal, and transmits the optical signal to the optical fiber.

[0357] Optical connector 648 is used to couple optical signals from an optical fiber to optical / electrical communication interface 644. In this example, optical connector 648 passes through an opening in circuit board 642. In some examples, optical connector 648 is securely fastened to optical / electrical communication interface 644. In some examples, optical connector 648 is configured to be removably coupled to optical / electrical communication interface 644, for example, using a pluggable and releasable mechanism, which may include one or more snap-on or screw-on mechanisms. In some other examples, an array of ten or more optical fibers is securely or fixedly attached to optical connector 648.

[0358] The optical / electrical communication interface 644 may be similar to, for example, the integrated communication device 210 ( Figure 2 )、252( Figure 4 )、374( Figure 11 )、382( Figure 12 )、402( Figure 13 ) and 428( Figure 14 In some examples, the optical / electrical communication interface 644 can be similar to the integrated optical communication devices 448, 462, 466, 472 ( Figure 17 ), except that the optical / electrical communication interface 644 is mounted on the same side of the circuit board 642 as the data processing chip 640. The optical connector 648 may be similar to, for example, the first optical connector component 213 ( Figure 2 、 4 ), first optical connector 356 ( Figure 11 、 12 ), the first optical connector 404 ( Figure 13 、 14 ) and the first optical connector component 456 ( Figure 17 In some examples, a portion of the optical connector 648 may be a portion of the optical / electrical communication interface 644. In some examples, the optical connector 648 may also include a second optical connector component 223 ( Figure 2 、 4 )、458( Figure 17 ), which is light coupled to an optical fiber. Figure 24An optical connector 648 is shown extending through the circuit board 642. In some examples, the optical connector 648 can be short such that the optical fiber extends entirely or partially through the circuit board 642. In some examples, the optical connector is not attached vertically to the photonic integrated circuit that is part of the optical / electrical communication interface 644, but rather can be attached coplanarly to the photonic integrated circuit using means such as V-groove fiber attachments, tapered or non-tapered fiber edge coupling, etc., followed by a mechanism to direct light interfacing with the photonic integrated circuit in a direction generally perpendicular to the photonic integrated circuit, such as one or more generally 90 degree turning mirrors, one or more generally 90 degree bent optical fibers, etc. Any such solution is conceptually included in Figures 24 to 27 The vertical light coupling attachment is schematically visualized.

[0359] Figure 25 6 is a top view of an exemplary data processing system 650 in which a data processing chip 670 is mounted near an optical / electrical communication interface 652 to implement a high-bandwidth data path (e.g., 1, 10, or more gigabits per second per data path) between the data processing chip 670 and the optical / electrical communication interface 652. In this example, the data processing chip 670 and the optical / electrical communication interface 652 are mounted on a circuit board 654, which is located near a front panel 656 of a housing 658 in the system 630, thereby allowing optical fibers to be easily coupled to the optical / electrical communication interface 652. In some examples, the data processing chip 670 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board 654.

[0360] The housing 658 has side panels 660 and 662, a rear panel 664, a top panel, and a bottom panel. In some examples, the circuit board 654 and the front panel 656 are perpendicular to the bottom panel. In some examples, the circuit board 654 and the front panel 656 are angled relative to the vertical direction of the bottom panel in a range of -60° to 60°. In some examples, the circuit board 654 is substantially parallel to the front panel 656. For example, the angle between the surface of the circuit board 654 and the surface of the front panel 656 can be in a range of -5° to 5°. In some examples, the circuit board 654 is angled relative to the front panel 656, wherein the angle is in a range of -45° to 45°.

[0361] Optical / electrical communication interface 652 is electrically coupled to data processing chip 670 via electrical connectors or traces 666 on or in circuit board 654. Similar to system 630, the signal path between data processing chip 670 and optical / electrical communication interface 652 can be unidirectional or bidirectional.

[0362] Optical connector 668 is used to couple optical signals from an optical fiber to optical / electrical communication interface 652. In this example, optical connector 668 passes through an opening in front panel 656 and an opening in circuit board 654. Similar to system 630, optical connector 668 can be fixedly secured or releasably connected to optical / electrical communication interface 652.

[0363] The optical / electrical communication interface 652 may be similar to, for example, the integrated communication device 210 ( Figure 2 )、252( Figure 4 )、374( Figure 11 )、382( Figure 12 )、402( Figure 13 ) and 428( Figure 14 In some examples, the optical / electrical communication interface 652 can be similar to the integrated optical communication devices 448, 462, 466, 472 ( Figure 17 ), except that the optical / electrical communication interface 652 is mounted on the same side of the circuit board 654 as the data processing chip 640. The optical connector 668 may be similar to, for example, the first optical connector component 213 ( Figure 2 、 4 ), first optical connector 356 ( Figure 11 、 12 ), the first optical connector 404 ( Figure 13 、 14 ) and the first optical connector component 456 ( Figure 17 ). In some examples, the optical connector is not attached vertically to the photonic integrated circuit as part of the optical / electrical communication interface 652, but can be attached coplanarly to the photonic integrated circuit using means such as V-groove fiber attachment, tapered or non-tapered fiber edge coupling, etc., followed by a mechanism to direct the light interfacing with the photonic integrated circuit in a direction generally perpendicular to the photonic integrated circuit, such as one or more generally 90-degree turning mirrors, one or more generally 90-degree bent optical fibers, etc. In some examples, a portion of the optical connector 668 can be part of the optical / electrical communication interface 652. In some examples, the optical connector 668 can also include a second optical connector component 223 ( Figure 2 、 4 )、458( Figure 17 ), which is light coupled to an optical fiber. Figure 25 An optical connector 668 is shown passing through the front panel 656 and the circuit board 654. In some examples, the optical connector 668 can be very short so that the optical fiber passes entirely or partially through the front panel 656. The optical fiber can also pass entirely or partially through the circuit board 654.

[0364] exist Figure 24 and 25In the example shown, only one optical / electrical communication interface (544, 652) is shown. Systems 630, 650 may be understood to include multiple optical / electrical communication interfaces mounted on the same circuit board as the data processing chip to implement a high-bandwidth data path (e.g., 1, 10, or more gigabits per second per data path) between the data processing chip and each optical / electrical communication interface.

[0365] Figure 26A FIG6 is a top view of an exemplary data processing system 680 in which a data processing chip 682 is mounted adjacent to optical / electrical communication interfaces 684a, 684b, and 684c (collectively, 684) to implement a high-bandwidth data path (e.g., 1, 10, or more gigabits per second per data path) between the data processing chip 682 and each optical / electrical communication interface 684. The data processing chip 682 is mounted on a first side of a circuit board 686 that serves as a front panel of a housing 688 in the system 680. In some examples, the data processing chip 682 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board 686. The optical / electrical communication interface 684 is mounted on a second side of the circuit board 686, with the second side facing the exterior of the housing 688. In this example, the optical / electrical communication interface 684 is mounted on the exterior of the housing 688 so that optical fibers can be easily coupled to the optical / electrical communication interface 684.

[0366] Housing 688 has side panels 690 and 692, a rear panel 694, a top panel, and a bottom panel. In some examples, circuit board 686 is perpendicular to the bottom panel. In some examples, the angle of circuit board 686 relative to the vertical direction of the bottom panel is in the range of -60° to 60° (or -30° to 30°, -10° to 10°, or -1° to 1°).

[0367] Each optical / electrical communication interface 684 is electrically coupled to the data processing chip 682 via an electrical connector or trace 696 that passes through the thickness of the circuit board 686. For example, the electrical connector or trace 696 can be configured as a through-hole in the circuit board 686. Similar to systems 630 and 650, the signal path between the data processing chip 682 and each optical / electrical communication interface 684 can be unidirectional or bidirectional.

[0368] For example, the system 680 may be configured such that signals are transmitted unidirectionally between the data processing chip 682 and one of the optical / electrical communication interfaces 684, and signals are transmitted bidirectionally between the data processing chip 682 and the other optical / electrical communication interface 684. For example, the system 680 may be configured such that signals are transmitted unidirectionally from the optical / electrical communication interface 684A to the data processing chip 682, and are transmitted unidirectionally from the data processing chip to the optical / electrical communication interface 684B and / or the optical / electrical communication interface 684C.

[0369] Optical connectors 698A, 698B, and 698C (collectively referred to as 698) are used to couple optical signals from optical fibers to optical / electrical communication interfaces 684A, 684B, and 684C, respectively. Similar to systems 630 and 650, optical connector 698 can be securely fixed or detachably connected to optical / electrical communication interface 684.

[0370] The optical / electrical communication interface 684 may be similar to, for example, the integrated communication device 210 ( Figure 2 )、252( Figure 4 )、374( Figure 11 )、382( Figure 12 )、402( Figure 13 )、428( Figure 14 ) and 512( Figure 32 ), except that the optical / electrical communication interface 684 is mounted on the side of the circuit board 686 opposite the data processing chip 682. In some examples, the optical / electrical communication interface 684 can be similar to the integrated optical communication devices 448, 462, 466, 472 ( Figure 17 ). The optical connector 698 may be similar to, for example, the first optical connector component 213 ( Figure 2 、 4 ), first optical connector 356 ( Figure 11 、 12 ), the first optical connector 404 ( Figure 13 、 14 ), the first optical connector component 456 ( Figure 17 ) and the first optical connector component 520 ( Figure 32 ). In some examples, the optical connector is not attached vertically to the photonic integrated circuit as part of the optical / electrical communication interface 684, but can be attached coplanarly to the photonic integrated circuit using, for example, V-groove fiber attachments, tapered or non-tapered fiber edge coupling, etc., followed by a mechanism to direct light interfacing with the photonic integrated circuit in a direction generally perpendicular to the photonic integrated circuit, such as one or more generally 90-degree turning mirrors, one or more generally 90-degree bent optical fibers, etc. In some examples, a portion of the optical connector 668 can be part of the optical / electrical communication interface 652. In some examples, the optical connector 668 can also include a second optical connector component 223 ( Figure 2 、 4 )、458( Figure 17 ), which is light coupled to an optical fiber.

[0371] In some examples, the optical / electrical communication interface 684 is securely fastened (e.g., by soldering) to the circuit board 686. In some examples, the optical / electrical communication interface 684 is removably connected to the circuit board 686, for example, by using a mechanical mechanism such as one or more snap-on or screw-on mechanisms. An advantage of the system 680 is that if one of the optical / electrical communication interfaces 684 fails, the failed optical / electrical communication interface 684 can be replaced without opening the housing 688.

[0372] Figure 26B 6 is a top view of an exemplary data processing system 690b, wherein a data processing chip 691b is mounted adjacent to optical / electrical communication interfaces 692a, 692b, and 692c (collectively, 692) to implement a high-bandwidth data path (e.g., 1, 10, or more gigabits per second per data path) between the data processing chip 691b and each of the optical / electrical communication interfaces 692. The data processing chip 691b is mounted on a first side of a circuit board 693b that serves as a front panel of a housing 694b in the system 690b. In this example, the optical / electrical communication interface 692a is mounted on the first side of the circuit board 693b, and the optical / electrical communication interfaces 692b and 692c are mounted on a second side of the circuit board 693b, with the second side facing the exterior of the housing 694b. In this example, optical / electrical communication interfaces 692b and 692c are mounted on the outside of housing 694b so as to connect to an optical fiber at the front of housing 694b, while optical / electrical communication interface 692a is located inside housing 694b, for example, so as to connect to an optical fiber at the rear of housing 694b. In some examples, two or more optical / electrical communication interfaces 692 may be located inside housing 694b and connected to an optical fiber at the rear of housing 694b.

[0373] Housing 694b has side panels 695b and 696b, a rear panel 697b, a top panel, and a bottom panel. In some examples, circuit board 693b is perpendicular to the bottom panel. In some examples, the angle of circuit board 693b relative to the vertical direction of the bottom panel is in the range of -60° to 60° (or -30° to 30°, -10° to 10°, or -1° to 1°).

[0374] Each optical / electrical communication interface 692 is electrically coupled to the data processing chip 691b by an electrical connector or trace 698b that passes through the circuit board 693b in the thickness direction. For example, the electrical connector or trace 698b can be configured as a through hole of the circuit board 693b. In this example, the electrical connector or trace 698b extends to both sides of the circuit board 693b (for example, for connecting to the optical / electrical communication interface 692 located inside and outside the housing 694b). Similar to systems 630, 650, and 680, the signal path between the data processing chip 691b and each optical / electrical communication interface 692 can be unidirectional or bidirectional.

[0375] For example, the system 690b may be configured such that signals are transmitted unidirectionally between the data processing chip 691b and one of the optical / electrical communication interfaces 692, and signals are transmitted bidirectionally between the data processing chip 691b and the other optical / electrical communication interface 692. For example, the system 690b may be configured such that signals are transmitted unidirectionally from the optical / electrical communication interface 692a to the data processing chip 691b, and are transmitted unidirectionally from the data processing chip 691b to the optical / electrical communication interface 692b and / or the optical / electrical communication interface 692c.

[0376] Optical connectors 699a, 699b, 699c (collectively referred to as 699) are used to couple optical signals from optical fibers to optical / electrical communication interfaces 692a, 692b, 692c, respectively. Similar to systems 630, 650, and 680, optical connector 699 can be securely fixed or removably connected to optical / electrical communication interface 692. In this example, optical connectors 699b and 699c can be connected to optical fibers at the front of housing 694b, and optical connector 699a can be connected to optical fibers at the rear of housing 694b. In this example, optical connector 699a is connected to optical fibers 1000b connected to rear panel interface 1001b (e.g., backplane), which is mounted on rear panel 697b. In some examples, optical connector 699 can be securely or securely attached to communication interface 692. In some examples, optical connector 699 can be securely or securely attached to an optical fiber array.

[0377] The optical / electrical communication interface 692 may be similar to, for example, the integrated communication device 210 ( Figure 2 )、252( Figure 4 )、374( Figure 11 )、382( Figure 12 )、402( Figure 13 )、428( Figure 14 ) and 512( Figure 32 ), except that the optical / electrical communication interfaces 692b and 692c are mounted on the side of the circuit board 693b opposite to the data processing chip 691b. In some examples, the optical / electrical communication interface 692 can be similar to the integrated optical communication devices 448, 462, 466, 472 ( Figure 17 ). The optical connector 699 may be similar to, for example, the first optical connector component 213 ( Figure 2 、 4 ), first optical connector 356 ( Figure 11 、 12 ), the first optical connector 404 ( Figure 13 、 14 ), the first optical connector component 456 ( Figure 17 ) and the first optical connector component 520 ( Figure 32 ). In some examples, the optical connector is not attached vertically to the photonic integrated circuit as part of the optical / electrical communication interface 692, but can be attached coplanarly to the photonic integrated circuit using, for example, V-groove fiber attachments, tapered or non-tapered fiber edge coupling, etc., followed by a mechanism to direct light interfacing with the photonic integrated circuit in a direction generally perpendicular to the photonic integrated circuit, such as one or more generally 90-degree turning mirrors, one or more generally 90-degree bent optical fibers, etc. In some examples, a portion of the optical connector 699 can be part of the optical / electrical communication interface 692. In some examples, the optical connector 699 can also include a second optical connector component 223 ( Figure 2 、 4 )、458( Figure 17 ), which is light coupled to an optical fiber.

[0378] In some examples, the optical / electrical communication interface 692 is securely fixed (e.g., by soldering) to the circuit board 693b. In some examples, the optical / electrical communication interface 692 is removably connected to the circuit board 693b, for example, by using a mechanical mechanism such as one or more snap-on or screw-on mechanisms. An advantage of system 690b is that if one of the optical / electrical communication interfaces 692 fails, the failed optical / electrical communication interface 692 can be replaced without opening the housing 694b.

[0379] Figure 26C 6 is a top view of an exemplary data processing system 690c, wherein a data processing chip 691c is mounted adjacent to optical / electrical communication interfaces 692d, 692e, and 692f (collectively, 692) to implement a high-bandwidth data path (e.g., 1, 10, or more gigabits per second per data path) between the data processing chip 691c and each of the optical / electrical communication interfaces 692. The data processing chip 691c is mounted on a first side of a circuit board 693c, which serves as a front panel of a housing 694c in the system 690c. In this example, the optical / electrical communication interface 692d is mounted on the first side of the circuit board 693c, and the optical / electrical communication interfaces 692e and 692f are mounted on a second side of the circuit board 693c, with the second side facing the exterior of the housing 694c. In this example, optical / electrical communication interfaces 692e and 692f are mounted on the outside of housing 694c so as to connect to optical fibers at the front of housing 694c, while optical / electrical communication interface 692d is located inside housing 694c, for example, so as to connect to optical fibers at the rear of housing 694c. In some examples, two or more optical / electrical communication interfaces 692 may be located inside housing 694c and connected to optical fibers at the rear of housing 694c.

[0380] Housing 694c has side panels 695c and 696c, a rear panel 697c, a top panel, and a bottom panel. In some examples, circuit board 693c is perpendicular to the bottom panel. In some examples, the angle of circuit board 693c relative to the vertical direction of the bottom panel is in the range of -60° to 60° (or -30° to 30°, -10° to 10°, or -1° to 1°).

[0381] Each optical / electrical communication interface 692 is electrically coupled to the data processing chip 691c via an electrical connector or trace 698c that passes through the circuit board 693c in the thickness direction. For example, the electrical connector or trace 698c can be configured as a through-hole in the circuit board 693c. In this example, the electrical connector or trace 698c extends to both sides of the circuit board 693b (e.g., for connecting to the optical / electrical communication interface 692 located inside and outside the housing 694b). Similar to systems 630, 650, and 680, the signal path between the data processing chip 691c and each optical / electrical communication interface 692 can be unidirectional or bidirectional.

[0382] For example, the system 690c can be configured so that signals are transmitted unidirectionally between the data processing chip 691c and one of the optical / electrical communication interfaces 692, and signals are transmitted bidirectionally between the data processing chip 691c and the other optical / electrical communication interface 692. For example, the system 690c can be configured so that signals are transmitted unidirectionally from the optical / electrical communication interface 692d to the data processing chip 691c, and are transmitted unidirectionally from the data processing chip 691c to the optical / electrical communication interface 692e and / or the optical / electrical communication interface 692f.

[0383] Optical connectors 699d, 699e, and 699f (collectively referred to as 699) are used to couple optical signals from optical fibers to optical / electrical communication interfaces 692d, 692e, and 692f, respectively. Similar to systems 630, 650, and 680, optical connector 699 can be securely fixed or detachably connected to optical / electrical communication interface 692. In this example, optical / electrical communication interface 692d and optical connector 699d are connected to Figure 26BCompared with the optical / electrical communication interface 692a and the optical connector 699a, its orientation is different. The orientation change here refers to a 90-degree counterclockwise rotation. Other types of orientation changes (e.g., rotation, pitch, tilt, etc.) can also be implemented. Position changes (e.g., translation) and other types of position changes can also be used. In this example, optical connector 699e and optical connector 699f can be connected to the optical fiber at the front of the housing 694c, and optical connector 699d can be connected to the optical fiber at the rear of the housing 694c. In this example, optical connector 699d is connected to the optical fiber 1000c connected to the rear panel interface 1001c (e.g., backplane, etc.), and the rear panel interface 1001c is installed on the rear panel 697c.

[0384] The optical / electrical communication interface 692 may be similar to, for example, the integrated communication device 210 ( Figure 2 )、252( Figure 4 )、374( Figure 11 )、382( Figure 12 )、402( Figure 13 )、428( Figure 14 ) and 512( Figure 32 ), except that the optical / electrical communication interfaces 692e and 692f are mounted on the side of the circuit board 693c opposite to the data processing chip 691c. In some examples, the optical / electrical communication interface 692 can be similar to the integrated optical communication devices 448, 462, 466, 472 ( Figure 17 ). The optical connector 699 may be similar to, for example, the first optical connector component 213 ( Figure 2 、 4 ), first optical connector 356 ( Figure 11 、 12 ), the first optical connector 404 ( Figure 13 、 14 ), the first optical connector component 456 ( Figure 17 ) and the first optical connector component 520 ( Figure 32 ). In some examples, the optical connector is not attached vertically to the photonic integrated circuit as part of the optical / electrical communication interface 692, but can be attached coplanarly to the photonic integrated circuit using, for example, V-groove fiber attachments, tapered or non-tapered fiber edge coupling, etc., followed by a mechanism to direct light interfacing with the photonic integrated circuit in a direction generally perpendicular to the photonic integrated circuit, such as one or more generally 90-degree turning mirrors, one or more generally 90-degree bent optical fibers, etc. In some examples, a portion of the optical connector 699 can be part of the optical / electrical communication interface 692. In some examples, the optical connector 699 can also include a second optical connector component 223 ( Figure 2 、 4)、458( Figure 17 ), which is light coupled to an optical fiber.

[0385] In some examples, the optical / electrical communication interface 692 is securely fastened (e.g., by soldering) to the circuit board 693c. In some examples, the optical / electrical communication interface 692 is removably connected to the circuit board 693c, for example, by using a mechanical mechanism such as one or more snap-on or screw-on mechanisms. An advantage of the system 690c is that if one of the optical / electrical communication interfaces 692 fails, the failed optical / electrical communication interface 692 can be replaced without opening the housing 694c.

[0386] Figure 27 is a top view of an exemplary data processing system 700, wherein a data processing chip 702 is mounted adjacent to optical / electrical communication interfaces 704a, 704b, and 704c (collectively referred to as 704) to implement a high-bandwidth data path (e.g., 1, 10, or more gigabits per second per data path) between the data processing chip 702 and each optical / electrical communication interface 704. Figure 25 ), data processing chip 702 is mounted on a first side of circuit board 706, which is located near the front panel of housing 710 in system 700. In some examples, data processing chip 702 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to circuit board 706. Optical / electrical communication interface 704 is mounted on a second side of circuit board 708. In this example, optical / electrical communication interface 704 passes through an opening in front panel 708, allowing optical fibers to be easily coupled to optical / electrical communication interface 704.

[0387] Housing 710 has side panels 712 and 714, a rear panel 716, a top panel, and a bottom panel. In some examples, the angle between circuit board 706 and front panel 708 relative to the vertical direction of the bottom panel is in the range of -60° to 60°. In some examples, circuit board 706 is substantially parallel to front panel 708, for example, the angle between the surface of circuit board 706 and the surface of front panel 708 can be in the range of -5° to 5°. In some examples, circuit board 706 is angled relative to front panel 708, wherein the angle is in the range of -45° to 45°.

[0388] For example, an angle may refer to a rotation about an axis parallel to the larger dimension of the front panel (e.g., the width dimension in a typical 1U, 2U, or 4U rack-mounted device), or a rotation about a shorter dimension parallel to the front panel (e.g., the height dimension in a 1U, 2U, or 4U rack-mounted device). An angle may also refer to a rotation about an axis in any other direction. For example, the circuit board 706 is positioned relative to the front panel so that components such as interconnect modules (including optical modules or photonic integrated circuits) mounted on or attached to the circuit board 706 can be accessed through the front side, or through one or more openings in the front panel, or by opening the front panel to expose the components, without having to separate the top panel or side panels from the bottom panel. This orientation of the circuit board (or a substrate with a data processing module mounted thereon) relative to the front panel also applies to Figure 21 to 2 Examples of 6, 28B to 29B, 69A, 70, 71A, 72, 73A, 74A, 75A, 75C, 76, 77A, 77B, 78, 96 to 98, 100, 110, 112, 113, 115, 117 to 122, 125A to 127, and 129 to 131.

[0389] Similar to system 680 ( FIG. 26 ), each optical / electrical communication interface 704 is electrically coupled to the data processing chip 702 via an electrical connector or trace 718 that passes through the circuit board 706 in the thickness direction. Figure 24 )、650( Figure 25 ) and 680 (Figure 26), the signal path between the data processing chip 702 and each optical / electrical communication interface 704 can be unidirectional or bidirectional.

[0390] Optical connectors 716a, 716b, 716c (collectively referred to as 716) are used to couple optical signals from optical fibers to optical / electrical communication interfaces 704a, 704b, 704c, respectively. Similar to systems 630, 650, and 680, optical connector 716 can be securely fixed or detachably connected to optical / electrical communication interface 704.

[0391] The optical / electrical communication interface 704 may be similar to, for example, the integrated communication device 210 ( Figure 2 )、252( Figure 4 )、374( Figure 11 )、382( Figure 12 )、402( Figure 13 )、428( Figure 14 ) and 512( Figure 32 ), except that the optical / electrical communication interface 704 is mounted on the side of the circuit board 706 opposite to the data processing chip 702. In some examples, the optical / electrical communication interface 704 can be similar to the integrated optical communication devices 448, 462, 466, 472 ( Figure 17). The optical connector 716 may be similar to, for example, the first optical connector component 213 ( Figure 2 、 4 ), first optical connector 356 ( Figure 11 、 12 ), the first optical connector 404 ( Figure 13 、 14 ), the first optical connector component 456 ( Figure 17 ) and the first optical connector component 520 ( Figure 32 ). In some examples, the optical connector is not attached vertically to the photonic integrated circuit as part of the optical / electrical communication interface 704, but can be attached coplanarly to the photonic integrated circuit using means such as V-groove fiber attachment, tapered or non-tapered fiber edge coupling, etc., followed by a mechanism to direct the light interfacing with the photonic integrated circuit in a direction generally perpendicular to the photonic integrated circuit, such as one or more generally 90-degree turning mirrors, one or more generally 90-degree bent optical fibers. In some examples, a portion of the optical connector 716 can be part of the optical / electrical communication interface 704. In some examples, the optical connector 716 can also include a second optical connector component 223 ( Figure 2 、 4 )、458( Figure 17 ), which is light coupled to an optical fiber.

[0392] In some examples, the optical / electrical communication interface 704 is securely fastened (e.g., by soldering) to the circuit board 706. In some examples, the optical / electrical communication interface 704 is removably connected to the circuit board 706, for example, by using a mechanical mechanism such as one or more snap-on or screw-on mechanisms. An advantage of the system 700 is that if one of the optical / electrical communication interfaces 704 fails, the failed optical / electrical communication interface 704 can be unplugged or disconnected from the circuit board 706 and replaced without opening the housing 710.

[0393] In some embodiments, the optical / electrical communication interface 704 does not protrude through an opening in the front panel 708. For example, Figure 77A 、 77B , 78, 125A, 125B, 129 and 130, each optical / electrical communication interface 704 can be located at a certain distance behind the front panel 708, and a fiber optic patch cord or pigtail can connect the optical / electrical communication interface 704 to the optical connector on the front panel 708. In some examples, Figure 77A 、 125A Similar to the example of 130 , the front panel 708 is configured to be removable or openable to allow maintenance of the communication interface 704 .

[0394] Figure 28A7 is a top view of an exemplary data processing system 720, wherein a data processing chip 722 is mounted near an optical / electrical communication interface 724 to implement a high-bandwidth data path (e.g., 1, 10, or more gigabits per second per data path) between the data processing chip 720 and the optical / electrical communication interface 724. The data processing chip 722 is mounted on a first side of a circuit board 730 that serves as a front panel of a housing 732 of the system 720. In some examples, the data processing chip 722 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board 730. The optical / electrical communication interface 724 is mounted on a second side of the circuit board 730, wherein the second side faces the exterior of the housing 732. In this example, the optical / electrical communication interface 724 is mounted on the exterior of the housing 732 so that an optical fiber 734 can be easily coupled to the optical / electrical communication interface 724.

[0395] Housing 732 has side panels 736 and 738, a rear panel 740, a top panel, and a bottom panel. In some examples, circuit board 730 is perpendicular to the bottom panel. In some examples, the angle of circuit board 730 relative to the vertical direction of the bottom panel is in the range of -60° to 60°.

[0396] The optical / electrical communication interface 724 includes a photonic integrated circuit 726 mounted on a substrate 728, which is electrically coupled to a circuit board 730. The optical / electrical communication interface 724 is electrically coupled to the data processing chip 722 via an electrical connector or trace 742 that passes through the thickness of the circuit board 730. For example, the electrical connector or trace 742 can be configured as a through-hole in the circuit board 730. Similar to systems 630, 650, 680, and 700, the signal path between the data processing chip 722 and the optical / electrical communication interface 724 can be unidirectional or bidirectional.

[0397] Optical connector 744 is used to couple the optical signal from optical fiber 734 to optical / electrical communication interface 724. Similar to systems 630, 650, 680, and 700, optical connector 744 can be fixedly or detachably connected to optical / electrical communication interface 724.

[0398] In some embodiments, the optical / electrical communication interface 724 may be similar to, for example, Figure 17 The optical signal from the optical fiber is processed by the photonic integrated circuit 726, which generates a serial electrical signal based on the optical signal. For example, the serial electrical signal is amplified by a set of transimpedance amplifiers and drivers (which can be part of the photonic integrated circuit 726 or a serializer / deserializer module in the data processing chip 722), which drives the output signal, which is transmitted to the serializer / deserializer module embedded in the data processing chip 722.

[0399] The optical connector 744 includes a first optical connector 746 and a second optical connector 748, wherein the second optical connector 748 is optically coupled to the optical fiber 734. The first optical connector 746 may be similar to, for example, the first optical connector component 213 ( Figure 2 、 4 ), first optical connector 356 ( Figure 11 、 12 ), the first optical connector 404 ( Figure 13 、 14 ), the first optical connector component 456 ( Figure 17 ), the first optical connector component 520 ( Figure 32 The second optical connector 748 may be similar to the second optical connector component 223 ( Figure 2 、 4 ) and 458( Figure 17 In some examples, optical connectors 746 and 748 can be formed as a single piece so that optical / electrical communication interface 724 is securely or fixedly attached to a bundle of optical fibers. In some examples, the optical connector is not attached vertically to photonic integrated circuit 726, but rather can be attached in-plane to the photonic integrated circuit using, for example, V-groove fiber attachment, tapered or non-tapered fiber edge coupling, followed by a mechanism to direct light interfacing with the photonic integrated circuit in a direction generally perpendicular to the photonic integrated circuit, such as one or more generally 90-degree turning mirrors, one or more generally 90-degree bent optical fibers, or the like.

[0400] In some examples, the optical / electrical communication interface 724 is securely fixed (e.g., by soldering) to the circuit board 730. In some examples, the optical / electrical communication interface 724 is removably connected to the circuit board 730, such as by a mechanical mechanism such as one or more snap-on or screw-on mechanisms. An advantage of the system 720 is that if the optical / electrical communication interface 724 fails, the failed optical / electrical communication interface 724 can be replaced without opening the housing 732.

[0401] Figure 28B is a top view of an exemplary data processing system 2800, which is Figure 28A 2800, except that the circuit board 730 is recessed from the front panel 2802 of the housing 732 of the system 2800. The photonic integrated circuit 726 is optically coupled to a first optical connector 2806 attached to the inside of the front panel 2802 via a fiber optic patch cord or pigtail 2804. The first optical connector 2806 is optically coupled to a second optical connector 2808, which is attached to the outside of the front panel 2802. The second optical connector 2808 is optically coupled to an external optical fiber 734.

[0402] The technique of optically coupling the photonic integrated circuit to the optical connector attached to the inside of the front panel using fiber optic patch cables or pigtails can also be applied to Figure 27 For example, the modified system may have a recessed substrate or circuit board, a plurality of co-packaged optical modules (e.g., 704) mounted on opposite sides of the data processing chip 702 relative to the substrate or circuit board, and fiber optic patch cables (e.g., 2804) that optically couple the co-packaged optical modules to the front panel.

[0403] exist Figure 28A and 28B In the example shown, the data processing chip 722 may be mounted on a substrate electrically coupled to a circuit board 730 .

[0404] like Figure 24 、 25 , 26, 27 and 28, the optical / electrical communication interfaces 644, 652, 684, 704 and 724 can be electrically coupled to the circuit boards 642, 654, 686, 706 and 730, respectively, using electrical contacts that include one or more of a spring-loaded element, a compression interposer and / or a planar grid array.

[0405] Figure 29A FIG2 is a schematic diagram of an exemplary data processing system 750 including a vertically mounted circuit board 752 that implements high-bandwidth data paths (e.g., 1, 10, or more gigabits per second per data path) between data processing chips 758 and optical / electrical communication interfaces 760. The data processing chips 758 and the optical / electrical communication interfaces 760 are mounted on the circuit board 752, with each data processing chip 758 electrically coupled to a corresponding optical / electrical communication interface 760. The data processing chips 758 are electrically coupled to each other via electrical connectors (e.g., electrical signal lines on one or more layers of the circuit board 752).

[0406] The data processing chip 758 may be similar to, for example, an electronic processor integrated circuit, a data processing chip, or a host-specific integrated circuit 240 ( Figure 2 、 4 , 6, 7, 11, 12), digital ASIC 444 ( Figure 17 ), data processor 502 ( Figure 20 )、Data processing chip 572( Figure 22 、 23 )、640( Figure 24 )、670( Figure 25 )、682( Figure 26A )、702( Figure 27 ) and 722 ( FIG. 28 ). Each data processing chip 758 can be, for example, a network switch, a central processing unit, a graphics processing unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application-specific integrated circuit (ASIC).

[0407] Although the figure shows that the optical / electrical communication interface 760 is installed on the side of the circuit board 752 facing the front panel 754, the optical / electrical communication interface 760 can also be installed on the side of the circuit board 752 facing the interior of the housing 756. The optical / electrical communication interface 760 can be similar to, for example, the integrated communication device 210 ( Figure 2 、 3 、10)、252( Figure 4 、 5 )、262( Figure 6 )、Integrated optical communication equipment 282( Figure 7-9 )、374( Figure 11 )、382( Figure 12 )、390( Figure 13 )、428( Figure 14 )、402( Figure 15 、 16 )、448、462、466、472( Figure 17 ), integrated communication equipment 574 ( Figure 22 )、612( Figure 23 ), and optical / electrical communication interface 644 ( Figure 24 )、652( Figure 25 )、684(Figure 26)、704( Figure 27 ).

[0408] The circuit board 752 is located near the front panel 754 of the housing 756, and the optical signal is coupled to the optical / electrical communication interface 760 through an optical path passing through an opening in the front panel 754. This allows a user to conveniently and removably connect a fiber optic cable 762 to the input / output interface 760. The position and orientation of the circuit board 752 relative to the housing 756 can be similar to, for example, the circuit board 654 ( Figure 25 ) and 706( Figure 27 )’s position and orientation.

[0409] In some embodiments, the data processing system 750 may include multiple types of optical / electrical communication interfaces 760. For example, some optical / electrical communication interfaces 760 may be mounted on the same side of the circuit board 752 as the corresponding data processing chip 758, and some optical / electrical communication interfaces 760 may be mounted on the opposite side of the circuit board 752 as the corresponding data processing chip 758. Figures 2 to 8 Similar to the examples in , 11 to 14, 20, 22 and 23, some optical / electrical communication interfaces 760 may include first and second serializer / deserializer modules, and the corresponding data processing chip 758 may include a third serializer / deserializer module. Figure 17Similar to the example in , some optical / electrical communication interfaces 760 may not include a serializer / deserializer module, and the corresponding data processing chip 758 may include a serializer / deserializer module. Some optical / electrical communication interfaces 760 may include multiple sets of transimpedance amplifiers and drivers, which are embedded in the photonic integrated circuit or in a separate chip outside the photonic integrated circuit. Some optical / electrical communication interfaces 760 do not include transimpedance amplifiers and drivers, where multiple sets of transimpedance amplifiers and drivers are included in the corresponding data processing chip 758. The data processing system 750 may also include an electrical communication interface that interfaces with a cable, such as a high-speed PCIe cable, an Ethernet cable, or a Thunderbolt cable. TM The electrical communication interface may include modules that perform various functions, such as conversion of communication protocols and / or conditioning of signals.

[0410] Other types of connections may also exist between circuit board 752 and other associated boards included in housing 756. For example, two or more circuit boards (e.g., vertically mounted circuit boards) may be connected, which may or may not include circuit board 752. For example, where at least one other circuit board (e.g., vertically mounted in housing 756) is connected to circuit board 752, one or more connection technologies may be employed. For example, an optical / electrical communication interface (e.g., similar to optical / electrical communication interface 760) may be used to connect data processing chip 758 to the other circuit boards. The interface used for such a connection may be located on the same side of circuit board 752 as that on which processing chip 758 is mounted. In some embodiments, the interface may be located on another portion of the circuit board (e.g., on a side opposite to that on which processing chip 758 is mounted). Connections may utilize other portions of circuit board 752 and / or one or more other circuit boards present in housing 756. For example, an interface may be located on an edge of one or more boards (e.g., the top edge of a vertically mounted circuit board), and the interface may be connected to one or more other interfaces (e.g., optical / electrical communication interface 760, another edge-mounted interface, etc.). Through such a connection, two or more circuit boards can connect, receive and send signals, etc.

[0411] like Figure 29A In the example shown, the circuit board 752 is placed near the front panel 754. In some examples, Figures 22 to 24 Similar to the examples in , 26 and 28, circuit board 752 can also serve as a front panel.

[0412] Figure 29B is a schematic diagram of an exemplary data processing system 2000, which illustrates Figures 26A to 26C and Figure 29ASome configurations and other capabilities described herein are described. System 2000 includes a vertically mounted printed circuit board 2002 (or, for example, a substrate) on which a data processing chip 2004 (e.g., an ASIC) is mounted, and a heat sink 2006 is thermally coupled to the data processing chip 2004. Optical / electrical communication interfaces are mounted on both sides of the printed circuit board 2002. Specifically, optical / electrical communication interface 2008 is mounted on the same side of the printed circuit board 2002 as the data processing chip 2004. In this example, optical / electrical communication interfaces 2010, 2012, and 2014 are mounted on opposite sides of the printed circuit board 2002. To transmit and receive signals (e.g., with other optical / electrical communication interfaces), each optical / electrical communication interface 2010, 2012, and 2014 is connected to an optical fiber 2016, 2018, and 2020, respectively. For example, electrical connection sockets / connectors may also be mounted on one or more sides of the printed circuit board 2002 for transmitting and receiving electrical signals. In this example, two electrical connectors 2022 and 2024 are mounted on the same side of printed circuit board 2002 as data processing chip 2004, and two electrical connectors 2026 and 2028 are mounted on the opposite side of printed circuit board 2002. In this example, electrical connector 2028 is connected to (or includes) timing module 2030, which provides various functions (e.g., regenerating data, retiming data, maintaining signal integrity, etc.). To transmit and receive electrical signals, each electrical connector 2022 to 2028 is connected to an electrical cable 2032, 2034, 2036, 2038, respectively. The cable can be of one or more types. For example, a jumper cable can be used to connect to one or more electrical connectors 2022 to 2028.

[0413] In this example, system 2000 includes vertically mounted line cards 2040, 2042, and 2044. In this particular example, line card 2040 includes an electrical connection receptacle / connector 2046 that connects to cable 2036, and line card 2042 includes an electrical connection receptacle / connector 2048 that connects to cable 2032. Line card 2044 includes an electrical connection receptacle / connector 2050. Each line card 2040, 2042, 2044 includes a pluggable optical module 2052, 2054, 2056 that can implement various interface technologies (e.g., QSFP, QSFP-DD, XFP, SFP, CFP).

[0414] In this particular example, printed circuit board 2002 is located near front panel 2058 of system 2000; however, printed circuit board 2002 can be located elsewhere within system 2000. Multiple printed circuit boards can also be included in system 2000. For example, a second printed circuit board 2060 (e.g., a backplane) is included in system 2000, and system 2000 is located near rear panel 2062. By positioning printed circuit board 2060 toward the rear, signals (e.g., data signals) can be sent to and received from other systems (e.g., another switch box) such as those located in the same switch rack or elsewhere as system 2000. In this example, data processing chip 2064 is mounted on printed circuit board 2060 and can perform various operations (e.g., data processing, preparing data for transmission, etc.). Similar to printed circuit board 2002 located at the front of system 2000, printed circuit board 2060 includes an optical / electrical communication interface 2066 (located on the same side of printed circuit board 2002 as data processing chip 2004), which is used to communicate with optical / electrical communication interface 2008 via optical fiber 2068. Printed circuit board 2060 includes an electrical connector 2070, which uses an electrical cable 2034 to send and receive electrical signals to and from electrical connector 2024. Printed circuit board 2060 can also communicate with other components of system 2000, such as one or more line cards. As shown, electrical connector 2072 located on printed circuit board 2060 uses an electrical cable 2074 to send and / or receive electrical signals to and from electrical connector 2050 of line card 2044. Similar to printed circuit board 2002, other components of system 2000 may include a timing module. For example, line cards 2040, 2042, and 2044 may include timing modules (identified by the symbols "*," "**," and "***," respectively). Similarly, second circuit board 2060 may include timing modules, such as timing modules 2076 and 2078, for regenerating data, retiming data, maintaining signal integrity, etc.

[0415] A feature of some of the systems described in this document is that the system's main data processing module, such as a switch chip in a switch server, and the communication interface module supporting the main data processing module are configured so as to be easily accessible to the user. Figures 21 to 29BIn the examples shown in Figures 69A, 70, 71A, 72, 72A, 74A, 75A, 75C, 76, 77A, 77B, 78, 96 to 98, 100, 110, 112, 113, 115, 117 to 122, 125A to 127, 129, 136 to 149, 159, and 160, the main data processing module and the communication interface module are located near the front panel, the rear panel, or both, and are easily accessible to the user through the front / rear panels. However, the main data processing module and the communication interface module can also be located near one or more side panels, the top panel, the bottom panel, or two or more of the above, depending on the placement of the system in the environment. In a plurality of racks (e.g., a rack-mounted device) including rack-mounted equipment Figure 76 and 86 ) system, the communication interface of each rack-mounted device (such as a co-packaged optical module) can be easily accessed and the housing can be opened to expose the internal components without removing the rack-mounted device from the rack.

[0416] In some embodiments, for a single rack of rack servers having open space at the front, rear, left, and right sides of the rack, in each rack server, a first main data processing module and a communication interface module may be placed to support the first main data processing module near the front panel; a second main data processing module and a communication interface module may be placed to support the second main data processing module near the left panel; a third main data processing module and a communication interface module may be placed to support the third main data processing module near the right panel; and a fourth main data processing module and a communication interface module may be placed to support the fourth main data processing module near the rear panel. The thermal solution, including the placement of fans and heat sinks, and the airflow configuration around the main data processing modules and the communication interface modules, may be adjusted accordingly.

[0417] For example, if the data processing server is mounted on the ceiling of a room or vehicle, the main data processing module and the communication interface module can be placed near the bottom panel for easy access. For example, if the data processing server is mounted below the floor of a room or vehicle, the main data processing module and the communication interface module can be placed near the top panel for easy access. The housing of the data processing system does not need to be box-shaped. For example, the housing can have curved walls, be shaped like a globe, or have any arbitrary three-dimensional shape.

[0418] Figure 30 is a block diagram of an exemplary data processing system 800, which may be similar to the system 200 described above. Figure 2 、 20 )、250( Figure 4 )、260( Figure 6 )、280( Figure 7 )、350( Figure 11 )、380( Figure 12 )、390( Figure 13 )、420( Figure 14 )、560( Figure 22 )、600( Figure 23 )、630( Figure 24 ) and 650( Figure 25 ). The first optical signal 770 is transmitted from the optical fiber to the photonic integrated circuit 772, which generates a first serial electrical signal 774 based on the first optical signal. The first serial electrical signal 774 is used to provide to the first serializer / deserializer module 776, which converts the first serial electrical signal 774 into a third group of parallel signals 778. The first serializer / deserializer module 776 performs adjustments when converting the serial electrical signal into a serial electrical signal, where the signal adjustment may include, for example, one or more of clock and data recovery and signal equalization. The third group of parallel signals 778 is used to provide to the second serializer / deserializer module 780, which generates a fifth serial electrical signal 782 based on the third group of parallel signals 778. The fifth serial electrical signal 782 is used to provide to the third serializer / deserializer module 784, which generates a seventh group of parallel signals 786 for providing to the data processor 788.

[0419] In some embodiments, the photonic integrated circuit 772, the first serializer / deserializer module 776, and the second serializer / deserializer module 780 can be mounted on a substrate of an integrated communication device, an optical / electrical communication interface, or an input / output interface module. The first serializer / deserializer module 776 and the second serializer / deserializer module 780 can be implemented in a single chip. In some embodiments, the third serializer / deserializer module 784 can be embedded in the data processor 788, or the third serializer / deserializer module 784 can be separate from the data processor 788.

[0420] The data processor 788 generates an eighth set of parallel signals 790, which are sent to the third serializer / deserializer module 784. The third serializer / deserializer module 784 generates a sixth serial electrical signal 792 based on the eighth set of parallel signals 790. The sixth serial electrical signal 792 is provided to the second serializer / deserializer module 780, which generates a fourth set of parallel electrical signals 794 based on the sixth serial electrical signals 792. The second serializer / deserializer module 780 may condition the serial electrical signals 792 when converting them into the fourth set of parallel electrical signals 794. The fourth set of parallel signals 794 is provided to the first serializer / deserializer module 780, which generates a second serial electrical signal 796 based on the fourth set of parallel signals 794 and sends it to the photonic integrated circuit 772. The integrated circuit 772 generates a second optical signal 798 based on the second serial electrical signal 796 and sends the second optical signal 798 to an optical fiber. The first and second optical signals 770 and 798 may propagate over the same or different optical fibers.

[0421] A feature of the system 800 is that the electrical signal paths traversed by the first, fifth, sixth, and second serial electrical signals 774, 782, 792, 796 are short (e.g., less than 5 inches), such that the first, fifth, sixth, and second serial electrical signals 782, 792 have high data rates (e.g., up to 50 Gbps).

[0422] Figure 31 is a schematic diagram of an exemplary high bandwidth data processing system 810, similar to systems 680 (FIG. 26), 700 ( Figure 27 ) and 750 (Figure 29). System 810 includes a data processor 812 for receiving signals from and sending signals to multiple photonic integrated circuits. System 810 includes a second photonic integrated circuit 814, a fourth serializer / deserializer module 816, a fifth serializer / deserializer module 818, and a sixth serializer / deserializer module 820. The operation of the second photonic integrated circuit 814, the fourth serializer / deserializer module 816, the fifth serializer / deserializer module 818, and the sixth serializer / deserializer module 820 can be similar to the operation of the first photonic integrated circuit 772, the first serializer / deserializer module 776, the second serializer / deserializer module 780, and the third serializer / deserializer module 784. The third serializer / deserializer module 784 and the sixth serializer / deserializer module 820 can be embedded in the data processor 812 or implemented in separate chips.

[0423] In some examples, the data processor 812 processes first data carried in a first optical signal received at the first photonic integrated circuit 772 and generates second data carried in a fourth optical signal output from the second photonic integrated circuit 814 .

[0424] Figure 30 and 31 In the example shown, three serializer / deserializer modules are included between the photonic integrated circuit and the data processor. It is generally understood that the same principle can be applied to a system with only one serializer / deserializer module between the photonic integrated circuit and the data processor.

[0425] In some embodiments, signals are transmitted unidirectionally from the photonic integrated circuit 772 to the data processor 788 ( Figure 30 In this case, the first serializer / deserializer module 776 may be replaced by a serial / parallel converter, the second serializer / deserializer module 780 may be replaced by a parallel / serial converter, and the third serializer / deserializer module 784 may be replaced by a serial / parallel converter. In some embodiments, the signal is received from the data processor 812 ( Figure 31 ) is transmitted unidirectionally to the second photonic integrated circuit 814. In this case, the sixth serializer / deserializer module 820 can be replaced by a parallel / serial converter, the fifth serializer / deserializer module 818 can be replaced by a serial / parallel converter, and the fourth serializer / deserializer module 816 can be replaced by a parallel / serial converter.

[0426] It will be understood by those skilled in the art that the description herein will be from one or more optical fibers, such as 226 ( Figure 2 and 4 ) or 272( Figure 6 and 7 ) is coupled to a photonic integrated circuit, such as 214 ( Figure 2 and 4 )、264( Figure 6 ) or 296( Figure 7 Various embodiments of the present invention may also couple light from a photonic integrated circuit to one or more optical fibers. This coupling direction reversibility is a general feature of at least some embodiments described herein, including some embodiments using polarization diversity.

[0427] The exemplary optical systems disclosed herein should be considered as only some of the many possible embodiments that can be used to perform polarization demultiplexing and independent array pattern scaling, array geometry rearrangement, spot size scaling, related optical elements using diffraction, refraction, reflection, and polarization-dependent incident angle adaptation, 3D waveguides, and 3D printed optical components. Other embodiments that achieve the same set of functions are also encompassed by the spirit of the present disclosure.

[0428] For example, optical fibers can be coupled to the edge of a photonic integrated circuit, such as using a fiber edge coupler. Signal conditioning (e.g., clock and data recovery, signal equalization, or encoding) can also be performed on serial signals, parallel signals, or both. Signal conditioning can also be performed during the conversion from serial to parallel signals.

[0429] In some embodiments, the above-described data processing systems may be used in systems such as data center switching systems, supercomputers, Internet Protocol (IP) routers, Ethernet switching systems, graphics processing workstations, and systems that apply artificial intelligence algorithms.

[0430] In the examples described above, in which the figures show a first serializer / deserializer module (e.g., 216) positioned adjacent to a second serializer / deserializer module (e.g., 217), it will be understood that the bus processing unit 218 can be located between the first and second serializer / deserializer modules and perform, for example, the switching, rerouting, and / or encoding functions described above.

[0431] In some embodiments, the data processing system includes multiple data generators that generate a large amount of data that is sent to a data processor via optical fiber for processing. For example, an autonomous vehicle (e.g., a car, truck, train, ship, boat, submarine, helicopter, drone, airplane, space rover, or spacecraft) or a robot (e.g., an industrial robot, an auxiliary robot, a medical surgical robot, a commodity distribution robot, a teaching robot, a cleaning robot, a cooking robot, a construction robot, or an entertainment robot) may include multiple high-resolution cameras and other sensors (e.g., LIDAR (light detection and ranging), radar) to generate video and other data with a high data rate. The camera and / or sensor can send video data and / or sensor data to one or more data processing modules via optical fiber. One or more data processing modules can use artificial intelligence technology (e.g., using one or more neural networks) to identify individual objects, sets of objects, scenes, individual sounds, sets of sounds, and / or situations in the vehicle environment and quickly decide on appropriate actions to control the vehicle or robot.

[0432] Figure 34 830 is a flow chart of an exemplary process for processing high-bandwidth data. Process 830 includes receiving, at 832, a first optical signal of a plurality of channels from a plurality of optical fibers. Process 830 includes generating, at 834, a plurality of first serial electrical signals based on the received optical signals, wherein each first serial electrical signal is generated based on one of the channels of the first optical signal. Process 830 includes generating, at 836, a plurality of first parallel electrical signals based on the plurality of first serial electrical signals, and conditioning the electrical signals, wherein each first parallel electrical signal is generated based on a corresponding first serial electrical signal. Process 830 includes generating, at 838, a plurality of second serial electrical signals based on the plurality of first parallel electrical signals, wherein each second serial electrical signal is generated based on a corresponding first parallel electrical signal.

[0433] In some embodiments, a data center includes multiple systems, each of which combines Figure 22 to 29 disclosed technology and corresponding description. Each system includes a vertically mounted printed circuit board, for example, 570 ( Figure 22 )、610( Figure 23 )、642( Figure 24 )、654( Figure 25 )、686(Figure 26)、706( Figure 27 ), 730 (FIG. 28), 752 (FIG. 29), used as the front panel of the housing or substantially parallel to the front panel. The printed circuit board is mounted with at least one data processing chip and at least one integrated communication device or optical / electrical communication interface. The integrated communication device or optical / electrical communication interface can be combined with Figures 2 to 22 and the disclosed techniques and corresponding descriptions in 30 to 34. Each integrated communication device or optical / electrical communication interface includes a photonic integrated circuit that receives an optical signal and generates an electrical signal based on the optical signal. The optical signal is transmitted to the photonic integrated circuit via one or more optical paths (or spatial paths), the optical path being provided by, for example, the core of an optical fiber cable, which can incorporate the techniques described in U.S. patent application Ser. No. 16 / 822,103. In addition, a large number of parallel optical paths (or spatial paths) can be arranged in a two-dimensional array using a connector structure, which can incorporate the techniques described in U.S. patent application Ser. No. 16 / 816,171.

[0434] Figure 35A An optical communication system 1250 is shown that provides high-speed communication between a first chip 1252 and a second chip 1254. Figures 2 to 5Similar to FIG17 , optical communication system 1250 utilizes a co-packaged optical interconnect module 1258 . Each of the first and second chips 1252 and 1254 can be a high-capacity chip, such as a high-bandwidth Ethernet switch chip. The first and second chips 1252 and 1254 communicate with each other via a fiber optic interconnect cable 1734 comprising multiple optical fibers. In some embodiments, fiber optic interconnect cable 1734 can include optical fiber cores that transmit data and control signals between the first and second chips 802 and 804 . As described in more detail below, in some examples, optical fibers 1730 and 1732, which can be partially bundled with interconnect cable 1734 , include one or more optical fiber cores that transmit optical power light from an optical power supply or photonic supply to a photonic integrated circuit that provides an optoelectronic interface for the first and second chips 1252 and 1254 . Fiber optic interconnect cable 1734 can include a single-core optical fiber or a multi-core optical fiber. Similarly, optical fibers 1730 and 732 can include a single-core optical fiber or a multi-core optical fiber. Each single-core fiber consists of a cladding and a core, usually made of glass with different refractive indices, such that the refractive index of the cladding is lower than that of the core, to establish a dielectric optical waveguide. Each multi-core fiber consists of a cladding and multiple cores, usually made of glass with different refractive indices, such that the refractive index of the cladding is lower than that of the core. In addition, more complex refractive index profiles can be used, such as refractive index grooves, multi-refractive index profiles, or gradient-varying refractive index profiles. More complex geometric structures can also be used, such as non-circular cores or claddings, photonic crystal structures, photonic bandgap structures, or nested antiresonant nodeless hollow core structures.

[0435] Figure 35A The example of FIG1 illustrates a switch-to-switch usage scenario. An external optical power supply, or photon supply 1256, provides an optical power signal, which can be, for example, continuous wave light, one or more periodic optical pulse trains, or one or more aperiodic optical pulse trains. The power light is provided from photon supply 1256 to a co-packaged optical interconnect module 1258 via optical fibers 1730 and 1732, respectively. For example, as described in U.S. Patent 11,153,670, optical power supply 1256 can provide both continuous wave light and pulsed light for data modulation and synchronization. This allows synchronization between first chip 1252 and second chip 1254.

[0436] For example, the photon supplier 1256 may correspond to Figure 1 The pulsed light from the photon supplier 1256 can be provided to Figure 20Link 102_6 of data processing system 200 in the optical fiber link 102_1. In some embodiments, photon supplier 1256 can provide a series of optical frame templates, where each optical frame template includes a respective frame header and a respective frame body, and the frame body includes a respective optical pulse train. Modulator 417 can load data into the corresponding frame body to convert the optical frame template sequence into a corresponding loaded optical frame sequence output via optical fiber link 102_1.

[0437] like Figure 35A The embodiment shown in uses the Figure 35B packaging solutions, and therefore with Figure 17 on the contrary, Figure 17 Substrates 454 and 460 are not used, and photonic integrated circuit 464 is directly attached to the serializer / deserializer module 446. Figure 35C Shows something like Figure 5 An embodiment in which the photonic integrated circuit 464 is directly attached to the serializer / deserializer 216.

[0438] Figure 36 An example of an optical communication system 1260 is shown, which uses a method similar to Figure 35A The co-packaged optical interconnect module 1258 shown in FIG. 1 provides high-speed communication between a high-capacity chip 1262 (e.g., an Ethernet switch chip) and multiple low-capacity chips 1264a, 1264b, and 1264c (e.g., multiple network interface chips connected to a computer server). The high-capacity chip 1262 communicates with the low-capacity chips 1264a, 1264b, and 1264c via a high-capacity fiber optic interconnect cable 1740. The high-capacity fiber optic interconnect cable 1740 then branches into several low-capacity fiber optic interconnect cables 1742a, 1742b, and 1742c, which are connected to the low-capacity chips 1264a, 1264b, and 1264c, respectively. This example illustrates a switch-to-server use case.

[0439] An external optical power supply or photon supply 1266 provides an optical power supply signal, which can be continuous wave light, one or more periodic optical pulse trains, or one or more non-periodic optical pulse trains. The power supply light is provided from the photon supply 1266 to the optical interconnect module 1258 via optical fibers 1744, 1746a, 1746b, and 1746c, respectively. For example, the optical power supply 1266 can provide pulsed light for data modulation and synchronization, as described in U.S. Patent No. 11,153,670. This allows the high-capacity chip 1262 to be synchronized with the low-capacity chips 1264a, 1264b, and 1264c.

[0440] Figure 37An optical communication system 1270 is shown that uses a mix of co-packaged optical interconnect modules 1258 similar to those shown in FIG. 35 and conventional pluggable optical interconnect modules 1272 to provide high-speed communications between a high-capacity chip 1262 (e.g., an Ethernet switch chip) and multiple low-capacity chips 1264a, 1264b (e.g., multiple network interface chips connected to a computer server).

[0441] An external optical power supply or photon supply 1274 provides an optical power supply signal, which can be continuous wave light, one or more periodic optical pulse trains, or one or more non-periodic optical pulse trains. For example, the optical power supply 1274 can provide pulsed light for data modulation and synchronization, as described in U.S. Patent 11,153,670. This allows the high-capacity chip 1262 to be synchronized with the low-capacity chips 1264a and 1264b.

[0442] Some aspects of systems 1250, 1260, and 1270 combine Figures 79 to 84B to describe in more detail.

[0443] Figure 43 An exploded view of an example of a front module 860 for a data processing system is shown, which includes a vertically mounted printed circuit board 862 (or a substrate made of, for example, organic or ceramic materials), a host-specific integrated circuit 864 mounted on the back side of the circuit board 862, and a heat sink 866. In some examples, the host-specific integrated circuit 864 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board 862. The front mounting module 860 can be a front panel of a data processing system housing, and Figure 26A 、 28A Similar configuration as shown, or located near the front panel of the housing, with Figure 27 、 28B The configuration shown in FIG. 3 shows three optical modules with connectors, such as 868a, 868b, and 868c, collectively referred to as 868. Additional optical modules with connectors may also be used. The data processing system may be similar to, for example, data processing system 680 ( Figure 26A ) or 700( Figure 27 PCB 862 may be similar to, for example, PCB 686 ( Figure 26A ) or 706( Figure 27 ASIC 864 may be similar to, for example, ASIC 682 ( Figure 26A ) or 702( Figure 27 ). Radiator 866 may be similar to, for example, radiator 576 ( Figure 23 ). The optical modules with connector 868 each include an optical module 880 (see Figure 44 、 45 ) and mechanical connector structure 900 (see Figure 46 、 47 ). The optical module 880 can be similar to, for example, the optical / electrical communication interface 682 ( Figure 26A ) or 704( Figure 27 ),or Figure 32 An integrated optical communication device 512.

[0444] Optical modules with connectors 868 can be inserted into a first grid structure 870, which can serve as (i) a heat dissipation device / heat sink and (ii) a mechanical fixture for optical modules with connectors 868. The first grid structure 870 includes an array of receptors, each of which can receive an optical module with connectors 868. When assembled, the first grid structure 870 is connected to the printed circuit board 862. The first grid structure 870 can be securely held in place relative to the printed circuit board 862 by sandwiching the printed circuit board 862 between the first grid structure 870 and a second structure 872 (e.g., a second grid structure) located on the opposite side of the printed circuit board 862, and attaching the first grid structure 870 via the printed circuit board 862 (e.g., using screws). Thermal vias between the first grid structure 870 and the second structure 872 can conduct heat from the front side of the printed circuit board 862 to the heat sink 866 on the back side of the printed circuit board 862. Additional heat sinks can also be mounted directly on the first grid structure 870 to provide cooling on the front side.

[0445] The printed circuit board 862 includes electrical contacts 876 for electrically connecting to the removable optical module with the connector 868 after the removable optical module with the connector 868 is inserted into the first grid structure 870. The first grid structure 870 may include an opening 874 located on the other side of the printed circuit board 862 where the host-ASIC 864 is mounted to allow components such as voltage regulators, filters, and / or decoupling capacitors to be mounted on the printed circuit board 862 in close lateral proximity to the host-ASIC 864.

[0446] In some examples, the host-specific integrated circuit 864 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board 862, similar to the examples shown in Figures 136 to 159. The substrate can be similar to the substrate 13602 of Figures 136 to 159, the second grid structure 872 can be similar to the rear lattice structure 13626 (lattice structure), the circuit board 862 can be similar to the printed circuit board 13604, the host-specific integrated circuit 864 can be similar to the data processing chip 12312, and the heat sink 866 can be similar to the heat dissipation device 13610. The first grid structure 870 can have an overall shape similar to the front lattice structure 13606 of Figures 136 to 159, except that the first grid structure 870 includes a mechanism for coupling to a detachable optical module via a connector 868.

[0447] Figure 44 and 45 An exploded view and an assembled view of an exemplary optical module 880 are shown, respectively, which can be used with Figure 32 The optical module 880 includes an optical connector component 882 (which can be connected to the optical communication device 512). Figure 32 ), which may receive optical signals from an upper connector component (e.g., a geometrically wider upper connector component 884) embedded in a second optical connector component ( Figure 44 、 45 (not shown) in an optical fiber, which can be used with Figure 6 and 7 The optical connector component 268 is similar. Figure 44 、 45 In the example shown, a fiber matrix, such as 2×18 fibers, can be optically coupled to the optical connector assembly 882. The fiber matrix can have other configurations, such as a 3×12, 1×12, 3×12, 6×12, 12×12, 16×16, or 32×32 fiber array. For example, the optical connector assembly 882 can have a configuration similar to Figure 15 The fiber coupling region 430 is configured to couple with 2×18 optical fibers or any other number of optical fibers. The upper connector component 884 may also include an alignment structure 886 (eg, a hole, a groove, a post) to receive a corresponding mating structure of the second optical connector component.

[0448] The optical module 880 may have any of a variety of configurations, including optical modules containing silicon photonic integrated optical devices, indium phosphide integrated optical devices, one or more vertical cavity surface emitting lasers (VCSELs), one or more direct detection optical receivers, or one or more coherent optical receivers. The optical module 880 may include optical modules described in this specification and in the documents incorporated by reference herein, co-packaged optical modules, integrated optical communication devices (e.g., Figure 17448, 462, 466 or 472, or Figure 20 210), integrated communication devices (e.g., Figure 23 612) or an optical / electrical communication interface (e.g., 684 of FIG. 26, 724 of FIG. 28, or 760 of FIG. 29).

[0449] The optical connector component 882 is inserted through the opening 888 of the substrate 890 and optically coupled to the photonic integrated circuit 896 mounted on the underside of the substrate 890. Figure 32 The substrate 814 is similar to the substrate 814 of FIG. 1 , and the photonic integrated circuit 896 can be similar to the photonic integrated circuit 524. A first serializer / deserializer chip 892 and a second serializer / deserializer chip 894 are mounted on the substrate 890, with the chip 892 located on one side of the optical connector component 882 and the chip 894 located on the other side of the optical connector component 882. The first serializer / deserializer chip 892 can include a similar Figure 32 The second serializer / deserializer chip 894 may include circuit systems similar to those of the first serializer / deserializer module 394 and the second serializer / deserializer module 396. The second board 898 (which may be connected to the Figure 32 A second plate 518 (similar to the second plate 518) may be provided on the underside of the substrate 890 to provide a detachable connection to a package substrate (eg, 230).

[0450] Figure 46 and 47 Shown around Figure 44 and 45 Exploded and assembled views of a mechanical connector structure 900 constructed with a functional optical module 880 are shown. In this exemplary embodiment, the mechanical connector structure 900 includes a lower mechanical component 902 and an upper mechanical component 904 that are configured to receive the optical module 880. Both the lower mechanical connector component 902 and the upper mechanical connector component 904 can be made of a thermally conductive and rigid material, such as metal.

[0451] In some embodiments, the upper mechanical component 904 is in thermal contact on its underside with the first SerDes chip 892 and the second SerDes chip 894. The upper mechanical component 904 is also in thermal contact with the lower mechanical component 902. The lower mechanical component 902 includes a removable latch mechanism, for example, two wings 906 that can be elastically bent inward (the movement of the wings 906 is controlled by the Figure 47 ), and each wing 906 includes a tongue 910 on the outside.

[0452] Figure 48Schematic diagram of a portion of first grid structure 870 and circuit board 862. In some examples, a substrate (e.g., a ceramic substrate) can be used in place of circuit board 862. Recesses 920 are provided on the walls of first grid structure 870. As shown, printed circuit board 862 (or substrate) has electrical contacts 876 that can be electrically coupled to electrical contacts on second board 898 of optical module 880. For example, electrical contacts 876 can include an electrical contact array having at least four rows and four columns of electrical contacts. For example, the electrical contact array can have ten or more rows or columns of electrical contacts. Electrical contacts 876 can be arranged in any two-dimensional pattern and do not necessarily need to be arranged in rows and columns. Circuit board 862 (or substrate) can also have three-dimensional features, such as protruding or recessed elements, and electrical contacts can be provided on these three-dimensional features. An optical module having connector 868 can have three-dimensional features with electrical contacts that mate with corresponding three-dimensional features with electrical contacts on circuit board 862 (or substrate).

[0453] Please refer to Figure 49 , when the lower mechanical member 902 is inserted into the first grid structure 870, the tongue 910 (on the wing 906 of the lower mechanical member 902) can snap into the corresponding groove 920 in the first grid structure 870 to mechanically hold the light module 880 in place. The position of the tongue 910 on the wing 906 is selected so that when the mechanical connector structure 900 and the light module 880 are inserted into the first grid structure 870, the electrical connector on the bottom of the second plate 898 is electrically coupled to the electrical contacts 876 on the printed circuit board 862 (or substrate). For example, the second plate 898 can include spring-loaded contacts that mate with the contacts 876.

[0454] Figure 50 A front view of the assembled front module 860 is shown. Three light modules (e.g., 868a, 868b, 868c) with connectors are inserted into the first grid structure 870. In some embodiments, the light modules 880 are arranged in a checkerboard pattern, with adjacent light modules 880 and corresponding mechanical connector structures 900 rotated 90 degrees so that no two wings touch. This facilitates the removal of individual modules. In this example, the light module with connector 868a is rotated 90 degrees relative to the light modules with connectors 868b and 868c.

[0455] Figure 51A A first side view of a mechanical connector structure 900 is shown. Figure 51B Shows the mechanical connector structure 900 along Figure 51A Cross-sectional view of midplane 930. In some examples, the compression interposer (eg, spring-loaded contacts) can be part of the receiving structure (eg, mounted on a circuit board or substrate) rather than a removable module.

[0456] Figure 52A A first side view of the mechanical connector structure 900 mounted within the first grid structure 870 is shown. Figure 52B The mechanical connector structure 900 is shown mounted within the first grid structure 870 along Figure 52A Cross-sectional view of mid-plane 940.

[0457] Figure 53 is a schematic diagram of an assembly 958 that includes a fiber optic cable 956 including a plurality of optical fibers, a fiber optic connector 950, a mechanical connector structure 900, and a first grid structure 870. The fiber optic connector 950 can be inserted into the mechanical connector structure 900, which can further be inserted into the first grid structure 870. The printed circuit board 862 (or substrate) is attached to the first grid structure 870 with the electrical contacts 876 facing the electrical contacts 954 on the bottom side of the second board 898 of the optical module 880.

[0458] Figure 53 Shows the individual components before they are connected. Figure 54 is a schematic diagram showing various components connected. Fiber optic connector 950 includes a locking mechanism 952 that prevents the snap-in mechanism of mechanical connector module 900, thereby locking mechanical connector structure 900 and optical module 880 in place. In this exemplary embodiment, locking mechanism 952 comprises a stud on fiber optic connector 950 that is inserted between wings 906 and the upper mechanical component 904 of mechanical connector module 900. This prevents wings 906 from elastically flexing inward, thereby locking mechanical connector structure 900 and optical module 880 in place. Furthermore, mechanical connector structure 900 includes a mechanism for retaining fiber optic connector 950 in place, such as a ball detent mechanism as shown. When fiber optic connector 950 is inserted into mechanical connector structure 900, a spring-loaded ball 962 on fiber optic connector 950 engages a detent 964 in wings 906 of mechanical connector structure 900. The spring pushes ball 962 against detent 964, securing fiber optic connector 950 in place.

[0459] To remove optical module 880 from first grid structure 870, the user can pull on fiber optic connector 950 and disengage ball 962 from detent 964. The user can then bend wings 906 inward so that tongue 910 disengages groove 920 in the wall of first grid structure 870.

[0460] Figure 55A and 55B The optical fiber connector 950 is shown before being inserted into the mechanical connector structure 900. Figure 53 and 54 A perspective view of the mechanism shown. Figure 55BAs shown, the underside of the optical connector 950 includes an alignment structure 960 that aligns with the alignment structure 886 ( Figure 44 )Cooperate. Figure 55B Also shown are a photonic integrated circuit 896 and a second plate 898 including electrical contacts (eg, spring-loaded electrical contacts).

[0461] Figure 56 is a perspective view showing the optical module 880 and the mechanical connector structure 900 being inserted into the first grid structure 870 , with the optical fiber connector 950 being separated from the mechanical connector structure 900 .

[0462] Figure 57 is a perspective view showing the fiber optic connector 950 mating with the mechanical connector structure 900 , which locks the optical module 880 within the mechanical connector structure 900 .

[0463] Figures 58A to 58D An alternative embodiment is shown in which a light module having a connector 970 includes a latching mechanism 972 that functions as a mechanical fastener to connect the light module 880 to a printed circuit board 862 (or substrate) supported by the first grid structure 870 . Figure 58A and 58B Various views of a light module are shown having a connector 970 that includes a latch mechanism 972 . Figure 58C and 58D Various views are shown of an optical module having a connector 970 coupled to a printed circuit board 862 (or substrate) and a first grid structure 870. For example, a user can easily attach or detach an optical module having the connector 970 by pressing a lever 974 that activates a latch mechanism 972. The lever 974 is constructed in a manner that does not prevent an optical fiber (not shown) from being removed from the optical module having the connector 970. Alternatively, an external tool can be used as a detachable lever.

[0464] Figure 59 FIG is a diagram of an optical module 1030 including an optical engine having a latch mechanism for achieving compression and attachment of the optical engine to a printed circuit board. Figure 58B The example shown is similar, but without the compression interposer. Figure 60A and 60B An exemplary latch mechanism is shown that can be used to secure (with sufficient compressive force) and remove the optical engine.

[0465] Figure 60A and 60B An exemplary embodiment of a lever 974 and latch mechanism 972 in a light module 1030 is shown. Figure 60AAn example is shown where lever 974 is pushed downward, causing latch mechanism 972 to latch to support structure 976 , which may be part of first grid structure 870 . Figure 60B An example is shown where lever 974 is pulled upward, causing latch mechanism 972 to release from support structure 976 .

[0466] Figure 61 Schematic diagram of an example of a fiber optic cable connection design 980 including nested fiber optic cables and co-packaged optical module connections. In this design, a co-packaged optical module 982 is removably coupled to a co-packaged optical port 1000 formed in a support structure such as a first grid structure 870, and a fiber optic connector 983 is removably coupled to the co-packaged optical module 982. The fiber optic connector 983 is coupled to a fiber optic cable 996 including multiple optical fibers. The fiber optic cable connection can be designed to be compatible with, for example, Multi-fiber Termination Push-on / Multi-fiber Push On (MTP / MPO) or with emerging new standards. Multi-fiber push-on (MPO) connectors are commonly used to terminate multi-fiber ribbon connections in indoor environments and comply with IEC-61754-7; EIA / TIA-604-5 (FOCIS 5) standards.

[0467] In some embodiments, the co-packaged optical module 982 includes a mechanical connector structure 984 and an intelligent optical assembly 986. The intelligent optical assembly 986 includes, for example, a photonic integrated circuit (e.g., Figure 44896) and components for light guiding, power distribution, polarization management, optical filtering and other beam management before photonic integrated circuits. These components may include, for example, optical couplers, waveguides, polarization optical devices, filters and / or lenses. Additional examples of components that may be included in the co-packaged optical module 982 are described in U.S. published application US2021 / 0286140. The mechanical connector structure 984 includes one or more fiber optic connector latches 988 and one or more co-packaged optical module latches 990. The mechanical connector structure 984 can be inserted into the co-packaged optical port 1000 (e.g., formed in the first grid structure 870), wherein the co-packaged optical module latch 990 engages the groove 992 in the wall of the first grid structure 870, thereby fixing the co-packaged optical module 982 to the co-packaged optical port 1000 so that the electrical contacts on the smart optical assembly 986 are electrically coupled to the electrical contacts 876 on the printed circuit board 862 (or substrate). When the fiber optic connector 983 is inserted into the mechanical connector structure 984, the fiber optic connector latch 988 engages the groove 994 in the fiber optic connector 983, thereby securing the fiber optic connector 983 to the co-packaged optical module 982 and optically coupling the fiber optic cable 996 to the smart optical assembly 986, e.g., through all optical paths in the fiber optic connector 983.

[0468] In some examples, fiber optic connector 983 includes guide pins 998 that are inserted into holes in smart optic assembly 986 to improve alignment of optical components (e.g., waveguides and / or lenses) in fiber optic connector 983 with optical components (e.g., optical couplers and / or waveguides) in smart optic assembly 986. In some examples, guide pins 998 can be chamfered or oval in shape to reduce wear.

[0469] In some embodiments, after the fiber optic connector 983 is installed in the co-packaged optical module 982, the fiber optic connector 983 prevents the co-packaged optical module latch 990 from flexing inward, thereby preventing the co-packaged optical module 982 from being inserted into or released from the co-packaged optical port 1000. To couple the fiber optic cable 996 to the data processing system, the co-packaged optical module 982 is first inserted into the co-packaged optical port 1000 without the fiber optic connector 983, and then the fiber optic connector 983 is inserted into the mechanical connector structure 984. To remove the fiber optic cable 996 from the data processing system, the fiber optic connector 983 can be removed from the mechanical connector structure 984 while the co-packaged optical module 982 remains coupled to the co-packaged optical port 1000.

[0470] In some embodiments, the nested connection latches can be designed to allow the co-packaged optical module 982 to be inserted into or removed from the co-packaged optical port 1000 when a fiber optic cable is connected to the co-packaged optical module 982 .

[0471] Figure 62 and 63 is a schematic diagram illustrating a cross-sectional view of an example of a fiber optic cable connection design 1010 including nested fiber optic cables and co-packaged optical module connections. Figure 62 An example is shown in which a fiber optic connector 1012 is removably coupled to a co-packaged optical module 1014 . Figure 63 An example is shown where the fiber optic connector 1012 is separated from the co-packaged optical module 1014 .

[0472] Figure 64 and 65 is a schematic diagram showing an additional cross-sectional view of the fiber optic cable connection design 1010. The cross section is cut vertically through Figure 62 and 63 The plane in the middle of the shown component is formed. Figure 64 An example is shown in which a fiber optic connector 1012 is removably coupled to a co-packaged optical module 1014 . Figure 65 An example is shown where the fiber optic connector 1012 is separated from the co-packaged optical module 1014 .

[0473] The following describes a rack unit thermal architecture for a rack-mount system (e.g., Figure 22 560, Figure 23 600, Figure 24 630 of Figure 26, 680 of Figure 26, 720 of Figure 28, 750 of Figure 29, Figure 43 860), which includes a data processing chip (e.g., Figure 22 、 23 572, Figure 24 640, Figure 26A 682, 722 in Figure 28, 758 in Figure 29, Figure 43 864), the circuit board is generally vertical relative to the bottom surface of the system housing or casing. In some embodiments, the rack unit thermal architecture uses air cooling to remove heat generated by the data processing chips. In these systems, the heat-generating data processing chips are located near input / output interfaces, which may include, for example, Figure 17 One or more of the integrated optical communication devices 448, 462, 466, or 472, Figure 22 Integrated communication equipment 574 or Figure 23 Integrated communication equipment 612, Figure 24The optical / electrical communication interface 644 of FIG. 26 , the optical / electrical communication interface 684 of FIG. 28 , the optical / electrical communication interface 724 of FIG. 28 , or the optical / electrical communication interface 760 of FIG. 29 , or having Figure 43 The optical modules with connectors 868 are located on or near the front panel to allow users to easily connect / disconnect optical transceivers to / from the rack-mounted system. The rack unit thermal architecture described in this specification includes mechanisms for increasing airflow across the surface of the data processing chip or a heat sink thermally coupled to the data processing chip, taking into account that most of the surface area of ​​the front panel of the housing needs to be allocated to input / output interfaces.

[0474] The rack-mounted systems and rack-mounted equipment described in this document may include (and are not limited to), for example, rack-mounted computer servers, rack-mounted network switches, rack-mounted controllers, and rack-mounted signal processors.

[0475] Please refer to Figure 67 A data server 1140 suitable for installation in a standard server rack may include a housing 1042 having a front panel 1034, a rear panel 1036, a bottom panel 1038, a top panel, and side panels 1040. For example, housing 1042 may have a form factor of 2 rack units (RU), with a width of approximately 482.6 mm (19 inches) and a height of 2 RU. A rack unit is approximately 44.45 mm (approximately 1.75 inches). A printed circuit board 1042 is mounted on bottom panel 1038, and at least one data processing chip 1044 is electrically coupled to printed circuit board 1042. A microcontroller unit 1046 is used to control various modules, such as a power supply 1048 and an exhaust fan 1050. In this example, exhaust fan 1050 is mounted on rear panel 1036. For example, a single-mode optical connector 1052 is provided on front panel 1034 for connection to an external fiber optic cable. Optical interconnect cable 1036 transmits signals between single-mode optical connector 1052 and at least one data processing chip 1044. Exhaust fans 1050 mounted on rear panel 1036 direct air from the front to the rear of housing 1042. The direction of air flow is indicated by arrows 1058. Hot air within housing 1042 is exhausted from housing 1042 by exhaust fans 1050 at rear panel 1036. In this example, front panel 1034 does not include any fans, thereby maximizing the area available for single-mode optical connector 1052.

[0476] For example, data server 1300 may be a network switch server, and at least one data processing chip 1044 may include at least one switch chip configured to process data having a total bandwidth of, for example, approximately 51.2 Tbps. The at least one switch chip 1044 may be mounted on a substrate 1054 having a size of, for example, approximately 100 mm x 100 mm, and a co-packaged optical module (CPO) 1056 may be mounted near an edge of the substrate 1054. The co-packaged optical module 1056 converts input optical signals received from optical interconnect cables 1036 into input electrical signals provided to the at least one switch chip 1044, and converts output electrical signals from the at least one switch chip 1044 into output optical signals provided to the optical interconnect cables 1036. When any co-packaged optical module 1056 fails, the user needs to remove the network switch server 1030 from the server rack and open the housing 1042 to repair or replace the failed co-packaged optical module 1056.

[0477] Please refer to Figure 68A and 68B In some embodiments, the rack server 1060 includes an outer housing or enclosure 1062 having a front panel 1064 (or faceplate), a rear panel 1036, a bottom panel 1038, a top panel, and side panels 1040. For example, the enclosure 1062 can have a 1RU, 2RU, 3RU, or 4RU form factor, having a width of approximately 482.6 mm (19 inches) and a height of 1, 2, 3, or 4 rack units. A first printed circuit board 1066 is mounted on the bottom panel 1038, and a microcontroller unit 1046 is electrically coupled to the first printed circuit board 1066 for controlling various modules, such as the power supply 1048 and the exhaust fan 1050.

[0478] In some embodiments, front panel 1064 includes a second printed circuit board 1068 oriented in a vertical orientation, e.g., substantially perpendicular to first circuit board 1066 and bottom panel 1038. Hereinafter, second printed circuit board 1068 is referred to as vertical printed circuit board 1068. While second printed circuit board 1066 is shown as forming part of front panel 1064, in some examples, second printed circuit board 1066 can also be attached to front panel 1064, where front panel 1064 includes openings through which input / output connectors can pass. Second printed circuit board 1066 includes a first side facing forward relative to housing 1062 and a second side facing rearward relative to housing 1062. At least one data processing chip 1070 is electrically coupled to the second side of vertical printed circuit board 1068, and a heat sink or heat spreader 1072 is thermally coupled to the at least one data processing chip 1070. In some examples, at least one data processing chip 1070 is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to printed circuit board 1068. Figure 68C FIG1 is a perspective view of an example heat dissipation device or heat sink 1072. For example, heat dissipation device 1072 may include a vapor chamber thermally coupled to a heat sink. An exhaust fan 1050 mounted on rear panel 1036 directs air from the front to the rear of housing 1042. The direction of air flow is indicated by arrows 1078. Exhaust fan 1050 at rear panel 1036 exhausts heated air from within housing 1042.

[0479] A co-packaged optical module 1074 (also known as an optical / electrical communication interface) is attached to a first side of the vertical printed circuit board 1068 (i.e., the side facing the front exterior of the housing 1062) for connection to external fiber optic cables 1076. Each fiber optic cable 1076 may include an array of optical fibers. By placing the co-packaged optical modules 1074 outside the front panel 1064, users can easily maintain (e.g., repair or replace) the co-packaged optical modules 1074 when needed. Each co-packaged optical module 1074 is configured to convert an input optical signal received from an external fiber optic cable 1076 into an input electrical signal, which is then transmitted to at least one data processing chip 1070 via signal lines in or on the vertical printed circuit board 1068. The co-packaged optical modules 1074 also convert output electrical signals from the at least one data processing chip 1070 into output optical signals for provision to the external fiber optic cables 1076. Hot air within the housing 1062 is exhausted from the housing 1062 by an exhaust fan 1050 mounted on the rear panel 1036.

[0480] For example, at least one data processing chip 1070 may include a network switch, a central processing unit, a graphics processing unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application-specific integrated circuit (ASIC). The rack server may be (and is not limited to), for example, a rack computer server, a rack switch, a rack controller, a rack signal processor, a rack storage server, a rack multi-purpose processing unit, a rack graphics processor, a rack tensor processor, a rack neural network processor, or a rack artificial intelligence accelerator. For example, each co-packaged optical module 1074 may include a similar Figure 17 Integrated optical communication device 448, 462, 466 or 472, Figure 20 Integrated optical communication device 210, Figure 23 26, the optical / electrical communication interface 684, the optical / electrical communication interface 724 in FIG. 28, or the optical / electrical communication interface 760 in FIG. 29, Figure 32 Integrated optical communication device 512 or Figure 43 For example, each fiber optic cable 1076 may include an optical fiber 226 ( Figure 2 、 4 )、272( Figure 6 、 7 )、582( Figure 22 、 23 ) or 734 (Fig. 28) or fiber optic cable 762 (Fig. 762), 956 ( Figure 53 ) or 996( Figure 61 ).

[0481] For example, the co-packaged optical module 1074 may include a first optical connector component (eg, Figure 17 456, Figure 22 or 578 of FIG. 23 or 746 of FIG. 28 ) for removably coupling to a second optical connector component (e.g., Figure 17 458, Figure 22 For example, the co-packaged optical module 1074 includes a photonic integrated circuit optically coupled to a first optical connector component (e.g., Figure 17 450, 464, 468 or 474, Figure 22 of 586, Figure 2328 ). The photonic integrated circuit receives an input optical signal from the first optical connector component and generates an input electrical signal based on the input optical signal. At least a portion of the input electrical signal generated by the photonic integrated circuit is transmitted to at least one data processing chip 1070 via electrical signal lines in or on vertical printed circuit board 1068. For example, the photonic integrated circuit can be configured to receive an output electrical signal from at least one data processing chip 1070 and generate an output optical signal based on the output electrical signal. The output optical signal is transmitted to external fiber optic cable 1076 via the first and second optical connector components.

[0482] In some examples, fiber optic cable 1076 may include, for example, 10 or more optical fiber cores, and the first optical connector component may be used to couple 10 or more channels of optical signals to the photonic integrated circuit. In some examples, fiber optic cable 1076 may include 100 or more optical fiber cores, and the first optical connector component may be used to couple 100 or more channels of optical signals to the photonic integrated circuit. In some examples, fiber optic cable 1076 may include 500 or more optical fiber cores, and the first optical connector component may be used to couple 500 or more channels of optical signals to the photonic integrated circuit. In some examples, fiber optic cable 1076 may include 1000 or more optical fiber cores, and the first optical connector component may be used to couple 1000 or more channels of optical signals to the photonic integrated circuit.

[0483] In some embodiments, the photonic integrated circuit can be used to generate a first serial electrical signal based on a received optical signal, wherein each first serial electrical signal is generated based on one of the channels of the first optical signal. Each co-packaged optical module 1074 may include a first serializer / deserializer module, the first serializer / deserializer module including a serializer unit and a deserializer unit, wherein the first serializer / deserializer module is used to generate multiple groups of first parallel electrical signals based on the first serial electrical signal and to condition the electrical signals, each group of first parallel electrical signals being generated based on a corresponding first serial electrical signal. Each co-packaged optical module 1074 may include a second serializer / deserializer module, the second serializer / deserializer module including a serializer unit and a deserializer unit, wherein the second serializer / deserializer module is used to generate a second serial electrical signal based on the multiple groups of first parallel electrical signals, each second serial electrical signal being generated based on a corresponding group of first parallel electrical signals.

[0484] In some examples, rack server 1060 may include four or more co-packaged optical modules 1074, which are configured to be removably coupled to corresponding second optical connector assemblies attached to corresponding fiber optic cables 1076. For example, rack server 1060 may include sixteen or more co-packaged optical modules 1074, which are configured to be removably coupled to corresponding second optical connector assemblies attached to corresponding fiber optic cables 1076. In some examples, each fiber optic cable 1076 may include ten or more optical fiber cores. In some examples, each fiber optic cable 1076 may include 10 or more optical fiber cores. In some examples, each fiber optic cable 1076 may include 500 or more optical fiber cores. In some examples, each fiber optic cable 1076 may include 1,000 or more optical fiber cores. Each optical fiber may transmit optical signals of one or more channels. For example, at least one data processing chip 1070 may include a network switch configured to receive data from an input port associated with an optical signal of a first channel and forward the data to an output port associated with an optical signal of a second channel.

[0485] In some embodiments, the co-packaged light module 1074 is removably coupled to the vertical printed circuit board 1068. For example, the co-packaged light module 1074 can be electrically coupled to the vertical printed circuit board 1068 using electrical contacts including, for example, spring-loaded elements, compression interposers, or a land grid array.

[0486] Please refer to Figure 69A and 69B In some embodiments, the rack server 1080 includes a housing 1082 having a front panel 1084. The rack server 1080 is similar to Figure 68A1060, in addition to having one or more fans mounted on the front panel 1084 and one or more air vents mounted in the housing 1082 to direct air toward the heat sink. For example, the rack server 1080 may include a first inlet fan 1086a mounted on the front panel 1084 to the left of the vertical printed circuit board 1068, and a second inlet fan 1086b mounted on the front panel 1084 to the right of the vertical printed circuit board 1068. The terms "right" and "left" refer to the relative positions of the components shown in the figures. It will be understood that, depending on the orientation of the device having the first and second modules, a first module positioned "to the left" or "to the right" of the second module may actually be positioned "to the right" or "to the left" of the second module (or any other relative position). For example, depending on the orientation of the rack server 1080, the inlet fans may be positioned below and / or above the vertical printed circuit board 1068. Depending on the shape of the rack server 1080, the inlet fans can be positioned to the left, right, below, and / or above the vertical printed circuit board 1068, or any combination of these locations. One or more fans can be positioned in front of the plane extending along the printed circuit board and designed to blow air toward components coupled to the front side of the printed circuit board, and one or more fans can be positioned behind the plane extending along the printed circuit board and designed to blow air toward components coupled to the rear side of the printed circuit board. The inlet and exhaust fans operate in a push-pull manner, with inlet fans 1086a and 1086b (collectively, 1086) pulling cool air into the housing 1082, while exhaust fans 1050 push hot air out of the housing 1082. The inlet fans 1086 in the front panel or faceplate 1064 and the exhaust fans 1050 on the rear side of the rack create a pressure gradient through the housing or enclosure to improve air cooling compared to a standard 1RU implementation that includes only rear exhaust fans.

[0487] The inlet fan does not necessarily have to be attached to the front panel and may also be positioned a distance in front of the front panel. The vertical printed circuit board 1068 may be positioned a distance from the front panel and the position of the inlet fan may be adjusted accordingly to maximize the efficiency of transferring heat away from the heat sink 1072.

[0488] In some embodiments, left and right air vents 1088a, 1088b are mounted in housing 1082 to direct airflow toward heat sink 1072. Air vents 1088a, 1088b (collectively, 1088) divide the space within housing 1082 and force air from inlet fans 1086a and 1086b to flow over the fin surfaces of heat sink 1072 and toward opening 1090 between the distal ends of air vents 1088. The direction of air flow 1086b near inlet fans 1086a and 1086b is indicated by arrows 1092a and 1092b. Air vents 1088 increase the amount of air flowing over the fin surfaces and improve heat dissipation efficiency. The fins are oriented to extend along a plane generally parallel to bottom surface 1038 of housing 1082. For example, air vents 1088 may have a curved shape, such as an S-shape as shown. The curved shape of the air vents 1088 can maximize the efficiency of the heat sink. In some examples, the air vents 1088 can also have a linear shape.

[0489] For example, the heat sink can be a plate-fin heat sink, a pin-fin heat sink, or a plate-pin-fin heat sink. The pins can have a square or circular cross-section. The heat sink configuration (e.g., pin pitch, pin or fin length) and vent configuration can be designed to optimize heat sink efficiency.

[0490] For example, the co-packaged light module 1074 can be electrically coupled to the vertical printed circuit board 1068 using electrical contacts such as spring-loaded elements, a compression interposer, or a planar grid array. For example, when a compression interposer is used, the vertical printed circuit board 1068 can be positioned so that the face of the compression interposer of the co-packaged light module 1074 is coplanar with the faceplate 1064 and the inlet fan 1086.

[0491] Please refer to Figure 70 In some embodiments, rack server 1090 is similar to rack server 1080 in FIG. 69 , including inlet fans mounted on the front panel. Compared to the inlet fans of rack server 1080 , the inlet fans of rack server 1090 are slightly rotated to improve heat sink efficiency. The rotational axes of the inlet fans, rather than being parallel to the front-to-back direction relative to housing 1082 , can be rotated slightly inward. For example, the rotational axis of left inlet fan 1092a can be rotated slightly clockwise, while the rotational axis of right inlet fan 1092b can be rotated slightly counterclockwise to enhance airflow across the heat sink surface and further improve heat dissipation efficiency.

[0492] In some embodiments, heat dissipation efficiency can be improved by positioning the vertical circuit board 1068 and the heat sink 1072 further toward the rear of the housing so that a greater amount of air flows over the surface of the heat sink 1072 fins.

[0493] Please refer to Figures 71A to 71B The rack server 1100 includes a housing 1102 having a front panel or faceplate 1104, wherein the portion of the faceplate 1104 that provides the compression interposer for the co-packaged optical module 1074 is inserted a distance d relative to the original faceplate 1104. The faceplate 1104 has a recessed portion or insert 1106 that is offset from the rear portion of the housing 1102 by a distance d (referred to as the "front panel insert distance") relative to other portions of the front panel 1104 (e.g., the portion where the inlet fans 1086a and 1086b are mounted). The insert 1106 is referred to as a "recessed front panel," "recessed faceplate," "front panel insert," or "faceplate insert." The vertical printed circuit board 1068 is attached to the insert 1106, which includes an opening that allows the co-packaged optical module 1074 to pass through. The insert 1106 has sufficient area to accommodate the co-packaged optical module 1074.

[0494] By providing an insert portion 1106 in the front panel 1104, the fins of the heat sink 1072 can be more optimally positioned closer to the primary airflow generated by the inlet fan 1086 while maintaining the serviceability of the co-packaged optical module 1074, for example, allowing a user to repair or replace a damaged co-packaged optical module 1074 without opening the housing 1102. The heat sink configuration (e.g., pin pitch, pin or fin length) and vent configuration can be designed to optimize heat sink efficiency. In addition, the front panel insert distance d can also be optimized to improve heat sink efficiency.

[0495] Please refer to Figure 72 In some embodiments, rack server 1110 is similar to rack server 1100 in FIG. 71 , except that server 1110 includes heat sink 1112, wherein heat sink 1112 has fins 1114a and 1114b extending beyond the edge of vertical printed circuit board 1068 and closer to inlet fans 1086a and 1086b than in FIG. The configuration of the heat sink (e.g., the shape, size, and number of the fins) can be selected to maximize heat dissipation efficiency.

[0496] Please refer to Figure 73A and 73BIn some embodiments, the rack server 1120 includes a housing 1122 having a front panel 1124, a rear panel 1036, a bottom panel 1038, a top panel, and side panels 1040. The width and height of the housing 1122 may be as large as Figure 68A The middle housing 1062 is similar. Server 1120 includes a first printed circuit board 1066 extending parallel to bottom panel 1038, and one or more vertical printed circuit boards, such as 1126a and 1126b (collectively referred to as 1126), mounted perpendicular to first printed circuit board 1066. Server 1120 includes one or more inlet fans 1086 mounted on front panel 1124 and one or more exhaust fans 1050 mounted on rear panel 1036. Airflow within housing 1122 is generally front-to-back. The direction of airflow is indicated by arrow 1134.

[0497] Each vertical printed circuit board 1126 has a first surface and a second surface. The first surface defines the length and width of vertical printed circuit board 1126. The distance between the first and second surfaces defines the thickness of vertical printed circuit board 1126. Vertical printed circuit board 1126a or 1126b is oriented so that the first surface extends substantially parallel to the front-to-back plane of housing 1122. At least one data processing chip 1128a or 1128b is electrically coupled to the first surface of vertical printed circuit board 1126a or 1126b, respectively. In some examples, at least one data processing chip 1128a or 1128b is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to printed circuit board 1126a or 1126b. Heat sink 1130a or 1130b is thermally coupled to at least one data processing chip 1128a or 1128b, respectively. Heat sink 1130 includes a heat sink extending along a plane substantially parallel to bottom panel 1038 of housing 1122. Heat sinks 1130 a and 1130 b are located behind inlet fans 1086 a and 1086 b , respectively, to maximize airflow across the fins and / or pins of heat sinks 1130 .

[0498] At least one co-packaged optical module 1132a or 1132b is mounted on the second side of vertical printed circuit board 1126a or 1126b, respectively. Co-packaged optical module 1132 is optically coupled to an optical interface (not shown) mounted on front panel 1124 via an optical interconnect link. The optical interface is optically coupled to an external fiber optic cable. The orientation of vertical printed circuit board 1126 and the heat sink of heat dissipation device 1130 can be selected to maximize heat dissipation.

[0499] Please refer to Figures 74A to 74BIn some embodiments, rack server 1150 includes vertical printed circuit boards 1152a and 1152b (collectively, 1152) having surfaces extending along planes generally parallel to the front-to-back direction relative to the housing or enclosure, similar to vertical printed circuit boards 1126a and 1126b of FIG. 73 . Rack server 1150 includes housing 1154 having a modified front panel or faceplate 1156 having an insert 1158 for improving access and field serviceability of co-packaged optical modules 1160a and 1160b (collectively, 1160), which are mounted on vertical printed circuit boards 1152a and 1152b, respectively. Insert 1158 is referred to as a "front panel insert" or "faceplate insert." The insert portion 1158 has a width w selected to enable hot-swap, field-serviceability of the co-packaged optical module 1160 , thereby avoiding the need to take the rack-mounted server 1150 out of service for maintenance.

[0500] For example, insert portion 1158 includes a first wall 1162, a second wall 1164, and a third wall 1166. First wall 1162 is generally parallel to second wall 1164, and third wall 1166 is located between first wall 1162 and second wall 1164. For example, first wall 1162 extends in a direction generally parallel to the front-to-rear direction relative to housing 1122. Vertical printed circuit board 1152a is attached to first wall 1162 of insert portion 1158, and vertical printed circuit board 1152b is attached to first wall 1162 of insert portion 1158. First wall 1162 includes an opening to allow co-packaged light module 1160a to pass through, and second wall 1164 includes an opening to allow co-packaged light module 1160b to pass through. For example, inlet fan 1086c may be mounted on third wall 1166.

[0501] Each vertical printed circuit board 1152 has a first surface and a second surface. The first surface defines the length and width of vertical printed circuit board 1152. The distance between the first and second surfaces defines the thickness of vertical printed circuit board 1152. Vertical printed circuit board 1152a or 1152b is oriented so that the first surface extends substantially parallel to a plane running in the front-to-back direction of housing 1154. At least one data processing chip 1170a or 1170b is electrically coupled to the first surface of vertical printed circuit board 1152a or 1152b, respectively. In some examples, at least one data processing chip 1170a or 1170b is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to printed circuit board 1152a or 1152b. Heat sink 1168a or 1168b is thermally coupled to at least one data processing chip 1170a or 1170b, respectively. Heat sink 1168 includes a heat sink extending along a plane substantially parallel to bottom panel 1038 of housing 1154. Heat sinks 1168a and 1168b are located behind inlet fans 1086a and 1086b, respectively, to maximize airflow across the fins and / or pins of heat sinks 1168a and 1168b.

[0502] Please refer to Figures 75A to 75B In some embodiments, a rack server 1180 includes a housing 1182 having a front panel 1184 having an insert portion 1186 (referred to as a "front panel insert" or "faceplate insert"). For example, the insert portion 1186 includes a first wall 1188 and a second wall 1190 that are oriented to make it easier for a user to connect or disconnect a fiber optic cable (e.g., 1076) from the server 1180 or a co-packaged optical module 1074. For example, the first wall 1188 can be at an angle θ1 relative to a nominal plane 1192 of the front panel 1184, where 0 < θ1 < 90°. The second wall 1190 can be at an angle θ2 relative to the nominal plane 1192 of the front panel, where 0 < θ2 < 90°. The angles θ1 and θ2 can be the same or different. The nominal plane 1192 of the front panel 1184 is perpendicular to the side panels 1040 and the bottom panel.

[0503] For example, the first vertical printed circuit board 1152a is attached to the first wall 1188, and the second vertical printed circuit board 1152b is attached to the second wall 1190. Figure 68A Rack server 1060, Figure 69A Compared to the rack server 1080 of FIG. 71 and the rack server 1100 of FIG. 71 , the rack server 1180 has a larger front panel area due to the inclined front panel insert and can be connected to more fiber optic cables.

[0504] Positioning the first and second walls 1188, 1190 at an angle between 0° and 90° relative to the nominal plane of the front panel improves accessibility and field serviceability of the co-packaged optical modules. Figure 74A Compared to rack-mounted server 1150 in Figure 1, server 1180 allows users to more easily access co-packaged optical modules located further from the nominal plane of the front panel. Angles θ1 and θ2 were selected to strike a balance between increasing the number of fiber optic cables that can be connected to the server and providing easy access to all of the server's co-packaged optical modules. The front panel insertion width and angle are configured to enable hot-swappable, field serviceability, eliminating the need to take the switch and rack out of service for maintenance.

[0505] For example, inlet fans 1086a and 1086b may be mounted on the front panel 1184. External air is drawn in by the inlet fans 1086a, 1086b, passes through the surfaces of the fins and / or pins of the heat sinks 1168a, 1168b, and flows toward the rear of the housing 1182. Examples of the flow direction of the air entering through the inlet fans 1186a and 1186b are represented by arrows 1198a, 1198b, 1198c, and 1198d.

[0506] Please refer to Figure 75B and 75C In some embodiments, the front panel 1184 includes upper vents 1194a and baffles to direct external air entering through the upper vents 1194a to flow downward and rearward, such that the air passes over the surfaces of some heat sink fins and / or pins of the heat sink 1186 (e.g., including the fins and / or pins closer to the top of the heat sink 1186) and then flows to the inlet fan 1086c mounted at or near the far end or rear end of the front panel. The front panel 1184 includes lower vents 1194b and baffles to direct external air entering through the lower vents 1194b to flow upward and rearward, such that the air passes over the surfaces of some heat sink fins and / or pins of the heat sink 1186 (e.g., including the fins and / or pins closer to the bottom of the heat sink 1186) and then flows to the inlet fan 1086c. An example of air flow through the upper and lower vents 1194a, 1194b to the inlet fan 1086c is shown by Figure 75C Indicated by arrows 1196a, 1196b, 1196c and 1196d.

[0507] For example, if the inlet fan 1086c is configured to receive air through an opening directly in front of the inlet fan 1086c, the fiber optic cables connected to the co-packaged optical module 1074 may block the air flow from the inlet fan 1086c. By using the upper vents 1194a, lower vents 1194b, and baffles to direct the air flow as described above, the cooling efficiency of the system can be improved (compared to without the vents 1194 and baffles).

[0508] Please refer to Figure 76 In some embodiments, the network switch system 1210 includes a plurality of rack-mounted switch servers 1212 mounted in a server rack 1214. The network switch rack includes a top-of-rack switch 1216 that routes data between the switch servers 1212 in the network switch system 1210 and acts as a gateway between the network switch system 1210 and other network switch systems. The rack-mounted switch servers 1212 in the network switch system 1210 can be configured similarly to any rack-mounted server described above.

[0509] In some embodiments, the vertical printed circuit board can be positioned behind the front panel to modify Figure 68A 、 69A and an example of a rack-mount server in Figure 70. The co-packaged optical module can be optically connected to a fiber optic connector assembly mounted on the front panel via a short optical connection path, such as a fiber optic patch cable.

[0510] Please refer to Figure 77A and 77B In some embodiments, rack server 1220 includes a housing 1222 having a front panel 1224, a rear panel 1036, a top panel 1226, a bottom panel 1038, and side panels 1040. Front panel 1224 can be opened to allow a user to access components without removing rack server 1220 from the rack. A vertically mounted printed circuit board 1230 is generally parallel to front panel 1224 and recessed into front panel 1224, i.e., spaced apart from the rear of front panel 1224 by a small distance (e.g., less than 12 inches, less than 6 inches, less than 3 inches, or less than 2 inches). Printed circuit board 1230 includes a first side facing forward relative to housing 1222 and a second side facing rearward relative to housing 1222. At least one data processing chip 1070 is electrically coupled to the second side of vertical printed circuit board 1226, and a heat sink or heat spreader 1072 is thermally coupled to at least one data processing chip 1070. In some examples, at least one data processing chip 1070 is mounted on a substrate (eg, a ceramic substrate), and the substrate is attached to the printed circuit board 1226 .

[0511] A co-packaged optical module 1074 (also referred to as an optical / electrical communication interface) is attached to a first side of the vertical printed circuit board 1230 (i.e., the side facing the front exterior of the housing 1222). In some examples, the co-packaged optical module 1074 is mounted on a substrate attached to the vertical printed circuit board 1230, where electrical contacts on the substrate are electrically coupled to corresponding electrical contacts on the vertical printed circuit board 1230. In some examples, at least one data processing chip 1070 is mounted on a rear side of the substrate, and the co-packaged optical module 1074 is removably attached to a front side of the substrate, where the substrate provides a high-speed connection between the at least one data processing chip 1070 and the co-packaged optical module 1074. For example, the substrate can be attached to the front side of the printed circuit board 1068, where the printed circuit board 1068 includes one or more openings for mounting the at least one data processing chip 1070 on the rear side of the substrate. The printed circuit board 1068 can provide power from the motherboard to the baseboard (and thus to the at least one data processing chip 1070 and the co-packaged optical module 1074), and enables the at least one data processing chip 1070 and the co-packaged optical module 1074 to be connected to the motherboard using a low-speed electrical link. Figure 69B and 71B Similar to the example in FIG. 1 , an array of co-packaged optical modules 1074 can be mounted on a vertical printed circuit board 1230 (or substrate). The electrical connection between the co-packaged optical modules 1074 and the vertical printed circuit board 1070 (or substrate) can be removable, for example, by using a flat grid array and / or a compression interposer. The co-packaged optical modules 1074 are optically connected to a first fiber optic connector assembly 1232 mounted on the front panel 1224 via short fiber optic jumpers 1234a, 1234b (collectively, 1234). When the front panel 1224 is closed, a user can insert a second fiber optic connector assembly 1236 into the first fiber optic connector assembly 1232 on the front panel 1224, where the second fiber optic connector assembly 1236 is connected to a fiber optic cable 1238 including an array of optical fibers.

[0512] In some embodiments, the rack server 1220 is pre-installed with the co-packaged optical module 1074, and the user does not need to touch the co-packaged optical module 1074 unless the module requires maintenance. During normal operation of the rack server 1220, the user primarily touches the first fiber optic connector assembly 1232 on the front panel 1224 to connect to the fiber optic cable 1238.

[0513] One or more inlet fans, such as 1086a, 1086b, may be mounted on the front panel 1224, similar to Figure 69A and 70 The location and configuration of the inlet fan 1086 , heat sink 1072 , and air vents 1088 a , 1088 b are selected to maximize the heat transfer efficiency of the heat sink 1072 .

[0514] Rack-mounted server 1220 can have many advantages. By placing vertical printed circuit board 1230 in a recessed position within housing 1222, vertical printed circuit board 1230 can be better protected by housing 1222, for example, preventing a user from accidentally bumping into board 1230. By orienting vertical printed circuit board 1230 substantially parallel to front panel 1224 and mounting co-packaged optical module 1074 on the forward-facing side of board 1230, a user can access co-packaged optical module 1074 for maintenance on rack-mounted server 1220 without disassembly.

[0515] In some embodiments, front panel 1224 is coupled to bottom panel 1038 using hinge 1228, allowing front panel 1224 to be securely closed during normal operation of rack server 1220 and easily opened for maintenance. For example, if co-packaged optical module 1074 fails, a technician can open front panel 1224 and rotate it downward to a horizontal position to access co-packaged optical module 1074 to repair or replace it. For example, the movement of front panel 1224 is represented by bidirectional arrow 1250. In some embodiments, different fiber optic patch cables 1234 can have different lengths depending on the distance between the components connected by fiber optic patch cables 1234. For example, the distance between co-packaged optical module 1074 and first fiber optic connector assembly 1232 connected by fiber optic patch cable 1234a is smaller than the distance between co-packaged optical module 1074 and first fiber optic connector assembly 1232 connected by fiber optic patch cable 1234b, and therefore, fiber optic patch cable 1234a can be shorter than fiber optic patch cable 1234b. In this manner, by using fiber optic patch cables having appropriate lengths, clutter caused by the fiber optic patch cables 1234 inside the housing 1222 when the front panel 1224 is closed and in its upright position can be reduced.

[0516] In some embodiments, the front panel 1224 can be configured to open and lift upward using a lifting hinge. This is helpful when the rack server is located near the top of the rack. In some examples, the front panel 1224 can be connected to the side panel 1040 using a hinge so that the front panel 1224 can be opened and rotated sideways. In some examples, the front panel may include a left front sub-panel and a right front sub-panel, wherein the left front sub-panel is coupled to the left side panel 1040 by a first hinge, and the right front sub-panel is coupled to the right side panel 1040 by a second hinge. The left front sub-panel can be opened and rotated toward the left, and the right front sub-panel can be opened and rotated toward the right. These different configurations of the front panel can protect the vertical printed circuit board 1230 and provide convenient access to the co-packaged optical module 1074.

[0517] In some examples, Figure 71ASimilar to the example shown, the front panel can have an insert portion, with the vertical printed circuit board being recessed relative to the front panel insert portion, i.e., a small distance from the rear of the front panel insert portion. The front panel insert distance, the distance between the vertical printed circuit board and the front panel insert portion, and the air vent configuration can be appropriately adjusted to maximize heat sink efficiency.

[0518] Please refer to Figure 78 In some embodiments, the rack server 1240 may be similar to Figure 74A 1 , except that the vertical printed circuit boards are recessed relative to the walls of the insert portion of the front panel. For example, vertical printed circuit board 1152a is recessed relative to first wall 1242a of insert portion 1244, i.e., vertical printed circuit board 1152a is spaced a short distance to the left of first wall 1242a. Vertical printed circuit board 1152b is recessed relative to second wall 1242b of insert portion 1244, i.e., vertical printed circuit board 1152b is spaced a short distance to the right of second wall 1242b.

[0519] For example, the first wall 1242a can be connected to the bottom panel or the top panel by a hinge, so that the first wall 1242a can be closed during normal operation of the rack server 1240 and opened during maintenance of the server 1240. The distance w2 between the first wall 1242a and the second wall 1242b can be appropriately adjusted to be large enough to enable the first wall 1242a and the second wall 1242b to open properly. This design has similar Figure 77A 、 77B Advantages of the mid-rack server 1220.

[0520] In some embodiments, a rack server may be similar to Figures 75A to 75C The rack server 1180 shown in FIG, except that the vertical printed circuit boards are in recessed positions relative to the walls of the insert portion of the front panel. For example, the first vertical printed circuit board is in a recessed position relative to the first wall 1188 of the insert portion 1186, and the second vertical printed circuit board is in a recessed position relative to the second wall 1190 of the insert portion 1186. For example, the first wall 1188 can be connected to the bottom panel or the top panel by a hinge so that the first wall 1188 can be closed during normal operation of the rack server and opened during server maintenance. The angles θ1 and θ2 can be adjusted appropriately to enable the first wall 1188 and the second wall 1190 to open correctly. This design has similar Figure 77A 、 77B Advantages of the mid-rack server 1220.

[0521] Compared to conventional designs, the above-mentioned rack-mounted units (e.g. Figure 68ARack Server 1060, Figure 69A 、 70 Rack Server 1090, Figure 71A 、 72 Rack Server 1100, Figure 73A Rack Server 1120, Figure 74A Rack Server 1150, Figure 75A Rack Server 1180, Figure 77B Rack servers 1120 and Figure 78 The thermal architecture of the rack-mounted server 1240 in FIG. 1 is characterized by the use of co-packaged optical modules or optical / electrical communication interfaces, each of which has a higher bandwidth. For example, each co-packaged optical module or optical / electrical communication interface can be coupled to a fiber optic cable carrying a large number of densely packed optical fiber cores. Figure 9 An example of an integrated optical communication device 282 is shown, in which the optical signals provided to the photonic integrated circuit can have a total bandwidth of approximately 12.8 Tbps. By using co-packaged optical modules or optical / electrical communication interfaces with higher bandwidth, the number of co-packaged optical modules or optical / electrical communication interfaces required for a given total bandwidth of the rack unit is reduced, thereby reducing the area reserved for optical fiber connections on the housing front panel. This allows for the addition of one or more inlet fans to the front panel to improve thermal management, while maintaining or even increasing the total bandwidth of the rack unit, compared to conventional designs.

[0522] In some embodiments, for Figure 72 、 74A , 75A and 78, and variations in which the vertical printed circuit board is recessed relative to the front panel, each of the top and bottom panels of the housing may be shaped to have an insert portion at the front to correspond to the insert portion of the front panel. This allows for easier access to co-packaged optical modules or optical connector components mounted on the front panel without being obstructed by the top and bottom panels. In some embodiments, a server rack (e.g., Figure 76 1214) is designed so that the front support structure of the server rack also has an insert portion corresponding to the insert portion of the front panel of the rack-mounted server installed in the server rack. For example, the custom server rack is designed to install rack-mounted servers, which have the same Figure 74A Insert portion similar to insert portion 1158. For example, a custom server rack can be designed to mount rack-mounted servers having the same Figure 75A The insert portion is similar to the middle insert portion 1186. In such an example, the insert portion extends vertically from the bottom server to the top server without any obstruction, making it easier for users to reach the co-packaged optical modules or optical connector components.

[0523] In some embodiments, for Figure 72 、 74A , 75A and 78, and variations in which the vertical printed circuit board is recessed relative to the front panel, the top and bottom panels of the housing can be shaped similarly to a standard rack-mount unit, for example, the top and bottom panels can have a generally rectangular shape.

[0524] Figure 68A 、 68B , 69A to 75C and 77A to 78, similar to Figure 43 The grid structure 870 shown in FIG can be attached to a vertical printed circuit board. The grid structure can serve as (i) a heat sink / heat spreader and (ii) a mechanical fixture for co-packaging optical modules (e.g., 1074) or optical / electrical communication interfaces.

[0525] Figures 96 to 97B is a schematic diagram of an example of a rack server 1820 that includes a vertically oriented circuit board 1822 located at a front portion of the rack server 1820 . Figure 96 Shows a top view of the rack server 1820. Figure 97A A perspective view showing a rack server 1820, and Figure 97B A perspective view of a rack server 1820 with the top panel removed is shown. The rack server 1820 has an active airflow management system that is used to remove heat from the data processors during operation of the rack server 1820.

[0526] Please refer to Figure 96 、 97A 97B, in some embodiments, the rack server 1820 includes a housing 1824 having a front panel 1826, a left side panel 1828, a right side panel 1840, a bottom panel 1841, a top panel 1843, and a rear panel 1842. The front panel 1826 may be similar to Figure 68A 、 68B , 69A to 72, 77A and 77B. For example, the vertically oriented circuit board 1822 can be part of the front panel 1826, or attached to the front panel 1826, or positioned near the front panel 1826, wherein the distance between the circuit board 1822 and the front panel 1826 is no greater than, for example, 6 inches. The data processor 1844 (which can be, for example, a network switch, a central processing unit, a graphics processing unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller or an application-specific integrated circuit) (see Figure 99 ) is mounted on circuit board 1822.

[0527] A heat dissipation module 1846, such as a heat sink, is thermally coupled to the data processor 1844 and is used to dissipate heat generated by the data processor 1828 during operation. The heat dissipation module 1846 may be similar to Figure 68A 、 68C , 69A, 70, and 71A. In some examples, to optimize heat dissipation, heat dissipation module 1846 includes a heat sink or heat dissipation pins having a heat dissipation surface. In some examples, heat dissipation module 1846 includes a heat sink thermally coupled to the heat sink or heat dissipation pins. Rack server 1820 may include other components, such as a power supply unit, a rear outlet fan, one or more additional horizontally oriented circuit boards, one or more additional data processors mounted on the horizontally oriented circuit boards, and one or more additional air vents, which have been described in other embodiments of the rack server and are not further described here.

[0528] In some embodiments, the active airflow management system includes an inlet fan 1848 located to the left of the thermal module 1846 and oriented to blow incoming air to the right toward the thermal module 1846. A front opening 1850 provides incoming air to the inlet fan 1848. The front opening 1850 can be located to the left of the inlet fan 1848. Figure 96 As shown, circuit board 1822 is generally parallel to front panel 1826, and the rotational axis of inlet fan 1848 is generally parallel to the plane of circuit board 1822. The orientation of inlet fan 1848 can also be slightly different. For example, the rotational axis of inlet fan 1848 can be at an angle θ relative to the plane of front panel 1826, where θ is measured along a plane parallel to bottom panel 1841, where θ≤45°, or in some examples, θ≤25°, or in some examples, θ≤5°, or in some examples, θ=0°.

[0529] In some embodiments, a baffle or air vent 1852 (or inner panel or wall) is used to direct air entering the opening 1850 toward the inlet fan 1848. Arrow 1854 illustrates the general direction of airflow from the opening 1850 to the fan 1848. In some examples, the air vent 1852 extends from the left panel 1828 of the housing 1840 to the rear edge of the inlet fan 1848. The air vent 1852 can be straight or curved. In some examples, the air vent 1852 can be used to direct the inlet air blown by the inlet fan 1848 toward the thermal module 1846. For example, the air vent 1852 can extend from the left side panel 1828 to the left edge of the thermal module 1846. For example, the air vent 1852 can extend from the left side panel 1828 to a location at or near the rear of the thermal module 1846, where the location can be anywhere from the left rear to the right rear of the thermal module 1846. The air vents 1852 may extend vertically from the bottom panel 1841 to the top panel 1843. Arrows 1856 illustrate the general direction of air flow through and out of the heat dissipation module 1846.

[0530] For example, air vents 1852, a front portion of left side panel 1828, front panel 1826, circuit board 1822, a front portion of bottom panel 1841, and a front portion of top panel 1843 can form an air duct that directs incoming cool air over the heat dissipating surfaces of heat dissipation module 1846. Depending on the design, the air duct can extend to the left edge of heat dissipation module 1846, to the middle of heat dissipation module 1846, or to approximately the entire length of heat dissipation module 1846 (from left to right).

[0531] The inlet fans 1848 and air vents 1852 are designed to improve airflow across the heat dissipation surface of the heat dissipation module 1846 to optimize or maximize the heat dissipation from the data processors 1844 through the heat dissipation module 1846 to the ambient air. Different rack servers may have vertically mounted circuit boards of different lengths, may have data processors with different heat dissipation requirements, and may have heat dissipation modules of different designs. For example, the heat sinks and / or pins may have different configurations. The inlet fans 1848 and air vents 1852 may also have any configuration to optimize or maximize the heat dissipation to the data processors 1844. Figure 96 In the example, inlet fan 1848 directs air across the heat dissipation surface of heat dissipation module 1846 in a direction generally parallel to the front panel (in this example, from left to right). In some embodiments, the front opening may be located on the right side of the front panel, and the inlet fan may be located on the right side of the heat dissipation module, directing air across the heat dissipation surface of the heat dissipation module from right to left. The air vents may be modified accordingly to optimize airflow and cooling of the data processor.

[0532] Figure 98is a schematic diagram of the front portion of rack server 1820. A baffle or air vent 1852, a portion of bottom panel 1841, a portion of top panel 1843, and a portion of left side panel 1828 form a duct that directs outside air toward inlet fan 1848. A safety mechanism (not shown), such as a protective screen, may be placed across opening 1850 to allow air to pass generally freely while preventing larger objects from contacting the fan blades. In some embodiments, an air filter may be provided in front of the inlet fan to reduce dust accumulation within the rack server.

[0533] In some examples, the inlet fans are oriented to face sideways rather than frontally (e.g., in Figure 69A and 71A In some examples, orienting the inlet fans to the side rather than the front can avoid areas in the cooling module where there is little or no airflow. Figure 71A In the example shown, the left and right inlet fans blow air toward the left and right areas of heat sink 1072, respectively. Due to the pressure gradient created by the front inlet fan and the rear exhaust fan, the incoming air is drawn toward the rear of the heat sink. In some cases, incoming air entering the left side of heat sink 1072 is pulled toward the rear of heat sink 1072 before reaching the center of heat sink 1072. Similarly, incoming air entering the right side of heat sink 1072 is pulled toward the rear of heat sink 1072 before reaching the center of heat sink 1072. As a result, the center or front-center area near heat sink 1072 may experience little to no airflow, reducing cooling efficiency. Figures 96 to 98 The design shown in avoids or reduces this problem.

[0534] Front panel 1826 includes an opening or interface port 1860 that allows rack server 1820 to be coupled to fiber optic cables and / or electrical cables. In some embodiments, a co-packaged optical module 1870 can be inserted into interface port 1860, where co-packaged optical module 1870 serves as an optical / electrical communication interface for data processor 1844. Co-packaged optical modules have been described previously in this document.

[0535] Figure 99Upper figure 1880 is a perspective front view of an example including front panel 1826, while lower figure 1882 is a perspective rear view of front panel 1826. Lower figure 1882 shows data processor 1844 mounted on the rear side of vertically oriented circuit board 1822. Front panel 1826 includes an opening or interface port 1860 to allow insertion of a communication interface module, such as a co-packaged optical module, to provide an interface between data processor 1844 and an external fiber optic cable or cables. The optical and electrical signal paths between data processor 1844 and the co-packaged optical module have been previously described in this document.

[0536] Figure 100 18 is a top view of an example of a rack server 1890 that includes a vertically oriented circuit board 1822 located at a front portion of the rack server 1890. A data processor 1844 is mounted on the circuit board 1822, and a heat sink module 1846 is thermally coupled to the data processor 1844. The rack server 1890 has an active airflow management system for removing heat from the data processor 1844 during operation. The rack server 1890 includes a plurality of components that are compatible with the rack server 1820 ( Figure 96 ) Similar components are not described here.

[0537] In some embodiments, the active airflow management system includes an inlet fan 1894 located to the left of the thermal module 1846 and oriented so that inlet air blows to the right toward the thermal module 1846. A front opening 1850 allows incoming air to pass through the inlet fan 1894. The front opening 1850 can be located to the left of the inlet fan 1894. For example, the inlet fan 1894 can have an axis of rotation at an angle θ relative to the front panel 1826, where θ ≤ 45°. In some examples, θ ≤ 25°. In some examples, θ ≤ 5°. In some examples, the circuit board 1822 is substantially parallel to the front panel 1826, and the axis of rotation of the inlet fan 1894 is substantially parallel to the circuit board 1822. The inlet fan 1894,

[0538] In some embodiments, a first baffle or air vent 1892 is provided to direct air from the opening 1850 toward the inlet fan 1894, and from the inlet fan 1894 toward the cooling module 1846. A second baffle or air vent 1908 is provided to direct air from the right portion of the cooling module 1846 toward the rear of the rack server 1890. The first and second air vents 1892, 1894 can extend vertically from the bottom panel to the top panel.

[0539] Arrow 1902 illustrates the general direction of airflow from opening 1850 to inlet fan 1894. Arrow 1904 illustrates the general direction of airflow from inlet fan 1894 through the center portion of thermal module 1846. Arrow 1906 illustrates the general direction of airflow through and out of the right side portion of thermal module 1846. First air vent 1892, the front portion of the left side panel, the front portion of the top panel, the front portion of the bottom panel, front panel 1826, circuit board 1822, and second air vent 1908 combine to form a duct that directs air flow through thermal module 1846 or a substantial portion of thermal module 1846, thereby increasing the efficiency of cooling data processor 1844.

[0540] In this example, first air vent 1892 includes a left curved segment 1896, a middle straight segment 1898, and a right curved segment 1900. The left curved segment 1896 extends from the left side panel to the inlet fan 1894. The left curved segment 1896 directs incoming air from flowing in a front-to-back direction to flowing in a left-to-right direction. The middle straight segment 1898 is positioned at the rear of the thermal module 1846 and extends from the inlet fan 1894 to beyond the center portion of the thermal module 1846. The middle straight segment 1898 generally directs a majority (e.g., more than half) of the air through the thermal module 1846 in a left-to-right direction. The combination of the right curved segment 1900 and the second air vent 1908 directs air from flowing in a left-to-right direction to flowing in a front-to-back direction. The designs of the first and second air vents 1892, 1908 can be adjusted appropriately to optimize thermal efficiency. The heat dissipation module 1846 may have a different design than shown, and the first and second air vents 1892, 1908 may be modified accordingly.

[0541] exist Figure 100 In the example shown, inlet fan 1894 directs air across the heat dissipation surface of heat dissipation module 1846 in a direction generally parallel to front panel 1826 (in this example, from left to right). In some embodiments, the front panel opening may be located on the right side of the front panel, and the inlet fan may be located on the right side of the heat dissipation module, directing air across the heat dissipation surface of the heat dissipation module from right to left. The first and second air vents may be ...

Claims

1. A device, characterized in that: The device comprises: a housing capable of being mounted in a rack; and A vertically oriented switch card, the vertically oriented switch card comprising: one or more vertically oriented application specific integrated circuits (ASICs), the one or more vertically oriented application specific integrated circuits being mounted on the vertically oriented switch card, a two-dimensional arrangement of a plurality of plug ports, wherein each plug port is configured to receive a pluggable optical module, and A two-dimensional arrangement of a plurality of channel inlets, wherein each channel inlet is located adjacent to at least one plug port in the two-dimensional arrangement of the plurality of plug ports, each channel inlet receiving air and directing the received air toward an interior of the rack-mountable housing.

2. The device according to claim 1, characterized in that Each channel inlet is connected to a channel that extends to the interior of the housing that is mountable in the rack.

3. The device according to claim 2, characterized in that The at least one channel extends through the cutout of the vertically-oriented switch card.

4. The device according to claim 3, characterized in that The at least one channel includes one or more structures for thermal regulation in the housing.

5. The device according to claim 4, characterized in that The one or more structures extend the entire length of the channel.

6. The device according to claim 4, characterized in that The one or more structures extend for a portion of the length of the channel.

7. The device according to claim 2, characterized in that Each of the channels includes one or more structures that are used for thermal regulation of the device.

8. The device according to claim 7, characterized in that Each of the one or more structures includes a heat sink geometry.

9. The device according to claim 1, characterized in that Two application specific integrated circuits are installed in the housing.

10. The device according to claim 1, characterized in that Each of the plug ports is configured to receive at least one of: (i) a small form factor pluggable, (ii) an octal small form factor pluggable, or (iii) an ultra small form factor pluggable (OSFP).

11. The device according to claim 2, characterized in that Each of the channels includes one or more structures that are used for thermal regulation of the device.

12. The device according to claim 1, characterized in that The apparatus further includes a structural support that provides mechanical rigidity to facilitate insertion and removal of the pluggable optical module at the corresponding plug port.

13. The device according to claim 11, characterized in that A structure of the one or more structures for thermal regulation of the device includes a first end of the structure having a first width and a second end of the structure having a second width, the second width being less than the first width.

14. A device, characterized in that: The device comprises: a housing capable of being mounted in a frame; and A vertically oriented switch card, the vertically oriented switch card comprising: one or more vertically oriented application specific integrated circuits (ASICs), the one or more vertically oriented application specific integrated circuits being mounted on the vertically oriented switch card, a two-dimensional arrangement of a plurality of plug ports, wherein each plug port is configured to receive a pluggable optical module, a two-dimensional arrangement of a plurality of channel inlets, wherein each channel inlet is located adjacent to at least one plug port in the two-dimensional arrangement of the plurality of plug ports, each channel inlet receiving air and directing the received air toward an interior of the housing that is mountable in the rack, a first heat sink air inlet located above the one or more vertically oriented ASICs, and A second heat sink air inlet is located below the one or more vertically-oriented ASICs.

15. The device according to claim 14, characterized in that The apparatus further comprises at least one of the following: (i) a first radiator air dam proximate to the first radiator air inlet and configured to receive air and direct the air toward the first radiator air inlet; or (ii) a second radiator air dam proximate to the second radiator air inlet and configured to receive air and direct the air toward the second radiator air inlet.

16. The device according to claim 14, characterized in that The first radiator air inlet is configured to direct air to a first set of fins, and the first set of fins extends from the first radiator air inlet.

17. The device according to claim 14, characterized in that The second radiator air inlet is configured to direct air to a second set of fins, and the second set of fins extends from the second radiator air inlet.

18. The device according to claim 14, characterized in that The vertically-oriented switch card includes a pair of connectors, wherein each connector of the pair of connectors is configured to connect the vertically-oriented switch card to a horizontal backside line card.

19. The device according to claim 18, characterized in that The vertically oriented switch card includes an input / output module coupled to one or both connectors of the pair of connectors.

20. The device according to claim 14, characterized in that At least one channel inlet in the two-dimensional arrangement of the multiple channel inlets includes a first end of the at least one channel inlet having a first width and a second end of the at least one channel inlet having a second width, wherein the first end is positioned adjacent to the at least one plug port and the second end is located at an interior of the shell, and the second width is greater than the first width.

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