Image processing system, method and device and computer readable storage medium

Abstract

The embodiment of the invention provides an image processing system which comprises a main control chip, a memory, a buffer and a clock generator, the memory, the buffer and the clock generator are connected with the main control chip, and the memory and the buffer are connected with each other. The memory is configured to: store a plurality of predetermined image correction parameters; the buffer is configured to obtain a plurality of pieces of to-be-processed image data; the clock generator is configured to provide clock signals, the clock signals are used for controlling writing or reading of the image correction parameters in the memory, and the clock signals at least comprise a first clock signal; the main control chip is configured to generate a first reading instruction under the control of the first clock signal, and send the first reading instruction to the memory so as to control the memory to read the plurality of image correction parameters to the buffer; and receiving the image correction parameter and the to-be-processed image data sent by the buffer, and performing correction processing to obtain corrected image data.

Description

Image processing system, method, device and computer-readable storage medium Technical Field

[0001] The present disclosure relates to the field of detector technology, and in particular to an image processing system, method, device, and computer-readable storage medium. Background Art

[0002] A flat-panel X-ray detector (FPXD) is a device that converts radiation energy into digital images and is a crucial component in digital imaging technology. Due to its fast imaging speed, excellent spatial and density resolution, high signal-to-noise ratio, and direct digital output, it is widely used in medical imaging (such as chest X-rays), industrial inspection (such as metal flaw detection), security testing, and aviation transportation.

[0003] The production and manufacturing process of FPXDs is complex, requiring high technical processes and precision. Even small fluctuations in the manufacturing process can affect the output image. However, in actual implementation scenarios, process fluctuations are inevitable during the FPXD production process, leading to deviations in image pixel parameters. Therefore, correcting images captured by FPXDs has become a pressing issue.

[0004] In related technologies, the FPXD-based image correction algorithm is processed by the host computer software. For example, after the computer acquires the image data, it performs corresponding algorithm processing to achieve image correction and finally displays it on the screen. Currently, most image correction algorithms are static image acquisition, while FPXD's image acquisition has the characteristics of a larger dynamic range, high acquisition speed and frame rate. The high frame rate dynamic acquisition places higher demands on the processing capabilities of the host computer software. In this case, the algorithm's processing power is limited and cannot handle such a high amount of data. In view of this, some of the content originally processed by the algorithm can be transferred to the board hardware for processing.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide an image processing system, method, device, and computer-readable storage medium.

[0007] In a first aspect, an embodiment of the present disclosure provides an image processing system, comprising: a main control chip, a memory, a buffer, and a clock generator respectively connected to the main control chip, wherein:

[0008] The memory is configured to: store a plurality of predetermined image correction parameters;

[0009] The buffer is configured to: obtain a plurality of image data to be processed;

[0010] The clock generator is configured to: provide a clock signal, wherein the clock signal is used to control writing or reading of the image correction parameter in the memory, and the clock signal includes at least a first clock signal;

[0011] The main control chip is configured to: generate a first read instruction under the control of the first clock signal and send it to the memory to control the memory to read out the multiple image correction parameters to the buffer; and receive the image correction parameters and the image data to be processed sent by the buffer, and perform correction processing to obtain corrected image data.

[0012] In some embodiments, the clock signal further includes a second clock signal;

[0013] The image processing system further includes a processor connected to the main control chip.

[0014] The processor is configured to: determine the image correction parameters; and generate a parameter issuing instruction and send it to the main control chip;

[0015] The main control chip is further configured to: in response to the parameter sending instruction, send the image correction parameter to the buffer at a first communication rate; and at the same time, under the control of the second clock signal, generate a data write instruction and send it to the buffer;

[0016] The buffer is configured to: receive the plurality of image correction parameters, and write the plurality of image correction parameters into the memory at a second communication rate in response to the data write instruction;

[0017] The first communication rate is greater than the second communication rate.

[0018] In some embodiments, the plurality of image correction parameters include a plurality of first parameter groups, each of the first parameter groups includes a sub-parameter corresponding to each pixel in the frame image, and the sub-parameters in different first parameter groups correspond to different image correction types;

[0019] The buffer is specifically configured to, in response to the data write instruction, write the plurality of first parameter groups into the memory in sequence according to a preset order at the second communication rate.

[0020] In some embodiments, the main control chip is further configured to:

[0021] After all of the first parameter groups are stored in the memory, a first feedback instruction is generated and sent to the processor, where the first feedback instruction is used to indicate that the sending of the first parameter groups is complete.

[0022] In some embodiments, the image processing system further includes a processor connected to the main control chip.

[0023] The processor is configured to: generate a parameter return instruction and send it to the main control chip;

[0024] The main control chip is further configured to: in response to the parameter return instruction, generate the second read instruction under the control of the first clock signal and send it to the memory;

[0025] The memory is configured to: in response to the second read instruction, read the plurality of image correction parameters to the buffer at a second communication rate;

[0026] The buffer is configured to: upload the plurality of image correction parameters to the processor via the main control chip at a first communication rate;

[0027] The first communication rate is greater than the second communication rate.

[0028] In some embodiments, the plurality of image correction parameters include a plurality of second parameter groups, each of the second parameter groups includes a plurality of sub-parameters corresponding to a pixel in the frame image, and the sub-parameters in different second parameter groups correspond to different pixels;

[0029] The buffer is specifically configured to receive the plurality of second parameter groups in the memory in sequence according to a preset order at the second communication rate.

[0030] In some embodiments, the buffer is specifically configured as follows:

[0031] receiving, in sequence and in a preset order, a plurality of second parameter groups in the memory at the second communication rate;

[0032] After all the second parameter groups are received, the plurality of second parameter groups are transmitted back to the processor via the main control chip at a first communication rate.

[0033] In some embodiments, the frame image includes n pixels, and the plurality of image correction parameters include a first sub-parameter, a second sub-parameter, and a third sub-parameter corresponding to each pixel;

[0034] The buffer is specifically configured to: in response to the data write instruction, write n first sub-parameters, n second sub-parameters and n third sub-parameters into the memory in sequence at the second communication rate;

[0035] The memory is specifically configured to: in response to the second read instruction, read out the three sub-parameters corresponding to pixel point 1 to pixel point n to the buffer in sequence at the second communication rate.

[0036] In some embodiments, the clock signal further includes a second clock signal;

[0037] The image processing system further includes a processor connected to the main control chip, wherein the processor is configured to: generate an image correction instruction and send the instruction to the main control chip;

[0038] The main control chip is further configured to: generate a first read instruction under the control of the second clock signal in response to the image correction instruction, and send the first read instruction to the memory;

[0039] The memory is further configured to read a plurality of image correction parameters to the buffer at a second communication rate in response to the first read instruction.

[0040] In some embodiments, the plurality of image correction parameters include a plurality of second parameter groups, each of the second parameter groups includes a plurality of sub-parameters corresponding to a pixel in the frame image, and the sub-parameters in different second parameter groups correspond to different pixels;

[0041] The memory is specifically configured to: in response to the first read instruction, sequentially read the plurality of second parameter groups at a second communication rate and in a preset order to cache them in the cache.

[0042] In some embodiments, the buffer is further configured to: integrate the plurality of the image data to be processed and the plurality of second parameter groups, determine the image data to be processed and the second parameter group corresponding to each pixel, and send the data to the main control chip;

[0043] The main control chip is specifically configured to perform image correction processing on multiple pixel points in the frame image one by one according to the image data to be processed corresponding to each pixel point and the second parameter group, so as to obtain the corrected image data corresponding to each pixel point.

[0044] In some embodiments, the frame image includes n pixels, and the plurality of image correction parameters include a first sub-parameter, a second sub-parameter, and a third sub-parameter corresponding to each pixel;

[0045] The buffer is specifically configured to: in response to the data write instruction, write n first sub-parameters, n second sub-parameters and n third sub-parameters into the memory in sequence at the second communication rate;

[0046] The memory is specifically configured to: in response to the first read instruction, read out the three sub-parameters corresponding to pixel points 1 to pixel points n to the buffer in sequence at the second communication rate;

[0047] The buffer is further configured to: perform the following steps in sequence for pixel points 1 to n according to a preset order:

[0048] Receive three sub-parameters corresponding to pixel point i, configure the image data to be processed corresponding to the pixel point i, and send the image data to be processed and the three sub-parameters corresponding to the pixel point i to the main control chip, where 1≤i≤n.

[0049] In some embodiments, the processor is further configured to:

[0050] receiving a plurality of the corrected image data at a first communication rate;

[0051] forming a corrected frame image based on the plurality of corrected image data;

[0052] The first communication rate is greater than the second communication rate.

[0053] In some embodiments, the first communication rate is 0.7 Gbit / s to 10 Gbit / s, and the second communication rate is 40 Mbit / s to 60 Mbit / s.

[0054] In some embodiments, the image processing system further includes a processor and an image acquisition module respectively connected to the main control chip, wherein:

[0055] The processor is configured to: generate an image acquisition instruction and send it to the main control chip;

[0056] The main control chip is configured to: control the image acquisition module to perform data acquisition in response to the image acquisition instruction;

[0057] The image acquisition module is configured to acquire a plurality of the to-be-processed image data according to the frame image and send the data to the buffer.

[0058] In a second aspect, an embodiment of the present disclosure provides an image processing method, the method comprising:

[0059] Acquiring a plurality of image data to be processed and a plurality of predetermined image correction parameters;

[0060] Acquire a clock signal, where the clock signal is used to control writing or reading of the image correction parameter in the memory, and the clock signal includes at least a first clock signal;

[0061] Under the control of the first clock signal, a first read instruction is generated and sent to the memory to control the memory to read the plurality of image correction parameters to the buffer;

[0062] The image correction parameters and the image data to be processed sent by the buffer are received, and correction processing is performed to obtain corrected image data.

[0063] In some embodiments, the clock signal further includes a second clock signal, and the step of obtaining a plurality of image correction parameters includes:

[0064] Determining the image correction parameters and generating parameter delivery instructions;

[0065] In response to the parameter sending instruction, sending the image correction parameters to the buffer at a first communication rate;

[0066] Under the control of the second clock signal, generating a data write instruction and sending the instruction to the buffer;

[0067] receiving a plurality of the image correction parameters, and writing the plurality of the image correction parameters into the memory at a second communication rate in response to the data write instruction;

[0068] The first communication rate is greater than the second communication rate.

[0069] In some embodiments, the method further comprises:

[0070] Generate parameter return instructions;

[0071] In response to the parameter return instruction, generating the second read instruction under the control of the first clock signal;

[0072] In response to the second read instruction, reading the plurality of image correction parameters to the buffer at a second communication rate;

[0073] The first communication rate is greater than the second communication rate.

[0074] In a third aspect, an embodiment of the present disclosure provides an image processing device, including:

[0075] at least one processor; and

[0076] a memory communicatively connected to the at least one processor; wherein,

[0077] The memory stores one or more computer programs that can be executed by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the image processing method as described in the second aspect.

[0078] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the image processing method as described in the second aspect when executed by a processor.

[0079] In the embodiment of the present disclosure, the image correction parameters corresponding to the detection panel are placed in the memory. Given that the memory has non-volatile storage characteristics, data loss after power failure can be avoided. At the same time, the cache mechanism of the buffer can solve the problem of limited memory transmission rate and asynchronous communication with other modules during data transmission. In addition, in the present disclosure, image correction processing is performed by the main control chip. Compared with the existing method of performing image correction processing by upper computer software, based on the strong serial processing capability of the main control chip, it can realize pixel-level operation of high-resolution images, and the processing is more real-time. It is particularly suitable for dynamic acquisition and high-data-volume processing tasks. Therefore, it can meet the high frame rate and high-resolution image correction requirements for the detection panel, improve the image correction rate, and avoid picture delay and frame loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0081] FIG1 is a schematic diagram of the structure of an image processing system provided by an embodiment of the present disclosure.

[0082] FIG2 is a schematic flow chart of an image processing method provided by an embodiment of the present disclosure.

[0083] FIG3 is a flow chart of a parameter delivery process provided by an embodiment of the present disclosure.

[0084] FIG4 is a schematic diagram of a parameter return process provided by an embodiment of the present disclosure.

[0085] FIG5 is a schematic flowchart of an image correction method according to an embodiment of the present disclosure.

[0086] FIG6 is a schematic structural diagram of an image processing device provided by an embodiment of the present disclosure.

[0087] FIG7 is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present disclosure.

[0088] Description of reference numerals: main control chip 1 , buffer DDR, memory SD, processor 2 , data transmission channel 12 , image acquisition module 3 , clock generator 4 . DETAILED DESCRIPTION

[0089] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0090] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0091] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0092] A flat-panel X-ray detector (FPXD) is a device that converts radiation energy into digital images and is a crucial component in digital imaging technology. Due to its fast imaging speed, excellent spatial and density resolution, high signal-to-noise ratio, and direct digital output, it is widely used in medical imaging (such as chest X-rays), industrial inspection (such as metal flaw detection), security testing, and aviation transportation.

[0093] The production and manufacturing process of FPXDs is complex, requiring high technical processes and precision. Even small fluctuations in the manufacturing process can affect the output image. However, in practice, FPXDs inevitably encounter process variations, which can lead to deviations in the pixel parameters of the images captured by the FPXDs. Therefore, correcting the images captured by FPXDs has become a pressing issue.

[0094] In related technologies, the FPXD-based image correction algorithm is processed by the host computer software. For example, after the computer acquires the image data, it performs corresponding algorithm processing to achieve image correction and finally displays it on the screen. Currently, most image correction algorithms are static image acquisition, while FPXD's image acquisition has the characteristics of a larger dynamic range, high acquisition speed and frame rate. The high frame rate dynamic acquisition places higher demands on the processing capabilities of the host computer software. In this case, the algorithm's processing power is limited and cannot handle such a high amount of data. In view of this, some of the content originally processed by the algorithm can be transferred to the board hardware for processing.

[0095] Furthermore, when the board serves as the primary processor for the image correction algorithm, the board's self-processing algorithm can be fully implemented by the board itself. However, this type of algorithm typically places high demands on the board's main control chip, primarily using RAM for parameter calculation and storage. In this case, if the device loses power, all data in the RAM is lost, requiring recalculation upon powering back on. Furthermore, the board's main control chip's operations on the entire image frame are complex and computationally intensive, severely impacting image correction efficiency.

[0096] In order to solve at least one of the above-mentioned technologies, the embodiments of the present disclosure provide an image processing system that can meet the detection panel's correction requirements for high frame rate and high resolution images, improve the image correction rate, and avoid image delay and frame loss.

[0097] Figure 1 is a structural diagram of the image processing system provided by an embodiment of the present disclosure. As shown in Figure 1, the image processing system includes: a main control chip 1, a memory SD, a buffer DDR, and a clock generator 4 respectively connected to the main control chip 1, and the memory SD and the buffer module DDR are interconnected.

[0098] The memory SD is configured to store a plurality of predetermined image correction parameters; the buffer DDR is configured to obtain a plurality of image data to be processed; the clock generator 4 is configured to provide a clock signal, which is used to control the writing or reading of the image correction parameters in the memory SD, and the clock signal includes at least a first clock signal; the main control chip 1 is configured to generate a first read instruction under the control of the first clock signal, and send it to the memory SD to control the memory SD to read the image correction parameters to the buffer DDR; and receive the image correction parameters and the image data to be processed sent by the buffer, and perform correction processing to obtain the corrected image data.

[0099] In the embodiment of the present disclosure, the image correction parameters of the detection panel are placed in the memory. Given that the memory has non-volatile storage characteristics, data loss after power failure can be avoided. At the same time, the cache mechanism of the buffer can solve the problem of limited memory transmission rate and asynchronous communication with other modules during data transmission. In the present disclosure, image correction processing is performed by the main control chip. Compared with the existing method of performing image correction processing by upper computer software, based on the strong serial processing capability of the main control chip, it can realize pixel-level operation of high-resolution images, and the processing is more real-time. It is particularly suitable for dynamic acquisition and high-data-volume processing tasks. Therefore, it can meet the high frame rate and high-resolution image correction requirements for the detection panel, improve the image correction rate, and avoid picture delay and frame loss.

[0100] It should be noted that the above-mentioned multiple image data to be processed can be image data corresponding to each pixel in the image to be processed; the multiple image correction parameters can be at least one parameter corresponding to each pixel. Specifically, the number of correction parameters corresponding to each pixel can be determined according to the number of correction types. For example, image correction includes three aspects: bad pixel removal, background noise removal, and gain compensation. Then the multiple image correction parameters can be three correction parameters corresponding to each pixel, namely, a bad pixel removal correction parameter, a background noise removal correction parameter, and a gain compensation parameter. Of course, other correction types can also be included in the image correction process, and the embodiments of the present disclosure are not limited to this.

[0101] In one example, the main control chip may be an FPGA chip. The FPGA chip has a strong serial processing capability for images, can stably forward parameters and perform image correction processing, and has high reliability.

[0102] In the embodiments of the present disclosure, the memory may be an SD memory card. An SD memory card is a memory device based on semiconductor flash memory. It features non-volatile storage, preventing data loss even in the event of a power outage. It is widely used due to its compact size, fast data transfer speed, and hot-swappability. In other embodiments, the memory may also be a Flash memory card, ROM memory, or the like. As long as the memory features non-volatile storage, the specific type of memory is not limited in the embodiments of the present disclosure.

[0103] The buffer may be a double data rate synchronous dynamic random access memory (DDR), which has a fast interface read and write speed and can provide a higher bandwidth for data transmission, and is more suitable for dynamic acquisition with high frame rate and high resolution.

[0104] The clock generator may include a clock oscillator circuit with a precisely determined oscillation frequency. This circuit, in conjunction with the oscillator circuit within the main control chip, forms a "quartz crystal resonator" (abbreviated as "crystal oscillator") to generate the clock signals required by each system. In a specific implementation, a multivibrator within the main control chip first generates an oscillation with a wide frequency spectrum. This oscillation signal, containing multiple "harmonic frequencies," is output from the main control chip and directly applied to both ends of the clock oscillator circuit. The clock oscillator circuit precisely selects the desired clock frequency, which is then fed back to the main control chip to control the multivibrator's oscillation frequency. In this way, the entire clock generator operates at the frequency selected by the clock oscillator circuit, generating a clock pulse with a stable frequency and constant amplitude that is provided to the system. This enables these storage devices with different structures and functions to operate in coordination under the control of the clock signal, at a unified data transmission rate (bit / s) and within a prescribed timing, thereby orderly completing the reception and transmission of image correction parameters and various instructions.

[0105] In some embodiments, as shown in FIG1 , the image processing system further includes a processor 2 connected to the main control chip 1 , and the processor 2 is configured to determine image correction parameters and send the image correction parameters to the memory SD.

[0106] It should be understood that the processor 2 can be a specific hardware structure or a virtual module structure formed by host computer software, that is, the corresponding functions are realized through algorithms / programs, which is not limited in the embodiments of the present disclosure.

[0107] It should be understood that after the detection panel is manufactured, it needs to undergo performance testing. During the testing process, a corresponding calibration image, i.e., the original image, is configured for use in generating correction parameters for the detection. Specifically, processor 2 sends a command to capture the original image to main control chip 1. In response to the command, main control chip 1 controls image acquisition module 3 to acquire image data and returns the acquired original image data to processor 2. Furthermore, processor 2 analyzes the original image data based on a preset algorithm and determines the image correction parameters corresponding to the detection panel for subsequent image correction.

[0108] Furthermore, the image correction process is primarily divided into two steps: generating image correction parameters and performing correction processing using the image correction parameters. During the image correction parameter generation process, in order to ensure the integrity and smoothness of the displayed image, it is necessary to obtain the image data of the current frame and at least one historical frame. For high-frame-rate and high-resolution images, this requires a very large amount of data, and the calculation process is extremely complex. Therefore, when processor 2 is the host computer software, the generation of image correction parameters can be completely performed by processor 2 and then sent to memory SD.

[0109] It should be understood that in the prior art, image correction is only performed by processor 2. In this case, processor 2 not only needs to receive and display high-frame-rate images, but also needs to perform algorithm correction. This process involves repeated reading and writing of a large amount of data, and the control process is complex, resulting in large delays in the algorithm processing process, and even frame loss, which makes it impossible to guarantee normal image display. In the embodiment of the present disclosure, on the one hand, processor 2 performs the step of generating image correction parameters, and on the other hand, main control chip 1 performs the step of performing correction processing using the image correction parameters. The processor 2, i.e., the upper computer software, and main control chip 1, i.e., the board-level main control chip, are used to perform collaborative processing to correct dynamic high-frame-rate images, which greatly leverages the processing advantages of software and hardware, reasonably allocates the working mechanisms of each module, and implements image correction processing based on dynamic high-frame-rate and high-resolution, rationally utilizes resources, reduces the cost of design, and effectively improves the performance of the image correction system.

[0110] In some embodiments, the image processing system further includes a data transmission channel 12 connected to the main control chip 1 and the processor 2, respectively, and configured to enable communication between the processor 2 and the main control chip 1. In one example, the data transmission channel 12 can be an Ethernet transmission mechanism, that is, the main control chip 1 can be connected to the processor 2 via Ethernet to enable signaling interaction, data upload and download, etc. between the two.

[0111] In some embodiments, the clock signal also includes a second clock signal; the processor 2 is configured to: determine the image correction parameters; and, generate a parameter sending instruction and send it to the main control chip 1; the main control chip 1 is further configured to: respond to the parameter sending instruction, send the image correction parameters to the buffer DDR at a first communication rate; at the same time, under the control of the second clock signal, generate a data write instruction and send it to the buffer DDR; the buffer DDR is configured to: receive multiple image correction parameters, and in response to the data write instruction, write the multiple image correction parameters to the memory SD at a second communication rate; wherein the first communication rate is greater than the second communication rate.

[0112] As can be seen from the above disclosure, processor 2 generates image correction parameters, sends them to main control chip 1 via Ethernet, and ultimately stores them in memory SD. Typically, the transmission rate of Gigabit Ethernet is about 1Gbit / s, and the transmission rate of 10Gbit / s can even reach 10Gbit / s for 10Gbit / s, while the transmission rate of memory SD is only about 50Mbit / s. In other words, the rate at which processor 2 sends image correction parameters does not match the rate at which memory SD writes them to its storage space. This results in a phenomenon where parameters are transmitted quickly but written slowly, which can easily lead to parameter loss.

[0113] Based on this, in the embodiment of the present disclosure, the image correction parameters sent by the processor 2 are first read out into the buffer DDR to solve the problem that the rates of parameter sending and parameter writing are different, resulting in Ethernet error packet return, slow parameter writing or even loss; the buffer DDR then slowly stores the image correction parameters into the memory SD to avoid the problem that the parameters of the buffer DDR are lost and need to be rewritten in the event of power failure.

[0114] Specifically, in the embodiment of the present disclosure, a clock signal is generated by the clock generator 4, and the communication rate between the buffer DDR and the memory SD is controlled based on the clock signal, so as to minimize the data reading / writing time as much as possible within the allowable transmission rate of the memory SD and improve the efficiency of image correction.

[0115] In an example, the clock generator 4 is configured to generate a first clock signal and a second clock signal, wherein the first clock signal is used to control the reading rate of the buffer DDR reading data stored in the memory SD; the second clock signal is used to control the writing rate of the buffer DDR writing data to the memory SD.

[0116] In some embodiments, the plurality of image correction parameters include a plurality of first parameter groups, each of which includes a sub-parameter corresponding to each pixel in the frame image, and the sub-parameters in different first parameter groups correspond to different image correction types. The buffer DDR is specifically configured to, in response to a data write instruction, sequentially write the plurality of first parameter groups to the memory SD in a predetermined order at the second communication rate.

[0117] It should be noted that the correction processing performed by the main control chip 1 based on the image correction parameters includes multiple correction types, such as bad pixel correction, background noise correction, gain compensation, etc.

[0118] Based on this, the multiple first parameter groups mentioned above can be a bad pixel correction parameter group, a noise reduction correction parameter group, and a gain compensation parameter group. The bad pixel correction parameter group includes a bad pixel correction parameter corresponding to each pixel in the frame image; the noise reduction correction parameter group includes a noise reduction correction parameter corresponding to each pixel in the frame image; and the gain compensation parameter group includes a gain compensation parameter corresponding to each pixel in the frame image. That is, different first parameter groups are written to the memory SD one by one according to the correction type. Furthermore, the order in which the multiple types of first parameter groups are written is not limited in the presently disclosed embodiments.

[0119] In some embodiments, the main control chip 1 is further configured to generate a first feedback instruction after all the first parameter groups are stored in the memory SD, and send it to the processor 2 , where the first feedback instruction is used to indicate that the sending of the first parameter groups is complete.

[0120] Since the processor 2 transmits the image correction parameters to the main control chip 1 through the data transmission channel 12, namely Ethernet high-speed transmission, and the memory SD is written at a low speed under the cache of the buffer DDR, the communication rates of the two do not match and communication synchronization cannot be achieved. Therefore, after the buffer DDR writes all the image correction parameters into the memory SD, the main control chip 1 needs to send a first feedback instruction to the processor 2 to form a complete image correction parameter sending process.

[0121] Based on the above analysis, it can be seen that in the embodiment of the present disclosure, on the one hand, the processor 2 performs the step of generating image correction parameters, and on the other hand, the main control chip 1 performs the step of using the image correction parameters for correction processing. Among them, the image correction parameters are related to the model of the corresponding detection panel.

[0122] Based on this, parameter transmission is required when replacing the mobile terminal corresponding to processor 2. Specifically, the above content has shown that processor 2 is a host computer software, that is, it is implemented through a mobile terminal. Mobile terminal A determines the image correction parameters and stores them in memory SD. Furthermore, if mobile terminal A is damaged, it can be replaced with mobile terminal B. In this case, it is only necessary to switch the communication interface between the mobile terminal and the main control chip 1. After the connection is established, the image correction parameters stored in memory SD are transmitted back to mobile terminal B, thereby eliminating the need to recalculate the parameters and saving computing resources.

[0123] In one example, since the mobile terminal and main control chip 1 are connected via a communication interface, the same mobile terminal can be connected to either main control chip 1A or main control chip 1B. Main control chip 1A serves as the control terminal for detection panel A, while main control chip 1B serves as the control terminal for detection panel B. Furthermore, processor 2 stores image correction parameters A corresponding to detection panel A. When its communication interface is switched to connect to main control chip 1B, processor 2 can directly analyze image correction parameters A based on the product interoperability between detection panels A and B, and determine image correction parameters B using a preset algorithm for subsequent image correction processing, significantly saving computing resources.

[0124] It should also be noted that the detection panel and the main control chip can be communicated through an independently set interface board. That is, when the main control chip remains unchanged, image acquisition supporting different models of detection panels can be achieved by simply replacing the interface board.

[0125] In some embodiments, the processor 2 is configured to: generate a parameter return instruction and send it to the main control chip 1; the main control chip 1 is further configured to: in response to the parameter return instruction, generate a second read instruction under the control of a first clock signal and send it to the memory SD; the memory SD is configured to: in response to the second read instruction, read multiple image correction parameters at a second communication rate to cache them in the buffer DDR; the buffer DDR is configured to: upload the multiple image correction parameters to the processor 2 via the main control chip 1 at a first communication rate; wherein the first communication rate is greater than the second communication rate.

[0126] During the parameter transmission process, the memory SD reads data at a slow rate, while the processor 2 receives data at a fast rate. Therefore, the main control chip 1 controls the buffer DDR to read the image correction parameters at a slow rate. That is, the image correction parameters are cached in the buffer DDR and then transmitted to the processing unit at a high speed by the buffer DDR to solve the communication rate mismatch between the memory SD and the processor 2.

[0127] In some embodiments, the multiple image correction parameters include multiple second parameter groups, each second parameter group includes multiple sub-parameters corresponding to one of the pixel points in the frame image, and the sub-parameters in different second parameter groups correspond to different pixels; the buffer DDR is specifically configured to: read the multiple second parameter groups in the memory SD in sequence according to a preset order at a second communication rate.

[0128] As can be seen from the above description, during the parameter transmission process, the buffer DDR receives data at a slow rate and sends data to the processor 2 at a fast rate. To avoid clock crosstalk and data packet loss, the buffer DDR in the embodiment of the present disclosure adopts a time-sharing method to respectively receive and send parameters.

[0129] In some embodiments, the buffer is specifically configured to sequentially receive multiple second parameter groups from the memory at the second communication rate in a preset order; after all second parameter groups have been received, the buffer is then transmitted back to the processor via the main control chip at the first communication rate. The buffer, based on time-sharing processing, avoids clock crosstalk and data packet loss, and addresses issues such as memory and processor clock mismatch and inconsistent communication rates.

[0130] In some embodiments, the processor 2 is further configured to: generate an image correction instruction and send it to the main control chip 1; the main control chip 1 is further configured to: generate a first read instruction under the control of a second clock signal in response to the image correction instruction, and send the first read instruction to the buffer DDR; the buffer DDR is further configured to: read multiple image correction parameters in the memory SD at a second communication rate in response to the first read instruction.

[0131] In the embodiment of the present disclosure, the processor 2 issues an image correction instruction, and the main control chip 1 generates a first read instruction in response to the image correction instruction, so as to control the buffer DDR to read the image correction parameters located in the memory SD through the first read instruction.

[0132] During the image correction process, the image correction parameters need to be cached in the buffer DDR first, so that the main control chip 1 can perform correction processing on the image data to be processed based on the parameters. It should be understood that during the correction processing, the main control chip 1 processes multiple pixels in the image one by one, and for each pixel, there are multiple correction types. For example, in the same example as the above example, each pixel corresponds to three image correction parameters, namely, bad pixel correction parameters, background noise correction parameters and gain compensation parameters. At this time, when the main control chip 1 performs correction processing on each pixel, it should obtain the image data to be processed corresponding to the pixel and the above three sub-parameters before correction.

[0133] In some embodiments, the plurality of image correction parameters include a plurality of second parameter groups, each second parameter group including a plurality of sub-parameters corresponding to a pixel in the frame image, where the sub-parameters in different second parameter groups correspond to different pixels. The memory SD is specifically configured to, in response to the first read instruction, sequentially read the plurality of second parameter groups at the second communication rate and in a predetermined order, and cache them in the buffer DDR.

[0134] That is, the main control chip 1 first places the image data and correction parameters corresponding to each pixel into the buffer DDR. Specifically, the buffer DDR responds to the first read instruction to obtain the image data to be processed for the target pixel and, at the same time, obtains the second parameter set for the target pixel, which includes the bad pixel correction parameter, noise background correction parameter, and gain compensation parameter corresponding to the target pixel.

[0135] During the parameter distribution process, image correction parameters are transmitted from processor 2 to main control chip 1, then to buffer DDR, and then written from buffer DDR to memory SD. Parameters are written sequentially. For example, if there are n pixels, the writing order is: bad pixel correction parameter module (1-n), noise reduction parameter module (1-n), and gain compensation parameter module (1-n). However, when correcting the image, the parameter reading method requires skipping. Specifically, due to the serial processing characteristics of main control chip 1 in the parameter reading and writing control of buffer DDR, the image data corresponding to the target pixel and the correction parameters of the three algorithms must be obtained synchronously at the same time. The order is 1 (bad pixel removal 1, noise reduction 1, gain compensation 1), 2 (bad pixel removal 2, noise reduction 2, gain compensation 2), ... n (bad pixel removal n, noise reduction n, gain compensation n). This achieves pixel-level image correction processing on main control chip 1.

[0136] In some embodiments, the buffer DDR is further configured to integrate the plurality of image data to be processed and the plurality of second parameter groups to determine the image data to be processed and the second parameter group corresponding to each pixel. The main control chip 1 is specifically configured to perform image correction processing on the plurality of pixels in the frame image one by one based on the image data to be processed and the second parameter group corresponding to each pixel, thereby obtaining corrected image data corresponding to each pixel.

[0137] In the embodiment of the present disclosure, the process of performing image correction processing using a preset algorithm to obtain corrected image data is not described in detail.

[0138] In some embodiments, the processor 2 is further configured to: receive a plurality of corrected image data at a first communication rate; and form a corrected frame image based on the plurality of corrected image data; wherein the first communication rate is greater than the second communication rate.

[0139] It should be understood that the image correction processing performed by the main control chip 1 is a pixel-level processing thread. Based on this, the processor 2 can generate a driving signal according to the corrected image data to form a corrected frame image on the detection panel.

[0140] In some embodiments, the first communication rate is the communication rate between the data transmission channel 12 and the processor 2, and the second communication rate is the communication rate when the memory SD writes or reads data, wherein the first communication rate is 0.7Gbit / s~10Gbit / s, and the second communication rate is 40Mbit / s-60Mbit / s.

[0141] In some embodiments, as shown in FIG1 , the image processing system further includes a processor 2 and an image acquisition module 3, each connected to a main control chip 1. The processor 2 is configured to generate an image acquisition instruction and send it to the main control chip 1; the main control chip 1 is configured to control the image acquisition module 3 to perform data acquisition in response to the image acquisition instruction; and the image acquisition module 3 is configured to acquire a plurality of image data to be processed based on a frame image and send it to a buffer DDR.

[0142] Specifically, the above-mentioned image acquisition instruction can be an instruction for acquiring an image to be processed, or it can be an instruction for acquiring an original image, which is not limited in the embodiment of the present disclosure.

[0143] In one example, the image acquisition module 3 includes a source controller and a gate controller, and the main control chip 1 acquires image data to be processed by controlling the driving timing of the source controller and the gate controller.

[0144] In some embodiments, the image acquisition module 3 is further configured to perform display according to the corrected image data to display the corrected frame image.

[0145] It should be understood that the image data collected by the image acquisition module 3 in the embodiment of the present disclosure is data on the detection panel.

[0146] In summary, the image correction system provided by the embodiments of the present disclosure includes a DDR buffer that performs numerous read and write control operations. Specifically, the DDR buffer can perform the following functions: 1. During parameter delivery, the buffer receives image correction parameters at a fast rate and writes them to the memory SD at a slow rate, resolving the issue of clock asynchrony between Ethernet writes and memory SD writes, thus preventing parameter loss and, consequently, image frame loss and display failure. 2. When reading parameters and writing them to its own storage space, it provides a mechanism to avoid retransmission of error packets during Ethernet transmission. 3. The DDR buffer's read operations during image correction, or during parameter return, are not processed in parallel but in a time-sharing manner. That is, the buffer DDR first reads the image correction parameters from the memory SD at the second communication rate, and after all reads are complete, sends them to the processor 2 at the first communication rate. 4. During parameter return or image correction, the buffer reads parameters from the memory SD and writes them to the DDR buffer, resolving the issue of asynchrony between the memory SD read clock and the image processing or Ethernet return module clock.

[0147] In the disclosed embodiment, the image correction function is moved to the main control chip by adding a DDR buffer and SD memory to the image processing system. Furthermore, considering the main control chip's inability to operate on data blocks, the image correction parameters are pre-generated by the host computer software, i.e., the processor, and then transmitted to the main control chip, which then stores them in the memory. This allows the main control chip to read the parameters from the memory and perform correction processing on the acquired image data during normal image acquisition, fully utilizing the main control chip's serial processing capabilities. Ultimately, the corrected image data is transmitted to the processor, effectively ensuring processing speed and high image frame rate requirements.

[0148] Based on the same inventive concept above, an embodiment of the present disclosure further provides an image processing method, which is applied to the image processing system provided by any of the above embodiments.

[0149] FIG2 is a schematic flow chart of an image processing method provided by an embodiment of the present disclosure. As shown in FIG2 , the image processing method includes steps S1 to S4, which are specifically as follows:

[0150] Step S1: Acquire a plurality of image data to be processed and a plurality of predetermined image correction parameters.

[0151] Step S2: Acquire a clock signal, where the clock signal is used to control writing or reading of image correction parameters in the memory SD. The clock signal includes at least a first clock signal.

[0152] The first clock signal is used to control the reading rate of the buffer DDR reading data stored in the memory SD; the clock signal may also include a second clock signal for controlling the writing rate of the buffer DDR writing data into the memory SD.

[0153] In step S3 , under the control of the first clock signal, a first read instruction is generated and sent to the memory SD, so as to control the memory SD to read the image correction parameters into the buffer DDR.

[0154] Step S4: receiving the image correction parameters and the image data to be processed sent by the buffer DDR, and performing correction processing to obtain corrected image data.

[0155] In the disclosed embodiment, the image correction parameters are placed in the memory SD. Given that the memory SD has non-volatile storage characteristics, this can prevent data loss after a power outage. At the same time, the caching mechanism of the buffer DDR can solve the problem of limited transmission rate of the memory SD and asynchronous communication with other modules during data transmission.

[0156] It should be noted that the image processing method provided in the embodiment of the present disclosure is applied to the above-mentioned image processing system. The specific structure and functions of each module of the image processing system are shown in FIG1 and the above-mentioned embodiment, which will not be described in detail.

[0157] The image processing method provided by the embodiment of the present disclosure is described in detail below with reference to the modules in FIG. 1 and specific embodiments corresponding to the three processing processes of parameter sending, parameter returning, and image correction.

[0158] Example 1: Parameter Distribution

[0159] FIG3 is a flow chart of a parameter sending process provided by an embodiment of the present disclosure. As shown in FIG3 , the image correction parameters determined by the processor 2 are sent to the memory SD, that is, the step of obtaining multiple image correction parameters in step S1 includes:

[0160] In step S11 , the processor 2 determines image correction parameters and generates a parameter delivery instruction.

[0161] The processor 2 determining the image correction parameters may include: the processor 2 sending an original image acquisition instruction to the main control chip 1; the main control chip 1 controlling the image acquisition module 3 to acquire image data in response to the original image acquisition instruction, and returning the acquired original image data to the processor 2. Furthermore, the processor 2 performs data analysis on the original image data based on a preset algorithm to determine the image correction parameters for subsequent image correction.

[0162] In some embodiments, the image acquisition module 3 can be a detection panel, and the processor determines the image correction parameters corresponding to the detection panel. It should be understood that the production and preparation process of the detection panel is complex, and it has high requirements for process flow, production accuracy, etc., and even small fluctuations in the production process may affect the output image. However, in actual implementation scenarios, process fluctuations are inevitable in the production and preparation of the detection panel. Detection panels of different sizes and models will result in different differences in the final product. Based on this, for different models of detection panels, the processor analyzes the original image data and determines the corresponding image correction parameters using a preset algorithm.

[0163] The above parameter sending instruction is sent to the main control chip 1 through the data transmission channel 12, that is, through Ethernet transmission.

[0164] In step S12 , the main control chip 1 sends the image correction parameters to the buffer DDR at the first communication rate in response to the parameter sending instruction; and generates a data write instruction under the control of the second clock signal and sends it to the buffer DDR.

[0165] In step S13 , the buffer DDR receives the plurality of image correction parameters and writes the plurality of image correction parameters into the memory SD at a second communication rate in response to the data write instruction, wherein the first communication rate is greater than the second communication rate.

[0166] Specifically, the multiple image correction parameters include multiple first parameter groups, each of which includes a sub-parameter corresponding to each pixel in the frame image, and the sub-parameters in different first parameter groups correspond to different image correction types. The buffer DDR is specifically configured to, in response to a data write instruction, sequentially write the multiple first parameter groups to the memory SD in a preset order at the second communication rate.

[0167] The multiple first parameter groups may include a bad pixel correction parameter group, a noise reduction correction parameter group, and a gain compensation parameter group. The bad pixel correction parameter group includes a bad pixel correction parameter corresponding to each pixel in the frame image; the noise reduction correction parameter group includes a noise reduction correction parameter corresponding to each pixel in the frame image; and the gain compensation parameter group includes a gain compensation parameter corresponding to each pixel in the frame image. Specifically, different first parameter groups are written to the memory SD one by one according to the correction type.

[0168] In step S14, after the memory SD completes writing the multiple image correction parameters, it feeds back the first information to the main control chip 1; after receiving the first information, the main control chip 1 generates a first feedback instruction and sends it to the processor 2. The first feedback instruction is used to indicate that the multiple image correction parameters have been sent.

[0169] Example 2: Parameter Return

[0170] FIG4 is a flow chart of a parameter return process provided by an embodiment of the present disclosure. As shown in FIG4 , after the parameters are sent, the image processing method may further include: returning the image correction parameters determined by the memory SD to the processor 2 , which may include steps S01 to S03 , specifically as follows:

[0171] In step S01, the processor 2 generates a parameter return instruction.

[0172] The above parameter return instruction is sent to the main control chip 1 through the data transmission channel 12, that is, through Ethernet transmission.

[0173] Step S02 : In response to the parameter return instruction, a second read instruction is generated under the control of the first clock signal and sent to the memory SD.

[0174] In step S03 , the memory SD reads the plurality of image correction parameters to the buffer at the second communication rate in response to the second read instruction.

[0175] In step S04 , the buffer DDR uploads the plurality of image correction parameters at a first communication rate; wherein the first communication rate is greater than the second communication rate.

[0176] It should be noted that the write operations of the buffer DDR during image correction, or the read and write operations during parameter transmission, are not processed in parallel but in a time-sharing manner. That is, the buffer DDR first reads the image correction parameters from the memory SD at the second communication rate, and after all transmissions are completed, sends them to the processor 2 at the first communication rate. The first communication rate and the second communication rate are transmission rates of different levels, meaning that the rate at which the buffer DDR sends parameters is much higher than the rate at which it receives parameters. At this point, the buffer DDR does not employ parallel processing, meaning it does not process parameters by simultaneously receiving and sending. Instead, the two operations of receiving and sending parameters are independent of each other, without interfering with each other. This avoids clock crosstalk and data packet loss. Furthermore, the image correction parameters correspond to each pixel on the detection panel, and the orderly transmission of the image correction parameters ensures the effectiveness of image correction.

[0177] Example 3: Image Correction

[0178] FIG5 is a schematic flow chart of an image correction provided by an embodiment of the present disclosure. As shown in FIG5 , the process in which the main control chip 1 obtains image correction parameters and corrects the image data to be processed according to the image correction parameters may include the above-mentioned steps S3, S4, and S5, wherein step S3 includes steps S31 to S34, and step S4 includes step S40, specifically as follows:

[0179] In step S31 , the processor 2 generates an image correction instruction.

[0180] In step S32 , the main control chip 1 generates a first read instruction in response to the image correction instruction under the control of the first clock signal, and sends the first read instruction to the memory SD.

[0181] In step S33, the memory SD responds to the first read instruction by reading out the second parameter set corresponding to each pixel point one by one at the second communication rate and in a predetermined read order. The second parameter set includes multiple sub-parameters corresponding to a pixel point in the frame image, with the sub-parameters in different second parameter sets corresponding to different pixels. Specifically, the second parameter set includes a bad pixel removal correction parameter, a noise floor correction parameter, and a gain compensation parameter corresponding to the target pixel point.

[0182] In step S34, the buffer DDR obtains the image data to be processed corresponding to the pixel while receiving the second parameter group corresponding to the pixel, and integrates the image data to be processed and the second parameter group corresponding to the same pixel, determines the image data to be processed and the second parameter group corresponding to each pixel, and sends them to the main control chip.

[0183] The image data to be processed corresponding to the pixel points is acquired by the image acquisition module 3 .

[0184] That is, during the image correction process, the parameter reading method requires skipping. Specifically, in the parameter reading and writing control of the buffer DDR, since the main control chip 1 has the characteristics of serial processing, it is necessary to synchronously obtain the image data to be processed corresponding to the target pixel and the correction parameters of the three algorithms at a certain time point. The order is 1 (bad pixel removal 1, noise removal 1, gain compensation 1), 2 (bad pixel removal 2, noise removal 2, gain compensation 2)...n (bad pixel removal n, noise removal n, gain compensation n), thus realizing the pixel-level image correction processing of the main control chip 1.

[0185] In step S40 , the main control chip 1 performs image correction processing on multiple pixels in the frame image one by one according to the image data to be processed corresponding to each pixel and the second parameter group, to obtain corrected image data corresponding to each pixel.

[0186] In step S5 , the processor 2 receives the plurality of corrected image data at a first communication rate, and forms a corrected frame image according to the plurality of corrected image data.

[0187] Figure 6 is a structural schematic diagram of an image processing device provided by an embodiment of the present disclosure. As shown in Figure 6, the electronic device 100 includes: a storage module 101 and a processing module 102. The storage module 101 stores a computer program, wherein when the computer program is executed by the processing module 102, the above-mentioned image processing method is implemented, for example, steps S1 to S4 in Figure 2 are implemented.

[0188] The electronic device 100 may be a computing device such as a desktop computer, laptop, PDA, or cloud server. The electronic device 100 may include, but is not limited to, a processing module 102 and a storage module 101. Those skilled in the art will appreciate that FIG6 is merely an example of the electronic device 100 and does not limit the electronic device 100. The electronic device 100 may include more or fewer components than shown, or may combine certain components or different components. For example, the electronic device 100 may also include input / output devices, network access devices, buses, and the like.

[0189] The processing module 102 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processing module 102 may be a microprocessor, or the processor may be any conventional processor, etc.

[0190] The storage module 101 can be an internal storage unit of the electronic device 100, such as a hard disk or memory of the electronic device 100. The storage module 101 can also be an external storage device of the electronic device 100, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 100. Furthermore, the storage module 101 can also include both the internal storage unit of the electronic device 100 and an external storage device. The storage module 101 is used to store the computer program and other programs and data required by the terminal device. The storage module 101 can also be used to temporarily store data that has been output or is to be output.

[0191] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0192] FIG7 is a schematic diagram of the structure of a computer-readable storage medium provided by an embodiment of the present disclosure. As shown in FIG7 , a computer program 201 is stored on a computer-readable storage medium 200, wherein the computer program 201 implements the above-mentioned image processing method when executed by a processor, for example, implementing steps S1 to S4 in FIG2 . The computer-readable storage medium 200 includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally contain computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0193] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A bracket structure, an image processing system, wherein: include: A main control chip, a memory, a buffer, and a clock generator respectively connected to the main control chip, and the memory and the buffer are connected to each other, wherein: The memory is configured to: store a plurality of predetermined image correction parameters; The buffer is configured to: obtain a plurality of image data to be processed; The clock generator is configured to: provide a clock signal, the clock signal is used to control the writing or reading of the image correction parameter in the memory, the clock signal at least comprising a first clock signal; The main control chip is configured to: generate a first read instruction under the control of the first clock signal and send it to the memory to control the memory to read out the multiple image correction parameters to the buffer; and receive the image correction parameters and the image data to be processed sent by the buffer, and perform correction processing to obtain corrected image data.

2. The image processing system according to claim 1, wherein: The clock signal also includes a second clock signal; The image processing system further includes a processor connected to the main control chip. The processor is configured to: determine the image correction parameters; and generate a parameter sending instruction and send it to the main control chip; The main control chip is further configured to: in response to the parameter sending instruction, send the image correction parameter to the buffer at a first communication rate; at the same time, under the control of the second clock signal, generate a data write instruction and send it to the buffer; The buffer is configured to: receive the plurality of image correction parameters, and in response to the data write instruction, write the plurality of image correction parameters into the memory at a second communication rate; The first communication rate is greater than the second communication rate.

3. The image processing system according to claim 2, wherein: The plurality of image correction parameters include a plurality of first parameter groups, each of the first parameter groups includes a sub-parameter corresponding to each pixel in the frame image, and the sub-parameters in different first parameter groups correspond to different image correction types; The buffer is specifically configured to, in response to the data write instruction, write the plurality of first parameter groups into the memory in sequence according to a preset order at the second communication rate.

4. The image processing system according to claim 3, wherein: The main control chip is also configured as: After all of the first parameter groups are stored in the memory, a first feedback instruction is generated and sent to the processor, where the first feedback instruction is used to indicate that the sending of the first parameter groups is complete.

5. The image processing system according to claim 3, wherein: The image processing system further includes a processor connected to the main control chip. The processor is configured to: generate a parameter return instruction and send it to the main control chip; The main control chip is further configured to: in response to the parameter return instruction, under the control of the first clock signal, generate the second read instruction and send it to the memory; The memory is configured to: in response to the second read instruction, read out the plurality of image correction parameters to the buffer at a second communication rate; The buffer is configured to: transmit the plurality of image correction parameters back to the processor via the main control chip at a first communication rate; The first communication rate is greater than the second communication rate.

6. The image processing system according to claim 5, wherein: The plurality of image correction parameters include a plurality of second parameter groups, each of the second parameter groups includes a plurality of sub-parameters corresponding to one of the pixels in the frame image, and the sub-parameters in different second parameter groups correspond to different pixels; The buffer is specifically configured to receive the plurality of second parameter groups in the memory in sequence according to a preset order at the second communication rate.

7. The image processing system according to claim 6, wherein: The cache is specifically configured as follows: receiving a plurality of second parameter groups in the memory in sequence according to a preset order at the second communication rate; After all the second parameter groups are received, the plurality of second parameter groups are transmitted back to the processor via the main control chip at a first communication rate.

8. The image processing system according to claim 6, wherein: The frame image includes n pixels, and the plurality of image correction parameters include a first sub-parameter, a second sub-parameter and a third sub-parameter corresponding to each pixel; The buffer is specifically configured to: in response to the data write instruction, write n first sub-parameters, n second sub-parameters and n third sub-parameters into the memory in sequence at the second communication rate; The memory is specifically configured to: in response to the second read instruction, read out the three sub-parameters corresponding to pixel point 1 to pixel point n to the buffer in sequence at the second communication rate.

9. The image processing system according to claim 3, wherein: The clock signal also includes a second clock signal; The image processing system further includes a processor connected to the main control chip, wherein the processor is configured to: generate an image correction instruction and send the instruction to the main control chip; The main control chip is further configured to: generate a first read instruction under the control of the second clock signal in response to the image correction instruction, and send the first read instruction to the memory; The memory is further configured to read a plurality of image correction parameters to the buffer at a second communication rate in response to the first read instruction.

10. The image processing system according to claim 9, wherein: The plurality of image correction parameters include a plurality of second parameter groups, each of the second parameter groups includes a plurality of sub-parameters corresponding to one of the pixels in the frame image, and the sub-parameters in different second parameter groups correspond to different pixels; The memory is specifically configured to: in response to the first read instruction, sequentially read a plurality of the second parameter groups at a second communication rate and in a preset order, so as to cache them in the buffer.

11. The image processing system according to claim 10, wherein: The buffer is further configured to: integrate the plurality of the image data to be processed and the plurality of second parameter groups, determine the image data to be processed and the second parameter group corresponding to each pixel, and send them to the main control chip; The main control chip is specifically configured to perform image correction processing on multiple pixel points in the frame image one by one according to the image data to be processed corresponding to each pixel point and the second parameter group, so as to obtain the corrected image data corresponding to each pixel point.

12. The image processing system according to claim 11, wherein: The frame image includes n pixels, and the plurality of image correction parameters include a first sub-parameter, a second sub-parameter and a third sub-parameter corresponding to each pixel; The buffer is specifically configured to: respond to the data write instruction with the second channel signal rate, sequentially writing n of the first sub-parameters, n of the second sub-parameters, and n of the third sub-parameters into the memory; The memory is specifically configured to: in response to the first read instruction, read out three sub-parameters corresponding to pixel points 1 to pixel points n to the buffer in sequence at the second communication rate; The buffer is further configured to: for pixel points 1 to n, perform the following steps in sequence according to a preset order: Receive three sub-parameters corresponding to pixel point i, configure the image data to be processed corresponding to the pixel point i, and send the image data to be processed and the three sub-parameters corresponding to the pixel point i to the main control chip, where 1≤i≤n.

13. The image processing system according to claim 11, wherein: The processor is further configured to: receiving a plurality of the corrected image data at a first communication rate; forming a corrected frame image according to the plurality of corrected image data; The first communication rate is greater than the second communication rate.

14. The image processing system according to any one of claims 2 to 13, wherein: The first communication rate is 0.7 Gbit / s to 10 Gbit / s, and the second communication rate is 40 Mbit / s to 60 Mbit / s.

15. The image processing system according to claim 1, wherein: The image processing system further includes a processor and an image acquisition module respectively connected to the main control chip, wherein: The processor is configured to: generate an image acquisition instruction and send it to the main control chip; The main control chip is configured to: in response to the image acquisition instruction, control the image acquisition module to perform data acquisition; The image acquisition module is configured to acquire a plurality of the to-be-processed image data according to the frame image, and send the data to the buffer.

16. An image processing method of an image processing system according to any one of claims 1 to 15, wherein: The method comprises: Acquiring a plurality of image data to be processed and a plurality of predetermined image correction parameters; Acquire a clock signal, where the clock signal is used to control writing or reading of the image correction parameter in the memory, and the clock signal at least includes a first clock signal; Under the control of the first clock signal, a first read instruction is generated and sent to the memory, so as to control the memory to read the plurality of image correction parameters to the buffer; The image correction parameters and the image data to be processed sent by the buffer are received, and correction processing is performed to obtain corrected image data.

17. The image processing method according to claim 16, wherein: The clock signal also includes a second clock signal, and the step of acquiring a plurality of image correction parameters includes: Determining the image correction parameters and generating parameter delivery instructions; In response to the parameter sending instruction, sending the image correction parameter to the buffer at a first communication rate; Under the control of the second clock signal, generating a data write instruction and sending it to the buffer; receiving a plurality of the image correction parameters, and in response to the data writing instruction, writing the plurality of the image correction parameters into the memory at a second communication rate; The first communication rate is greater than the second communication rate.

18. The image processing method according to claim 16, wherein: The method further comprises: Generate parameter return instructions; In response to the parameter return instruction, generating the second read instruction under the control of the first clock signal; In response to the second read instruction, reading the plurality of image correction parameters to the buffer at a second communication rate; uploading a plurality of the image correction parameters at a first communication rate; The first communication rate is greater than the second communication rate.

19. An image processing device, wherein: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor so that the at least one processor can perform the image processing method according to any one of claims 16 to 18.

20. A computer-readable storage medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the computer program implements the image processing method according to any one of claims 16 to 18.

Images