Data verification method and device for programming operation and electronic equipment

Abstract

The invention relates to the technical field of semiconductor digital verification, and discloses a data verification method for programming operation, which comprises the following steps: determining the width of verification data according to the organization form of a flash array; setting a plurality of groups of data modes with the same length according to the width of the verification data; wherein each group of data modes comprises a plurality of programming data; verifying each group of data modes in sequence to obtain verification results; wherein the verification result represents whether an address corresponding to the programming data in the data mode needs to be programmed or not; and executing a programming instruction on the address needing to be programmed to perform data verification until all the data modes are verified. According to the method, the data verification is more comprehensive, and the verification efficiency is also improved. The invention further discloses a data verification device for the programming operation and electronic equipment.

Description

Technical Field

[0001] The present application relates to the field of semiconductor digital verification technology, for example, to a data verification method and device, and electronic equipment for programming operations. Background Art

[0002] In the current field of FLASH storage technology, the execution of programming operations relies on sophisticated control logic, which involves precise management of the internal state machine of the FLASH memory and strict control of the data transmission process. The state machine is responsible for controlling the various operating states of the FLASH memory, such as idle, programming, erasing, and reading, to ensure that these states can be correctly converted in a predetermined order. The data transmission process involves transferring data from the main controller to the FLASH chip, and also includes data buffering, error detection, and verification. In order to ensure the correctness and reliability of programming operations in the FLASH memory, a series of verification steps must be performed.

[0003] In order to verify the correctness of the programming operation, the related art discloses a verification scheme, including sending a data chain of random width and random value during programming; after the programming operation is completed, reading out these data chains to check whether they are consistent.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] Random values ​​are not constrained, resulting in most of them being non-8'hff random values, which need to be programmed and then verified. This can only trigger a very small part of the state machine, most of the state jumps are not triggered, and it is not certain whether there is a bug. Although the random data changes each time, it cannot necessarily cover other state jumps.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a data verification method and device, and an electronic device for programming operations, which make data verification more comprehensive and improve the efficiency of verification.

[0009] In some embodiments, the data verification method for programming operations includes: determining the width of verification data according to the organizational form of the flash array; setting multiple groups of data patterns with the same length according to the width of the verification data; wherein each group of data patterns includes multiple programming data; verifying each group of data patterns in turn to obtain verification results; wherein the verification results represent whether the addresses corresponding to the programming data in the data patterns need to be programmed; executing programming instructions on the addresses that need to be programmed to perform data verification until all data patterns have completed verification.

[0010] Optionally, each group of data patterns is verified in turn to obtain a verification result, including: determining whether the data pattern is all-f data; when the data pattern is all-f data, the verification result is that all bytes of the data pattern pass; when the data pattern is not all-f data, the verification result is that non-f bytes in the data pattern fail.

[0011] Optionally, judging whether the data pattern is all-f data includes: judging the data pattern is all-f data when all programming data in the data pattern is 8'hff; judging the data pattern is not all-f data when there is programming data in the data pattern that is not 8'hff.

[0012] Optionally, determining the width of the verification data according to the organization form of the flash array includes: obtaining a maximum byte length of a single verification of the state machine according to the organization form of the flash array; and using the maximum byte length as the width of the verification data.

[0013] Optionally, according to the width of the verification data, multiple groups of data patterns with the same length are set, including: when the width of the verification data is N, the data pattern is set to 2 N .

[0014] Optionally, data verification is performed, including: reading data at an address programmed by a programming instruction through a read instruction; and verifying whether the data at the address programmed by the programming instruction is correct, so as to verify the jump of the state machine.

[0015] Optionally, each group of data patterns is verified in turn to obtain a verification result, and the method further includes: after the current data pattern is verified, switching to an empty address to verify the next group of data patterns.

[0016] Optionally, a programming instruction is executed on the address to be programmed to perform data verification until all data patterns have been verified, and the method also includes: after the current data pattern has been verified, determining whether the current data pattern is the last group of data patterns; if the current data pattern is the last group of data patterns, determining that all data patterns have been verified; if the current data pattern is not the last group of data patterns, verifying the next group of data patterns.

[0017] In some embodiments, the data verification device for programming operation includes a processor and a memory storing program instructions, and the processor is configured to execute the data verification method for programming operation as described above when running the program instructions.

[0018] In some embodiments, the electronic device includes: an electronic device body; and a data verification device for programming operations as described above, installed in the electronic device body.

[0019] The data verification method and device for programming operation and the electronic device provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the programming operation of the FLASH memory, in order to ensure that the data is correctly written into the storage unit and maintain its integrity, the width of the verification data is first determined according to the organizational form of the FLASH array. Then, based on the determined verification data width, multiple groups of data patterns with the same length are set, and each group of data patterns contains multiple programming data. Then, each group of data patterns is verified in turn, and the verification results are obtained through the read operation. For the address that needs to be programmed according to the verification result, the programming instruction is executed, the data is written into the FLASH memory, and the data verification is completed. This process continues until all preset data patterns are verified. Through a systematic verification process, the accuracy of the programming operation and the integrity of the data in the FLASH memory are ensured. From the perspective of state jump, the disclosed embodiment ignores the details of the state machine design, and performs all possible permutations and combinations of the programming data according to the bytes that need to be programmed and the bytes that do not need to be programmed. There is no need to design a lot of cases for each state, which reduces the number of cases, reduces the maintenance of cases, and increases the reusability of cases. Even if there are changes in the code design and the state machine changes, there is no need to rewrite the case, only the data verification width needs to be modified. This ensures coverage of all state jumps without the need for multiple random executions, which not only saves simulation time, but also saves time for modifying cases, greatly improving efficiency while ensuring the comprehensiveness of data verification.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1is a schematic diagram of an implementation environment of a data verification method for programming operation according to an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of a data verification method for programming operation provided by an embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of another data verification method for programming operation provided by an embodiment of the present disclosure;

[0026] Figure 4 is a schematic diagram of another data verification method for programming operation provided by an embodiment of the present disclosure;

[0027] Figure 5 Schematic diagram of a data verification device for programming operation provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0029] The terms "first", "second", etc. in the technical solutions described in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0030] Unless otherwise stated, the term "plurality" means two or more.

[0031] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0032] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0033] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0034] In today's semiconductor technology, FLASH storage technology has become one of the preferred options for data storage due to its non-volatile characteristics. However, the complexity of FLASH memory programming operations requires precise control logic and strict verification steps to ensure the correctness and reliability of the operation. FLASH memory programming involves the careful management of the internal state machine and the strict control of the data transmission process, which together determine whether data can be accurately and durably written to the storage unit.

[0035] The storage structure of FLASH memory is complex, consisting of a large number of storage cells, which are organized in pages and blocks. Therefore, the programming operation must be performed accurately on the correct page and block address to avoid data corruption or loss. In addition, due to the limited programming / erase cycles of FLASH memory cells, the accuracy of the programming operation is directly related to the service life of the memory. Improper programming may not only cause data errors, but also accelerate the aging of the storage cells and shorten the service life of the memory.

[0036] During data transmission, data integrity must be ensured to prevent data corruption due to noise, interference or hardware failure. FLASH programming operations also require specific voltage conditions and strict timing control. Improper voltage or timing may cause programming failure or data errors. Therefore, error detection and verification steps, such as parity check, CRC check, etc., are essential to ensure that data has not been tampered with during transmission.

[0037] In summary, in order to ensure the correctness and reliability of programming operations in FLASH memory, it is crucial to perform a series of verification steps. These steps include data integrity check, state machine verification, programming result verification, etc., to ensure the correct writing of data and the long-term stability of the memory.

[0038] In order to verify the correctness of the programming operation, the embodiment of the present disclosure performs verification from the perspective of digital state machine control, and verifies the jump of the state machine by traversing the combination of programming and non-programming within a fixed interval length.

[0039] Figure 1 FIG. 1 is a schematic diagram of an implementation environment of a data verification method for programming operation according to an embodiment of the present disclosure. Figure 1 As shown, the implementation environment may include a digital state machine 100 and a processor 500 .

[0040] The processor 500 can input all programming data combinations, and the digital state machine 100 can implement data verification by traversing these combinations.

[0041] Combination Figure 2 As shown, the embodiment of the present disclosure provides a data verification method for a programming operation, comprising:

[0042] S201: The processor determines the width of the verification data according to the organization form of the flash array.

[0043] S202, the processor sets a plurality of groups of data patterns with the same length according to the width of the verification data; wherein each group of data patterns includes a plurality of programming data.

[0044] S203, the processor verifies each group of data patterns in turn to obtain a verification result; wherein the verification result indicates whether the address corresponding to the programming data in the data pattern needs to be programmed.

[0045] S204, the processor executes a programming instruction on the address to be programmed to perform data verification until all data patterns have completed verification.

[0046] According to the method provided by the embodiment of the present disclosure, in the programming operation of the FLASH memory, in order to ensure that the data is correctly written into the storage unit and maintain its integrity, the width of the verification data is first determined according to the organizational form of the FLASH array. Then, based on the determined verification data width, multiple groups of data patterns with the same length are set, and each group of data patterns contains multiple programming data. Then, each group of data patterns is verified in turn, and the verification result is obtained through a read operation. For the address that needs to be programmed according to the verification result, the programming instruction is executed, and the data is written into the FLASH memory to complete the data verification. This process continues until all preset data patterns are verified. Through a systematic verification process, the accuracy of the programming operation and the integrity of the data in the FLASH memory are ensured. Starting from the perspective of state jump, the embodiment of the present disclosure ignores the details of the state machine design, and performs all possible permutations and combinations of the programming data according to the bytes that need to be programmed and the bytes that do not need to be programmed. There is no need to design a lot of cases for each state, which reduces the number of cases, reduces the maintenance of cases, and increases the reusability of cases. Even if there are changes in the code design and the state machine changes, there is no need to rewrite the case, and only the data verification width needs to be modified. This ensures coverage of all state jumps without the need for multiple random executions, which not only saves simulation time, but also saves time for modifying cases, greatly improving efficiency while ensuring the comprehensiveness of data verification.

[0047] Optionally, each group of data patterns is verified in turn to obtain a verification result, including: determining whether the data pattern is all-f data; when the data pattern is all-f data, the verification result is that all bytes of the data pattern pass; when the data pattern is not all-f data, the verification result is that non-f bytes in the data pattern fail.

[0048] In the disclosed embodiment, the system verifies each set of preset data patterns in turn. Each set of data patterns consists of multiple bytes, which may be all f (i.e., all bits are 1, representing data that does not need to be programmed) or contain non-f bytes (i.e., contain 0, representing data that needs to be programmed). The verification process first determines whether the data pattern is all f data. If the data pattern is all f data, the verification result will mark all bytes of the data pattern as pass, meaning that no further programming operations are required. On the contrary, if the data pattern is not all f data, that is, it contains bytes that need to be programmed, the system will identify these non-f bytes and mark them as fail, indicating that these addresses need to be programmed. In this way, the data that needs to be programmed can be accurately identified, thereby avoiding unnecessary programming operations and improving programming efficiency and the service life of the memory.

[0049] Optionally, judging whether the data pattern is all-f data includes: judging the data pattern is all-f data when all programming data in the data pattern is 8'hff; judging the data pattern is not all-f data when there is programming data in the data pattern that is not 8'hff.

[0050] In the disclosed embodiment, each programming data in each group of data patterns is checked one by one. "All f data" means that each byte in the data pattern is 8'hff, that is, 1111 in binary representation, which means that the byte does not need to be programmed and is already in the initial state of the FLASH memory programming operation. The system checks byte by byte to confirm whether each byte in the data pattern meets the 8'hff standard. If all bytes are 8'hff, the system determines that the data pattern is all f data, which means that all bytes of the entire data pattern are marked as pass, indicating that the requirements have been met and no further programming operation is required. On the contrary, if any byte is found in the data pattern that is not 8'hff, that is, there is programming data that is not 8'hff, the system determines that the data pattern is non-all f data. In this case, the system will further mark the non-8'hff bytes as fail, indicating that these bytes need to be programmed. This precise judgment mechanism can improve the accuracy and efficiency of the programming operation, and reduce unnecessary programming operations by quickly identifying the data that needs to be programmed and the data that is not needed. Secondly, traversing the combination of programming and non-programming within a fixed interval length makes data verification more comprehensive.

[0051] Optionally, determining the width of the verification data according to the organization form of the flash array includes: obtaining a maximum byte length of a single verification of the state machine according to the organization form of the flash array; and using the maximum byte length as the width of the verification data.

[0052] In the disclosed embodiment, according to the organizational form of the FLASH array, it is necessary to identify and obtain the maximum byte length of a single check of the state machine. The length is usually related to the physical structure of the FLASH array. For example, the FLASH memory is programmed in pages, and usually, the size of a page may be 256 bytes. This maximum byte length is the maximum amount of data that the state machine can process in a single operation. Then, the system uses the maximum byte length as the width of the check data, that is, when performing data verification, each operation will check the data of the maximum byte length.

[0053] By determining the width of the verification data, the system can organize and execute verification operations more efficiently. Each verification is performed on a data block of a fixed size, which helps reduce redundant operations during the verification process and improves verification efficiency while ensuring verification accuracy.

[0054] Optionally, according to the width of the verification data, multiple groups of data patterns with the same length are set, including: when the width of the verification data is N, the data pattern is set to 2 N .

[0055] In the embodiment of the present disclosure, when the width of the check data is determined to be N bytes, the number of data patterns is set to 2. N Each byte has two states: need to be programmed (non-8'hff) and do not need to be programmed (8'hff), thus generating all possible combinations. Each combination is programmed and verified to check the state machine of the FLASH memory.

[0056] Optionally, data verification is performed, including: reading data at an address programmed by a programming instruction through a read instruction; and verifying whether the data at the address programmed by the programming instruction is correct, so as to verify the jump of the state machine.

[0057] In the disclosed embodiment, a programming instruction is executed in the FLASH memory to write a specific data pattern to a predetermined address. Subsequently, the data in these programmed addresses are read by sending a read instruction. After the read instruction is executed, the system obtains the data in the memory and compares it with the expected programming data. If the read data is consistent with the expected data, it can be considered that the programming operation of the address is successful and the state machine jumps correctly. If it is inconsistent, it indicates that the programming operation has failed or there is a problem with the state machine jump. Specifically, if a byte in the data pattern is non-8'hff, then during verification, the byte should change from the initial state (usually all 1, i.e. 8'hff) to the programmed state (non-8'hff), thereby confirming the success of the programming operation.

[0058] The disclosed embodiment provides a direct and effective way to verify whether the programming operation of the FLASH memory is successful, ensuring the integrity and accuracy of the data. Secondly, through verification, it can be detected whether the state machine jumps according to the expected logic to ensure the reliability and stability of the FLASH memory. In addition, this method helps to promptly discover and correct errors that may occur during the programming process, reduce the risk of data corruption, and increase the service life of the memory. At the same time, the verification process can also optimize the development and verification costs, reduce the number of test cases that need to be designed, and improve the efficiency and accuracy of the test.

[0059] Optionally, each group of data patterns is verified in turn to obtain a verification result, and the method further includes: after the current data pattern is verified, switching to an empty address to verify the next group of data patterns.

[0060] Combination Figure 3 As shown, the embodiment of the present disclosure provides another data verification method for programming operation, comprising:

[0061] S301, the processor determines the width of the verification data according to the organization form of the flash array.

[0062] S302, the processor sets a plurality of data patterns of the same length according to the width of the verification data; wherein each data pattern includes a plurality of programming data.

[0063] S303, the processor verifies each group of data patterns in turn and obtains verification results; wherein the verification results indicate whether the addresses corresponding to the programming data in the data patterns need to be programmed. After the current data pattern is verified, the empty address is switched to verify the next group of data patterns.

[0064] S304, the processor executes a programming instruction on the address to be programmed to perform data verification until all data patterns have completed verification.

[0065] In the disclosed embodiment, the system selects an empty address, that is, an address area that has not been programmed, as the verification area for the current data pattern. According to the set data pattern, data is written to the empty address through programming instructions. After programming is completed, the data in the address is read through a read instruction and compared with the expected data pattern to verify whether the data is programmed correctly. Once the verification of the current data pattern is completed, regardless of whether the result passes or not, it will switch to the next empty address to ensure that the verification of the next set of data patterns will not be affected by the previous data.

[0066] This ensures that the verification of each set of data patterns is performed in an independent and consistent environment, avoiding data contamination caused by repeated use of addresses. Secondly, this method improves the accuracy of verification, as each verification is performed on a brand new address, reducing potential errors caused by changes in address status.

[0067] Optionally, a programming instruction is executed on the address to be programmed to perform data verification until all data patterns have been verified, and the method also includes: after the current data pattern has been verified, determining whether the current data pattern is the last group of data patterns; if the current data pattern is the last group of data patterns, determining that all data patterns have been verified; if the current data pattern is not the last group of data patterns, verifying the next group of data patterns.

[0068] Combination Figure 4 As shown, the embodiment of the present disclosure provides another data verification method for programming operation, comprising:

[0069] S401, the processor determines the width of the verification data according to the organization form of the flash array.

[0070] S402, the processor sets a plurality of data patterns of the same length according to the width of the verification data; wherein each data pattern includes a plurality of programming data.

[0071] S403, the processor verifies each group of data patterns in turn to obtain a verification result; wherein the verification result indicates whether the address corresponding to the programming data in the data pattern needs to be programmed.

[0072] S404, the processor executes a programming instruction on the address to be programmed to perform data verification.

[0073] S405, after completing verification of the current data pattern, the processor determines whether the current data pattern is the last set of data patterns.

[0074] S406: When the current data pattern is the last group of data patterns, the processor determines that all data patterns have completed verification.

[0075] S407: When the current data pattern is not the last data pattern, the processor verifies the next data pattern.

[0076] In the disclosed embodiment, a programming instruction is executed for each address that needs to be programmed, and a predetermined data pattern is written into the FLASH memory. After programming is completed, the data of the address is read and compared with the expected data to verify whether the data is programmed correctly. Once the verification of the current data pattern is completed, it will be determined whether the current data pattern is the last group of data patterns. If the current data pattern is the last group, the system will determine that all data patterns have been verified, and the entire verification process ends. If the current data pattern is not the last group, the system will automatically verify the next group of data patterns until all preset data patterns are verified. In this way, it is ensured that each group of data patterns can be verified one by one, thereby fully covering all programming states of the FLASH memory and improving the comprehensiveness and accuracy of the verification.

[0077] Combination Figure 5 As shown, the embodiment of the present disclosure provides a data verification device 50 for programming operation, including a processor 500 and a memory 501. Optionally, the device 50 may also include a communication interface 502 and a bus 503. The processor 500, the communication interface 502, and the memory 501 may communicate with each other through the bus 503. The communication interface 502 may be used for information transmission. The processor 500 may call the logic instructions in the memory 501 to execute the data verification method for programming operation of the above embodiment.

[0078] In addition, the logic instructions in the memory 501 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0079] The memory 501 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor 500 executes the functional application and data processing by running the program instructions / modules stored in the memory 501, that is, the data verification method for programming operation in the above-mentioned embodiments is implemented.

[0080] The memory 501 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 501 may include a high-speed random access memory and may also include a non-volatile memory.

[0081] The embodiments of the present disclosure provide an electronic device, comprising: an electronic device body, and the above-mentioned data verification device for programming operations. The data verification device for programming operations is installed on the electronic device body. The installation relationship described here is not limited to placement inside the electronic device body, but also includes installation connections with other components of the electronic device, including but not limited to physical connections, electrical connections, or signal transmission connections. It can be understood by those skilled in the art that the data verification device for programming operations can be adapted to a feasible electronic device body, thereby realizing other feasible embodiments.

[0082] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0083] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0084] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0085] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0086] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A data verification method for programming operation, characterized in that: include: Determine the width of the verification data according to the organization of the flash array; According to the width of the verification data, a plurality of data patterns of the same length are set; wherein each data pattern includes a plurality of programming data; Verifying each group of data patterns in turn to obtain verification results; wherein the verification results indicate whether the addresses corresponding to the programming data in the data patterns need to be programmed; Execute the programming instruction for the address to be programmed to perform data verification until all data patterns have been verified.

2. The data verification method according to claim 1, characterized in that: Verify each set of data patterns in turn and obtain verification results, including: Determine whether the data mode is full f data; In the case where the data pattern is all f data, the verification result is that all bytes of the data pattern pass; When the data pattern is non-all-f data, the verification result is that the non-f bytes in the data pattern fail.

3. The data verification method according to claim 2, characterized in that: Determine whether the data mode is full f data, including: When each programming data in the data pattern is 8'hff, the data pattern is determined to be all-f data; When there is programming data other than 8'hff in the data pattern, it is determined that the data pattern is not all-f data.

4. The data verification method according to claim 1, characterized in that: Determine the width of the verification data according to the organization of the flash array, including: According to the organization form of the flash array, obtain the maximum byte length of a single check of the state machine; Use the maximum byte length as the width of the checksum data.

5. The data verification method according to claim 1, characterized in that: According to the width of the verification data, set multiple groups of data patterns with the same length, including: When the width of the check data is N, the data mode is set to 2 N .

6. The data verification method according to any one of claims 1 to 5, characterized in that: Perform data verification, including: Read the data of the address programmed by the programming instruction through the read instruction; Verify whether the data at the address programmed by the programming instruction is correct to verify the jump of the state machine.

7. The data verification method according to any one of claims 1 to 5, characterized in that: Verify each set of data patterns in turn and obtain verification results, which also includes: After the current data pattern is verified, the empty address is switched to verify the next set of data patterns.

8. The data verification method according to any one of claims 1 to 5, characterized in that: Execute programming instructions on the addresses to be programmed to perform data verification until all data patterns are verified, including: After the current data pattern is verified, determine whether the current data pattern is the last set of data patterns; In the case where the current data pattern is the last set of data patterns, determining that all data patterns have completed verification; When the current data pattern is not the last set of data patterns, verification of the next set of data patterns is performed.

9. A data verification device for programming operation, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the data verification method for programming operation according to any one of claims 1 to 8 when running the program instructions.

10. An electronic device, characterized in that: include: Electronic device body; The data verification device for programming operation as claimed in claim 9 is installed in the electronic device body.

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