Filter instruction code generation method applied to controller

Abstract

The invention discloses a filtering instruction code generation method applied to a controller, and relates to the technical field of controller logic design. According to the filtering instruction code generation method, a structured query statement input by a user is obtained, then the structured query statement input by the user is processed to obtain a first instruction code, and a second instruction code is generated according to the first instruction code; generating a first truth table according to the logical operation in the first instruction code, and generating a second truth table according to the first truth table; finally, a third instruction code is generated according to the second instruction code, and a permutation matrix is determined according to the third instruction code; and determining the second instruction code, the second truth table and the permutation matrix as a filtering instruction code applied to the controller, and configuring the filtering instruction code applied to the controller into the controller. By the adoption of the technical scheme, the speed of database calculation operation can be increased, and the throughput rate of database calculation can be effectively increased and delay can be effectively reduced for calculation-intensive operation in the database.

Description

Technical Field

[0001] The present application relates to the technical field of controller logic design, and in particular to a method for generating filtering instruction codes applied to a controller. Background Art

[0002] Database operations generally require a lot of computing resources and time. In related technologies, the central processing unit (CPU) is used for serial execution, but CPU-based execution can only use serial computing to execute computing tasks in the database one by one. As the amount of data continues to grow, performance bottlenecks will be faced when processing large-scale data sets.

[0003] Therefore, there is an urgent need for a filtering instruction code generation method for a controller that can increase the speed of database computing operations and effectively improve the database computing throughput and reduce latency for computationally intensive operations in the database. Summary of the invention

[0004] The present application provides a method for generating filtering instruction codes applied to a controller to improve the speed of database computing operations. For computing-intensive operations in the database, it can effectively improve the throughput of database computing and reduce latency.

[0005] The present application provides a method for generating a filtering instruction code applied to a controller, which is executed by a host side, and the method includes: Obtaining a structured query statement input by a user, and generating a filtering expression according to the structured query statement input by the user; Generate a first instruction code according to the filtering expression, and generate a second instruction code according to the first instruction code; cyclically executing the logic operation in the first instruction code to generate a first truth table, and generating a second truth table according to the first truth table; generating a third instruction code according to the second instruction code, and determining a permutation matrix according to the third instruction code; The second instruction code, the second truth table and the permutation matrix are determined as a filtering instruction code applied to a controller, and the filtering instruction code applied to the controller is configured in the controller.

[0006] The present application also provides a filtering instruction code generation device applied to a controller, which is executed by a host side, and the device includes: A first acquisition module is used to acquire a structured query statement input by a user, and generate a filtering expression according to the structured query statement input by the user; A first generating module, used to generate a first instruction code according to the filtering expression, and to generate a second instruction code according to the first instruction code; A second generating module, used for cyclically executing the logic operation in the first instruction code to generate a first truth table, and generating a second truth table according to the first truth table; A third generating module, used to generate a third instruction code according to the second instruction code, and determine a permutation matrix according to the third instruction code; A determination module is used to determine the second instruction code, the second truth table and the permutation matrix as a filtering instruction code applied to a controller, and configure the filtering instruction code applied to the controller into the controller.

[0007] The present application also provides a host, including: a memory for storing a computer program; a processor for implementing the steps of the above-mentioned method for generating a filtering instruction code applied to a controller when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method for generating a filtering instruction code applied to a controller are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned method for generating a filtering instruction code applied to a controller when the computer program is executed by a processor.

[0010] Through the present application, by obtaining a structured query statement input by a user, and then processing the structured query statement input by the user, a first instruction code is obtained, and based on the first instruction code, a second instruction code is generated, and then a first truth table is generated based on the logical operation in the first instruction code, and then a second truth table is generated based on the first truth table. Finally, a third instruction code is generated based on the second instruction code, and a permutation matrix is ​​determined based on the third instruction code; the second instruction code, the second truth table and the permutation matrix are determined as filtering instruction codes applied to the controller, and the filtering instruction code applied to the controller is configured in the controller. The use of this technical solution can improve the speed of database computing operations, and for computationally intensive operations in the database, it can effectively improve the throughput of database computing and reduce latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 A schematic diagram of a structure comparison between a multi-core CPU technology and an FPGA hardware acceleration technology provided in an embodiment of the present application; Figure 2 A schematic diagram of creating a corresponding hardware circuit in an FPGA provided in an embodiment of the present application; Figure 3 A schematic diagram of a circuit structure provided in an embodiment of the present application; Figure 4 A schematic diagram of a user configuration circuit structure provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure comparison between hardware acceleration of structured query statements and related technologies provided in an embodiment of the present application; Figure 6 A schematic diagram of an overall architecture provided for an embodiment of the present application; Figure 7 A flowchart of a method for generating a filtering instruction code applied to a controller provided in an embodiment of the present application; Figure 8 A schematic diagram of a filtering expression provided in an embodiment of the present application; Fig. 9 A schematic diagram of parallel processing of row data provided in an embodiment of the present application; Fig.10 A schematic diagram of a process for generating a first instruction code provided in an embodiment of the present application; Fig.11 A schematic diagram of a second instruction code generation process provided in an embodiment of the present application; Fig.12 A schematic diagram of a second truth table generation process provided in an embodiment of the present application; Fig.13 A schematic diagram of the execution process of a filtering expression provided in an embodiment of the present application; Fig.14 A schematic diagram of a generation process of a third instruction code provided in an embodiment of the present application; Fig.15 A flowchart of a method for generating a filtering instruction code applied to a controller provided in an embodiment of the present application; Fig.16 A schematic diagram of a valid bit mask generation process provided in an embodiment of the present application; Fig.17 A schematic diagram of a search code generation process provided in an embodiment of the present application; Fig.18 A schematic diagram of the structure of a permutation matrix provided in an embodiment of the present application; Fig.19A schematic diagram of the structure of a filtering instruction code generating device applied to a controller provided in an embodiment of the present disclosure; Fig. 20 It is a structural diagram of a host in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0014] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0015] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0016] In this embodiment, the multi-core CPU technology in the related art has alleviated the performance bottleneck of database computing to a certain extent. However, since the CPU is designed for general computing, the complexity of its architecture design requires a large amount of logic resources, resulting in a limited number of CPU cores that can be created, and the parallel computing improvement effect is still not ideal. In order to increase the speed of database computing operations, FPGA hardware acceleration technology is used. For computationally intensive operations in the data, customized dedicated circuits are used. A large number of dedicated logic circuits are used to form acceleration cores for parallel computing, which can effectively improve the throughput of database computing and reduce latency. For details, please refer to Figure 1 A schematic diagram showing a structural comparison between multi-core CPU technology and FPGA hardware acceleration technology.

[0017] Specifically, in the related art, the entire calculation process of the structured query statement is implemented by creating a corresponding hardware circuit in the FPGA to accelerate the computing performance.

[0018] The structured query statement may be an SQL statement. This technical solution uses customized circuit calculation in FPGA for the calculation process of a structured query statement, and obtains extremely high calculation throughput, showing the great potential of FPGA in improving database performance. For details, please refer to Figure 2 A schematic diagram showing a corresponding hardware circuit created in an FPGA. Figure 2 For the Q6 query statement in the TPC-H test set, in this technical solution: First, the filtering calculation process of the where clause part is converted into 3 range comparisons and 2 and logic operations, and the corresponding logic circuit is created in the FPGA, and its logic circuit is only 3 range comparators and 2 logic and operations. After that, the data that meets the conditions is multiplied again, and its logic circuit is only filtering and a multiplication operation. Finally, the data after the multiplication calculation is accumulated in the FPGA, and its logic circuit is only an accumulator. The FPGA logic structure in the solution is simple and efficient, occupies very little resources, and can perform high-throughput concurrent pipeline operations, thereby obtaining extremely high computing performance.

[0019] Specifically, in the related technology, redundant calculations can also be used to achieve dynamic support for structured query statements. This technical solution only processes the where clause part of the structured query statement, and is used to accelerate the filtering calculation of the scan query. The circuit structure in the solution is composed of multiple parallel comparators and tree-shaped logical operators. Parallel computing acceleration is achieved by creating multiple comparator circuits. Each comparator circuit contains all possible comparison operations. The comparators are connected to each other through pipelines to transfer row data. The user configures the selector in the comparator to select the data to be used, so as to achieve dynamic support for structured query statements. See also Figure 3 For example, for the filter condition where (a = 2020-01-01) and (b>100) or(c<0.5) entered by the user, you can refer to Figure 4 A schematic diagram of a user configuration circuit structure is shown. Figure 4 The configuration method is as follows: 1) The first filter condition: a=2020-01-01, column a is of date type, the selector of comparator 1 is configured as date type, and the operator selector is =.

[0020] 2) The second filter condition: b>100, b is an integer, the selector of comparator 2 is configured as an integer, and the operator selector is >.

[0021] 3) The third filter condition: c<0.5, c is a floating point number, the selector of comparator 2 is configured as a floating point number, and the operator selector is <.

[0022] 4) The fourth filter condition is an AND operation between the first and second filter conditions, so the first selector of the first layer in the tree logic operation circuit is configured as an AND operation.

[0023] 5) The fifth filter condition is an OR operation between the fourth filter condition and the third filter condition, so the second layer selector in the tree logic operation circuit is configured as an OR calculation.

[0024] After the circuit in the technical solution starts to operate, all possible operations will be executed. The user configures the selector in the circuit to select the comparison operation and logical operation used in this structured query statement, thereby realizing dynamic support for the structured query statement.

[0025] In the related technology, the use of FPGA for database hardware acceleration still faces technical challenges: how to support complex and changeable structured query statements in customized fixed circuits is the core problem that needs to be solved in the related technical field. Since FPGA is a customized circuit, it can only perform computing tasks in a fixed format after the logic design is completed. In related technology one, only fixed-format filtering queries can be supported, and users can only replace the constant part in the predefined SQL statement, which leads to extremely limited application scenarios. In actual applications, the structured query statements input by users are often more complex and changeable. Therefore, the problem that needs to be solved urgently is how to customize the FPGA circuit so that it can adapt to complex structured query statements.

[0026] How to reduce resource consumption to create more parallel computing units. Each logic circuit in the FPGA consumes on-chip logic resources. In order to create more parallel computing units, the FPGA design should save the consumption of logic resources as much as possible.

[0027] The exhaustive method used in the related technology 2 designs all possible computing circuits in each computing unit, and selects the results used in this structured query statement from the calculation results. Although this design can improve the parallel computing performance by creating a large number of computing units, there are a large number of redundant and invalid logic circuits, resulting in a large consumption of logic resources, which in turn leads to a limited number of supported filtering conditions and the number of computing units created.

[0028] In response to the above problems, this embodiment proposes a hardware acceleration method for structured query statements, which splits the calculation operations in the structured query statements and maps them to the calculation units of the FPGA accelerator. It supports dynamic structured query statements through matrix operations, and implements parallel calculation of multiple rows in the data table through the long bit width data input of the FPGA, thereby improving the parallel calculation performance, greatly reducing the consumption of redundant circuits, and improving the overall performance of the accelerator. For details, please refer to Figure 5 A schematic diagram showing a structural comparison between hardware acceleration of a structured query statement and related technologies is shown.

[0029] In this embodiment, the comparator and the logic operator are optimized and designed, specifically including: (1) Create a comparator operation unit with the corresponding number or ratio according to the column field type in the table to be queried.

[0030] (2) In the comparator operation unit, the maximum data bit width of the data bus is used as the input of the comparator to realize the comparison operation of column fields in multiple rows at the same time.

[0031] (3) The results of all comparison operation units are input into the permutation matrix multiplier as valid values.

[0032] (4) In the permutation matrix multiplier, parallel matrix multiplication operations are used to merge the valid calculation results in this calculation to form a search code.

[0033] (5) Use the search code to find the corresponding result value in the truth table, which serves as the value to determine whether the SQL filter operation result meets the filter condition.

[0034] The following is an example: For example, you can refer to the different types of data shown in Table 1. There are a total of 8 column fields, including 2 integer type columns (column A and column C), 2 date type columns (column E and column G), 3 floating point type columns (column B, column D, column F), and 1 string type (column H).

[0035] Table 1 Different types of data

[0036] In related technologies, if full-column comparison filtering is to be supported, a comparison calculation unit is created for each column field. The calculation unit is composed of multiple different types of comparators, including all possible data types. For Table 1, at least 8 comparison calculation units need to be created. Since each calculation unit needs to support the comparison operations of integers, floating points, dates, and strings, 8 comparators for integers, dates, floating points, and strings are required, which means that a total of 32 comparators are required.

[0037] It is worth noting that in actual products, the types of fields in the database may be far more than the above four categories, and there may be wide tables with many fields (including a large number of column fields), which means that a large number of redundant data type comparators need to be created in each comparison calculation unit, and a large number of comparison calculation units need to be created to meet the needs of hardware accelerated calculation of data tables. This leads to a huge consumption of FPGA on-chip logic resources, thus affecting the number of computing units that can be realized in the end. The number of comparators required is: ; In this embodiment, according to the field type of the table to be queried, 2 integer comparators, 2 date comparators, 3 floating point comparators, and a string comparator are used, totaling 8 comparators to form a comparison operation unit, thereby greatly reducing the required FPGA logic resource amount. During the operation, the query filter conditions are mapped to each comparator by mapping and converting the structured query statement. The results of all comparator operations are merged by using a permutation matrix multiplier to utilize parallel computing to obtain a search code, and the search code is used to determine whether the row meets the condition in the truth table. The specific method will be described in detail later. The number of comparators required in this embodiment is equal to the number of column fields.

[0038] ; It is worth noting that, in actual products, the present invention can plan the number of different types of comparators in the comparison operation unit according to the ratio of field types in all tables in the database.

[0039] In this embodiment, the host side and the FPGA need to cooperate to complete the task, which can be seen in Figure 6 A schematic diagram of the overall architecture is shown.

[0040] Figure 7 FIG. 1 is a flow chart of a method for generating a filtering instruction code applied to a controller provided by an embodiment of the present disclosure, and the method can be executed by a host side. Figure 7 As shown, the method provided in this embodiment includes the following steps: S701: Obtain a structured query statement input by a user, and generate a filtering expression according to the structured query statement input by the user.

[0041] In one example, a structured query statement input by a user is obtained from a preset interface.

[0042] In one example, a filter expression is generated according to a structured query statement input by a user, including: The filter conditions of the preset clauses in the structured query statement input by the user are processed to generate a filter expression.

[0043] In one example, in the database, for the filter condition of the where clause in the structured query statement entered by the user, the filter condition string in the structured query statement will be reconstructed through lexical and grammatical analysis to generate a filter expression. In the filter expression, a binary tree structure is used to represent the comparison operation, and a linked list structure is used to represent the logical operation. The calculation order of each operator in the filter operation is determined by traversing the linked list + binary tree. For example, the following expression: select A, Bfrom table where (A>10 and B<0.5 and C<100) or(E>2024-01-01) can be converted to a filter expression. Figure 8 , Figure 8 A schematic diagram of a filtering expression is shown.

[0044] The CPU performs the corresponding comparison or logic operation by sequentially traversing each operation node on the linked list + binary tree to complete the filtering operation. In the related art, the operation of each node is converted into FPGA instruction code by imitating the CPU's traversal process of the operation node. In the FPGA, a large number of computing unit (CU) hardware circuits are created. In each computing unit, the target fields in the row are compared and logically operated one by one in a pipeline manner to achieve parallel calculation of multiple rows of data, thereby improving the performance of query filtering. For details, please refer to Fig. 9 A schematic diagram of row data parallel processing is shown.

[0045] S702: Generate a first instruction code according to the filtering expression, and generate a second instruction code according to the first instruction code.

[0046] In one example, generating a first instruction code according to a filtering expression includes: The filter expression is traversed, and the operator encoding on the nodes in the filter expression is generated into a first instruction code.

[0047] In one example, the operation information of each node in the filter expression is recorded sequentially. The operation information of each node includes the necessary parameters required for the operation, such as the node operation data type, operator, number of parameters, parameter type (column field number or constant). Optionally, the constant can contain multiple constants to simplify the in comparison operation in the structured query statement. Optionally, for rows where the column fields are all fixed-length, the column number can be directly expressed as the offset of the column field in the row. Get the first instruction code. For a clearer explanation, please refer to Fig.10 A schematic diagram of a generation process of a first instruction code is shown.

[0048] In one example, generating a second instruction code according to a first instruction code includes: Traverse the first instruction code, extract the comparison operation, and generate the second instruction code. For details, please refer to Fig.11 A schematic diagram of a second instruction code generation process is shown.

[0049] S703 , loopingly executing the logic operation in the first instruction code to generate a first truth table, and generating a second truth table according to the first truth table.

[0050] In one example, the logic operation in the first instruction code is executed cyclically, and the input parameters are all possible values ​​of the comparison operation. In this example, there are 4 comparison operations, with a total of 2 to the power of 4 (a total of 16) possibilities. These 16 possibilities are used as inputs, and the corresponding logic operation results are used as a truth table. Specifically, see Table 2 for a schematic diagram of the generation process of a first truth table. In Table 2, 0 represents no, and 1 represents true.

[0051] Table 2 First truth table

[0052] In one example, generating a second truth table according to the first truth table includes: The columns in the first truth table are merged and rearranged according to the order of the FPGA comparison calculation units to obtain a second truth table.

[0053] In one example, the columns in the first truth table are rearranged according to the order of the comparison calculation units preset in the FPGA to obtain the second truth table. Assume that the FPGA creates a corresponding number of comparison calculation units according to the data type in the target table. Since the same type of data units are placed in the same bit width, parallel access can be achieved. Therefore, the same type of calculation units are placed together in the design inside the FPGA. In this example, column B needs to be swapped with column C. For details, please refer to Fig.12 A schematic diagram of a second truth table generation process is shown.

[0054] In this embodiment, by separating the comparison operation from the logic operation, there is no mutual dependence between the calculation operations in the filter expression, so as to support the simultaneous parallel calculation of all comparison operations, so as to give full play to the characteristics of FPGA parallel calculation. For example, in the filter expression in the example, each calculation operation does not need to be executed sequentially. For details, please refer to Fig.13 A schematic diagram of the execution process of a filtering expression is shown.

[0055] S704: Generate a third instruction code according to the second instruction code, and determine a permutation matrix according to the third instruction code.

[0056] In one example, generating a third instruction code according to the second instruction code includes: The comparison operation instructions in the second instruction code are merged and rearranged according to the order of the FPGA comparison calculation units to obtain a third instruction code.

[0057] In one example, the comparison operation instructions in the second instruction code are merged and rearranged according to the order of the FPGA comparison calculation unit to obtain a third instruction code. For this example, the operation instructions in column B need to be exchanged with the operation instructions in column C. For details, see Fig.14 A schematic diagram of the generation process of a third instruction code is shown. Specifically, the instruction code has the following technical features: Fig.14 501 indicates that each instruction in the instruction code corresponds to a comparison node in the filter expression in SQL, including necessary information of the comparison operation such as comparison data type, operator, number of parameters, column number, constant, etc. Fig.14 502 represents the order of comparison instructions in the comparison instruction code. The filter expression in the SQL is rearranged and generated according to the order of the comparators set in the FPGA. The comparison instructions of the same data type are placed together.

[0058] S705 , determining the second instruction code, the second truth table and the permutation matrix as a filtering instruction code applied to the controller, and configuring the filtering instruction code applied to the controller into the controller.

[0059] In one example, the controller may be an FPGA. After the filter instruction code applied to the FPGA is configured into the relevant register of the FPGA, the calculation of the data can be started, and it is only executed once in the entire SQL query process.

[0060] Through this application, by obtaining the structured query statement input by the user, and then processing the structured query statement input by the user, a first instruction code is obtained, and based on the first instruction code, a second instruction code is generated, and then based on the logical operation in the first instruction code, a first truth table is generated, and then a second truth table is generated based on the first truth table. Finally, a third instruction code is generated based on the second instruction code, and a permutation matrix is ​​determined based on the third instruction code; the second instruction code, the second truth table and the permutation matrix are determined as filtering instruction codes applied to FPGA, and the filtering instruction code applied to FPGA is configured in FPGA. The advantage of this setting is that by separating the comparison operation from the logical operation, there is no mutual dependence between the calculation operations in the filter expression, thereby supporting the simultaneous parallel calculation of all comparison operations to give play to the characteristics of FPGA parallel calculation.

[0061] Fig.15The flowchart of a method for generating a filtering instruction code applied to a controller provided by an embodiment of the present disclosure is shown. The embodiment of the present disclosure is optimized on the basis of the above embodiment, and the embodiment of the present disclosure can be combined with various optional solutions in one or more of the above embodiments.

[0062] like Fig.15 As shown, the filtering instruction code generation method applied to the controller may include the following steps: S1501: Obtain a structured query statement input by a user, and generate a filter expression according to the structured query statement input by the user.

[0063] S1502. Generate a first instruction code according to the filter expression, and generate a second instruction code according to the first instruction code.

[0064] S1503, loopingly executing the logic operation in the first instruction code to generate a first truth table, and generating a second truth table according to the first truth table.

[0065] S1504: Generate a third instruction code according to the second instruction code.

[0066] S1505, calculate the valid bit mask in the third instruction code.

[0067] In one example, calculating the valid bit mask in the third instruction code includes: According to the first comparison operation in the third instruction code and the comparison operator created in the FPGA, the second comparison operation used in the structured query sentence input by the user is calculated to obtain a valid bit mask.

[0068] In one example, the comparators created by FPGA are: 2 integers, 3 floating points, 2 dates, and 1 string. However, this SQL query only requires the comparison results of 2 integers, 1 floating point, and 1 date, so a mask is needed to indicate which comparator operation results enter the next operation unit. For details, please refer to Fig.16 A schematic diagram of a valid bit mask generation process is shown.

[0069] In one example, the valid bit mask indicates which positions are valid (i.e., the value is 1), and the purpose of the permutation matrix is ​​to rearrange these valid positions to the front of the matrix for subsequent processing. In this way, the parallel computing characteristics of FPGA can be used to quickly merge the valid calculation results to obtain a shorter search code, which greatly reduces the memory size required for the truth table. For details, please refer to Fig.17 A schematic diagram of a search code generation process is shown.

[0070] S1506. Calculate a permutation matrix according to the valid bit mask.

[0071] In one example, a permutation matrix is ​​calculated based on the valid bit mask, including: Create a matrix M of size N×N; the elements in the matrix M are initialized to 0; the row index row is initialized to 0; Use column traversal index i to traverse the elements mask[i] in the valid bit mask; where i is a value greater than or equal to 0 and less than or equal to N-1; If the element mask[i] in the current valid bit mask is 1, set the row i column in the matrix M to 1, and increase the row index row by 1; If the element mask[i] in the current valid bit mask is not 1, the permutation matrix is ​​determined according to whether the element mask[i] in the current valid bit mask is the last valid bit mask element.

[0072] In one example, determining the permutation matrix according to whether the element mask[i] in the current valid bit mask is the last valid bit mask element includes: If so, we get the permutation matrix; If not, the column traversal index i is increased by 1, and the column traversal index i is used to traverse the elements mask[i] in the valid bit mask until the permutation matrix is ​​obtained.

[0073] In one example, through permutation matrix operations, support for different structured query statements is achieved, while the FPGA on-chip memory space required for the truth table is greatly reduced. The truth table solution supports logical operations of query results of various different data types and has practical value. For example: due to the need to support multi-table queries, each table will have several different types of fields. Relatively redundant comparators need to be designed in the FPGA, and common comparison operation requirements are: 4 integer, 4 floating point, 4 date, and 4 string comparison operations. In this requirement, 16 comparison operation results need to be generated. If a truth table is created for all comparison operation results, 2^16 bits (8192B) of cache space are required to store the truth table. In reality, the structured query statements entered by users often have very few comparison conditions, usually no more than 8, and 16 filter comparison conditions are not entered at a time. It's just that the data type required each time will change. The permutation matrix in this embodiment is to solve this problem. For a clearer explanation, please refer to Fig.18 A schematic diagram of the structure of a permutation matrix is ​​shown.

[0074] The structured query statement in the example uses only 6 comparison operations, and a 16x16 permutation matrix (occupying 32B of memory space) is used to put the comparison results of the valid bits together to form a search code. The corresponding truth table size only requires 2^6 bits (8B) of memory space.

[0075] It is worth noting that in actual products, more comparators are often needed, such as 8 integers, 8 floating points, 8 dates, and 8 strings, which means that 2^32 bits (512MB) of truth table storage space is required, while the on-chip cache of FPGA is extremely valuable, usually only 16MB-32MB. This makes the traditional truth table solution for processing logical operations impractical.

[0076] S1507, determining the second instruction code, the second truth table and the permutation matrix as a filtering instruction code applied to the controller, and configuring the filtering instruction code applied to the controller into the controller.

[0077] In one example, the method further includes: Receive the calculation results of the controller and find the rows that meet the filter conditions from the calculation results; Get the index number of the row in the page, and get the row data in the page row meta information according to the index number.

[0078] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0079] The embodiment of the present application also provides a filtering instruction code generating device applied to a controller. Fig.19 A schematic diagram of a filter instruction code generating device for a controller provided in an embodiment of the present disclosure. The device 1900 is executed by a host side and includes: The first acquisition module 1901 is used to acquire a structured query statement input by a user and generate a filtering expression according to the structured query statement input by the user; A first generating module 1902, used to generate a first instruction code according to a filtering expression, and to generate a second instruction code according to the first instruction code; The second generating module 1903 is used to cyclically execute the logic operation in the first instruction code to generate a first truth table, and generate a second truth table according to the first truth table; A third generating module 1904 is used to generate a third instruction code according to the second instruction code, and determine a permutation matrix according to the third instruction code; The determination module 1905 is used to determine the second instruction code, the second truth table and the permutation matrix as a filtering instruction code applied to the controller, and configure the filtering instruction code applied to the controller into the controller.

[0080] In an example, the first acquisition module 1901 is specifically configured to process a filter condition of a preset clause in a structured query statement input by a user to generate a filter expression.

[0081] In one example, the first generating module 1902 is used to: The filter expression is traversed, and the operator encoding on the nodes in the filter expression is generated into a first instruction code.

[0082] In one example, the first generating module 1902 is used to: traverse the first instruction code, extract the comparison operation, and generate the second instruction code.

[0083] In one example, the third generating module 1904 is used to merge and rearrange the comparison operation instructions in the second instruction code according to the order of the comparison calculation units of the controller to obtain the third instruction code.

[0084] In one example, the second generating module 1903 is used to: The columns in the first truth table are merged and rearranged according to the order of the comparison calculation units of the controller to obtain a second truth table.

[0085] In one example, the third generating module 1904 is used to: Calculate the valid bit mask in the third instruction code; According to the effective bit mask, the permutation matrix is ​​calculated.

[0086] In one example, the third generating module 1904 is used to: According to the first comparison operation in the third instruction code and the comparison operator created in the controller, the second comparison operation used in the structured query statement input by the user is calculated to obtain a valid bit mask.

[0087] In one example, the third generating module 1904 is used to: create a matrix M of size N×N; wherein the elements in the matrix M are initialized to 0; and the row index row is initialized to 0; Use column traversal index i to traverse the elements mask[i] in the valid bit mask; where i is a value greater than or equal to 0 and less than or equal to N-1; If the element mask[i] in the current valid bit mask is 1, set the row i column in the matrix M to 1, and increase the row index row by 1; If the element mask[i] in the current valid bit mask is not 1, the permutation matrix is ​​determined according to whether the element mask[i] in the current valid bit mask is the last valid bit mask element.

[0088] In one example, the third generation module 1904 is used to: if yes, obtain a permutation matrix; If not, the column traversal index i is increased by 1, and the column traversal index i is used to traverse the elements mask[i] in the valid bit mask until the permutation matrix is ​​obtained.

[0089] In one example, the apparatus further comprises: A receiving module 1906 is used to receive the calculation results of the controller and find the rows that meet the filtering conditions from the calculation results; The second acquisition module 1907 is used to acquire the index number of the row in the page, and acquire the row data in the page row meta information according to the index number.

[0090] The description of the features in the embodiment corresponding to a filtering instruction code generating device applied to a controller can refer to the relevant description of the embodiment corresponding to a filtering instruction code generating method applied to a controller, which will not be repeated here.

[0091] An embodiment of the present application further provides a host, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the filtering instruction code generation method applied to the controller.

[0092] For example, Fig. 20 This is a schematic diagram of the structure of a host in an embodiment of the present disclosure. Fig. 20 , which shows a schematic diagram of a structure of a host 1000 suitable for implementing the embodiment of the present disclosure. The host 1000 in the embodiment of the present disclosure may include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig. 20 The host shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0093] like Fig. 20 As shown, the host 1000 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 to a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the host 1000 are also stored. The processing device 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0094] Typically, the following devices may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the host 1000 to communicate with other devices wirelessly or by wire to exchange data. Although Fig. 20 The host 1000 is shown with various devices, but it should be understood that it is not required to implement or have all the devices shown. More or fewer devices may be implemented or have instead.

[0095] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 1009, or installed from a storage device 1008, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0096] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above-mentioned XX method embodiments when running.

[0097] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0098] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned embodiments of the method for generating a filtering instruction code applied to a controller are implemented.

[0099] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps in any of the above-mentioned embodiments of the filtering instruction code generation method applied to the controller.

[0100] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0101] The above is a detailed introduction to a method for generating a filtering instruction code for a controller provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for generating a filtering instruction code applied to a controller, characterized in that: Executed by the host side, the method includes: Obtaining a structured query statement input by a user, and generating a filtering expression according to the structured query statement input by the user; Generate a first instruction code according to the filtering expression, and generate a second instruction code according to the first instruction code; cyclically executing the logic operation in the first instruction code to generate a first truth table, and generating a second truth table according to the first truth table; generating a third instruction code according to the second instruction code, and determining a permutation matrix according to the third instruction code; The second instruction code, the second truth table and the permutation matrix are determined as a filtering instruction code applied to a controller, and the filtering instruction code applied to the controller is configured in the controller.

2. The method according to claim 1, characterized in that Generating a filtering expression according to the structured query statement input by the user includes: The filter condition of the preset clause in the structured query statement input by the user is processed to generate the filter expression.

3. The method according to claim 1, characterized in that: The step of generating a first instruction code according to the filtering expression comprises: The filter expression is traversed, and the operator encoding on the nodes in the filter expression is encoded to generate the first instruction code.

4. The method according to claim 1, characterized in that: The step of generating a second instruction code according to the first instruction code comprises: The first instruction code is traversed, comparison operations are extracted, and the second instruction code is generated.

5. The method according to claim 4, characterized in that Generating a third instruction code according to the second instruction code includes: The comparison operation instructions in the second instruction code are merged and rearranged according to the order of the comparison calculation units of the controller to obtain the third instruction code.

6. The method according to claim 1, characterized in that The generating a second truth table according to the first truth table comprises: The columns in the first truth table are merged and rearranged according to the order of the comparison calculation units of the controller to obtain the second truth table.

7. The method according to claim 1, characterized in that Determining a permutation matrix according to the third instruction code includes: Calculating a valid bit mask in the third instruction code; The permutation matrix is ​​calculated based on the valid bit mask.

8. The method according to claim 7, characterized in that The calculating the valid bit mask in the third instruction code comprises: According to the first comparison operation in the third instruction code and the comparison operator created in the controller, the second comparison operation used in the structured query statement input by the user is calculated to obtain the valid bit mask.

9. The method according to claim 7, characterized in that: The step of calculating the permutation matrix according to the valid bit mask comprises: Create a matrix M of size N×N; wherein the elements in the matrix M are initialized to 0; and the row index row is initialized to 0; Using column traversal index i, traverse the element mask[i] in the valid bit mask; where i is a value greater than or equal to 0 and less than or equal to N-1; If the element mask[i] in the current valid bit mask is 1, set the row i column in the matrix M to 1, and increase the row index row by 1; If the element mask[i] in the current valid bit mask is not 1, the permutation matrix is ​​determined according to whether the element mask[i] in the current valid bit mask is the last valid bit mask element.

10. The method according to claim 9, characterized in that The determining the permutation matrix according to whether the element mask[i] in the current valid bit mask is the last valid bit mask element comprises: If so, the permutation matrix is ​​obtained; If not, the column traversal index i is increased by 1, and the column traversal index i is used to traverse the elements mask[i] in the valid bit mask until the permutation matrix is ​​obtained.

11. The method according to claim 1, characterized in that: The method further comprises: receiving the calculation result of the controller, and finding the row satisfying the filtering condition from the calculation result; The index number of the row in the page is obtained, and the row data is obtained from the page row meta information according to the index number.

12. A filtering instruction code generating device applied to a controller, characterized in that: Executed by the host side, the device includes: A first acquisition module is used to acquire a structured query statement input by a user, and generate a filtering expression according to the structured query statement input by the user; A first generating module, used to generate a first instruction code according to the filtering expression, and to generate a second instruction code according to the first instruction code; A second generating module, used for cyclically executing the logic operation in the first instruction code to generate a first truth table, and generating a second truth table according to the first truth table; A third generating module, used to generate a third instruction code according to the second instruction code, and determine a permutation matrix according to the third instruction code; A determination module is used to determine the second instruction code, the second truth table and the permutation matrix as a filtering instruction code applied to a controller, and configure the filtering instruction code applied to the controller into the controller.

13. A host, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the filtering instruction code generation method applied to a controller as claimed in any one of claims 1 to 11 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method for generating a filtering instruction code applied to a controller as claimed in any one of claims 1 to 11.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for generating filtering instruction codes applied to a controller as claimed in any one of claims 1 to 11 are implemented.

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