Pixel driving circuit and display panel

Abstract

The present invention provides a pixel driving circuit and a display panel. The pixel driving circuit includes: a driving unit for driving a light-emitting element to emit light; a first switching unit for receiving a data signal; a second switching unit for controlling threshold voltage compensation; a first storage unit connected between a fourth node and a second node; a timing control circuit for respectively controlling the conduction and cutoff of the first switching unit and the second switching unit to separate the data signal writing time from the compensation time, and controlling the Vth compensation time to be greater than one line scanning time; and in the light-emitting stage, pulse-resetting the source potential of the driving unit by outputting a pulse signal. The pixel driving circuit provided by the present invention effectively solves the technical problem of difficult compatibility between high and low refresh rates in the prior art, achieves the goals of high-quality display at high refresh rates and low-power and flicker-free display at low refresh rates, and significantly improves the performance and user experience of the display device.

Description

Technical Field

[0001] The present invention relates to the field of display panel circuits, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] With the rapid development of display technology, people have higher and higher requirements for display devices, especially in the fields of mobile devices, virtual reality (VR) / augmented reality (AR) devices and high-definition televisions, which pose higher challenges to the performance of display screens. Among them, refresh rate is one of the important indicators to measure the performance of display screens.

[0003] High refresh rates can provide smoother display effects, reduce motion blur, and improve user experience, especially in scenes such as games and fast-motion video playback. In addition, high refresh rates can also help reduce eye fatigue and protect eyesight. However, traditional pixel drive circuits face some technical difficulties at high refresh rates. As the scanning time of each row of pixels is shortened, the time used for threshold voltage (Vth) compensation is also reduced accordingly, resulting in insufficient Vth compensation, which causes problems such as uneven display and brightness deviation, seriously affecting display quality. On the other hand, although low refresh rates can significantly reduce display power consumption and extend the battery life of the device, at low refresh rates, the threshold voltage drift and hysteresis effect of the driver transistor (Driver TFT) become more obvious, resulting in unstable OLED light emission, and the human eye can perceive obvious screen flicker, reducing viewing comfort.

[0004] Currently, most display devices on the market use a fixed refresh rate or a few fixed refresh rates, such as 60Hz, 90Hz, 120Hz, etc. This single or several refresh rate mode cannot meet the needs of users in different application scenarios. For example, when browsing static web pages or reading e-books, a high refresh rate is unnecessary and will increase power consumption; while when playing games or watching high-speed motion videos, a low refresh rate will cause the picture to freeze and blur.

[0005] Therefore, how to design a pixel driving circuit that is compatible with high and low refresh rates so that it can provide high-quality image display at a high refresh rate and effectively reduce power consumption and reduce screen flicker at a low refresh rate has become a technical problem that needs to be urgently solved in the current display technology field.

[0006] It should be noted that the information claimed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In view of this, the present invention provides a pixel driving circuit and a display panel, enabling sufficient Vth compensation at high refresh rates, improving display uniformity and picture quality; and effectively suppressing the hysteresis effect of driving transistors at low refresh rates, reducing screen flicker and enhancing the viewing experience.

[0008] An aspect of an embodiment of the present invention provides a pixel driving circuit, including:

[0009] A driving unit for driving a light-emitting element to emit light;

[0010] A first switching unit for receiving a data signal from a data input terminal and transmitting it to a fourth node;

[0011] A second switching unit for controlling threshold voltage compensation and transmitting the compensated voltage to a second node;

[0012] A first storage unit connected between the fourth node and the second node;

[0013] A timing control circuit is configured to output control signals to a first control signal terminal, a second control signal terminal, a third control signal terminal, and a fourth control signal terminal respectively, to control the conduction and cutoff of the first switching unit and the second switching unit, thereby separating the data signal writing time from the threshold voltage compensation time, and controlling the conduction time of the second switching unit such that the threshold voltage compensation time is greater than one line scanning time; and during the light-emitting stage, by outputting a pulse signal to the third control signal terminal, to perform a pulsed reset on the driving unit.

[0014] In some optional embodiments, the first switching unit includes a first transistor, the gate of the first transistor is connected to the first control signal terminal, the first pole of the first transistor is connected to the data input terminal, and the second pole of the first transistor is connected to the fourth node.

[0015] In some optional embodiments, the second switching unit includes a third transistor, the gate of the third transistor is connected to the second control signal terminal, the first pole of the third transistor is connected to a third node, and the second pole of the third transistor is connected to the second node.

[0016] In some optional embodiments, it further includes a third switching unit, the third switching unit includes a sixth transistor, the sixth transistor is a double-gate thin-film transistor, its gate is connected to the fourth control signal terminal, the first pole of the sixth transistor is connected to a first reference voltage input terminal, and the second pole of the sixth transistor is connected to the second node.

[0017] In some optional embodiments, it further includes a third storage unit, the third storage unit is connected between the midpoint of the double-gate thin-film transistor of the sixth transistor and the gate of the sixth transistor, for stabilizing the potential of the second node.

[0018] In some alternative embodiments, it further includes:

[0019] A fourth switching unit connected between the second reference voltage input terminal and the fifth node;

[0020] A fifth switching unit connected between the driving unit and the third reference voltage input terminal; the timing control circuit controls the conduction and cutoff of the fourth switching unit and the fifth switching unit respectively through the third control signal terminal to perform a pulsed reset on the driving unit.

[0021] In some alternative embodiments, the fourth switching unit includes a seventh transistor, the gate of the seventh transistor is connected to the third control signal terminal, the first pole of the seventh transistor is connected to the second reference voltage input terminal, and the second pole of the seventh transistor is connected to the fifth node; the fifth switching unit includes an eighth transistor, the gate of the eighth transistor is connected to the third control signal terminal, the first pole of the eighth transistor is connected to the third reference voltage input terminal, and the second pole of the eighth transistor is connected to the first node.

[0022] In some alternative embodiments, at least the transistors in the first switching unit and the transistors in the second switching unit are double-gate thin-film transistors.

[0023] In some alternative embodiments, the light-emitting element is an organic light-emitting diode.

[0024] Another aspect of the embodiments of the present invention provides a display panel including the pixel driving circuit described above.

[0025] In the pixel driving circuit and the display panel of the present invention, by controlling the conduction and cutoff of the first switching unit and the second switching unit respectively through the timing control circuit, the data signal writing time and the threshold voltage compensation time are completely separated, so that the threshold voltage compensation process is no longer limited by the scanning time of each row of pixels. Therefore, sufficient threshold voltage compensation can be performed even at a high refresh rate, effectively improving the uniformity of the display screen and eliminating problems such as brightness deviation and afterimage. By precisely controlling the conduction time of the second switching unit, the present invention ensures that the threshold voltage compensation time can be greater than one row scanning time, which further enhances the effect of threshold voltage compensation and ensures the accuracy of threshold voltage compensation even at a high refresh rate, thus significantly improving the display quality at a high refresh rate. In the light-emitting stage of the present invention, a pulse signal is output to the third control signal terminal through the timing control circuit to control the conduction and cutoff of at least two switching units connected to the driving unit, realizing a pulsed reset of the potential of the driving unit. This multiple reset effectively suppresses the hysteresis effect of the driving transistor, reduces the instability of OLED light emission, thus significantly reducing the screen flicker at a low refresh rate and improving the viewing comfort.

[0026] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0028] Figure 1 is a schematic circuit connection diagram of a pixel driving circuit according to an embodiment of the present invention;

[0029] Figure 2 is a waveform diagram during the operation of an internal compensation pixel driving circuit according to an embodiment of the present invention.

[0030] Wherein, T1 - the first transistor, T2 - the second transistor, T3 - the third transistor, T4 - the fourth transistor, T5 - the fifth transistor, T6 - the sixth transistor, T7 - the seventh transistor, T8 - the eighth transistor, T9 - the ninth transistor, T10 - the tenth transistor, N1 - the first node, N2 - the second node, N3 - the third node, N4 - the fourth node, N5 - the fifth node, C1 - the first capacitor, C2 - the second capacitor, C3 - the third capacitor, SN_T1 - the first control signal terminal, SN_T3 - the second control signal terminal, SN+1 - the third control signal terminal, SN-1 - the fourth control signal terminal, Data - the data input terminal, ELVDD - the first power supply terminal, ELVSS - the second power supply terminal, Vint1 - the first reference voltage input terminal, Vint2 - the second reference voltage input terminal, Vint3 - the third reference voltage input terminal, Vint4 - the fourth reference voltage input terminal, EM - the enable signal input terminal. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] To make the technical problems solved by the present invention, the technical solutions adopted, and the achieved technical effects clearer, the technical solutions of the embodiments of the present invention will be further described in detail below with reference to the drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0032] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application may be practiced without one or more of the specific details, or other methods, modules, devices, steps, etc. may be employed. In other cases, well-known modules, methods, devices, implementations, steps, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0033] In an OLED display, the pixel brightness is determined by the current flowing through the organic light-emitting diode (OLED) controlled by a driving transistor (Driver TFT). Due to the inherent process variations of TFT devices, there are differences in the threshold voltages (Vth) of the driving transistors of different pixels, resulting in different currents flowing through the OLEDs even when the same gate voltage is applied, thus causing display brightness non-uniformity. The threshold voltage compensation technology aims to eliminate or mitigate the impact of such Vth differences on the display effect. Its basic principle is to detect or compensate the Vth of the driving transistor through a specific circuit structure and driving timing to ensure the consistency of the brightness of each pixel. In addition, the data writing process is a process of converting a digital signal representing pixel brightness into an analog voltage signal and writing it into a pixel capacitor. The rate and accuracy of this process directly affect the refresh rate and display quality of the display screen. On the other hand, the hysteresis effect of the driving transistor, that is, the phenomenon that the output current cannot reach the steady-state value instantaneously after the gate voltage changes, is particularly significant at low refresh rates and will cause unstable light emission of the OLED, resulting in perceptible flicker by the human eye. The pulse driving technology can reduce the flicker at low refresh rates while reducing the average power consumption by applying a high-voltage pulse to drive the OLED to emit light within a short time and utilizing the persistence of vision of the human eye. The present invention addresses the problems of insufficient compensation time in the traditional row-by-row Vth compensation method at high refresh rates and the flicker caused by the hysteresis effect of the driving transistor at low refresh rates. By precisely controlling the on and off of the switching unit through a timing control circuit, the separation of the data writing and Vth compensation processes is achieved, and the Vth compensation time is made greater than the one-line scanning time, thereby ensuring the sufficiency of Vth compensation at high refresh rates. At the same time, by applying multiple pulse signals to the source electrode of the driving unit during the light-emitting stage, the hysteresis effect of the driving transistor is effectively suppressed, and the screen flicker at low refresh rates is reduced, thereby achieving good compatibility between high and low refresh rates.

[0034] As Figure 1 shown, one aspect of an embodiment of the present invention provides a pixel driving circuit, including:

[0035] A driving unit for driving a light-emitting element to emit light. Usually, a thin-film transistor (TFT) is used as a driving transistor to control the current flowing through the OLED, thereby controlling the light-emitting brightness of the OLED. In an embodiment of the present invention, the driving unit is preferably a thin-film transistor, more preferably a P-type thin-film transistor TFT. For example, Figure 1 the second transistor T2 in

[0036] is a PMOS TFT. The gate of the second transistor T2 receives a voltage signal from the second node N2. The first pole of the second transistor T2 is connected to the first node N1, and the second pole of the second transistor T2 is connected to the third node N3. The current between the source and drain of the second transistor T2 is controlled by the magnitude of the gate voltage, thereby driving the OLED to emit light. In other embodiments, the second transistor T2 may also adopt other circuit structures or devices with similar driving functions.

[0037] A first switching unit for receiving a data signal from a data input terminal Data and transmitting it to a fourth node N4. In an embodiment of the present invention, the first switching unit is preferably a thin-film transistor, more preferably a P-type thin-film transistor, such as a PMOS TFT. The control terminal of the first switching unit is connected to a first control signal terminal SN_T1, the input terminal is connected to the data input terminal Data, and the output terminal is connected to the fourth node N4. When the first control signal terminal SN_T1 is at an effective level, such as a low level, the first switching unit is turned on, and the data signal is transmitted to the fourth node N4; when the first control signal terminal SN_T1 is at an ineffective level, such as a high level, the first switching unit is turned off, preventing the data signal from being transmitted. In other embodiments, the first switching unit may also adopt other circuit structures or devices with a switching function, such as a transmission gate.

[0038] The first storage unit is connected between the fourth node N4 and the second node N2. The function of the first storage unit is to keep the voltage of the second node stable during the data writing stage and the light emitting stage, so as to ensure the normal operation of the driving transistor. In the embodiment of the present invention, the first storage unit is preferably a capacitor. In some embodiments, the first storage unit includes a first capacitor C1, and the first capacitor C1 is connected between the fourth node N4 and the second node N2, and is used to store the charge written to the fourth node N4 during the data writing stage, and affect the potential of the second node N2 through the capacitive coupling effect, so as to control the gate voltage of the second transistor T2. Specifically, when the data signal is written to the fourth node N4 through the first switching unit, the potential of the fourth node N4 changes. Since the voltage across the two ends of the first capacitor C1 cannot change suddenly, the potential of the second node N2 will also change accordingly, and the magnitude of the change depends on the capacitance value of the first capacitor C1 and the capacitance values of other relevant capacitors. This capacitive coupling effect enables the data signal to be effectively transmitted to the gate of the second transistor T2, thereby controlling the light emitting brightness of the OLED. In addition, during the light emitting stage, the first capacitor C1 also plays a role in maintaining the potential stability of the second node N2, preventing the gate voltage of the second transistor T2 from fluctuating due to factors such as leakage, thereby affecting the light emitting stability of the OLED.

[0039] In some optional embodiments, the pixel driving circuit further includes a second capacitor C2. The second capacitor C2 is connected between the first power supply terminal ELVDD and the fourth node N4, and is used to stabilize the potential of the fourth node N4 during the Vth compensation stage, and assist the first capacitor C1 in maintaining the potential stability of the fourth node N4 during the data writing stage. Specifically, during the Vth compensation stage, by controlling the relevant switching unit, the potential of the fourth node N4 can be pre-charged to a specific voltage value. The second capacitor C2 can store the charge corresponding to this voltage, and play a role in maintaining the potential stability of the fourth node N4 during the subsequent data writing stage and light emitting stage, reducing the influence of factors such as interference or leakage of other circuit elements on the potential of the fourth node N4, thereby improving the accuracy of data writing and Vth compensation.

[0040] The timing control circuit is used to output control signals to the first control signal terminal SN_T1, the second control signal terminal SN_T3, the third control signal terminal SN+1, and the fourth control signal terminal SN-1 respectively, so as to control the conduction and cutoff of the first switching unit and the second switching unit, thereby separating the data signal writing time from the threshold voltage compensation time, and controlling the conduction time of the second switching unit to make the compensation time of the threshold voltage Vth greater than one line scanning time; and in the light emitting stage, by outputting a pulse signal to the third control signal terminal SN+1, to perform a pulsed reset on the potential of the driving unit. Specifically, the timing control circuit generates specific timing signals, so that in different time periods, the first switching unit and the second switching unit are respectively turned on or off, thereby realizing the time-sharing of data writing and Vth compensation. And, the timing control circuit controls the conduction time of the second switching unit, so that the Vth compensation time can exceed one line scanning time to ensure that Vth is fully compensated. In addition, in the light emitting stage, the timing control circuit outputs a pulse signal through the third control signal terminal SN+1 to control the conduction and cutoff of at least two switching units connected to the first pole of the second transistor T2, and realizes the pulsed reset of the potential of the first pole of the second transistor T2 to reduce the hysteresis effect of the driving transistor. The specific implementation manner of the timing control circuit can adopt various known timing control circuit structures, such as shift registers, logic gate circuits, etc.

[0041] In some embodiments, the first switching unit includes a first transistor T1. The gate of the first transistor T1 is connected to the first control signal terminal SN_T1. The first pole of the first transistor T1 is connected to the data input terminal Data. The second pole of the first transistor T1 is connected to the fourth node N4. Specifically, in this embodiment, the first switching unit uses a thin-film transistor to implement the transmission control of the data signal. The signal of the first control signal terminal SN_T1 is used to control the conduction and cutoff of the first transistor T1. When the first control signal terminal SN_T1 is at an effective level, such as a low level, the first transistor T1 conducts. When the first control signal terminal SN_T1 is at an ineffective level, such as a high level, the first transistor T1 cuts off. By controlling the level change of the first control signal terminal SN_T1, the writing timing of the data signal can be accurately controlled. The data input terminal Data is used to provide the data signal to be written into the pixel. This data signal is usually an analog voltage signal, representing the brightness information of the pixel. The first pole of the first transistor T1, such as the source, is connected to the data input terminal Data, so as to transmit the data signal when the first transistor T1 conducts. The second pole of the first transistor T1, such as the drain, is connected to the fourth node N4. When the first transistor T1 conducts, the data signal is transmitted from the data input terminal Data through the first transistor T1 to the fourth node N4, thus completing the data writing process. In other embodiments, the first switching unit further includes a ninth transistor T9. The gate of the ninth transistor T9 is connected to the second control signal terminal SN_T3. The first pole of the ninth transistor T9 is connected to the fourth reference voltage input terminal Vint4. The second pole of the ninth transistor T9 is connected to the fourth node N4. The ninth transistor T9 is used to reset the fourth node N4 during the threshold voltage (Vth) compensation stage in this embodiment. Specifically, during the Vth compensation stage, the second control signal terminal SN_T3 outputs an effective level, such as a low level, so that the ninth transistor T9 conducts, pulling the potential of the fourth node N4 to the potential of the fourth reference voltage input terminal Vint4. In this way, the potential of the fourth node N4 can be initialized to a known state before performing Vth compensation, thus ensuring the accuracy of Vth compensation. In other stages, such as the data writing stage and the light emitting stage, the second control signal terminal SN_T3 outputs an ineffective level, such as a high level, so that the ninth transistor T9 cuts off, avoiding its influence on the data writing and light emitting processes. The ninth transistor T9 is preferably a thin-film transistor TFT, and more preferably a P-type metal oxide semiconductor thin-film transistor PMOS TFT.

[0042] By adopting the above-described embodiment, the conduction and cutoff of the first transistor T1 are controlled by using the first control signal terminal SN_T1, which can accurately control the writing timing of the data signal. In cooperation with the timing control circuit, the separation of the data signal writing time and the threshold voltage compensation time is achieved, laying a foundation for subsequent Vth compensation and driving the OLED to emit light. It should be noted that in this embodiment, as Figure 1 shown, using the PMOS TFT as the first switching unit is only a preferred embodiment and does not limit the present invention. Any circuit structure or device capable of realizing the control of data signal transmission and capable of cooperating with the timing control circuit to achieve the separation of the data signal writing time and the threshold voltage compensation time should fall within the protection scope of the present invention.

[0043] In some embodiments, the second switching unit includes a third transistor T3. The gate of the third transistor T3 is connected to the second control signal terminal SN_T3. The first pole of the third transistor T3 is connected to the third node N3. The second pole of the third transistor T3 is connected to the second node N2. In the embodiments of the present invention, the signal of the second control signal terminal SN_T3 is used to control the conduction and cutoff of the third transistor T3. When the second control signal terminal SN_T3 is at an effective level, such as a low level, the third transistor T3 is turned on. When the second control signal terminal SN_T3 is at an ineffective level, such as a high level, the third transistor T3 is turned off. By controlling the level change of the second control signal terminal SN_T3, the start and end times of Vth compensation can be accurately controlled. In combination with the timing control circuit, it is possible to achieve that the Vth compensation time is longer than one line scan time. The third node N3 is connected to the second pole of the second transistor T2. The second node N2 is connected to the gate of the second transistor T2. When the third transistor T3 is turned on, the voltage after Vth compensation is transmitted from the third node N3 to the second node N2 through the third transistor T3, thereby adjusting the gate voltage of the second transistor T2 to compensate for its threshold voltage drift. In other embodiments, the second switching unit further includes a tenth transistor T10. The tenth transistor T10 is connected between the first power supply terminal ELVDD and the first node N1 and is controlled by the signal of the second control signal terminal SN_T3. The tenth transistor T10 is used in this embodiment to provide a compensation voltage, such as the potential of the first power supply terminal ELVDD, to the first node N1 during the threshold voltage (Vth) compensation stage. Specifically, during the Vth compensation stage, the second control signal terminal SN_T3 outputs an effective level, such as a low level, so that the third transistor T3 and the tenth transistor T10 are turned on simultaneously. The conduction of the tenth transistor T10 applies the voltage of the first power supply terminal ELVDD to the first node N1. In combination with the circuit connection relationship and timing control, this helps to establish an appropriate voltage difference between the gate and source of the second transistor T2, that is, between the second node N2 and the third node N3, during the Vth compensation stage, thereby achieving Vth compensation. By controlling the duration of the effective level of the second control signal terminal SN_T3, the time length of Vth compensation can be controlled, so as to achieve that the Vth compensation time is longer than one line scan time. In other stages, such as the data writing stage and the light emitting stage, the second control signal terminal SN_T3 outputs an ineffective level, such as a high level, so that the tenth transistor T10 is turned off to avoid its influence on the data writing and light emitting processes. The tenth transistor T10 is preferably a thin film transistor TFT, and more preferably a P-type metal oxide semiconductor thin film transistor PMOS TFT.

[0044] By adopting the above embodiments, the conduction and cutoff of the third transistor T3 are controlled by using the second control signal terminal SN_T3. Combining with other related circuits and timing control, Vth compensation can be effectively achieved, and the time of Vth compensation can be accurately controlled to be greater than one line scanning time, so as to ensure the sufficiency of Vth compensation even at a high refresh rate, and significantly improve the uniformity of the display screen. It should be noted that using PMOS TFT as the second switch unit in this embodiment is only a preferred embodiment, not a limitation to the present invention. Any circuit structure or device that can achieve Vth compensation control and voltage transmission, and can cooperate with the timing control circuit to make the Vth compensation time greater than one line scanning time, should fall within the protection scope of the present invention.

[0045] In some embodiments, the pixel driving circuit further includes a third switch unit. The third switch unit includes a sixth transistor T6. The sixth transistor T6 is a double-gate thin-film transistor, whose gate is connected to the fourth control signal terminal SN-1. The first pole of the sixth transistor T6 is connected to the first reference voltage input terminal Vint1, and the second pole of the sixth transistor T6 is connected to the second node N2. The sixth transistor T6 adopts a double-gate thin-film transistor (Double-Gate TFT) structure. Compared with the traditional single-gate TFT, the double-gate TFT has better switching characteristics, lower leakage current and higher stability. In the embodiments of the present invention, using the double-gate TFT as the sixth transistor T6 can more effectively control its conduction and cutoff, and reduce its influence on other circuit elements. Especially in the Vth compensation and reset stages, it can better stabilize the potential of the second node N2 and improve the accuracy of compensation and reset. The signal of the fourth control signal terminal SN-1 is used to control the conduction and cutoff of the sixth transistor T6. When the fourth control signal terminal SN-1 is at an effective level such as a low level, the sixth transistor T6 conducts; when the fourth control signal terminal SN-1 is at an invalid level such as a high level, the sixth transistor T6 cuts off. By controlling the level change of the fourth control signal terminal SN-1, the working state of the sixth transistor T6 can be controlled. Combining with the timing control circuit, the sixth transistor T6 can be conducted within a specific time period to stabilize the potential of the second node N2. The first reference voltage input terminal Vint1 provides a stable reference voltage to assist in stabilizing the potential of the second node N2. When the sixth transistor T6 conducts, the voltage of the first reference voltage input terminal Vint1 will affect the potential of the second node N2, reducing the influence of noise and interference on the potential of the second node N2. In other embodiments, the third switch unit can also be implemented by using other circuit structures or devices with similar functions.

[0046] By adopting the above-described embodiments, by using the dual-gate TFT as the sixth transistor T6 and controlling it with the fourth control signal terminal SN-1, the potential of the second node N2 can be more effectively stabilized, reducing the influence of noise and interference on the potential of the second node N2, thereby improving the accuracy of Vth compensation and reset, and ultimately contributing to improving the quality of the display screen. The use of the dual-gate TFT also enhances the stability of the circuit and improves the reliability of the device. It should be noted that using the dual-gate PMOS TFT as the sixth transistor T6 of the third switching unit in this embodiment is only a preferred embodiment and not a limitation of the present invention. Any circuit structure or device that can achieve the stable potential of the second node N2 and can cooperate with the timing control circuit to achieve related functions should fall within the protection scope of the present invention.

[0047] In some embodiments, the pixel driving circuit further includes a third storage unit. The third storage unit is connected between the midpoint of the dual-gate thin film transistor of the sixth transistor T6 and the gate of the sixth transistor T6, and is used to stabilize the potential of the second node N2. In the embodiments of the present invention, in order to further improve the stability of the potential of the second node N2, the third storage unit further includes a third capacitor C3. The dual-gate TFT has two gates, and these two gates can be used in parallel or controlled separately. Due to its special structure, there is a certain parasitic capacitance at the midpoint between the two gates of the dual-gate TFT. After connecting an additional capacitor, namely the third capacitor C3, it is equivalent to increasing this parasitic capacitance, forming a capacitive voltage division network. This capacitive voltage division network can effectively filter out high-frequency noise and interference, and reduce the potential fluctuation of the second node N2 caused by factors such as the switching action or leakage of other circuit components. When the two gates are used in parallel, as Figure 1 shown, there is a midpoint between the two gates, and this midpoint usually has a certain capacitive effect. The third capacitor C3 is not directly connected between the N2 node and the gate of the sixth transistor T6, but is connected between the midpoint of the dual-gate of the sixth transistor T6 and the gate of the sixth transistor T6. This connection method utilizes the inherent capacitive characteristics of the dual-gate TFT and combines with the additional third capacitor C3 to form a more effective capacitive network, thereby more effectively stabilizing the potential of the second node N2. The function of the third capacitor C3 is to stabilize the potential of the second node N2 in different working stages, such as the Vth compensation stage, the data writing stage, and the light emitting stage, and reduce the influence of noise and interference on the potential of the second node N2. Since the second node N2 is directly connected to the gate of the second transistor T2, the stability of the potential of the second node N2 directly affects the working state of the second transistor T2, and further affects the light emitting brightness of the OLED.

[0048] By adopting the above-described embodiments, by using the third capacitor C3 connected between the midpoint of the double-gate TFT and the gate, the potential of the second node N2 can be more effectively stabilized, noise and interference can be reduced, the accuracy of Vth compensation can be improved, and ultimately the quality of the display screen can be improved. Especially when the driving transistor works for a long time or works at a high ambient temperature, the stabilizing effect of the third storage unit is more obvious, and problems such as screen flicker or uneven brightness of the display screen can be effectively prevented. It should be noted that using the capacitor connected between the midpoint of the double-gate TFT and the gate, i.e., the third capacitor C3, to stabilize the potential of the second node N2 in this embodiment is only a preferred embodiment and not a limitation of the present invention. Any circuit structure or device that can effectively stabilize the potential of the second node N2 should fall within the protection scope of the present invention.

[0049] In some embodiments, in order to reduce the hysteresis effect of the driving unit at a low refresh rate, thereby reducing screen flicker, the pixel driving circuit further includes:

[0050] A fourth switching unit, connected between the second reference voltage input terminal Vint2 and the fifth node N5. In the embodiment of the present invention, the fourth switching unit is used to pull the potential of the fifth node N5, i.e., the first pole of the OLED, to the potential of the second reference voltage input terminal Vint2 during the reset stage.

[0051] A fifth switching unit, connected between the driving unit and the third reference voltage input terminal Vint3. The timing control circuit controls the conduction and cutoff of the fourth switching unit and the fifth switching unit through the third control signal terminal SN+1 to perform a pulsed reset on the driving unit. Due to the hysteresis effect of the second transistor T2, its output current will exhibit different characteristics due to different historical states when the same gate voltage is applied. In the embodiment of the present invention, the fifth switching unit is used to pull the potential of the first pole of the driving unit to the potential of the third reference voltage input terminal Vint3 during the reset stage. During the light-emitting stage, i.e., when the OLED emits light, the timing control circuit outputs a series of pulse signals through the third control signal terminal SN+1. By reasonably setting the values of the second reference voltage input terminal Vint2 and the third reference voltage input terminal Vint3, the change in VGS of the second transistor T2 during the reset period can be effectively controlled, so as to achieve the best reset effect, and further the hysteresis effect of the second transistor T2 can be effectively suppressed, the instability of OLED light emission can be reduced, and thus the screen flicker can be alleviated.

[0052] By adopting the above embodiments, the fourth switch unit and the fifth switch unit are controlled by the timing control circuit, realizing the pulsed reset of the first pole potential of the driving unit, which can effectively suppress the hysteresis effect of the second transistor T2, significantly reduce the screen flicker at low refresh rates, and improve the viewing comfort. In addition, by adjusting the frequency and amplitude of the pulse, it can be optimized according to different display requirements, further improving the display performance.

[0053] In some embodiments, the pixel driving circuit further includes: the fourth switch unit includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the third control signal terminal SN+1, the first pole of the seventh transistor T7 is connected to the second reference voltage input terminal Vint2, and the second pole of the seventh transistor T7 is connected to the fifth node N5. In the embodiments of the present invention, the seventh transistor T7 is preferably a thin film transistor TFT, and more preferably a P-type metal oxide semiconductor thin film transistor PMOS TFT. When the third control signal terminal SN+1 is at an effective level such as a low level, the seventh transistor T7 is turned on, pulling the potential of the fifth node N5, that is, the second pole of the second transistor T2, to Vint2 to achieve reset.

[0054] The fifth switch unit includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the third control signal terminal SN+1, the first pole of the eighth transistor T8 is connected to the third reference voltage input terminal Vint3, and the second pole of the eighth transistor T8 is connected to the first node N1, that is, the first pole of the driving unit. In the embodiments of the present invention, the eighth transistor T8 is preferably a PMOS TFT. When the third control signal terminal SN+1 is at an effective level such as a low level, the eighth transistor T8 is turned on, pulling the potential of the first node N1 to the potential of the third reference voltage input terminal Vint3. It should be noted that since the second pole of the eighth transistor T8 is connected to the first node N1, that is, the first pole of the second transistor T2, the conduction of the eighth transistor T8 actually indirectly affects the potential change by affecting the potential of the first pole of the driving unit. Combining the function of the seventh transistor T7, the seventh transistor T7 pulls the potential of the fifth node N5 to the potential of the second reference voltage input terminal Vint2, and the eighth transistor T8 pulls the potential of the first node N1 to the potential of the third reference voltage input terminal Vint3. By the pulsed change of the signal of the third control signal terminal SN+1, the conduction and cutoff of the seventh transistor T7 and the eighth transistor T8 are controlled simultaneously to achieve the pulsed reset of the driving unit, that is, the second transistor T2.

[0055] In some embodiments, the transistors in at least the first switching unit and the transistors in the second switching unit are double-gate thin-film transistors. Compared with single-gate TFTs, double-gate TFTs have smaller leakage current and higher stability. The two gates of the double-gate TFT can more effectively control the formation and conduction of the channel, thereby reducing the leakage current and improving the switching speed and stability of the device. The first switching unit is used to control the writing of data signals, and its performance directly affects the accuracy and speed of data writing. By using double-gate TFTs as the transistors in the first switching unit, the leakage current can be effectively reduced, the switching speed can be increased, and thus the accuracy of data writing can be improved. The second switching unit is used to control Vth compensation, and its performance directly affects the accuracy of Vth compensation. By using double-gate TFTs as the transistors in the second switching unit, the leakage current can also be effectively reduced, the switching speed can be increased, and thus the accuracy of Vth compensation can be improved. Specifically, in the embodiments of the present invention, in order to further improve the performance and stability of the circuit, especially to better stabilize the potentials of the second node N2 and the fourth node N4 and to improve the hysteresis and leakage phenomena, the transistors in at least the first switching unit and the second switching unit adopt a double-gate thin-film transistor (Double-Gate TFT) structure. Preferably, the thin-film transistors TFTs connecting the second node N2 and the fourth node N4, namely the first transistor T1, the third transistor T3, and the ninth transistor T9 are all double-gate TFTs. Compared with single-gate TFTs, double-gate TFTs have smaller leakage current, which can reduce the leakage of charges, and thus better maintain the voltage stability of the nodes.

[0056] By adopting the above-described embodiments, using double-gate TFTs to replace some or all of the thin-film transistors TFTs connecting the second node N2 and the fourth node N4 can more effectively stabilize the potentials of the second node N2 and the fourth node N4, reduce the leakage and hysteresis effects, and thus improve the screen flicker perceived by the human eye, especially more significantly at low refresh rates. This enables the pixel driving circuit of the present invention to support lower refresh rate displays, such as displays of 30 Hz or even lower than 30 Hz, and thus further reduces the display power consumption on the premise of ensuring the display quality. It should be noted that replacing the transistors in at least the first switching unit and the second switching unit with double-gate TFTs and preferably replacing all the TFTs connecting the second node N2 and the fourth node N4 with double-gate TFTs in this embodiment is only a preferred implementation manner and not a limitation to the present invention. Any circuit structure or device that can effectively reduce the leakage current, improve the stability of the node potential, and thus improve the display effect should fall within the protection scope of the present invention.

[0057] In some embodiments, the thin film transistor (TFT) connected to the first capacitor C1 and the second capacitor C2 is not limited to a P-type TFT or an N-type TFT. Specifically, the thin film transistors (TFTs) connected to the first capacitor C1 and the second capacitor C2, such as the first transistor T1, the third transistor T3, the sixth transistor T6, and the ninth transistor T9, may use a P-type TFT, i.e., a PMOS TFT, as the transistor in the switching unit. Preferably, if the thin film transistor (TFT) connected to the first capacitor C1 and the second capacitor C2 is an N-type TFT. The leakage current of the transistor is one of the important factors affecting the circuit performance. The leakage current will cause the leakage of charges, thereby affecting the stability and power consumption of the circuit. In the pixel driving circuit, the leakage current will cause the charges stored on the capacitor to decrease, thereby affecting the display brightness. Especially at a low refresh rate, due to the longer refresh period, the influence of the leakage current is more obvious. Using a transistor with lower leakage current characteristics can effectively slow down the charge leakage and improve the display effect. Then the refresh rate can be further reduced to about 1 Hz. The N-type TFT can have lower leakage current characteristics under certain process conditions, such as using an oxide semiconductor material (such as IGZO). Lower leakage current means that the charges stored on the first capacitor C1 and the second capacitor C2 leak more slowly, so that the potential of the node can be kept stable for a longer time, which is suitable for application scenarios with extremely low refresh rates.

[0058] In some embodiments, the light-emitting element is an organic light-emitting diode (OLED). The OLED is composed of multiple organic thin films and is connected between the cathode and the anode. Specifically, in this embodiment, the pixel driving circuit is used to drive the organic light-emitting diode (OLED) to emit light. The OLED is a current-driven light-emitting device, and its emission brightness is proportional to the magnitude of the current flowing through it. Under the action of an electric field, electrons and holes are respectively injected from the cathode and the anode into the organic layer, and recombine in the light-emitting layer to generate photons and emit light. The OLED has the advantages of self-luminescence, wide viewing angle, high contrast ratio, fast response speed, low power consumption, etc., so it has been widely used in the display field. In the present invention, the OLED is connected between the fifth node N5 and the second power supply terminal ELVSS, and the magnitude of the current flowing through it is controlled by the driving unit, thereby controlling its emission brightness. It should be noted that using the OLED as the light-emitting element in this embodiment is only a preferred implementation manner and does not limit the present invention. Any element that can emit light through current driving and can cooperate with the pixel driving circuit of the present invention should fall within the protection scope of the present invention.

[0059] Based on the same inventive concept, on the other hand, an embodiment of the present invention further provides a display panel, including the above-mentioned pixel driving circuit. This display panel can be applied to any product or component with a display function, such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, etc. For the specific implementation manners of this display panel, reference can be made to the embodiments of the above-mentioned pixel driving circuit, and the repeated technical solutions and technical effects will not be elaborated herein.

[0060] As Figure 2 shown, a waveform diagram during the operation of a pixel driving circuit provided by an embodiment of the present invention. Based on the same inventive concept, on the other hand, an embodiment of the present invention further provides a driving method for a pixel driving circuit, including the following stages:

[0061] Stage t1, i.e., the initialization stage: The fourth control signal terminal SN-1 is at an effective level, such as a low level, the sixth transistor T6 is turned on, and the voltage of the first reference voltage input terminal Vint1 is applied to the second node N2 to reset the second node N2, so that the potential of the second node N2 is reset to the potential of the first reference voltage input terminal Vint1. The enable signal input terminal EM is at an invalid level, i.e., a high level, the fourth transistor T4 and the fifth transistor T5 are turned off, and the second transistor T2 and the OLED do not work. The first control signal terminal SN_T1, the second control signal terminal SN_T3, and the third control signal terminal SN+1 are at invalid levels (high levels), and the first transistor T1, the third transistor T3, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned off. The purpose of stage t1 is to initialize the potential of the second node N2 to prepare for subsequent Vth compensation.

[0062] Stage t2, i.e., the Vth compensation stage: When the second control signal terminal SN_T3 is at an effective level, i.e., a low level, the third transistor T3, the ninth transistor T9, and the tenth transistor T10 are turned on. When the ninth transistor T9 is turned on, the voltage of the fourth reference voltage input terminal Vint4 is applied to the fourth node N4 to initialize the fourth node N4. When the tenth transistor T10 is turned on, the voltage of the first power supply terminal ELVDD is applied to the first node N1. When the third transistor T3 is turned on, the potential of the first node N1 is transmitted to the third node N3 through the second transistor T2, the potential of the second pole of the second transistor T2 starts to rise, and then is transmitted to the second node N2 through the third transistor T3. Under the charging effect of the first capacitor C1, the potential of the second node N2 gradually rises to ELVDD + Vth, and the gate of the second transistor T2, i.e., the potential of the second node N2, rises to ELVDD + Vth, using the first power supply terminal ELVDD to compensate for the threshold voltage Vth of the second transistor T2, that is

[0063] The compensation time in this stage can be greater than one line scan time to ensure that Vth is fully compensated. The fourth control signal terminal SN-1, the first control signal terminal SN_T1, the enable signal input terminal EM, and the third control signal terminal SN+1 are at an invalid level, i.e., high level, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. The purpose of the t2 stage is to perform Vth compensation on the second transistor T2 and ensure that the compensation time is greater than one line scan time.

[0064] The t3 stage, i.e., the data writing stage: The first control signal terminal SN_T1 is at a low level, and the first transistor T1 is turned on. The data signal of the data input terminal Data is written into the fourth node N4, making the potential of the fourth node N4 change from the potential of the fourth reference voltage input terminal Vint4 to the potential of the data input terminal Data, i.e., ΔN4 = Data - Vint4. The potential of the second node N2 is coupled by ΔN4. Since the first capacitor C1 is connected between the fourth node N4 and the second node N2, the change in the potential of the fourth node N4 will affect the potential of the second node N2 through the capacitive coupling effect, making

[0065]

[0066] where A = C1 / C total_N2 , C total_N2 is the sum of all the capacitors of the second node N2. When the first capacitor C1 is relatively large compared to other capacitors, A ≈ 1, then N2 ≈ ELVDD + Vth + Data - Vint4. The fourth control signal terminal SN-1, the second control signal terminal SN_T3, the enable signal input terminal EM, and the third control signal terminal SN+1 are at a high level, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned off. The purpose of this stage is to write the data signal into the pixel circuit and transfer the data signal to the gate of the driving unit, i.e., the second transistor T2, using the capacitive coupling effect.

[0067] The t4 stage is the reset stage: the third control signal terminal SN+1 is at a low level, the seventh transistor T7 is turned on, pulling the potential of the fifth node N5 to the potential of the second reference voltage input terminal Vint2 to reset the OLED device. The eighth transistor T8 is turned on, pulling the potential of the first node N1 to the potential of the third reference voltage input terminal Vint3, and at the same time controlling the conduction and cutoff of the seventh transistor T7 and the eighth transistor T8 to achieve a pulsed reset of the second transistor T2 of the driving unit, improving the hysteresis effect of the second transistor T2. The fourth control signal terminal SN-1, the first control signal terminal SN_T1, the second control signal terminal SN_T3, and the enable signal input terminal EM are at a high level, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 are turned off. The purpose of this stage is to reset the OLED device and achieve a pulsed reset by affecting the potential of the driving unit to reduce the hysteresis effect of the second transistor T2.

[0068] The t5 stage is the light-emitting stage: the enable signal input terminal EM is at a low level, the fourth transistor T4 and the fifth transistor T5 are turned on, the second transistor T2 of the driving unit starts to work, and drives the OLED to emit light. The current I flowing through the OLED OLED can be expressed by the following formula:

[0069]

[0070] It can be seen that the current of the OLED is proportional to the square of the difference between the Data signal and Vint4, and has nothing to do with the Vth of the driving unit, thus achieving Vth compensation. The fourth control signal terminal SN-1, the first control signal terminal SN_T1, the second control signal terminal SN_T3, and the third control signal terminal SN+1 are at a high level, and the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned off. The purpose of this stage is to drive the OLED to emit light and achieve a current output related to the data signal.

[0071] Through the above driving method, the pixel driving circuit of the present invention can effectively separate the data writing and Vth compensation time, and make the Vth compensation time longer than one line scanning time, so that sufficient Vth compensation can be performed even at a high refresh rate, improving the uniformity of the display screen. At the same time, by performing a pulsed reset during the light-emitting stage, the screen flicker at a low refresh rate can be effectively reduced. Therefore, the present invention can be well compatible with high and low refresh rate displays, improving the display quality and user experience. It should be noted that, as Figure 2The waveform diagram shown and the above driving method are only a preferred embodiment, and are not intended to limit the present invention. The frequency, amplitude, duty cycle of the pulse signal, as well as the timing relationship of each control signal, and the voltage values of the first reference voltage input terminal Vint1, the second reference voltage input terminal Vint2, the third reference voltage input terminal Vint3, and the fourth reference voltage input terminal Vint4 can all be adjusted according to specific circuit parameters and display requirements. Any driving method that can achieve the separation of data writing and Vth compensation time, with the Vth compensation time being greater than one line scanning time, and perform pulse reset during the light-emitting stage should fall within the protection scope of the present invention.

[0072] In summary, for the pixel driving circuit, driving method, and display panel of the present invention, the timing control circuit precisely controls the conduction and cutoff of the switching unit, completely separating the data writing and Vth compensation processes, such that the Vth compensation process is no longer limited by the scanning time of each row of pixels. This enables sufficient Vth compensation even at high refresh rates, thereby supporting higher refresh rates, such as higher than 240 Hz. By precisely controlling the conduction time of the second switching unit, it is ensured that the Vth compensation time can be greater than one row scanning time, which further enhances the Vth compensation effect and guarantees the Vth compensation accuracy even at high refresh rates, thus significantly improving the display quality at high refresh rates. By the timing control circuit performing a pulsed reset on the source potential of the driving unit during the light-emitting stage, the hysteresis effect of the driving transistor is effectively suppressed, thereby reducing the screen flicker at low refresh rates. Combining the use of low-leakage transistors such as double-gate TFTs or IGZO TFTs can further reduce charge leakage, thereby supporting lower refresh rates, such as lower than 30 Hz, and even reaching around ~1 Hz. The 10T3C circuit proposed in some embodiments of the present invention, i.e., a pixel circuit including 10 transistors and 3 capacitors, through the circuit design and timing control in the embodiments of the present invention, can better balance the Vth compensation at high refresh rates and the flicker suppression at low refresh rates, thereby achieving a wider range of dynamic refresh rate support. In particular, using double-gate TFTs or low-leakage IGZO TFTs, in cooperation with the second capacitor C2 and the third capacitor C3, can further reduce the leakage current of the circuit, improve the low-frequency driving ability, and support lower refresh rates, such as ~1 Hz. Through the combined application of the above technical means, the pixel driving circuit, driving method, and display panel of the present invention can effectively support a wide range of dynamic refresh rates, at least achieving a dynamic refresh rate of 30 Hz to 240 Hz, and through optimizing the circuit design and device selection, it can be further extended to high refresh rates higher than 240 Hz and low refresh rates lower than 30 Hz, and even reaching around ~1 Hz. This enables the display device to flexibly switch the refresh rate in different application scenarios, such as using a high refresh rate during high-frame-rate gaming or video playback to obtain a smooth picture, and using a low refresh rate when browsing static web pages or reading e-books to reduce power consumption, thereby maximizing the user experience and extending the device battery life.

[0073] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A pixel driving circuit, characterized in that: include: A driving unit, used for driving the light-emitting element to emit light; A first switch unit, configured to receive a data signal from a data input terminal and transmit the data signal to a fourth node; A second switch unit, used for controlling threshold voltage compensation and transmitting the compensated voltage to a second node; a fourth switch unit connected between the second reference voltage input terminal and the fifth node; a fifth switch unit, connected between the driving unit and a third reference voltage input terminal; a first storage unit connected between the fourth node and the second node; The timing control circuit is used to output control signals to the first control signal terminal, the second control signal terminal, the third control signal terminal and the fourth control signal terminal respectively, so as to control the on and off of the first switch unit and the second switch unit, thereby separating the data signal writing time from the threshold voltage compensation time, and controlling the on time of the second switch unit so that the threshold voltage compensation time is greater than a row scanning time; the timing control circuit controls the on and off of the fourth switch unit and the fifth switch unit respectively through the third control signal terminal; And in the light-emitting stage, a pulse signal is output to the third control signal terminal to perform a pulse reset on the driving unit.

2. The pixel driving circuit according to claim 1, characterized in that: The first switch unit includes a first transistor, a gate of the first transistor is connected to the first control signal terminal, a first electrode of the first transistor is connected to the data input terminal, and a second electrode of the first transistor is connected to the fourth node.

3. The pixel driving circuit according to claim 1, characterized in that: The second switch unit includes a third transistor, a gate of the third transistor is connected to the second control signal terminal, a first electrode of the third transistor is connected to a third node, and a second electrode of the third transistor is connected to the second node.

4. The pixel driving circuit according to claim 1, characterized in that: It also includes a third switching unit, which includes a sixth transistor. The sixth transistor is a dual-gate thin-film transistor, whose gate is connected to the fourth control signal terminal, the first electrode of the sixth transistor is connected to the first reference voltage input terminal, and the second electrode of the sixth transistor is connected to the second node.

5. The pixel driving circuit according to claim 4, characterized in that: It also includes a third storage unit, which is connected between the midpoint of the double-gate thin film transistor of the sixth transistor and the gate of the sixth transistor and is used to stabilize the potential of the second node.

6. The pixel driving circuit according to claim 1, characterized in that: The fourth switch unit includes a seventh transistor, the gate of the seventh transistor is connected to the third control signal terminal, the first electrode of the seventh transistor is connected to the second reference voltage input terminal, and the second electrode of the seventh transistor is connected to the fifth node; the fifth switch unit includes an eighth transistor, the gate of the eighth transistor is connected to the third control signal terminal, the first electrode of the eighth transistor is connected to the third reference voltage input terminal, and the second electrode of the eighth transistor is connected to the first node.

7. The pixel driving circuit according to any one of claims 1 to 6, characterized in that: At least the transistor in the first switch unit and the transistor in the second switch unit are dual-gate thin film transistors.

8. The pixel driving circuit according to any one of claims 1 to 6, characterized in that: The light emitting element is an organic light emitting diode.

9. A display panel, characterized in that: The method comprises a pixel driving circuit according to any one of claims 1 to 8.

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