OLED voltage driver with current-voltage compensation

Abstract

The embodiment of the invention relates to an OLED voltage driver with current-voltage compensation. Disclosed herein is an electronic device including a display having a reference array, the reference array including a first pixel. The display also includes a first transmit power source coupled to the first pixel. The display also includes an active array having a second pixel. The display also includes a second transmit power source coupled to the second pixel.

Description

[0001] This application is a divisional application of a patent application with international application number PCT / US2018 / 051023, international application date September 14, 2018, entering the Chinese national stage on February 24, 2020, national application number 201880054977.8, and invention name “OLED voltage driver with current-voltage compensation”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 561,529, filed on September 21, 2017, entitled “OLED Voltage Driver with Current-Voltage Compensation,” the contents of which are incorporated herein by reference in their entirety for all purposes. Background Art

[0004] The present disclosure relates generally to electronic displays, and more particularly to compensating for voltage degradation in electronic displays having voltage driven pixels and / or current driven pixels.

[0005] This section is intended to introduce the reader to various aspects of the art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements should be read in this light, and not as an admission of the prior art.

[0006] Flat panel displays such as light emitting diode (LED) displays are commonly used in a variety of electronic devices, including consumer electronics such as televisions, computers, and handheld devices (e.g., cellular phones, audio and video players, gaming systems, etc.). Such display panels typically provide flat panel displays in relatively thin packages suitable for use in a variety of electronic products. In addition, such devices may use less power than comparable display technologies, making them suitable for use in battery-powered devices or other environments where it is desirable to minimize power usage.

[0007] LED displays typically include picture elements (e.g., pixels) arranged in a matrix to display images that can be viewed by a user. When an electric current is applied to each pixel, each pixel of the LED display can generate light. Electric current can be applied to each pixel in the following manner: a voltage is programmed into the pixel, and the voltage is converted into an electric current by a pixel circuit. The pixel circuit that converts the voltage into an electric current may include, for example, a thin film transistor (TFT). However, when a specific voltage is applied, certain operating conditions such as aging or temperature may affect the amount of electric current applied to the pixel.

[0008] Voltage degradation in a pixel may occur at least due to aging. For example, initially, a first voltage may be applied to a diode of a pixel such that a target current is generated at the diode and the target current causes the diode to emit light at a target brightness level. However, over time and with the use of the pixel, voltage degradation may occur. That is, a second voltage different from the first voltage (e.g., greater than the first voltage) may be applied to the diode to generate the target current and cause the diode to emit light at a target brightness level. Summary of the invention

[0009] The following is a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented only to provide the reader with a concise summary of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may cover a number of aspects that may not be described below.

[0010] The present disclosure relates to compensating for voltage degradation in an electronic display having voltage-driven pixels and / or current-driven pixels. The present disclosure can be used in combination with a variety of self-luminous electronic displays including, for example, light-emitting diode (LED) displays, such as organic light-emitting diode (OLED) displays, active matrix organic light-emitting diode (AMOLED) displays, or micro-LED (μLED) displays. Each pixel of an LED display can generate light based at least in part on a current applied to each pixel. Current can be applied to each pixel in the following manner: a voltage is programmed into the pixel, where the voltage can be converted into a current applied to the pixel. The conversion of voltage to current can be regulated by a circuit including, for example, a thin film transistor (TFT). Since the performance of a pixel circuit may change over time due to aging of the pixel, uneven temperature gradients, or other factors, the voltage applied to the pixel on the display can be adjusted to compensate for these changes, thereby improving image quality by reducing visible image artifacts caused by pixel non-uniformity. Non-uniformity of pixels in a display may vary between devices of the same type (e.g., two similar phones, tablets, wearable devices, etc.), may vary over time and use (e.g., due to aging and / or degradation of the pixels or other components of the display), and / or may vary with respect to temperature and in response to additional factors such as electromagnetic interference (EMI) from other electronic components.

[0011] To improve display panel uniformity, adaptive correction or compensation of the display may be employed using performance observed on a "reference array" of the display. The reference array may be adjacent to or part of an active array or area of ​​the display that is hidden from view (e.g., at an edge of the display that is covered by a housing of the display). Thus, the pixels of the reference array may have similar characteristics to the pixels of the visible portion or active area of ​​the display, but may not be visible when activated. However, because the reference array may be used primarily for pixel testing, the operating frequency of the pixels of the reference array may be much lower than the pixels in the visible portion or active array of the display. Therefore, the pixels of the reference array may be considered to be substantially free of aging compared to the rest of the pixels of the display. The performance of the pixels of the reference array may therefore provide a baseline performance expected of pixels in the visible portion or active array of the display that do not experience aging effects.

[0012] Thus, measurements of the performance of a reference array of a display can be used to determine a baseline current-voltage relationship for pixels of a primary active area. The measurements can be obtained based at least in part on a power source voltage level, and based at least in part on a current-voltage curve to capture a gamma tap point for each brightness setting of the display. The reference array can be used to determine a current-voltage relationship when the temperature at the display changes (e.g., when compared to a particular threshold). As another example, a processing circuit coupled to the display can drive pixels of the active array based at least in part on a current-voltage relationship of the pixel and a reference current-voltage relationship of a reference pixel of the reference array. In some cases, the processing circuit may include a current-voltage compensation circuit that receives a degradation ratio, an input voltage, and an input reference current, and outputs a compensation voltage. The digital-to-analog converter can then drive the pixel based at least in part on the compensation voltage.

[0013] Various improvements to the above-mentioned features may be made for various aspects of the present disclosure. Other features may also be added to these various aspects. These improvements and additional features may be made individually or in any combination. For example, the various features associated with one or more of the illustrated embodiments discussed below may be incorporated into any of the above-mentioned aspects of the present invention individually or in any combination. The brief summary presented above is intended only to familiarize the reader with the specific aspects and context of the embodiments of the present disclosure and does not limit the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various aspects of the present disclosure may be better understood upon reading the following detailed description and referring to the accompanying drawings, in which:

[0015] Figure 1 is a schematic block diagram of an electronic device that performs display sensing and compensation according to an embodiment;

[0016] Figure 2 Yes means Figure 1 A perspective view of a laptop computer of an embodiment of the electronic device;

[0017] Figure 3 Yes means Figure 1 A front view of a handheld device of another embodiment of the electronic device;

[0018] Figure 4 Yes means Figure 1 A front view of another handheld device of another embodiment of the electronic device;

[0019] Figure 5 Yes means Figure 1 A front view of a desktop computer of another embodiment of the electronic device;

[0020] Figure 6 Yes means Figure 1 A front view and a side view of a wearable electronic device of another embodiment of the electronic device;

[0021] Figure 7 is a block diagram of a system for display sensing and compensation according to an embodiment of the present disclosure;

[0022] Figure 8 is to illustrate the use of embodiments according to the present disclosure Figure 7 A flowchart of a method for performing display sensing and compensation in a system;

[0023] Fig. 9 The present invention is a method for Figure 7 A graphical representation of a power source for an active array of an electronic display separated from a power source for a reference array;

[0024] Fig.10 The present invention is used to illustrate the embodiment of the present invention. Figure 7 A graph of a brightness control scheme for an electronic display;

[0025] Fig.11 is a method for using a fixed power source voltage level according to an embodiment of the present disclosure Figure 7 A graph of a current-voltage curve of the electronic display 18;

[0026] Fig.12 According to the embodiments of the present disclosure, Figure 7 A flow chart of a method for compensating voltage degradation by a reference array;

[0027] Fig.13 A method for setting a power source voltage level in response to temperature changes according to an embodiment of the present disclosure is shown. Figure 7A block diagram of components of a reference array;

[0028] Fig.14 is a graph showing a current-voltage curve obtained by temperature change according to an embodiment of the present disclosure;

[0029] Fig.15 is a diagram showing an embodiment according to the present disclosure Figure 7 A power source level search circuit of the reference array determines a graph of a power source voltage level that generates a target current;

[0030] Fig.16 is a graph comparing a previous current-voltage curve generated by a previous power source voltage level before a temperature change with a current-voltage curve generated by a set power source voltage level after the temperature change according to an embodiment of the present disclosure;

[0031] Fig.17 is a method for determining the temperature after a temperature change according to an embodiment of the present disclosure. Figure 7 A flow chart of a method for providing a target current power source voltage level to a pixel of an electronic display;

[0032] Fig.18 is a method for determining the set of current and voltage values ​​according to an embodiment of the present disclosure Figure 7 A schematic diagram of a sensing circuit of a reference array;

[0033] Fig.19 is to illustrate the use of embodiments according to the present disclosure Figure 7 A graph of a reference array performing a sensing operation;

[0034] Fig. 20 is a graph showing portions of a current-voltage curve that would be interpolated from a set of current and voltage values ​​associated with various brightness settings according to an embodiment of the present disclosure;

[0035] Fig.21 is a diagram showing an embodiment according to the present disclosure Fig. 20 a graph of gamma tapping points on portions of a current-voltage curve associated with various brightness settings;

[0036] Fig. 22 According to an embodiment of the present disclosure, Fig.21 A flowchart of a method for performing grayscale tracking or gamma correction on a gamma tap point;

[0037] Fig.23 is a graph comparing gamma level to voltage level conversion using a system on chip and a gamma digital-to-analog converter according to an embodiment of the present disclosure;

[0038] Fig.24According to the embodiments of the present disclosure Figure 7 A diagram of a reference array of , the diagram showing features for reducing lateral leakage and / or bias current;

[0039] Fig.25 According to the embodiments of the present disclosure Figure 7 A circuit diagram of a pixel of a reference array;

[0040] Fig.26 The present invention is a method for more accurately sensing Figure 7 A circuit diagram of a first technique for current flow in pixels of a reference array;

[0041] Fig. 27 The present invention is a method for more accurately sensing Figure 7 A circuit diagram of a second technique for current flow in pixels of a reference array;

[0042] Fig.28 The present invention is a method for more accurately sensing Figure 7 A circuit diagram of a third technique for current flow in pixels of a reference array;

[0043] Fig.29 is a method for calibrating a Figure 7 A flowchart of a method for obtaining a reference array;

[0044] Fig.30 is a timing diagram illustrating the operation of a reference array according to an embodiment of the present disclosure;

[0045] Fig.31 is a block diagram of a system for performing current-voltage sensing according to an embodiment of the present disclosure;

[0046] Fig.32 According to the embodiments of the present disclosure, Figure 7 A graph of a current-voltage curve of a pixel of a display;

[0047] Fig.33 According to the embodiments of the present disclosure Figure 7 A diagram of a display at different times;

[0048] Fig.34 According to the embodiments of the present disclosure, Figure 7 A schematic diagram of a current and voltage sensing system for a display;

[0049] Fig.35 According to an embodiment of the present disclosure, a method for reducing data retention to more accurately sense Figure 7 A set of timing diagrams of current in pixels of a display;

[0050] Fig.36 is a diagram showing a method of reducing data retention before performing compensation to more accurately sense the Figure 7 A graph of current in a pixel of a display;

[0051] Fig.37 is a diagram showing a method of reducing data retention after performing compensation to more accurately sense the Figure 7 A graph of current in a pixel of a display;

[0052] Fig.38 According to the embodiments of the present disclosure Figure 7 A diagram of pixels of a display;

[0053] Fig.39 is a diagram showing a method for reducing the Figure 7 A circuit diagram of a first technology for reducing leakage current from a sub-pixel of a display to an adjacent sub-pixel;

[0054] Fig.40 is a diagram showing an embodiment of the present disclosure for considering Figure 7 A circuit diagram of a second technique for leakage and bias currents flowing from a sub-pixel of display 18 to an adjacent sub-pixel;

[0055] Fig.41 According to the embodiments of the present disclosure, Figure 7 A flow chart of a method for determining leakage and bias currents flowing from a pixel of a display to adjacent pixels;

[0056] Fig.42 is a diagram showing the determination according to an embodiment of the present disclosure Figure 7 A circuit diagram of the sum of leakage current, bias current and diode current of a pixel of a display;

[0057] Fig.43 is a diagram showing the determination according to an embodiment of the present disclosure Figure 7 A circuit diagram of the sum of leakage current and bias current of a pixel of a display;

[0058] Fig.44 is a diagram showing the embodiment according to the present disclosure. Figure 7 A circuit diagram for eliminating common mode leakage when providing an operating supply voltage in the display 18;

[0059] Fig.45 is a diagram showing the embodiment according to the present disclosure. Figure 7 A circuit diagram for eliminating common mode leakage when providing an increased supply voltage in a display of FIG. 1 ;

[0060] Fig.46is a circuit diagram showing a source follower pixel according to an embodiment of the present disclosure;

[0061] Fig.47 is a circuit diagram showing a class A amplifier pixel according to an embodiment of the present disclosure;

[0062] Fig.48 is a circuit diagram showing a class AB amplifier pixel according to an embodiment of the present disclosure;

[0063] Fig.49 is a diagram showing the reduction of the Fig.48 Circuit diagram of class AB amplifier pixel noise;

[0064] Fig.50 is a circuit diagram illustrating determination of a bias mismatch current between two pixels according to an embodiment of the present disclosure;

[0065] Fig.51 is a flow chart of a method for determining a current through a diode according to an embodiment of the present disclosure;

[0066] Fig.52 FIG. 2 shows a schematic diagram of a blue sub-pixel caused by sensing the current through the diode of the blue sub-pixel according to an embodiment of the present disclosure. Fig.49 lateral leakage current in the class AB amplifier pixel;

[0067] Fig.53 is a circuit diagram showing a method of reducing a lateral leakage current when a current is sensed in a sub-pixel according to an embodiment of the present disclosure;

[0068] Fig.54 is an exemplary circuit diagram showing a sensing operation performed on a red sub-pixel according to an embodiment of the present disclosure;

[0069] Fig.55 is an exemplary circuit diagram showing a sensing operation performed on a blue sub-pixel according to an embodiment of the present disclosure;

[0070] Fig.56 According to an embodiment of the present disclosure, a method for sensing Figure 7 A timing diagram of current in pixels of an active array of a display;

[0071] Fig.57 According to the embodiments of the present disclosure Figure 7 An illustration of a pixel group of a display;

[0072] Fig.58 The sensing method according to the embodiment of the present disclosure is shown in FIG. Figure 7 Schematic diagram of current in a pixel of a display;

[0073] Fig.59 is a diagram showing the use of incremental-based model generation for Figure 7 A graph of a current-voltage curve of a pixel of a display;

[0074] Fig.60 is a diagram showing the use of an interpolation-based model to generate a Figure 7 A graph of a current-voltage curve of a pixel of a display;

[0075] Fig.61 A method for determining a degradation current-voltage curve to drive a Figure 7 A flowchart of a method for displaying pixels of a display;

[0076] Fig.62 According to the embodiments of the present disclosure Figure 7 A block diagram of a system for compensating for voltage degradation in a display;

[0077] Fig.63 is a diagram showing an embodiment according to the present disclosure Figure 7 A graph showing a linear relationship between a degradation ratio of pixels of a display;

[0078] Fig.64 is a graph illustrating reconstruction of a current-voltage curve based at least in part on two extrapolated current-voltage values ​​according to an embodiment of the present disclosure;

[0079] Fig.65 is a graph showing determination of an output voltage for driving a pixel and compensating for voltage degradation according to an embodiment of the present disclosure; and

[0080] Fig.66 According to an embodiment of the present disclosure, a method for compensating for current-voltage degradation to drive a Figure 7 Flow chart of a method for displaying pixels. DETAILED DESCRIPTION

[0081] One or more specific embodiments will be described below. In order to provide a brief description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, decisions specific to many implementations must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints that may change from one implementation to another. In addition, it should be understood that such development work may be complex and time-consuming, but it will still be a routine task of design, processing and manufacturing for those of ordinary skill in the art who benefit from this disclosure.

[0082] When introducing elements of various embodiments of the present disclosure, the articles "one / an" and "the / said" are intended to mean that there are one or more of the elements. The terms "comprises," "comprising," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that reference to "one embodiment" or "embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the cited features. Also, the phrase A "based on" B is intended to mean that A is based at least in part on B. Moreover, the term "or" is intended to be inclusive (e.g., logical or) and not exclusive (e.g., logical exclusive or). In other words, the phrase A "or" B is intended to mean A, B, or both A and B.

[0083] Electronic displays are widely used in modern electronic devices. As electronic displays gain higher and higher resolution and dynamic range capabilities, image quality is increasing. Generally speaking, an electronic display contains a number of picture elements or "pixels" that are programmed with image data. Each pixel emits a specific amount of light based at least in part on the image data. By programming different pixels with different image data, graphical content including images, video, and text can be displayed.

[0084] Display panel sensing allows identification of the operational properties of pixels of an electronic display to improve the performance of the electronic display. For example, changes in temperature and pixel aging (and other factors) on an electronic display cause pixels at different locations on the display to behave differently. In fact, due to changes in temperature and pixel aging, the same image data programmed on different pixels of a display may look different. For example, a pixel emits a certain amount of light, gamma, or grayscale based at least in part on the amount of current supplied to a diode (e.g., an LED) of the pixel. For voltage-driven pixels, a target voltage may be applied to the pixel so that a target current is applied to the diode (e.g., as represented by a current-voltage relationship or curve) to emit a target gamma value. Changes may affect the pixel by, for example, changing the resulting current applied to the diode when the target voltage is applied. Without proper compensation, these changes may produce undesirable visual artifacts.

[0085] Thus, the techniques and systems described below can be used to compensate for operational variations on a display using a reference array having a control circuit that determines a current-voltage relationship based at least in part on a power source voltage level and captures a gamma tap point for each brightness setting of the display based at least in part on a current-voltage curve. The reference array control circuit can determine the current-voltage relationship when the temperature at the display changes (e.g., when compared to a specific threshold). In addition, a processing circuit coupled to the display can drive pixels of the active array based at least in part on the current-voltage relationship of the pixel and a reference current-voltage relationship of a reference pixel of the reference array. In addition, the processing circuit can include a current-voltage compensation circuit that is configured to receive a degradation ratio, an input voltage, and an input reference current, and output a compensation voltage. The digital-to-analog converter can then drive the pixel based at least in part on the compensation voltage.

[0086] With this in mind, Figure 1 , a block diagram of electronic device 10 is shown in FIG. As will be described in more detail below, electronic device 10 may represent any suitable electronic device, such as a computer, a mobile phone, a portable media device, a tablet computer, a television, a virtual reality headset, a vehicle dashboard, etc. Electronic device 10 may represent, for example, Figure 2 The notebook computer 10A shown in FIG. Figure 3 The handheld device 10B shown in FIG. Figure 4 The handheld device 10C shown in FIG. Figure 5 The desktop computer 10D shown in FIG. Figure 6 The wearable electronic device 10E shown or a similar device.

[0087] Figure 1 The illustrated electronic device 10 may include, for example, a processor core complex 12 , local memory 14 , main memory storage 16 , an electronic display 18 , input structures 22 , input / output (I / O) interfaces 24 , a network interface 26 , and a power supply 28 . Figure 1 The various functional blocks shown in may include hardware elements (including circuits), software elements (including machine executable instructions stored on tangible non-transitory media such as local memory 14 or main memory storage device 16), or a combination of hardware and software elements. It should be noted that Figure 1 This is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10. In practice, the various depicted components may be combined into fewer components or separated into additional components. For example, local memory 14 and main memory storage device 16 may be included in a single component.

[0088] The processor core complex 12 may perform various operations of the electronic device 10, such as causing the electronic display 18 to perform display panel sensing and using feedback to adjust image data for display on the electronic display 18. The processor core complex 12 may include any suitable data processing circuitry for performing these operations, such as one or more microprocessors, one or more application specific processors (ASICs), or one or more programmable logic devices (PLDs). In some cases, the processor core complex 12 may execute programs or instructions (e.g., an operating system or application) stored on a suitable article of manufacture, such as a local memory 14 and / or a main memory storage device 16. In addition to instructions for the processor core complex 12, the local memory 14 and / or the main memory storage device 16 may also store data to be processed by the processor core complex 12. By way of example, the local memory 14 may include a random access memory (RAM), and the main memory storage device 16 may include a read-only memory (ROM), a rewritable non-volatile memory (such as a flash memory, a hard drive, an optical disk, etc.).

[0089] The electronic display 18 may display image frames, such as a graphical user interface (GUI) or application interface for an operating system, still images, or video content. The processor core complex 12 may provide at least some of the image frames. The electronic display 18 may be a self-luminous display, such as an organic light emitting diode (OLED) display, a micro-LED display, a micro-OLED-type display, or a liquid crystal display (LCD) illuminated by a backlight. In some embodiments, the electronic display 18 may include a touch screen that allows a user to interact with the user interface of the electronic device 10. The electronic display 18 may employ display panel sensing to identify operational changes of the electronic display 18. This may allow the processor core complex 12 to adjust the image data sent to the electronic display 18 to compensate for these changes, thereby improving the quality of the image frames that appear on the electronic display 18.

[0090] The input structure 22 of the electronic device 10 can enable the user to interact with the electronic device 10 (e.g., press a button to increase or decrease the volume level). As with the network interface 26, the I / O interface 24 can enable the electronic device 10 to interact with various other electronic devices. The network interface 26 may include, for example, an interface for the following network: for a personal area network (PAN) such as a Bluetooth network, for a local area network (LAN) or a wireless local area network (WLAN) such as an 802.11x Wi-Fi network, and / or for a wide area network (WAN) such as a cellular network. The network interface 26 may also include, for example, an interface for the following: a broadband fixed wireless access network (WiMAX), a mobile broadband wireless network (mobile WiMAX), an asynchronous digital subscriber line (e.g., ADSL, VDSL), a digital video terrestrial broadcast (DVB-T) and its extension DVB handheld device (DVB-H), an ultra-wideband (UWB), an alternating current (AC) power line, etc. The power supply 28 may include any suitable power supply, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0091] In some embodiments, the electronic device 10 may take the form of a computer, a portable electronic device, a wearable electronic device, or other types of electronic devices. Such computers may include computers that are generally portable (e.g., laptops, notebook computers, and tablet computers) as well as computers that are generally used in one location (e.g., conventional desktop computers, workstations, and / or servers). In some embodiments, the electronic device 10 in the form of a computer may be a computer available from Apple Inc. Pro, mini or Mac For example, according to one embodiment of the present invention, Figure 2 1 shows an electronic device 10 in the form of a notebook computer 10A. The illustrated computer 10A may include a housing or casing 36, an electronic display 18, input structures 22, and ports of an I / O interface 24. In one embodiment, the input structures 22 (such as a keyboard and / or a touchpad) may be used to interact with the computer 10A, such as to launch, control, or operate a GUI or application running on the computer 10A. For example, the keyboard and / or touchpad may allow a user to navigate a user interface or application program interface displayed on the electronic display 18.

[0092] Figure 3A front view of a handheld device 10B is depicted, which represents one embodiment of an electronic device 10. The handheld device 10B may represent, for example, a portable telephone, a media player, a personal data organizer, a handheld gaming platform, or any combination of such devices. For example, the handheld device 10B may be a portable device available from Apple Inc. (Cupertino, California). or The handheld device 10B may include a housing 36 for protecting the internal components from physical damage and for shielding the internal components from electromagnetic interference. The housing 36 may surround the electronic display 18. The I / O interface 24 may be opened through the housing 36 and may include, for example, an I / O port for a hardwired connection for charging and / or content manipulation using a standard connector and protocol such as a lightning connector provided by Apple Inc., a universal serial bus (USB), or other similar connectors and protocols.

[0093] The user input structures 22 in conjunction with the electronic display 18 can allow the user to control the handheld device 10B. For example, the input structures 22 can activate or deactivate the handheld device 10B, navigate the user interface to the home screen, the user-configurable application screen, and / or activate the voice recognition feature of the handheld device 10B. Other input structures 22 can provide volume control, or can switch between vibration and ring mode. The input structures 22 can also include a microphone to obtain the user's voice for various voice-related features, and a speaker that can enable audio playback and / or certain telephone functions. The input structures 22 can also include a headphone input that can provide a connection to an external speaker and / or headphones.

[0094] Figure 4 A front view of another handheld device 10C is depicted, which represents another embodiment of the electronic device 10. The handheld device 10C may represent, for example, a tablet computer, or one of a variety of portable computing devices. For example, the handheld device 10C may be a tablet-sized embodiment of the electronic device 10, specifically, may be, for example, a tablet-sized embodiment available from Apple Inc. (Cupertino, California). Type handheld device.

[0095] See also Figure 5 , the computer 10D can represent Figure 1 The computer 10D may be any computer, such as a desktop computer, a server, or a notebook computer, but may also be a stand-alone media player or a video game console. For example, the computer 10D may be a iPod Touch from Apple Inc. or other similar devices. It should be noted that the computer 10D may also represent a personal computer (PC) of another manufacturer. A similar housing 36 may be provided to protect and surround the internal components of the computer 10D, such as the electronic display 18. In some embodiments, a user of the computer 10D may interact with the computer 10D using various peripheral input devices, such as input structures 22A or 22B (e.g., a keyboard and mouse), that may be connected to the computer 10D.

[0096] Similarly, Figure 6 Depicted Figure 1 Another embodiment of the electronic device 10 of the present invention is a wearable electronic device 10E, which can be configured to operate using the techniques described herein. For example, the wearable electronic device 10E can include a wristband 43, which can be an Apple However, in other embodiments, the wearable electronic device 10E may include any wearable electronic device, such as, for example, a wearable motion monitoring device (e.g., a pedometer, an accelerometer, a heart rate monitor) or other device of another manufacturer. The electronic display 18 of the wearable electronic device 10E may include a touch screen display 18 (e.g., an LCD, an OLED display, an active matrix organic light emitting diode (AMOLED) display, etc.) and an input structure 22, which may allow a user to interact with the user interface of the wearable electronic device 10E.

[0097] Figure 7 is a block diagram of a system 50 for display sensing and compensation according to an embodiment of the present disclosure. The system 50 includes a processor core complex 12 that includes an image correction circuit 52. The image correction circuit 52 may receive image data 54 and compensate for non-uniformities of the display 18 based at least in part on and caused by process non-uniformity temperature gradients, aging of the display 18, and / or other factors across the display 18 to improve the performance of the display 18 (e.g., by reducing visible anomalies). The non-uniformity of pixels in the display 18 may vary between devices of the same type (e.g., two similar phones, tablets, wearable devices, etc.), vary over time and use (e.g., due to aging and / or degradation of pixels or other components of the display 18), and / or vary with respect to temperature, as well as in response to other factors.

[0098] As shown, system 50 includes aging / temperature determination circuitry 56 that may determine or facilitate determination of non-uniformity of pixels in display 18 due to, for example, aging and / or degradation of the pixels or other components of display 18. Aging / temperature determination circuitry 56 may also determine or facilitate determination of non-uniformity of pixels in display 18 due to, for example, temperature.

[0099] The image correction circuit 52 may send the image data 54 (for which the non-uniformity of the pixels in the display 18 may or may not have been compensated by the image correction circuit 52) ​​to the analog-to-digital converter 58 of the driver integrated circuit 60 of the display 18. The analog-to-digital converter 58 may digitize the image data 54 while the image data 54 is in an analog format. The driver integrated circuit 60 may send a signal across the gate lines of the display panel 61 to cause a row of pixels including the pixel 63 in the active array 62 of the display panel 61 to become activated and programmable, at which point the driver integrated circuit 68 may transmit the image data 54 across the data lines to program the pixels including the pixel 63 to display a specific gray level (e.g., individual pixel brightness). By providing different pixels with different colors to display different gray levels with the image data 54, a full-color image may be programmed into the pixels of the active array 62 of the display panel 61.

[0100] The driver integrated circuit 60 may also send a signal across the gate line so that a row of pixels including pixels 65 in the reference array 64 of the display panel 61 becomes activated and programmable. The reference array 64 may be invisible to the user of the electronic device 10. For example, the reference array 64 may be covered by an opaque structure or material (e.g., a black material) that prevents the reference array 64 from being visible. In some embodiments, the reference array 64 may surround the edge or back of the electronic device 10 so that the reference array is hidden from view. The driver integrated circuit 60 may also include a sensing analog front end (AFE) 66 to perform analog sensing of the pixel's response to data input (e.g., image data 54). In some embodiments, the AFE 66 may be used for sensing in both the active array 62 and the reference array 64. In alternative or additional embodiments, there may be at least a first AFE for sensing in the active array 62 and at least a second AFE for sensing in the reference array 64.

[0101] The processor core complex 12 may also send a sensing control signal 68 to cause the display 18 to perform display panel sensing. In response, the display 18 may send display sensing feedback 70, which represents digital information related to the operational changes of the display 18. The display sensing feedback 70 may be input to the aging / temperature determination circuit 56 and may take any suitable form. The output of the aging / temperature determination circuit 56 may take any suitable form and is converted by the image correction circuit 52 into a compensation value that, when applied to the image data 54, appropriately compensates for the operational changes of the display 18 (e.g., resulting in operational non-uniformity or overall changes in the display 18). This may result in higher fidelity of the image data 54, reducing or eliminating visual artifacts that would otherwise occur due to operational changes of the display 18. In some embodiments, the processor core complex 12 may be part of the driver integrated circuit 60, and therefore part of the display 18.

[0102] Figure 8 is to illustrate the use of embodiments according to the present disclosure Figure 7 Flowchart of a method 80 for display sensing and compensation for system 50; method 80 may be performed by any suitable device that can sense operational changes in display 18 and compensate for operational changes, such as display 18 and / or processor core complex 12.

[0103] The display 18 senses (processing block 82) operational changes of the display 18 itself. In particular, the processor core complex 12 may send one or more instructions (e.g., sensing control signals 68) to the display 18. The instructions may cause the display 18 to perform display panel sensing. The operational changes may include any suitable changes that cause non-uniformities in the display 18, such as process non-uniformity temperature gradients, aging of the display 18, etc.

[0104] The processor core complex 12 then adjusts the display 18 based at least in part on the operational change (block 84). For example, the processor core complex 12 may receive display sensing feedback 70 that represents digital information related to the operational change from the display 18 in response to receiving the sensing control signal 68. The display sensing feedback 70 may be input to the aging / temperature determination circuit 56 and may be in any suitable form. The output of the aging / temperature determination circuit 56 may be in any suitable form and may be converted into compensation values ​​by the image correction circuit 52. For example, the processor core complex 12 may apply the compensation values ​​to the image data 54, which may then be sent to the display 18. In this way, the processor core complex 12 may perform the method 80, at least in part, to improve the performance of the display 18 (e.g., by reducing visible anomalies).

[0105] Reference array

[0106] The above-mentioned pixels 65 (and 63) may be voltage-driven pixels (so that the pixels are controlled by adjusting the voltage input converted into current in the pixels 63 and 65) and / or current-driven pixels. That is, the pixels 63 and 65 may not be controlled by directly adjusting the current input. Instead, the pixels 63 and 65 may be controlled by providing some specific voltage values ​​to the pixels 63 and 65 and allowing the current to be generated by the input voltage in the pixels 63 and 65 to be indirectly adjusted by adjusting the current input. In fact, the brightness of each pixel 65 is directly related to the current provided to the pixel 65. The current provided to each pixel 65 depends on the voltage input to the pixel 65, and operational changes such as temperature may change the current provided to the pixel 65 for a set of voltage inputs. Therefore, more accurately capturing or sensing the current-voltage relationship (represented as a curve) of each pixel 65 enables the pixels 63, 65 to more accurately display the image data 54. In additional or alternative embodiments, the pixels 63 and 65 may be controlled by directly adjusting the current input.

[0107] Thus, the reference array 64 can be used to more accurately sense the current-voltage relationship of each pixel 65. In some embodiments, the control circuit of the reference array 64 can control the power source (e.g., the ELVSS power source coupled to the source of the thin film transistor (TFT) of the pixel 65) voltage level or current level to maintain a specific brightness setting. The reference array control circuit can generate a current-voltage curve based at least in part on the power source voltage level, and capture a gamma tap point based at least in part on the current-voltage curve. The reference array control circuit can perform grayscale tracking or gamma correction on the gamma tap point, and program the gamma tap point into a gamma digital-to-analog converter (DAC).

[0108] The reference array control circuit can more accurately sense the current-voltage relationship of each pixel 65 by separating its ELVSS power source from the ELVSS power source of the active array 62. In addition, in some embodiments, but not necessarily in all embodiments, the reference array control circuit can use a fixed ELVSS voltage level or current level (which can be set at a certain temperature) throughout the brightness setting range, rather than sensing, generating and using the ELVSS voltage level or current level for each brightness setting. The sensing circuit of the reference array 64 can apply a voltage to sense the current on the diode of the pixel 65 (e.g., force voltage sensing current) to determine a set of current and voltage values, which can be used to determine the current-voltage relationship or curve associated with the ELVSS voltage level. In this way, the reference array control circuit can allow its ELVSS power source 86 to be adjusted without affecting the emission of the active array. In addition, the reference array 64 can achieve faster, almost instantaneous brightness adjustments (rather than having to perform a sensing operation before each brightness adjustment).

[0109] Fig. 9 is a diagram showing an embodiment according to the present disclosure Figure 7 FIG. 6 is an illustration of an active array subsystem 71 and a reference array subsystem 73 of a display panel 61. The reference array subsystem 73 may include an ELVSS power source 86 (e.g., another different cathode) that is separate from the ELVSS power source 88 (e.g., cathode) of the active array subsystem 71. The reference array 64 may include any suitable number (e.g., 1 to 1000) of columns of pixels 65. The ELVSS power source 86 of the reference array subsystem 73 may thus be adjusted without affecting the emission of the active array 62. Thus, the separate ELVSS power sources 86, 88 may enable a low noise sensing scheme.

[0110] The reference array subsystem 73 may also include a reference array control circuit 89 coupled to the pixel 65. The reference array control circuit 89 may include any suitable circuitry for controlling the reference array 64, such as processing circuitry, sensing circuitry 87, and the like. In some embodiments, the reference array control circuit 89 may include control circuitry external to the reference array 64, such as control circuitry of the active array 62, the processor core complex 12, and the like. The reference array sensing circuitry 87 may enable sensing of operating parameters of the reference array 64, such as voltage measurements, current measurements, and the like. The reference array sensing circuitry 87 may include any suitable circuitry for sensing operating parameters of the reference array 64, such as voltage sensors, current sensors, and the like. In some embodiments, the reference array sensing circuitry 87 may be external to the reference array control circuit 89. In some cases, the reference array control circuit 89 may be Figure 7 A portion of a driver integrated circuit 60 is shown.

[0111] Similarly, the active array subsystem 71 may also include a control circuit 85 coupled to the pixel 63 for controlling the active array 62. The active array control circuit 85 may include any suitable circuit for controlling the active array 62, such as a processing circuit, a sensing circuit 83, etc. For example, as shown, the active array control circuit 85 may include a current step limiter circuit 72, which may limit a current compensation value used to compensate for voltage degradation in the electronic display 18. Specifically, the current step limiter circuit 72 may be used to limit the current compensation value to below a visibility threshold (e.g., so that an observer of the display 18 may not perceive the change in current value caused by compensating for voltage degradation). In alternative or additional embodiments, the reference array control circuit 89 may include the current step limiter circuit 72. In some embodiments, the active array control circuit 85 may include a control circuit external to the active array 62, such as the reference array control circuit 89, the processor core complex 12, etc. The active array sensing circuit 83 may enable sensing of operating parameters of the active array 62, such as voltage measurement, current measurement, etc. Active array sensing circuitry 83 may include any suitable circuitry for sensing operating parameters of active array 62, such as a voltage sensor, a current sensor, etc. In some embodiments, active array sensing circuitry 83 may be external to active array control circuitry 85. In some cases, active array control circuitry 85 may be Figure 7 A portion of a driver integrated circuit 60 is shown.

[0112] Fig.10 The present invention is used to illustrate the embodiment of the present invention. Figure 7 9. The brightness control scheme 90 may use both a digital brightness control scheme 92 and an analog brightness control scheme 94. Specifically, the brightness control scheme 90 may avoid using only the analog brightness control scheme 94 (over the entire brightness range 96) because this may cause the low-level current level (e.g., 98) to approach a nearly unmeasurable current level.

[0113] For a certain brightness range 100, the brightness control scheme 90 can use an analog brightness control scheme 94 to control the brightness of the pixel 65 by adjusting the current 102 provided to the pixel 65, while keeping the duty cycle or pulse width 104 of the corresponding voltage input to the pixel 65 (e.g., the data signal that causes the current 102) constant. A certain brightness range 100 can be within the data voltage domain. Advantageously, the use of the analog brightness control scheme 94 can slow down the aging of the pixel 65. For a lower brightness range 101 (when compared to the specific brightness range 100), the brightness control scheme 90 can use a digital brightness control scheme 92 to keep the current 106 constant, while adjusting the duty cycle or pulse width 108 of the corresponding voltage input to the pixel 65 to control the brightness of the pixel 65. Advantageously, the digital brightness control scheme 92 can use a smaller current range (when compared to the analog brightness control scheme 94) and result in lower bias power usage. In this way, the range of the operating current 103 can be relaxed so that the current 103 can be controlled at a low current level.

[0114] Some electronic displays may adjust the ELVSS voltage level to control the brightness setting. However, when the ELVSS voltage level is adjusted, the current-voltage relationship of each pixel 65 may change. Therefore, whenever the brightness setting changes (as a result of adjusting the ELVSS voltage level), some electronic displays may sense or rescan the current-voltage relationship of each pixel 65 (which current-voltage relationship may be represented and saved as a curve) (at both the new brightness setting and one or more intermediate brightness settings to prevent changes visible to the naked eye). Therefore, changing the brightness setting of these electronic displays may be inefficient and slow (e.g., in the range of tens of seconds).

[0115] To avoid this time-consuming process, Figure 7 The reference array 64 can use a fixed ELVSS voltage level over the entire range of brightness settings (which can be set at a certain temperature). Thus, the current-voltage relationship or curve for each pixel 65 can remain constant (and rescanning a separate current-voltage relationship or curve for each brightness setting and intermediate brightness settings can be avoided). In some embodiments, the reference array control circuit 89 can adjust the ELVSS voltage level for different temperatures.

[0116] Fig.11 is a method for using a fixed ELVSS voltage level according to an embodiment of the present disclosure Figure 7 18. The current (e.g., I 二极管 ) is provided to a diode (eg, an LED) of pixel 65, and a voltage (V 数据) is provided to the gate of the TFT of the pixel 65. The current-voltage curve 110 may be based at least in part on a set of current and voltage values ​​provided via the reference array 64. In addition, the current-voltage curve 110 may also include interpolated values ​​and / or extrapolated values ​​of the set of current and voltage values ​​provided via the reference array 64. The current-voltage curve 110 may be associated with a grayscale level (G0-G255) for each brightness setting. For example, a first portion 112 of the current-voltage curve 110 may correspond to a range of grayscale levels (e.g., from a minimum grayscale level 1 (G1) to a maximum grayscale level 255 (G255)) for a first brightness setting (e.g., 50 nits) for the pixel 65. A second portion 114 of the current-voltage curve 110 may correspond to a range of grayscale levels for a second brightness setting (e.g., 150 nits) for the pixel 65.

[0117] Once the current-voltage curve 110 has been captured or realized, for any brightness setting, the data generated by the current-voltage curve 110 can be used to immediately update the associated gamma value. Thus, the response of the electronic display to changes in brightness settings can be significantly improved by avoiding rescanning of a new current-voltage relationship or curve.

[0118] The interpolation technique used may be any suitable technique for representing the set of current and voltage values ​​as a curve, such as logarithmic space splines, linear splines, exponentials, etc. The pixel current may include a range of multiple (e.g., 6 to 8) orders of magnitude, and the set of current and voltage values ​​may include a finite number (e.g., 5 to 14) of current and voltage value pairs. Logarithmic space spline interpolation is an example of a suitable and effective interpolation technique for generating gamma from several value pairs. Specifically, the use of logarithmic space spline interpolation allows for fairly small errors (e.g., 0% to 12%, 8% to 10%, etc.) at various temperatures. For example, the interpolation method can be expressed as:

[0119]

[0120] Equation 1 allows for the interpolation of 8 to 10 sets of current and voltage value pairs to provide each grayscale voltage ( G1 to G255 ) at the brightness setting of pixel 65 .

[0121] In some embodiments, the second power source (e.g., an ELVDD power source coupled to the drain of the TFT of pixel 65) can be adjusted to increase power savings. The ELVSS power source can supply the diode current of pixel 65 (to the LED), but does not supply a bias current to pixel 65. However, the ELVDD power source can supply both a diode current and a bias current to pixel 65. Therefore, by supplying a variable ELVDD voltage level to pixel 65 to keep the ELVSS voltage level constant (so that the current provided by the ELVDD power source to pixel 65 can be reduced), power savings can be achieved when operating pixel 65.

[0122] Fig.12 According to the embodiments of the present disclosure, Figure 7 Flowchart of method 130 for compensating for voltage degradation in reference array 64 of FIG. 130. Method 130 may be performed by any suitable device or combination of devices that may determine temperature changes, set ELVSS voltage levels, determine current and voltage values, generate current-voltage curves, determine a set of gamma tap points, and perform grayscale tracking correction. Although method 130 is described using a particular sequence of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in an order different from that shown, and that certain described steps may be skipped or not performed at all. In some embodiments, at least some of the steps of method 130 may be performed by reference array control circuitry 89, as described below. However, it should be understood that any suitable device or combination of devices is contemplated for performing method 130, such as control circuitry for active array 62, processor core complex 12, and the like.

[0123] The reference array control circuit 89 may determine (decision block 132) whether a temperature change exists. The temperature change may be the result of ambient temperature changes, operating the electronic device 10, etc. In some embodiments, the reference array control circuit 89 may determine whether a temperature change exists by comparing the temperature change to a threshold temperature change.

[0124] If there is no temperature change, the reference array control circuit 89 may return to decision block 132. If there is a temperature change, the reference array control circuit 89 may set or determine (block 134) the ELVSS voltage level. Specifically, the reference array control circuit 89 may iterate through a series of different ELVSS voltage levels until the target current is provided to the pixel 65 via the target voltage. For example, the ELVSS voltage level may be set so that the target current is provided to the pixel 65 using the target voltage (e.g., V 255 ) provides a peak current (e.g., I 255 , corresponding to the peak gray level of G255).

[0125] The reference array control circuit 89 may determine (block 136) a set of current and voltage values ​​associated with the ELVSS voltage level. Specifically, the reference array control circuit 89 may determine the set of current and voltage values ​​associated with the ELVSS voltage level based at least in part on the voltage provided to the pixel 65 (e.g., V 数据 ) to measure multiple (e.g., 6 to 14) current values ​​provided to the LED of pixel 65.

[0126] The reference array control circuit 89 may then generate (block 138) a current-voltage relationship or curve 110 based at least in part on the set of current and voltage values. That is, the reference array control circuit 89 may use the set of current and voltage values ​​to interpolate and / or extrapolate the current-voltage relationship or curve 110. In some embodiments, a log-space spline interpolation technique may be used.

[0127] The reference array control circuit 89 may determine a portion of the current-voltage relationship or curve 110 for one or more brightness settings of the pixel 65. Based at least in part on the portion of the current-voltage curve 110, the reference array control circuit 89 may determine (block 140) a set of gamma tap points. In some embodiments, the set of gamma tap points may be mapped to and used to generate corresponding gray levels.

[0128] The reference array control circuit 89 may then perform (block 142) grayscale tracking or gamma correction on the gamma tap points using an integrated circuit such as a system on a chip (SoC) and / or the processor core complex 12. For example, the image correction circuit 52 of the processor core complex 12 may perform grayscale tracking or gamma correction on the gamma tap points.

[0129] The active array 64 may (process block 144) display image data based at least in part on the gamma tap point. Specifically, the active array 64 may display grayscale levels of the image data using data voltages corresponding to grayscale levels as provided or defined by the gamma tap point. In some embodiments, the current step limiter circuit 72 of the active array control circuit 85 may limit the current compensation value used to provide the data voltage. Specifically, the current step limiter circuit 72 may be used to limit the current compensation value for providing the data voltage to below a visibility threshold. The visibility threshold may correspond to a change in current value that may not be perceived by an observer of the display 18 when the data voltage is applied (compared to displaying the grayscale level of the image data using the data voltage before the current compensation value is applied). In this way, the observer may not notice the applied compensation, thereby improving the overall viewing experience of the display 18.

[0130] If there is another temperature change, then the method 130 may be repeated. In this way, the reference array control circuit 89 may compensate for voltage degradation in the electronic display 18.

[0131] Fig.13 FIG. 1 shows a method for setting an ELVSS voltage level (eg, VSS150) in response to temperature changes according to an embodiment of the present disclosure. Figure 7 64. The analog-to-digital converter (ADC) 152 may sense or receive an analog current (I ) provided to a diode 156 (eg, an LED or OLED) of a pixel 65. 二极管)154, and the simulated current (I 二极管 )154 is converted into a digital signal 158.

[0132] The comparison circuit 160 then compares the digital current signal 158 with the reference current (I Ref )162 to generate a comparison between the digital current signal 158 and the reference current (I Ref ) 162 is associated with a difference signal 164. The reference current (I Ref ) 162 may be a current associated with the target data voltage (eg, I 255 ), which target data voltage is used to generate a target gray level (e.g., a peak gray level of G255) at a target brightness setting (e.g., 150 nits) at a previous temperature at which, for example, the ELVSS voltage level was previously set (before the temperature change).

[0133] The ELVSS voltage level search circuit 166 can receive the difference signal 164 and determine the ELVSS voltage level that generates the reference current 162 (and thus the target grayscale level) at the target brightness setting when the target data voltage is applied. The ELVSS voltage level can be determined using any suitable search method, such as a binary search method, a step search method, etc.

[0134] ELVSS voltage level search circuit 166 may generate a digital ELVSS voltage level signal 168 that may be received by a digital-to-analog converter (DAC) 170. DAC 170 may convert digital ELVSS voltage level signal 168 to an analog format and send result 172 to buffer 174 to generate a buffered analog ELVSS voltage level signal 176. Buffered analog ELVSS voltage level signal 176 may be sent to pixels 65 of reference array 64 and / or pixels 63 of active array 62 to provide new source voltages.

[0135] Fig.14 1 is a graph showing a current-voltage curve resulting from temperature change according to an embodiment of the present disclosure. The first current-voltage curve 190 is associated with a first ELVSS voltage level 192 set at a previous temperature. The first current-voltage curve 190 can be used to generate a voltage from a first V G1 194 to the first V G255 196, which corresponds to generating gray levels from G1 to G255 (under the target brightness setting). To generate gray level G255, the first data voltage level V G255 196 causes a current level I to be provided to diode 156 G255 197.

[0136] After the temperature changes, the first current-voltage curve 190 moves to the second current-voltage curve 198, while the ELVSS voltage level remains at the first ELVSS voltage level 192. Since the first current-voltage curve 190 moves due to the temperature change, the data voltage level changes accordingly. G1 194 Move to the second V G1' 200, and the first V G255 196 Move to the second V G255' 202.

[0137] Fig.15 is a diagram showing an embodiment according to the present disclosure Figure 7 The ELVSS voltage level search circuit 166 of the reference array 64 determines a graph of ELVSS voltage levels that generate a target current (e.g., reference current 162) associated with a target grayscale level at a target brightness setting when a target data voltage is applied. The first ELVSS voltage level 192 is set at a previous temperature and used to generate a current-voltage curve 198. Due to temperature changes, when a target voltage (e.g., V G255 196), the first ELVSS voltage level no longer generates the target current (eg, I associated with generating gray level G255). G255 198).

[0138] The search method may determine a second ELVSS voltage level 204 that may be used to generate a second current-voltage curve 206. However, as shown, when the supply V 255 196, the resulting current is not the target current I associated with generating gray level G255 G255 198. The search method can determine a third ELVSS voltage level 208 that can be used to generate a third current-voltage curve 210. As with the second ELVSS voltage level 204, when the supply V 255 196, the resulting current associated with the third ELVSS voltage level 208 is not the target current I G255 198. The search method can also determine a fourth ELVSS voltage level (ELVSS') 212 that can be used to generate a fourth current-voltage curve 214. As shown, when the supply V 255 196, the resulting current associated with the fourth ELVSS voltage level 212 is the target current I G255 198. The search method may be any suitable search method, such as a binary search method, a step search method, and the like.

[0139] Fig.162 is a graph comparing a previous current-voltage curve 190 generated by a previous ELVSS voltage level 192 before a temperature change with a current-voltage curve 214 generated by setting an ELVSS voltage level (ELVSS′) 212 after the temperature change according to an embodiment of the present disclosure. As shown in the figure, when the supply V 255 196, the resulting current associated with the previous current-voltage curve 190 before the temperature change and the resulting current associated with the current-voltage curve 214 after the temperature change are both the target current I G255 198.

[0140] Fig.17 is a method for determining when a target voltage (eg, V 255 196) After the temperature changes Figure 7 The pixel 65 of the electronic display 18 provides a target current (eg, I G255 198). Method 220 may be performed by any suitable device or combination of devices that can determine a diode current and an ELVSS voltage level that supplies a target diode current, and apply the ELVSS voltage level. Although method 220 is described using a particular sequence of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in an order different from that shown, and that certain described steps may be skipped or not performed at all. In some embodiments, at least some of the steps of method 220 may be performed by reference array control circuitry 89, as described below. However, it should be understood that any suitable device or combination of devices is contemplated for performing method 220, such as control circuitry for active array 62, processor core complex 12, and the like.

[0141] The reference array control circuit 89 may receive (block 222) a previous ELVSS voltage level. The previous ELVSS voltage level may have been set by the reference array control circuit 89 for a previous temperature.

[0142] In some embodiments, reference array control circuit 89 can estimate the search range based at least in part on the temperature characteristics of the pixel. That is, reference array control circuit 89 can receive a temperature associated with pixel 65 and estimate a voltage range to which the ELVSS voltage level can be set based at least in part on the temperature.

[0143] The reference array control circuit 89 may then determine or sense (block 224) a first diode current (e.g., a current provided to the pixel 65). Specifically, the first diode current may be a result of providing a target voltage level to the diode 156. The target voltage level may be a voltage supplied to the diode 156 that resulted in providing the target current level to the diode 156 at a previous temperature. In some embodiments, the target voltage level (e.g., V 255 ) can result in providing a peak current level (e.g., I 255 ) so that diode 156 emits a peak gray level (e.g., G255).

[0144] The reference array control circuit 89 may determine (decision block 226) whether the first diode current is equal to the target diode current (eg, I ref 162). Comparison circuit 160 may perform this determination. In some embodiments, the target diode current may be a peak current level (e.g., I G255 ) so that diode 156 emits a peak gray level (e.g., G255).

[0145] If not, the reference array control circuit 89 determines (block 228) that the target diode current (eg, I ref 162) supplies the ELVSS voltage level to the diode 156 (e.g., Fig.16 For example, when a target voltage level (eg, V 255 ), the ELVSS voltage level can supply a current level equal to the peak current level (e.g., I 255 ) The search may be performed by the ELVSS voltage level search circuit 166 using a binary search method, a step search method, or the like.

[0146] After the reference array control circuit 89 determines the ELVSS voltage level at process block 228, or if the first diode current is equal to the target diode current at decision block 226, the reference array control circuit 89 applies (process block 230) the ELVSS voltage level to the pixel 65. Thus, the target diode current (e.g., peak current level, I 255 ) is applied to diode 156 (e.g., using a target voltage level (e.g., V 255 )), thereby causing diode 156 to emit a peak gray level (eg, G255). In this way, the ELVSS voltage level that provides a target current (eg, when a target voltage is supplied) to pixel 65 of electronic display 18 after a temperature change can be determined.

[0147] Once the ELVSS voltage level is determined (e.g. Fig.16 ELVSS' 212 as shown), the reference array control circuit 89 can determine a set of current and voltage values. Fig.18 is a method for determining the set of current and voltage values ​​according to an embodiment of the present disclosure Figure 7 Schematic diagram of the sensing circuit 240 of the reference array control circuit 89. The sensing circuit 240 can be used to implement the force voltage sensing current technology, so that the sensing circuit 240 can apply or force the data voltage V 数据 242 and determining or sensing the current I on the diode 156 of the pixel 65 for the ELVSS voltage level 246 二极管 244. The data voltage 242 provided by the sensing circuit 240 may be referred to as a sensing voltage V 感测 248, and the resulting current 244 may be referred to as the sensing current I 感测 250. Advantageously, sensing circuit 240 may perform a single sensing operation to determine one current and voltage value pair, and may perform the same technique for off-time sensing (eg, sensing when electronic device 10 is turned off or otherwise not being used).

[0148] Sense voltage V 感测 248 may be determined using a sense voltage generator 252 . Fig.19 is to illustrate the use of embodiments according to the present disclosure Figure 7 64 performs a sensing operation. Since the temperature change between two sensing operations may be relatively small (e.g., less than or equal to about 5 degrees Celsius), the curvature change between the previous current-voltage curve 260 (e.g., before the temperature change) and the current current-voltage curve 262 (e.g., after the temperature change) may also be relatively small. Therefore, the sensing voltage generator 252 may derive the sensing voltage (e.g., V 感测 248). With respect to the previous current-voltage curve 260, the sensing voltage V 感测 248 corresponds to the target current I 目标 262. The reference array control circuit 89 may use the same sense voltage V from the previous current-voltage curve 260 感测 248, and determining and / or measuring the corresponding current (I 二极管 244), which is the sensed current I 感测 250. In this way, the reference array control circuit 89 can perform a sensing operation to determine the set of current and voltage values ​​used to interpolate the current-voltage curve 262.

[0149] Fig. 202 is a graph showing portions of a current-voltage curve 270 that would be interpolated from the set of current and voltage values ​​(eg, 272) associated with various brightness settings according to an embodiment of the present disclosure. G1 274 to V DBV1 The first portion of 276 may correspond to a first brightness setting. G1 274 may correspond to a voltage level that emits gray level 1 when supplied to pixel 65 at the first brightness setting. It should be noted that V G1 274 may include a small range (e.g., approximately 100 millivolts) variation at different brightness settings (e.g., 50 nits to 150 nits). Although V G1 274 may be associated with the voltage that produces the lowest gray level (G1) using the first brightness setting, but V DBV1 276 may be associated with a voltage that produces a maximum gray level (G255) using a first brightness setting. For example, the first brightness setting may be 50 nits.

[0150] The current-voltage curve 270 is from V G1 274 to V DBV2 The second portion of 278 may correspond to a second brightness setting. G1 274 may be associated with a voltage that produces the lowest gray level (G1) using the second brightness setting, and V DBV2 278 may be associated with a voltage that produces a maximum gray level (G255) using a second brightness setting. For example, the second brightness setting may be 70 nits.

[0151] The current-voltage curve 270 is from V G1 274 to V DBV3 The third portion of 280 may correspond to a third brightness setting. G1 274 may be associated with a voltage that produces the lowest gray level (G1) using the third brightness setting, and V DBV3 280 may be associated with a voltage that produces the highest gray level (G255) using the third brightness setting. For example, the third brightness setting may be 90 nits.

[0152] The current-voltage curve 270 is from V G1 274 to V DBV4 The fourth portion of 282 may correspond to a fourth brightness setting. G1 274 may be associated with a voltage that produces the lowest gray level (G1) using the fourth brightness setting, and V DBV4 282 may be associated with a voltage that produces a highest gray level (G255) using a fourth brightness setting. For example, the fourth brightness setting may be 110 nits.

[0153] The current-voltage curve 270 is from V G1 274 to V DBV5 The fifth portion of 284 may correspond to a fifth brightness setting. G1 274 may be associated with a voltage that produces the lowest gray level (G1) using the fifth brightness setting, and V DBV5 284 may be associated with a voltage that produces the highest gray level (G255) using the fifth brightness setting. For example, the fifth brightness setting may be 130 nits.

[0154] The current-voltage curve 270 is from V G1 274 to V DBV6 The sixth portion of 286 may correspond to a sixth brightness setting. G1 274 may be associated with a voltage that produces the lowest gray level (G1) using the sixth brightness setting, and V DBV6 286 may be associated with a voltage that produces a maximum gray level (G255) using a sixth brightness setting. For example, the sixth brightness setting may be 150 nits.

[0155] Fig.21 is a diagram showing an embodiment according to the present disclosure Fig. 20 A graph of gamma tap points on portions of the current-voltage curve 270 associated with various brightness settings. The first curve 300 may correspond to Fig. 20 The first portion of the current-voltage curve 270 spans from V G1 274 to V DBV1 276. The first curve 300 may correspond to a first brightness setting (eg, 50 nits). Thus, the gamma tap point for gray level 1 includes a voltage V G1 274, and the gamma tapping point for gray level 255 includes a voltage V DBV1 276 (for the first brightness setting). The reference array control circuit 89 may similarly use the first curve 300 for each gray level at the first brightness setting to associate or map the gamma tap points.

[0156] For example, the second gamma tap point 302 may be associated with a second gray level (e.g., G8) and include a second corresponding voltage 304. The third gamma tap point 306 may be associated with a third gray level (e.g., G18) and include a third corresponding voltage 308. The fourth gamma tap point 310 may be associated with a fourth gray level (e.g., G188) and include a fourth corresponding voltage 312. The fifth gamma tap point 314 may be associated with a fourth gray level (e.g., G231) and include a fifth corresponding voltage 316.

[0157] The reference array control circuit 89 can be similarly used Fig. 20The second curve 318 may correspond to other portions of the current-voltage curve 270 for other brightness settings to correlate or map the gamma tap points. Fig. 20 The sixth portion of the current-voltage curve 270 spans from V G1 274 to V DBV6 286. The second curve 318 may correspond to a second brightness setting (eg, 150 nits). Thus, the gamma tap point for gray level 1 includes a voltage V G1 274, and the gamma tapping point for gray level 255 includes a voltage V DBV6 286 (for a second brightness setting). For example, a second gamma tap point 320 may be associated with a second gray level (e.g., G8) and include a second corresponding voltage 322. A third gamma tap point 324 may be associated with a third gray level (e.g., G18) and include a third corresponding voltage 326. A fourth gamma tap point 328 may be associated with a fourth gray level (e.g., G188) and include a fourth corresponding voltage 330. A fifth gamma tap point 332 may be associated with a fourth gray level (e.g., G231) and include a fifth corresponding voltage 334. In this way, the reference array control circuit 89 may generate a gamma tap point between the data voltage and the gray level for each brightness setting of the pixel 65. It should be noted that V G1 274 may include a small range (eg, approximately 100 millivolts) of variation at different brightness settings (eg, 50 nits to 150 nits).

[0158] Fig. 22 According to an embodiment of the present disclosure, Fig.21 Flowchart of method 350 for performing grayscale tracking or gamma correction on a gamma tap point of a reference array 64. Method 350 may be performed by any suitable device or combination of devices that may convert grayscale levels into voltage values ​​and vice versa, map interpolated voltage levels to grayscale levels, compensate for voltage degradation, and apply high-frequency pulsation to grayscale levels. Although method 350 is described using a particular sequence of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in an order different from that shown, and that certain described steps may be skipped or not performed at all. In some embodiments, at least some of the steps of method 350 may be performed by a reference array control circuit 89 or a system on chip (SoC) of a reference array 64, as described below. However, it should be understood that any suitable device or combination of devices is contemplated to perform method 350, such as a control circuit for an active array 62, a processor core complex 12, or the like.

[0159] The reference array control circuit 89 may receive or determine (block 352) a set of gamma tap points. The set of gamma tap points may map data voltage values ​​to gray levels. For example, the set of gamma tap points may be defined by Fig. 20 The current-voltage curve 270 Fig.21 The set of gamma tap points may include gamma tap points for one or more brightness settings.

[0160] The reference array control circuit 89 may then convert a set of gray levels for the set of gamma tap points into a first set of voltage values ​​(block 354). Specifically, the reference array control circuit 89 may receive, determine, and / or store data voltage values ​​corresponding to the gray levels. Since there are 255 gray levels (G1 to G255), the reference array control circuit 89 may receive, determine, and / or store 255 data voltage values. The same set of gray levels as the gamma tap points may be selected for each brightness setting.

[0161] Specifically, the system on chip (SoC) of the reference array 64 can perform this step, rather than, for example, a gamma DAC which may have a larger interpolation error. This is because the gamma DAC can perform a piecewise linear gamma level to voltage level conversion, while the SoC can calculate a more accurate voltage level due to the stored current-voltage curve (e.g., 270). For example, Fig.23 360 and gamma DAC 362 according to an embodiment of the present disclosure. The graph includes two tap points 364, 366, where a curve 368 connects the two tap points 364, 366. The curve 368 can be Fig. 20 The gamma DAC 362 can generate an interpolation line 370 connecting the two tap points 364, 366. For a gray level G n 374, the gamma DAC 362 may store the interpolated data voltage V based at least in part on the interpolation line 370. n,内推 376, instead of the "real" voltage V n 378. Conversely, to generate a more accurate gamma tap point, the SoC may interpolate line 370 closer to the true voltage V n The voltage of 378 is mapped to the gray level G n 374. For example, the SoC may internalize the data voltage V m,内推 380 (the interpolated data voltage corresponds to another gray level G on the interpolated line 370) m 382) mapped to gray level G n 374, because V m,内推 380 Vn,内推 376 is closer to the real voltage V n 378.

[0162] Thus, for each respective gray level in the set of gray levels, the reference array control circuit 89 may determine (decision block 390) whether there is a linearly interpolated voltage level associated with another gray level in the set of gray levels (e.g., interpolated by the gamma DAC 362) that is closer to the voltage level of the respective gray level provided by the current-voltage curve (stored in the SoC 360) than the linearly interpolated voltage level associated with the respective gray level. The current-voltage curve may be interpolated from a set of current and voltage values ​​(e.g., with greater accuracy than linear interpolation) using various brightness settings.

[0163] If yes, the reference array control circuit 89 may map (block 392) the linear interpolation voltage level associated with the other gray level to the corresponding gray level to generate a second set of voltage values. If no, the reference array control circuit 89 may map (block 394) the linear interpolation voltage level associated with the corresponding gray level to the corresponding gray level to generate a second set of voltage values.

[0164] The reference array control circuit 89 may compensate for voltage degradation in the second set of voltage values ​​(block 396). Voltages at individual pixels, lines, connections, interconnects, buses, circuit components, etc. may vary (e.g., increase or decrease) over time and normal operation. For example, voltage degradation may be due to degradation of components over time and normal use in the active array 62. Any suitable voltage compensation technique may be used to compensate for voltage degradation in the second set of voltage values.

[0165] The reference array control circuit 89 may convert (block 398) the second set of voltage values ​​to the set of gray levels. If the reference array control circuit 89 maps the linear interpolated voltage level associated with another gray level (from block 392) to the corresponding gray level, then outputting the corresponding gray level may result in outputting the other gray level. That is, if the interpolated data voltage V m,内推 380 (the interpolated data voltage corresponds to another gray level G on the interpolated line 370) m 382) has been mapped to gray level G n 374, then output G n 374 can result in output G m 382.

[0166] The reference array control circuit 89 may then apply (block 400) dithering to the set of gray levels, thereby further reducing gray tracking or gamma errors. The dithering may be noise applied to the set of gray levels to randomize any quantization errors, and therefore undesirable patterns, such as color banding in an image. Any suitable form of dithering may be applied, such as a 4-bit dithering. The reference array control circuit 89 may program the resulting set of gray levels in the gamma DAC 362. When the brightness setting of a pixel 65 is changed, the gamma DAC 362 may be programmed with a new set of gray levels (by repeating the method of 350). In this way, the reference array control circuit 89 may program the gamma DAC 362 to a desired set of gray levels. Fig.21 The gamma tap point performs grayscale tracking or gamma correction.

[0167] To accurately sense the current across the diode (eg, 156 ) of pixel 65 , reference array control circuitry 89 may reduce and / or eliminate lateral leakage and / or bias current of pixel 65 . Fig.24 According to the embodiments of the present disclosure Figure 7 64, which shows a feature portion that reduces lateral leakage and / or bias current. As shown, the reference array 64 includes 12 columns 400 of pixels 65, each of which may have a sub-pixel 412 associated with a color (e.g., red, green, or blue). In some embodiments, each pair of columns 400 can be used for color sensing. For example, the first pair of columns 400 can be used to sense the color red, the second pair of columns 400 can be used to sense the color green, and the third pair of columns 400 can be used to sense the color blue. In alternative or additional embodiments, any suitable number of columns 400 and pixels 65 in the reference array 64 are contemplated. The reference array control circuit 89 can use the following techniques to reduce lateral leakage current (e.g., 414) and / or bias current (e.g., 416) between pixels 65. Fig.25 According to the embodiments of the present disclosure Figure 7 64 of the reference array 65. The lateral leakage current I lk 414 refers to the current that can leak to other pixels 65 when the pixel 65 is in operation (eg, emitting light). Similarly, the bias current I 偏置 ,I n，偏置 416 refers to the current that may be leaked from the pixel 65 based at least in part on the bias current of other pixels 65. Thus, when the sensing current (e.g., I 感测 250), if there is a lateral leakage current I lk 414 and / or bias current I 偏置 ,I n，偏置 416, then I 感测 250 may not be equal to the current on diode 156 (e.g., I 二极管 154). Therefore, using I感测 250 The current sensed on diode 156 may not be accurate.

[0168] See again Fig.24 , a differential sensing circuit 418 (which may include an operational amplifier 420, a capacitor 422, and a common-mode feedback circuit 424) may be used to reduce noise and / or interference between pixel columns 410 and increase dynamic range. It should be understood that the reference array 64 may include differential sensing circuits 418 between one or more columns 410 of pixels 65. In some embodiments, a pair of pixel columns 410 may be used as a reference for differential sensing of each color of the pixel 65 (e.g., one column for a power source (e.g., V DD ) of each polarity (positive, negative). In alternative or additional embodiments, correlated double sampling and / or chopping may be used to reduce leakage current, mismatch and / or offset.

[0169] Fig.26 The present invention is a method for more accurately sensing Figure 7 64. The ELVSS power source can provide a supply voltage VSSEL 434 to the two pixels 430, 432 of the reference array 64. As shown in the figure, the ELVSS power source can first provide an operating supply voltage 436 (e.g., approximately -1.6V (volts)) to the two pixels 430, 432. Providing the operating supply voltage 436 can result in an operating leakage current I lk 438. Operation bias current I 偏置 440 and the operating diode current I 二极管 442. Therefore, the sensing current (e.g., I 感测 446) can obtain the sum of the three currents (for example, I 感测 =I lk +I 偏置 +I 二极管 ).

[0170] The ELVSS power source may then provide an increased voltage 448 (eg, approximately 3V) to the two pixels 430, 432, which prevents current from flowing through the diodes (eg, LEDs) 444, 450 of the two pixels 430, 432, resulting in a leakage current I* lk 452 and bias current I* 偏置 452. Therefore, the sense current (eg, I* 感测 456) can obtain the sum of the two currents (for example, I* 感测 =I* lk +I* 偏置 ). Thus, from I 感测Subtract I* from 446 感测 456 can get more accurate I 二极管 Value (for example, I 二极管 =I 感测 –I* 感测 ). It should be noted that Fig.26 A first technique may perform double sensing or double sampling of the time in pixels 430 , 432 .

[0171] Fig. 27 The present invention is a method for more accurately sensing Figure 7 64 of the reference array 64. The second technique takes advantage of the knowledge that the current flowing into a pixel can be equal to the current flowing out of the pixel. Therefore, the diode 470 of the pixel 472 can be forced to turn off by providing a low (e.g., 0V) data voltage 474 to the diode 470, so that the current on the diode 470 is zero. The reference array control circuit 89 can then sense the current I provided by the drain power source (ELVDD) to the adjacent pixel 480 and the pixel 472, respectively. VDD1 476 and I VDD2 478. The reference array control circuit 89 can also sense the bias current I of the adjacent pixel 480 and the pixel 472, respectively. 偏置1 482 and I 偏置2 484. Since the current flowing into a pixel may be equal to the current flowing out of the pixel and the current across diode 470 is zero, the current I across diode 486 of adjacent pixel 480 may be more accurately determined by determining the difference between the sum of the current flowing into the two pixels 480, 472 and the sum of the current flowing out of the two pixels 480, 472. 二极管 486 (for example, I 二极管 =(I VDD1 +I VDD2 )–(I 偏置1 +I 偏置2 ).

[0172] Fig.28 The present invention is a method for more accurately sensing Figure 7 64. As shown, each sub-pixel 500 (corresponding to red, green, or blue) of the pixel 502 can be coupled to an ELVSS port 504, which provides a source voltage supply (VSS) to the pixel 502. The current I on each pixel 502 can be measured directly from the ELVSS port 504. 像素506. Each ELVSS port 504 can be coupled to a cathode 508. A pair of cathodes 508 can be coupled to an operational amplifier 510 and a capacitor 512. In some embodiments, the ELVSS port 504 can be coupled to a differential sensing circuit 418. In this way, the reference array control circuit 89 can more accurately sense the current on each pixel.

[0173] Fig.29 is a method for calibrating a Figure 7 Flowchart of method 520 for determining a reference array 64 of the present invention. Method 520 may be performed by any suitable device or combination of devices that can determine the peak current and data voltage associated with the gray level. Although method 520 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in an order different from the order shown, and that certain described steps may be skipped or not performed at all. In some embodiments, at least some of the steps of method 520 may be performed by reference array control circuitry 89, as described below. However, it should be understood that any suitable device or combination of devices is contemplated to perform method 520, such as control circuitry for active array 62, processor core complex 12, etc.

[0174] The reference array control circuit 89 may select (block 522) a brightness setting for one or more pixels. For example, the reference array control circuit 89 may select a maximum brightness setting (eg, 150 nits, 750 nits, etc.) for the one or more pixels.

[0175] The reference array control circuit 89 may then determine (block 524) a peak current for the one or more pixels. Specifically, the peak current may be associated with the current provided to the one or more pixels that causes the gray level 255 to be displayed or emitted. In some embodiments, the reference array control circuit 89 may estimate the peak current and perform optical measurements on the one or more pixels to determine whether the one or more pixels are emitting G255 within a certain threshold. If not, the reference array control circuit 89 may adjust the estimated peak current until the one or more pixels emit G255.

[0176] The reference array control circuit 89 may determine (process block 526) a set of data voltages associated with a set of gray levels for each brightness setting based at least in part on the peak current. Specifically, for each gray level (G1 to G255) of each brightness setting, the reference array control circuit 89 may estimate the data voltage that emits the gray level at the brightness setting, and perform optical measurements on the one or more pixels to determine whether the one or more pixels are emitting the gray level within a certain threshold. The reference array control circuit 89 may estimate the data voltage based at least in part on the current-voltage curve and the peak current determined and / or stored by the reference array 64. Specifically, the reference array control circuit 89 may determine a portion of the current-voltage curve associated with each brightness setting based at least in part on the peak current. If the one or more pixels are not emitting the gray level within a certain threshold, the reference array control circuit 89 may adjust the estimated data voltage until the one or more pixels emit the gray level. In this way, the reference array 64 may be calibrated to obtain better performance.

[0177] Fig.30 5 is a timing diagram illustrating the operation of the reference array 64 according to an embodiment of the present disclosure. As shown, when the brightness setting 540 (e.g., display brightness value (DBV)) changes (e.g., from DBV1 to DBV2, to DBV3, to DBV4), the ELVSS voltage value 542 (e.g., ELVSS0) remains constant. In addition, calculating the gamma or gray level 544 corresponding to changing the brightness setting 540 of the reference array 64 may include a delay of one frame 546 of time. Once the gamma level 544 has been calculated, the active array 62 may use the gamma level 544 (as shown in 548) to display and / or transmit image data.

[0178] Additionally, when the temperature 550 of the electronic display 18 reaches a certain threshold 552, the reference array control circuit 89 may change the ELVSS voltage value 542 (e.g., to ELVSS1) after the sensing operation 554. Because the ELVSS voltage supplies of the reference array 64 and the active array 62 are separate, the ELVSS power supply of the reference array 64 may be adjusted without affecting the emission of the active array 62. The active array 62 may synchronize updating its gamma level 548 (e.g., to a gamma level associated with ELVSS1) with the reference array control circuit 89 updating its ELVSS power supply 542. Similarly, the active array 62 may synchronize updating its ELVSS power supply level with the reference array control circuit 89 updating its ELVSS power supply 542.

[0179] Current-voltage sensing in active arrays

[0180] The pixel emits a certain light, gamma, or grayscale level based at least in part on the amount of current supplied to the diode (e.g., LED) of the pixel. For voltage-driven pixels, a target voltage may be applied to the pixel so that a target current is applied to the diode (e.g., as represented by a current-voltage relationship or curve) to emit a target gamma value. Changes (e.g., caused by temperature, aging of the pixel, etc.) may affect the pixel by, for example, changing the resulting current applied to the diode when the target voltage is applied. These changes may be the result of pixel degradation and may affect multiple pixels of the display such that non-uniformity between pixels may cause visual artifacts without proper compensation.

[0181] Accurately sensing the current across the diode can more accurately identify when changes affect the pixel. Fig.31 is a block diagram of a system 570 that performs current-voltage sensing according to an embodiment of the present disclosure. The system 570 includes a display 18 having a reference array 64 and an active array 62. The active array 62 may include a digital-to-analog converter 572, one or more pixels 574, and a sensing and / or prediction circuit 576. The sensing and / or prediction circuit 576 may sense or predict a shift in a current-voltage relationship or curve. The remainder of the present disclosure discusses the use of the sensing circuit 576 to sense the current-voltage relationship or curve. However, it should be understood that a prediction circuit that performs prediction-based tracking based at least in part on sensing data collection is contemplated.

[0182] In some embodiments, the sensing circuit 576 can periodically (e.g., approximately once every two weeks) perform sensing operations on the one or more pixels 574 of the active array 62. In additional or alternative embodiments, the sensing operations can be performed during "off time" (e.g., when the electronic device 10 is not in use, when the electronic device is powered on but not in use, at certain times associated with non-operation, etc.). The reference array 64 can also include a digital-to-analog converter 577, one or more pixels 578, and sensing and / or prediction circuitry 579.

[0183] After performing the sensing operation, the buffer 580 of the timing controller 581 may store the results of the sensing operation (e.g., current-voltage characteristics, values, measurements, etc.) for a suitable period of time (e.g., approximately two weeks). The timing controller 581 may be a component of the processor core complex 12, the display 18, or the electronic device 10. The results of the sensing operation may then be sent to and stored in a lookup table 582 of the processor core complex 12 (e.g., a system on a chip). The lookup table 582 may also store the current-voltage characteristics, values, measurements, etc. of the one or more pixels 578 of the reference array 64 (e.g., received from the sensing circuit 579 of the reference array 64). The voltage comparator circuit 584 may determine the amount of voltage to be corrected for the one or more pixels 574 of the active array 62 (based at least in part on the previous results of the sensing operation stored in the lookup table 582 and the current-voltage characteristics of the pixels of the reference array 64). The current-voltage compensation circuit 586 may then generate a current-voltage curve based at least in part on the voltage amount to be corrected (e.g., for one or more pixels 574), and drive the corresponding pixel 574 via the digital-to-analog converter 572 based at least in part on the current-voltage curve. Fig.31 The arrows in indicate a current-voltage sensing and compensation pipeline 588 , which illustrates the flow of current and voltage data in the system 570 for sensing and compensation purposes.

[0184] Fig.32 According to the embodiments of the present disclosure, Figure 7 A graph of a current-voltage curve 590 for a pixel (e.g., 574) of a display 18 of FIG. 50 may be displayed after operating the display 18 or pixel 574 for an N amount of time at a certain time T. N The current-voltage curve 590 is generated at T. N Two (or more) current-voltage values ​​592, 594 may be determined or sensed at the display 18, and the voltage comparator circuit 584 may interpolate the two current-voltage values ​​to generate the current-voltage curve 590. A reference current-voltage curve 596 may also be generated by the control circuitry of the reference array of the display 18. The reference current-voltage curve 596 may represent a “raw” version of the current-voltage curve 590 because the operating frequency of the reference array may be lower than or minimized (e.g., and thus experience less aging) than the active array of the display 18, but the operating temperature may be similar to the active array.

[0185] As shown, ΔV1 598 indicates the difference in data voltage according to current-voltage curve 590 and reference current-voltage curve 596 to generate target current I1 602 at the diode of pixel 574. Similarly, ΔV2 600 indicates the difference in data voltage according to current-voltage curve 590 and reference current-voltage curve 596 to generate target current I2 604 at the diode.

[0186] Fig.33 According to the embodiments of the present disclosure Figure 7 The display 18 at different times T0 to T N The display includes an active array 62, which can be programmed to display image data, and a reference array 64, which can be an original copy of the active array 62. N At , the control and / or sensing circuitry of the reference array 64 may sense a set (e.g., eight pairs) of current-voltage values ​​624 (e.g., associated with currents I1 to I8), which may be sent, for example, to the processor core complex 12 for storage in the lookup table 582. At the same time, the sensing circuitry 576 of the active array 62 may sense a set (e.g., two pairs) of current-voltage values ​​626 for each pixel (I, J) 628 of the active array 62, which may be sent, for example, to the processor core complex 12 for storage in the lookup table 582. The set of current-voltage values ​​626 sensed by the sensing circuitry 576 of the active array 62 may be associated with I1, I2, and / or V 数据1 、V 数据2 That is, in some embodiments, the set of current-voltage values ​​626 may include I1 and I2 (of the set of current-voltage values ​​sensed by the sensing circuit of the reference array 64) and the data voltages that produce I1 and I2 at each pixel (I, J) 628 of the active array 62. In alternative or additional embodiments, the set of current-voltage values ​​626 may include V 数据1 and V 数据2 (The V 数据1 and V 数据2 I1 and I2) and V are generated in the reference array 64 数据1 and V 数据2 The resulting current produced at each pixel (I, J) 628 of the active array 62 .

[0187] The voltage comparator circuit 584 of the processor core complex 12 may generate each current-voltage curve 590 and a reference current-voltage curve 596 for each pixel I,J 628 of the active array, and compare 630 the corresponding current-voltage curve 590 with the reference current-voltage curve 596. The voltage comparator circuit 584 may then determine a voltage difference 632 between the corresponding current-voltage curve 590 and the reference current-voltage curve 596 for correction for each pixel 628. The current-voltage compensation circuit 586 may then generate a compensated current-voltage curve for each pixel 628 based at least in part on the voltage difference 632, and drive the corresponding pixel 628 via the digital-to-analog converter 572.

[0188] Fig.34 According to the embodiments of the present disclosure, Figure 7 Schematic diagram of a current and voltage sensing system 640 for a display 18 of FIG. The system 640 includes a sensing and compensation pipeline 588 that can sense, determine, and / or receive gamma and / or grayscale information 642 of a reference array 64 (e.g., based at least in part on current and voltage values ​​and / or current-voltage curves). The sensing and compensation pipeline 588 can also sense, determine, and / or receive current and voltage values ​​for each pixel (e.g., 644, 646) of the active array 62 from a power source (e.g., ELVDD) wiring 648 via a sensing analog front end (AFE) 650. As shown, when the active array 62 is in normal operation (e.g., displaying image data), the ELVDD wiring 648 can couple the VDD supply line 652 of each pixel 644, 646 to the ELVDD power source 654. When the active array 62 is performing a sensing operation, the switch 656 of the sensing AFE 650 may couple the VDD supply line 652 of each pixel 644 , 646 to the sensing AFE 650 .

[0189] After performing the sensing of the gamma information 642 and the current and voltage values ​​of each pixel (e.g., 644, 646), the voltage comparator circuit 584 can generate a voltage difference based at least in part on the gamma information 642 and the current and voltage values. The current-voltage compensation circuit 586 can then generate a set of data voltages 664 to compensate for the voltage difference, which can be applied to each pixel by one or more column drivers 666.

[0190] Additionally, temperature and / or brightness variations may enable overall ELVSS power source 668 adjustments followed by gamma point sensing. As shown, current and voltage sensing system 640 may be applied to different types of pixels, such as pixel 658. Although current and voltage sensing system 640 is shown using an ELVDD power source to sense current and voltage values, it should be noted that any suitable alternative or additional power source (e.g., ELVSS 662) is contemplated for use.

[0191] When sensing current across diodes 670 (e.g., LEDs, OLEDs, etc.) in pixels 644, 646 of the active array 62 and / or pixels of the reference array 64, data retention may be inconsistent. Specifically, when programming pixels 644, 646, current may leak from the gate or metal oxide semiconductor 672 that provides the data voltage, which in turn may cause the voltage in the storage capacitor 674 to leak or drop. This may cause different amounts or average values ​​of current across diodes 670 during operation of pixels 644, 646 (e.g., when sensing current across diodes of reference array 64, sensing current across diodes 670 of pixels 644, 646 of active array 64, and using diodes 670 of pixels 644, 646 of active array 64 to display image data), thereby causing inconsistent data retention and thus affecting accurate current sensing (e.g., across diodes 670) of pixels 644, 646.

[0192] Additionally, due to the close proximity of pixels (e.g., in active array 62 and / or reference array 64), attempting to sense or determine the current in a pixel (or across a diode of a pixel) may include sensing or receiving current that leaks from one pixel to another (e.g., lateral leakage current). Furthermore, bias current may also be a source of error when sensing or determining the current in a pixel.

[0193] 1. Maintain data retention

[0194] To maintain data retention, the gate or metal oxide semiconductor providing the data voltage of each pixel of the reference array 64 may provide the data voltage when performing a sensing operation. Similarly, the gate or metal oxide semiconductor providing the data voltage of each pixel of the active array 62 (e.g., 672) may provide the data voltage when performing a sensing operation. The average currents in the pixels of the corresponding arrays may be similar. The difference between the average currents in the pixels of the corresponding arrays may be determined, and the difference may be applied to the normal operation of the active array 62 (e.g., displaying image data). Specifically, the difference between the average currents in the pixels of the corresponding arrays may be captured by optical calibration (e.g., by a manufacturer, in a factory manufacturing the display 18, etc.). The optical calibration may capture the difference between continuously driving the pixels (e.g., of the active array 62) and driving the pixels by sampling and holding (e.g., driving a target time such as 2 milliseconds, and allowing current to leak from the pixels).

[0195] Fig.35 According to an embodiment of the present disclosure, a method for reducing data retention to more accurately sense Figure 7 68. A set of timing diagrams for current in pixels of display 18 of FIG. 68 is shown. A first timing diagram 680 shows that a data voltage is directly driven (e.g., maintained) at the gate of a pixel of reference array 64 for approximately 300 microseconds, and thus a first current 682 is provided on the diode of the pixel. A second timing diagram 684 shows that a data voltage is directly driven (e.g., maintained) at the gate of a pixel of active array 62 (e.g., when performing a sensing operation) for approximately 1 to 2 milliseconds, and thus a first current 682 is provided on the diode of the pixel. A third timing diagram 686 shows that a data voltage is sampled and maintained at the gate of a pixel of active array 62 (e.g., when performing a normal display operation) for approximately 2 milliseconds, and current is allowed to leak from the pixel, and thus a second average current 688 is provided on the diode of the pixel.

[0196] Fig.36 is a diagram showing a method of reducing data retention before performing compensation to more accurately sense the Figure 7 18. The first current-voltage curve 702 shows the data voltage V driven directly at the gate of the pixel of the reference array 64 at the initial time T0 of the operation of the display 18. 数据 Specifically, the first current-voltage curve 702 indicates that the target current I is provided at the first data voltage 706. 目标 704. A second current-voltage curve 708 shows sampling and holding the data voltage at the gate of the pixel of the active array 62 (e.g., when performing normal display operation). The second current-voltage curve 708 indicates that before the optical calibration 712, the first data voltage 706 is provided with a current less than the target current I 目标704, and after optical calibration 712, provides a target current I at a second data voltage 714. 目标 704.

[0197] Fig.37 is a diagram showing a method of reducing data retention after performing compensation to more accurately sense the Figure 7 18. The first current-voltage curve 702 shows the data voltage V driven directly at the gate of the pixel of the reference array 64 at the initial time T0 of the operation of the display 18. 数据 Specifically, the first current-voltage curve 702 indicates that the target current I is provided at the first data voltage 706. 目标 704. A second current-voltage curve 722 shows the data voltage V driven directly at the gate of the pixel of the active array 62 during the off-time sensing of the current and voltage. 数据 The second current-voltage curve 722 indicates that the current I is less than the target current I provided at the first data voltage 706. 目标 704, and the difference in the compensated data voltage 726 between the first current-voltage curve 702 and the second current-voltage curve 722 after calibration 712. The third current-voltage curve 728 shows sampling and holding the data voltage at the gate of the pixel of the active array 62 after compensation and calibration (for example, when performing normal display operation). That is, in addition to calibrating by capturing the difference between continuously driving the pixel of the active array 62 and driving the pixel by sampling and holding, the third current-voltage curve 728 is generated based at least in part on the sensed current-voltage characteristic and the compensation voltage degradation. Therefore, the third current-voltage curve 728 indicates that the target current I is provided at the second data voltage 730. 目标 704.

[0198] 2. Reduce lateral leakage and / or bias current

[0199] Due to the close proximity of pixels and sub-pixels (e.g., in active array 62 and / or reference array 64), attempting to sense or determine the current in a pixel or sub-pixel (or across a diode of a pixel or sub-pixel) may include sensing or receiving current that leaks from one pixel or sub-pixel to another pixel or sub-pixel (e.g., lateral leakage current). Fig.38 According to the embodiments of the present disclosure Figure 718. Pixel 740 may be included in active array 62 or reference array 64. Pixel 740 may include sub-pixels, such as red sub-pixel 742, green sub-pixel 744, blue sub-pixel 746, etc. It should be noted that references to pixels (e.g., 740) in this disclosure may equally apply to sub-pixels (e.g., 742, 744, 746), and vice versa.

[0200] When sensing the current in a pixel or subpixel, the surrounding pixels or subpixels may be turned off or programmed to zero. For example, when sensing the current in the red subpixel 742, the surrounding subpixels 744, 746 may be turned off. If the lateral leakage current from the red subpixel 742 is not reduced or decreased, a voltage difference may be generated between the anode of the red subpixel 742 and the anodes of the surrounding subpixels 744, 746. Since there may be a finite impedance between the red subpixel 742 and the surrounding subpixels 744, 746, there may be leakage current from the anode of the red subpixel 742 and the anodes of the surrounding subpixels 744, 746. Since the current may be sensed from the "top" side 748 (e.g., from a power source located at the top, such as an ELVDD power source coupled to the drain of the TFT of the subpixel 742), the resulting sensed current may include not only the current on the diode of the subpixel 742, but also the leakage current.

[0201] Fig.39 is a diagram showing a method for reducing the Figure 7 18 of the display 18. The digital-to-analog converter 572 can drive the adjacent sub-pixel so that the voltage of the anode 760 of the adjacent sub-pixel (e.g., V 阳极，相邻 ) can be connected to the voltage of the anode 762 of the sub-pixel 742 (eg, V 阳极 ) without turning off the adjacent subpixel (e.g., 744) or programming the adjacent subpixel to zero. In some implementations, the digital-to-analog converter 572 can drive the current in the adjacent subpixel so that the resulting voltage (e.g., V 阳极，相邻 ) can be connected to the voltage of the anode 762 of the sub-pixel 742 (eg, V 阳极 ) are substantially matched. This can result in the sub-pixel 742 and the adjacent sub-pixel 744 having the same potential, thereby reducing, minimizing and / or reducing current leakage 764 from the sub-pixel 742 to the adjacent sub-pixel 744. In some embodiments, in order to control the V of the anode 760 of the adjacent sub-pixel 阳极，相邻 To control the voltage or current, each column of pixels or sub-pixels may include a dedicated power source (e.g., coupled to ELVDD power source 748) line 766.

[0202] Fig.40 is a diagram showing an embodiment of the present disclosure for considering Figure 7 A circuit diagram of a second technique for determining leakage and bias currents of a sub-pixel 742 of a display 18 flowing to an adjacent sub-pixel (e.g., 744). The second technique is similar to that of FIG. Fig.26 The technique described for the pixel of reference array 64 in FIG. As shown, a data voltage 781 of 0V may be applied to the adjacent sub-pixel 744, while a data voltage V may be applied to the sub-pixel 742. 数据 782. The ELVSS power source 780 may first provide an operating supply voltage 783 (eg, approximately -1.6V (volts)) to the two sub-pixels 742 and 744. Providing the operating supply voltage 783 may result in an operating leakage current I on the diode 790 of the sub-pixel 744. lk 784, Operation bias current I 偏置 786 and the operating diode current I 二极管 788. Therefore, the sensing current (e.g., I 感测 790) can obtain the sum of the three currents (for example, I 感测 =I lk +I 偏置 +I 二极管 ).

[0203] The ELVSS power source 780 may then provide an increased voltage 792 (eg, approximately 3 V) to the two sub-pixels 742, 744, causing the diodes 790, 794 of the sub-pixels 744, 742 to be reverse biased and prevent current from flowing through the diodes 790, 794, resulting in a leakage current I* lk 796 and bias current I* 偏置 798. Therefore, the sensing current (e.g., I* 感测 800) can obtain the sum of the two currents (for example, I* 感测 =I* lk +I* 偏置 ). Thus, from I 感测 Subtract I* from 790 感测 800 can get more accurate I 二极管 Value (for example, I 二极管 =I 感测 –I* 感测 ). The increased voltage 792 may be based at least in part on the temperature and generated by the control circuit of the reference array 64. For example, the reference array control circuit may generate the increased voltage 792 so that the maximum voltage applied to the pixels of the reference array 64, given the increased voltage 792, may achieve the target brightness. It should be noted that Fig.40A second technique may double sense or double sample the time in sub-pixels 742, 744. In some embodiments, the ELVSS power source 780 may instead provide an increased current to both sub-pixels 742, 744, such that the diodes 790, 794 of the sub-pixels 744, 742 are reverse biased and current is prevented from flowing through the diodes 790, 794, resulting in a leakage current I* lk 796 and bias current I* 偏置 798. With respect to the increased voltage 792 above, the sense current (eg, I* 感测 800) can get the sum of the two currents (I* 感测 =I* lk +I* 偏置 ). Thus, from I 感测 Subtract I* from 790 感测 800 can get more accurate I 二极管 Value (for example, I 二极管 =I 感测 –I* 感测 ). The increased current may be based at least in part on temperature and generated by control circuitry of reference array 64.

[0204] Fig.41 According to the embodiments of the present disclosure, Figure 7 Flowchart of method 801 for determining leakage and bias current flowing from a pixel of display 18 to an adjacent pixel. Method 801 may be performed by any suitable device or combination of devices that may supply a voltage to a pixel, supply an ELVSS voltage level or current level to the pixel (e.g., via an ELVSS power source coupled to the source of the pixel's thin film transistor), determine the current in the pixel, and drive the pixel. Although method 801 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in an order different from that shown, and that certain described steps may be skipped or not performed at all. In some embodiments, at least some of the steps of method 801 may be performed by processor core complex 12, as described below. However, it should be understood that any suitable device or combination of devices is contemplated for performing method 801, such as Fig.31 The digital-to-analog converter 572, the sensing circuit 576, the ELVSS power source 780, the display 18, etc.

[0205] The processor core complex 12 supplies a first data voltage to a pixel (block 802). Fig.40 As shown, the processor core complex 12 can instruct the digital-to-analog converter 572 to supply the data voltage V to the pixel 744. 数据782. The processor core complex 12 also supplies a zero data voltage to an adjacent pixel (eg, a pixel adjacent to the pixel) (block 803). Fig.40 As shown, the processor core complex 12 may instruct the digital-to-analog converter 572 to supply 0V 781 to the adjacent pixel 742 .

[0206] The processor core complex 12 supplies (block 804) an operating ELVSS supply voltage or current to the pixel and adjacent pixels. Fig.40 As shown, the processor core complex 12 may instruct the ELVSS power source 780 to provide an operating supply voltage 783 (eg, approximately −1.6 V (volts)) or current to the two pixels 742 , 744 .

[0207] The processor core complex 12 then determines (block 805) a first current in the pixel. Fig.40 As shown, the processor core complex 12 may instruct the sensing circuit 576 to determine a first current, which may include an operating leakage current I lk 784, Operation bias current I 偏置 786 and the operating diode current I on the diode 790 of the pixel 744 二极管 788. Thus, the sensing circuit 576 can determine the first current (eg, I 感测 790) is the sum of the three currents (e.g., I 感测 =I lk +I 偏置 +I 二极管 ).

[0208] The processor core complex 12 supplies (block 806) the increased ELVSS supply voltage or current to the pixel and adjacent pixels. Fig.40 As shown, the processor core complex 12 may instruct the ELVSS power source 780 to provide an increased ELVSS supply voltage 792 (e.g., approximately 3V) to the two pixels 742, 744. The increased ELVSS supply voltage 792 may cause the diodes 790, 794 of the pixels 744, 742 to be reverse biased, thereby stopping the current from flowing through the diodes 790, 794. In some embodiments, the ELVSS power source 780 may provide an increased current to the two pixels 742, 744, thereby causing the diodes 790, 794 of the pixels 744, 742 to be reverse biased, thereby stopping the current from flowing through the diodes 790, 794.

[0209] The processor core complex 12 then determines (block 807) a second current in the pixel. Fig.40As shown, the processor core complex 12 may instruct the sensing circuit 576 to determine a second current, which may include a leakage current I* lk 796 and bias current I* 偏置 798. Thus, the sensing circuit 576 can determine the second current (eg, I*) in the pixel 742. 感测 800) is the sum of the two currents (e.g., I* 感测 =I* lk +I* 偏置 ).

[0210] The processor core complex 12 then drives (block 808) the pixel 742 based at least in part on the first current and the second current. For example, the processor core complex 12 may instruct the digital-to-analog converter 572 to drive the pixel 742 based at least in part on the first current and the second current. Specifically, from I 感测 Subtract I* from 790 感测 800 can get a more accurate current value I on the diode 二极管 (For example, I 二极管 =I 感测 –I* 感测 ). The processor core complex 12 can store the data voltage V on the diode. 数据 The current sensed on the diode for the other data voltage, and the corresponding data voltage in the buffer 580. After a certain amount of time (e.g., approximately two weeks), these current and voltage values ​​can be sent from the buffer 580 to the lookup table 582. The voltage comparator circuit 584 can generate a current-voltage curve for the pixel 744 based at least in part on the current and voltage values, and compare the current-voltage curve with another current-voltage curve generated by the reference array control circuit. The voltage comparator circuit 584 can generate a set of voltage differences based at least in part on this comparison, and the current-voltage compensation circuit 586 can instruct the digital-to-analog converter 572 to drive the pixel 744 based at least in part on the set of voltage differences (to compensate for the set of voltage differences).

[0211] In some embodiments, the current step limiter circuit 72 of the active array control circuit 85 can limit the current compensation value corresponding to the set of voltage differences. Specifically, the current step limiter circuit 72 can be used to limit the current compensation value corresponding to the set of voltage differences to below a visibility threshold. The visibility threshold can correspond to a change in current value that may not be perceived by an observer of the display 18 when applied to drive the pixel 744 (compared to driving the pixel 744 before applying the current compensation value). In this way, the observer may not notice the applied compensation, thereby improving the overall viewing experience of the display 18.

[0212] Fig.42 and Fig.43 is a circuit diagram further illustrating a second technique for accounting for leakage and bias currents flowing from a pixel 810 to a plurality of adjacent pixels 812 according to an embodiment of the present disclosure. Fig.42 is a diagram showing the determination according to an embodiment of the present disclosure Figure 7 18 of the display 18. Specifically, the ELVSS power source provides an operating supply voltage 814 (e.g., approximately -1.6V) or current to the pixel 810 and the adjacent pixel 812. As shown, the diode 816 of the pixel 810 can be supplied with a data voltage VX 818, which causes the diode 816 to emit a gray level GX 820. The diode 822 of the adjacent pixel 812 can be supplied with a data voltage V0 824, which causes the diode 822 to emit a gray level G0 826. This can generate a leakage current I lk-L 828、I lk-Y 830 and I lk-H 832, bias current I 偏置 834, and the diode current I 二极管 836. Therefore, the current (e.g., I 感测 ) can be used to obtain the sum of the three types of current (for example, I 感测 =I lk-L +I lk-Y +I lk-H +I 偏置 +I 二极管 ).

[0213] Fig.43 is a diagram showing the determination according to an embodiment of the present disclosure Figure 7 18. Specifically, the ELVSS power source can provide an increased voltage 850 (e.g., approximately 3V) or current to the pixel 810 and the adjacent pixel 812, so that the diodes 816 and 822 of the pixel 810 and the adjacent pixel 812 are reverse biased and prevent the current from flowing through the diodes 816 and 822, thereby generating a leakage current I lk-L 828、I lk-Y 830 and I lk-H 832 and bias current I 偏置 834. Therefore, the sensed current (eg, I* 感测 ) can be used to obtain the sum of the two types of current (for example, I* 感测 =I lk-L +I lk-Y +I lk-H +I 偏置 ). Thus, from I 感测 (From Fig.42 ) minus I* 感测 A more accurate I 二极管 Value (for example, I 二极管 =I 感测 –I* 感测 ).

[0214] Fig.44 and Fig.45 is a circuit diagram illustrating elimination of common-mode leakage using a second technique for accounting for leakage and bias current flowing from a pixel 810 to a plurality of adjacent pixels 812 in accordance with an embodiment of the present disclosure. Fig.44 is a diagram showing the embodiment according to the present disclosure. Figure 7 18 is a circuit diagram for eliminating common-mode leakage when providing an operating supply voltage 814 in a display 18 of FIG. Specifically, the ELVSS power source provides an operating supply voltage 814 (e.g., approximately -1.6V) to the pixel 810 and the adjacent pixel 812. The pixels 810, 812 may be coupled to a common-mode amplifier 860 and a sense amplifier 862 (e.g., a differential sense amplifier such as the sensing analog front end 66). When differential sensing is performed, the currents in the positive branch 864 and the negative branch 866 of the common-mode amplifier 860 and the sense amplifier 862 may include a large common-mode signal in terms of bias current. The common-mode amplifier 860 may eliminate or absorb the common-mode signal so that the remaining differential signal may be received at the sense amplifier 862.

[0215] For example, the current in the positive branch 864 may include a corresponding leakage current I lk-L 828、I lk-Y 830、I lk-H 832 and I lk-V 868, bias current I 偏置 834, and the diode current I 二极管 836 (e.g., I lk-L +I lk-Y +I lk-H +I lk-V +I 偏置 +I 二极管 ). The current in the negative branch 866 may include the corresponding leakage current I lk-L' 870、I lk-Y' 872、I lk-H 832 and I lk-V' 874, and the bias current I 偏置 834 (e.g., I lk-L' +I lk-Y' –I lk-H +I lk-V +I 偏置Passing the current in the positive branch 864 through the common-mode amplifier 860 may result in the cancellation of the common-mode signal 876 (eg, I lk-L +I lk-Y +I lk-V +I 偏置 +(I 二极管 +ΔI lk-L +ΔI lk-Y +ΔI lk-V ) / 2)), so that the remaining differential signal 878 (e.g., (I 二极管 +ΔI lk-L +ΔI lk-Y +ΔI lk-V ) / 2+I lk-H Similarly, passing the current in the negative branch 866 through the common-mode amplifier 860 may result in the cancellation of the common-mode signal 880 (eg, I lk-L +I lk-Y +I lk-V +I 偏置 +(I 二极管 +ΔI lk-L +ΔI lk-Y +ΔI lk-V ) / 2)), so that the remaining differential signal 882 (e.g., (I 二极管 +ΔI lk-L +ΔI lk-Y +ΔI lk-V ) / 2–I lk-H ). Therefore, the total current 884 received at the sense amplifier 862 via the differential signals 878 and 882 may be I 二极管 +ΔI lk-L +ΔI lk-Y +ΔI lk-V +2*I lk-H .

[0216] Fig.45 is a diagram showing the embodiment according to the present disclosure. Figure 7 18. Specifically, the ELVSS power source provides an increased supply voltage 850 (eg, approximately 3V) to the pixel 810 and the adjacent pixel 812. The current in the positive branch 864 may include a corresponding leakage current I lk-L 828、I lk-Y 830、I lk-H 832 and I lk-V 868, and the bias current I 偏置 834 (e.g., I lk-L +I lk-Y +Ilk-H +I lk-V +I 偏置 ). The current in the negative branch 866 may include the corresponding leakage current I lk-L' 870、I lk-Y' 872、I lk-H 832 and I lk-V' 874, and the bias current I 偏置 834 (e.g., I lk-L' +I lk-Y' –I lk-H +I lk-V +I 偏置 Passing the current in the positive branch 864 through the common-mode amplifier 860 may result in the cancellation of the common-mode signal 900 (eg, I lk-L +I lk-Y +I lk-V +I 偏置 +(ΔI lk-L +ΔI lk-Y +ΔI lk-V ) / 2)), so that the remaining differential signal 902 (eg, (ΔI lk-L +ΔI lk-Y +ΔI lk-V ) / 2+I lk-H Similarly, passing the current in the negative branch 866 through the common-mode amplifier 860 may result in the cancellation of the common-mode signal 904 (eg, I lk-L +I lk-Y +I lk-V +I 偏置 +(ΔI lk-L +ΔI lk-Y +ΔI lk-V ) / 2)), so that the remaining differential signal 906 (eg, (ΔI lk-L +ΔI lk-Y +ΔI lk-V ) / 2–I lk-H ). Therefore, the total current 908 received at the sense amplifier 862 via the differential signals 878 and 882 may be ΔI lk-L +ΔI lk-Y +ΔI lk-V +2*I lk-H Thus, the difference between the total current 884 received at the sense amplifier 862 when the operating supply voltage 814 is provided to the pixels 810, 812 and the total current 908 received at the sense amplifier 862 when the increased supply voltage 850 is provided to the pixels 810, 812 may be I 二极管 (For example, (I 二极管 +ΔIlk-L +ΔI lk-Y +ΔI lk-V +2*I lk-H )–(ΔI lk-L +ΔI lk-Y +ΔI lk-V +2*I lk-H )).

[0217] As shown in the figure, according to the embodiment of the present disclosure, Figure 42 to Figure 45 The pixels 810 and 812 in the circuit diagram of FIG. 8 may be source follower pixels, such as Fig.46 909. However, the present disclosure may include any suitable type of pixel according to an embodiment of the present disclosure, such as Fig.47 The circuit diagram of the class A amplifier pixel 910 shown in FIG. Fig.48 The circuit diagram of the class AB amplifier pixel 911 is shown.

[0218] In which the pixel includes the top current source 912 (at data voltage V 数据 913 line) and the bottom current source 914 (at the data voltage V 数据 913 line) in an embodiment such as using a class AB amplifier pixel 911 (or a class B amplifier pixel), Figure 42 to Figure 45 The circuit diagram of FIG. 1 can sense the current from the topmost current source 912 but not the bottommost current source 914. This is because the sense amplifier (e.g., Fig.44 862) may be coupled to the topmost current source 912 instead of the bottommost current source 914. Therefore, the sense amplifier 862 may not be able to compensate for or reduce the noise generated from the bottommost current source 914 because the current and noise generated by the bottommost current source 914 may not be measured.

[0219] Fig.49 is a diagram showing the reduction of the Fig.48 The circuit diagram of the noise of the AB class amplifier pixel 911. Fig.44 For the circuit diagram of FIG. 1 , there is a topmost sense amplifier 915 coupled to a topmost current source 912 of each of the class AB amplifier pixels 911 . Fig.49 The circuit diagram of FIG. 1 also includes a bottommost sense amplifier 916 coupled to a bottommost current source 914 of each of the class AB amplifier pixels 911. By receiving a data voltage V 数据Sensing on both sides of line 913, sense amplifiers 915, 916 can be useful to reduce or minimize noise from current sources 912, 914, because the noise from each class AB amplifier pixel 911 may be correlated.

[0220] For example, the diode 917 of one class AB amplifier pixel 911 may be forced off by providing a low (e.g., 0V) data voltage 913 to the diode 917 so that the current across the diode 917 is zero. Thus, the current I1 918 across the corresponding pixel 911 may include noise from the corresponding current source 912 but not the current across the diode 917. The diode 919 of another class AB amplifier pixel 911 may be operable so that the current across the diode 919 is non-zero. Thus, the current I2 920 across the corresponding pixel 911 may include both the current across the diode 919 and the noise from the corresponding current source 914. Subtracting the current I1 918 from the current I2 920 may provide an accurate measurement or estimate of the current across the diode 919. In fact, in some embodiments, reducing or reducing the noise from the current sources 912, 914 in this manner may extend the signal-to-noise ratio in the current supplied from the current sources 912, 914 by 20 dB to 70 dB (e.g., up to 55 dB) per pixel.

[0221] Advantageously, sense amplifiers 915, 916 can accurately sense the current in class AB amplifier pixel 911 even when the bias conditions in class AB amplifier pixel 911 change, such as when the power supplied by ELVSS power source 921 changes. Furthermore, the outputs of sense amplifiers 915, 916 can be added at the inputs of existing analog-to-digital converters (e.g., 152) without adding an additional analog-to-digital converter 152 to the circuit.

[0222] However, due to non-ideal differences between pixels 911, such as manufacturing defects, in some cases, subtracting the current I1 918 on the first pixel 911 from the current I2 920 on the second pixel 911 may not provide an accurate measurement or estimate of the current on the diode 919. In fact, even if the same amount of voltage may be supplied to the two pixels 911, the current values ​​on the corresponding diodes 917, 919 may be different. Therefore, subtracting the current I1 918 on the first pixel 911 from the current I2 920 on the second pixel 911 may not only produce the current on the diode 919, but also produce an additional current value due to the non-ideal differences between pixels 911, which may be referred to as a bias mismatch current (between the two pixels 911).

[0223] Therefore, to accurately determine the current on the diode 919 , the bias mismatch current may be subtracted from the difference between the current I1 918 on the first pixel 911 and the current I2 920 on the second pixel 911 . Fig.50 15 is a circuit diagram illustrating determining the bias mismatch current between two pixels 1500 according to an embodiment of the present disclosure. To determine the bias mismatch current, the signal current 1502 may be disabled (e.g., by pushing a cutoff voltage such as the voltage supplied by the ELVSS power source 1504 high) so that no current flows through the diode 1506. Thus, the current measured by the sense amplifier 1508 is the current through the transistor of the pixel 1500—that is, the bias current ( Fig.26 440)—rather than the current through diode 1506. The difference between these bias currents is the bias mismatch current, as measured by sense amplifier 1508. The side transistor 1510 of the circuit diagram can reduce or eliminate the bias mismatch current, thereby enabling a more accurate determination of the current through diode 1506.

[0224] Fig.51 15 is a flow chart of a method 1520 for determining a current through a diode (eg, 1506) according to an embodiment of the present disclosure. Specifically, the method 1520 may use Fig.50 In some embodiments, the diode may be a Fig.48 14. Although method 1520 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the steps described may be performed in an order different from that shown, and that certain steps described may be skipped or not performed at all. In some embodiments, at least some of the steps of method 1520 may be performed by processor core complex 12, as described below. However, it should be understood that any suitable device or combination of devices is contemplated for performing method 1520, such as Fig.31 The digital-to-analog converter 572, the sensing circuit 576, the ELVSS power source 780, the display 18, etc.

[0225] The processor core complex 12 disables (block 1522) the signal current in both pixels 1500. For example, the processor core complex 12 may push a cutoff voltage, such as the voltage supplied by the ELVSS power source 1504, higher. Thus, no current may flow through the diode 1506.

[0226] The processor core complex 12 then determines (block 1524) the bias mismatch current between the two pixels 1500. Specifically, the processor core complex 12 may be configured Fig.50, to determine the bias mismatch current using the side transistor 1510. For example, the side transistor 1510 may sample the bias current at the gate of the current source 1502, and the processor core complex 12 may determine the difference between the bias currents.

[0227] The processor core complex 12 enables (block 1526) the signal current at the pixel 911. Specifically, the processor core complex 12 may enable the signal current at the corresponding pixel 911 for which it is desired to determine the current on the corresponding diode 1506. Therefore, the processor core complex 12 may push a cutoff voltage, such as the voltage supplied by the ELVSS power source 1504, lower.

[0228] The processor core complex 12 then determines (block 1528) the difference between the currents through the pixel 911. That is, the processor core complex 12 may determine the current 1512 through the pixel 911 having the diode 1506 providing the signal current from block 1526 and the current 1514 through the pixel 911 having the diode 1506 not providing the signal current. For example, the processor core complex 12 may determine the currents 1512, 1514 by measuring the current at the output capacitor 1516. The processor core complex 12 may then determine the difference between the two currents 1512, 1514. The difference may therefore include the expected current on the diode 1506 of the pixel 911 as well as the bias mismatch current.

[0229] The processor core complex 12 extracts (block 1530) the bias mismatch current from the difference between the currents through the pixels 911. That is, the processor core complex 12 may subtract the bias mismatch current from the difference between the currents through the pixels 911. The remaining current is therefore the current across the diode 1506 of the pixel 911. Thus, the method 1520 and Fig.50 The circuit diagram can accurately measure the current across the diode in the class AB amplifier pixel 911 (and other pixels having a current source on each side of the voltage data line 913) while also compensating for bias mismatches between pixels 911.

[0230] As reference Fig.38 As discussed, when current in a pixel or subpixel is sensed, the surrounding pixels or subpixels may be turned off or programmed to zero. Thus, current may leak from the pixel or subpixel being sensed to the surrounding pixels or subpixels. Fig.38 Pixel 740 is shown in a configuration where the left column of sub-pixels includes a top row of red sub-pixels 742 and a bottom row of green sub-pixels 744. Pixel 740 also includes a right column of blue sub-pixels 746.

[0231] For some pixels (e.g. Fig.47In the case of class A amplifier pixel 910 shown, lateral leakage current can flow from a voltage drain (e.g., VDD) to a voltage source (e.g., VSS). However, pixels with current sources on each side of the data voltage line, such as class AB amplifier pixel 911, circulate lateral leakage current from VDD and VSS, as shown in FIG. Fig.52 Specifically, Fig.52 FIG. 1 shows a graph of the current caused by sensing the current through the diode of the blue sub-pixel 1540 according to an embodiment of the present disclosure. Fig.49 lateral leakage current in pixel 911. Thus, data is being sent to blue sub-pixel 1540 (via data voltage line 1542) to cause blue sub-pixel 1540 to emit gray level X ("GX", where X can be any suitable gray level (e.g., G100)). In addition, red sub-pixel 1544 and green sub-pixel 1546 of pixel 911 are turned off, so that data is sent to red sub-pixel 1544 and green sub-pixel 1546 (via corresponding data voltage line 1542), causing red sub-pixel 1544 and green sub-pixel 1546 to emit zero gray level ("G0") and appear to be turned off. Red arrow 1548 indicates the leakage current flow from blue sub-pixel 1540 to red sub-pixel 1544 and green sub-pixel 1546.

[0232] If the VDD and VSS lines of the leakage paths are combined (eg, neighboring sub-pixels to the sub-pixel being sensed), then the lateral leakage current may be accounted for or subtracted. Fig.53 is a circuit diagram illustrating a method of reducing lateral leakage current when sensing current in a subpixel according to an embodiment of the present disclosure. As shown, a VDD / VSS power wiring or supply line 1560 may be disposed between each column 1562 of pixels 911. Thus, each subpixel may be adjacent to a power wiring 1560, which may be coupled to a three-way switch or multiplexer 1564, which in turn is coupled to a sense amplifier 1566. In some embodiments, each power wiring line 1560 is coupled to two three-way multiplexers 1564, 1568 (one three-way multiplexer disposed above the first row 1570 of pixels 911, and one three-way multiplexer disposed below the last row 1572 of pixels 911). The first multiplexer 1564 may be coupled to the topmost sense amplifier 1566, and the second multiplexer 1568 may be coupled to the bottommost sense amplifier 1568. The two sense amplifiers 1566, 1568 can reduce or minimize noise from two current sources (eg, 912, 914) disposed on each side of the data voltage line (eg, 913), as compared to Fig.49 discussed.

[0233] When sensing the current of pixel 911, multiplexer 1564 may connect those power supply wiring lines 1560 that supply VDD / VSS signals to sub-pixels that may receive leakage current. Fig.54 In the exemplary circuit diagram of , a sensing operation is performed on the red sub-pixel 1580 according to an embodiment of the present disclosure. Specifically, data is sent to the red sub-pixel 1580 (via the data voltage line) that causes the red sub-pixel 1580 to emit a gray level of X, while data is sent to the other sub-pixels (e.g., 1540, 1544, 1546) that causes the other sub-pixels to emit a zero gray level. Therefore, the multiplexer 1564 is instructed (e.g., by the processor core complex 12) to close the switch, which couples the node 1582 (which connects the multiplexer 1564 to the sense amplifier 1566) to the power supply wiring lines 1584, 1586, which supply VDD / VSS signals to the sub-pixels that can receive leakage current when current is sensed in the red sub-pixel 1580 (e.g., the neighboring sub-pixels of the red sub-pixel 1580). As shown, the power supply wiring lines 1584, 1586 that supply VDD / VSS signals to the sub-pixels that may receive leakage current when current is sensed in the red sub-pixel 1580 may be the two power supply wiring lines 1584, 1586 closest to the red sub-pixel 1580. Fig.54 The bottommost sense amplifier 1568 is not shown, but it should be understood that if Fig.54 The same technique applies if the bottom-most sense amplifier 1568 is used in FIG.

[0234] Similarly, in Fig.55 In the exemplary circuit diagram of , a sensing operation is performed on a blue sub-pixel 1590 according to an embodiment of the present disclosure. Specifically, data is sent to the blue sub-pixel 1590 (via a data voltage line) that causes the blue sub-pixel 1590 to emit a gray level of X, while data is sent to the other sub-pixels (e.g., 1540, 1544, 1546) that causes the other sub-pixels to emit a zero gray level. Thus, the multiplexer 1564 is instructed (e.g., by the processor core complex 12) to close a switch that couples a node 1592 (which connects the multiplexer 1564 to the sense amplifier 1566) to power wiring lines 1594, 1596 that supply VDD / VSS signals to sub-pixels that may receive leakage current when current is sensed in the blue sub-pixel 1590 (e.g., neighboring sub-pixels of the blue sub-pixel 1590). As shown, the power supply wiring lines 1594, 1596 that supply VDD / VSS signals to the sub-pixels that may receive leakage current when current is sensed in the blue sub-pixel 1590 may be the two power supply wiring lines 1594, 1596 closest to the blue sub-pixel 1590. Fig.55The bottommost sense amplifier 1568 is not shown, but it should be understood that if Fig.55 The same technique applies if the bottommost sense amplifier 1568 is used in the data line. Thus, when current is sensed in a pixel having a current source on each side of the data voltage line, such as the class AB amplifier pixel 911, the current can be taken into account or subtracted. Figure 53 to Figure 55 Circuit diagram of the .

[0235] Fig.56 According to an embodiment of the present disclosure, a method for sensing Figure 7 1 is a timing diagram of current in pixels 922, 923 of the active array 62 of the display 18. The ELVSS power source may first provide an operating supply voltage 924 (e.g., approximately -1.6V) to the pixels 922, 923, and then provide an increased supply voltage 926 (e.g., approximately 3V). The timing diagram shows a data value 928 and a data voltage 930 provided to the pixel 922, a source amplifier chopping polarity 932 in the pixel 922, 923, a transmit signal 934 in the pixel 922, 923, and an analog front end (AFE) operation 936 in the pixel 922, 923.

[0236] As shown, each sensing operation 938, 940 may take approximately 2 milliseconds, and two pairs of current-voltage values ​​may be sensed for each pixel 922 (or sub-pixel). The timing diagram also shows the timing of correlated double sampling 942, source amplifier offset cancellation 944, and lateral leakage and bias current cancellation 946.

[0237] The sensing operation may be performed periodically (e.g., approximately once every two weeks) and / or based at least in part on certain conditions. The lookup table 582 of the processor core complex 12 may be updated based at least in part on the sensing results and applied to the display 18 to be used until the next sensing operation. It should be noted that sensing of all pixels 922, 923 or sub-pixels may be performed within a target time. The number of analog front-end channels performing the sensing operation may depend on the target time. For example, assuming that the number of sub-pixels to be sensed is 7,875,000 and the time to sense these number of sub-pixels is 4200 minutes, the number of analog front-end channels used to perform sensing within 30 minutes may be 140. In order to perform sensing within 90 minutes, the number of analog front-end channels may be 50.

[0238] Performing the sensing operation in a shorter time may result in a lower chance that the sensing operation is interrupted (e.g., by activating or using device 10). An interrupted sensing operation may be less accurate and more prone to error because the temperature may change when the sensing operation is resumed after the interruption (e.g., at the next shutdown time of device 10). However, because the resolution of display 18 may be very high, driving the pixels of display 18 at the target refresh rate may use a large amount of bandwidth. Similarly, driving the pixels of display 18 may consume a large amount of power, and implementing a sensing scheme for a high-resolution display 18 may be complex. Therefore, in some embodiments, the pixels may be grouped, and representative pixels of the grouped pixels may be sensed rather than each individual pixel of each group.

[0239] Fig.57 According to the embodiments of the present disclosure Figure 7 950 is a diagram of pixel groups of display 18 of FIG. 950 is a pixel of the active array, pixel group 952 is a 2×2 configuration of four pixels 950, and pixel group 954 is a 4×4 configuration of sixteen pixels 950. Because the pixels in each group are adjacent to each other, the pixels of the corresponding groups experience similar aging, usage, and operating conditions (such as temperature). Therefore, instead of sensing each individual pixel 950 of the group, representative pixels of the groups 952, 954 may be sensed, and the remaining pixels of the group may not be sensed. In this way, fewer pixels 950 may be sensed in each sensing operation, thereby reducing power consumption, bandwidth usage, and complexity during the sensing operation.

[0240] In some embodiments, different groupings may be used based at least in part on the location of the pixels of each grouping. For example, in portions of display 18 that are more likely to be in focus (e.g., by a viewer), such as near the center of display 18, pixels 950 may be sensed individually or via smaller groups such as 2×2 configuration 952. In portions of display 18 that are less likely to be in focus, such as near the perimeter or border of display 18, pixels 950 may be sensed via larger groups such as 4×4 configuration 954. Thus, even fewer pixels 950 may be sensed in each sensing operation, thereby reducing power consumption, bandwidth usage, and complexity during the sensing operation. Although Fig.57 Only 2x2 and 4x4 pixel groups are shown, but it should be understood that any suitable grouping of pixels 950 is contemplated.

[0241] Although it has been discussed that current sensing is performed from the "top" side (e.g., from a top-located power source, such as an ELVDD power source coupled to the drain of the pixel's TFT), as described by Fig.38 748, but in some embodiments, current sensing can be performed from a bottom located power source such as an ELVSS power source coupled to the source of the pixel's TFT. Fig.58The sensing method according to the embodiment of the present disclosure is shown in FIG. Figure 7 Schematic diagram of current in pixel 970 of display 18. Specifically, the current sensed in pixel 970 can be determined as the sum of current 972 through diode 974 of pixel 970 (which diode is open) and one or more currents 976 through one or more diodes 978 of one or more adjacent pixels 980.

[0242] Current-voltage compensation method

[0243] exist Fig.31 After the sensing circuit 576 senses or predicts a corresponding set of current-voltage values ​​for each pixel of the active array 62 (the corresponding set of current-voltage values ​​may be stored in the lookup table 582), the voltage comparator circuit 584 may generate a current-voltage curve for each pixel based at least in part on the corresponding set of current-voltage values. Since providing the voltage comparator circuit 584 with an entire curve or an excessive set of current-voltage values ​​for each pixel (e.g., each image frame) may be impractical in terms of memory or bandwidth usage, the sensing circuit 576 may instead send a reduced amount (e.g., two pairs) of current-voltage values, and the voltage comparator circuit 584 may generate a current-voltage curve for each pixel (e.g., in real time) based at least in part on the corresponding set of current-voltage values. The voltage comparator circuit 584 may compare the current-voltage curve generated for each pixel with a reference current-voltage curve received from the reference array control circuit and generate a set of voltage differences or degradations (e.g., corresponding to the resulting current values). The current-to-voltage compensation circuit 586 may then instruct the digital-to-analog converter 572 to compensate for the set of voltage differences or degradations (eg, by providing increased data voltages for certain corresponding current values).

[0244] The voltage comparator circuit 584 may generate a current-voltage curve for each pixel using any suitable method, such as a delta-based model or an interpolation-based model. Fig.59 is a diagram showing the use of an incremental-based model 992 to generate a Figure 7 18. The graph includes a "raw" reference current-voltage curve 994 that may be generated from a set of reference current-voltage values ​​received from a reference array control circuit. For example, the voltage comparator circuit 584 may receive eight pairs of current-voltage values ​​and interpolate the reference current-voltage curve 994 based at least in part on the eight pairs of current-voltage values.

[0245] The graph also includes two pairs of sensed current-voltage values ​​996, 998 for the pixel received from the sense circuit 576. The voltage comparator circuit 584 may determine a first voltage difference or delta value 1000 between the voltages of the first pair of sensed current-voltage values ​​996 at corresponding currents 1002 and the reference voltage of the reference current-voltage curve 994 at the corresponding current 1002. The voltage comparator circuit 584 may also determine a second voltage difference or delta value 1004 between the voltages of the second pair of sensed current-voltage values ​​998 at corresponding currents 1006 and the reference voltage of the reference current-voltage curve 994 at the corresponding current 1006.

[0246] Using the delta-based model 992, the voltage comparator circuit 584 may then determine a linear relationship between the first voltage difference 1000 and the second voltage difference 1004, and apply the linear relationship to the reference current-voltage curve 994 to reconstruct the current-voltage curve 990. The current-voltage compensation circuit 586 may then instruct the digital-to-analog converter 572 to compensate for the voltage degradation as provided and based at least in part on the current-voltage curve 990. For example, the current-voltage compensation circuit 586 may determine a set of voltage differences (e.g., including the first voltage difference 1000 and the second voltage difference 1004) between the current-voltage curve 990 and the reference current-voltage curve 994, and increase the data voltage or current for the pixel at the corresponding current value based at least in part on the set of voltage differences.

[0247] In some embodiments, a linear relationship may not accurately model the current-voltage curve for each pixel. For example, certain materials used to make display 18 may cause the relationship of the current-voltage curve for each pixel to tend to be nonlinear. Therefore, voltage comparator circuit 584 may use an interpolation-based model to generate a current-voltage curve for each pixel. Fig.60 is a diagram showing the use of an interpolation-based model 1022 for Figure 7 18. The graph includes a "raw" reference current-voltage curve 1024 that may be generated from a set of reference current-voltage values ​​received from a reference array control circuit. The graph also includes an "aged" current-voltage curve 1026 that may be generated by stressing one or more pixels of the display over a period of time such that the aged current-voltage curve 1026 represents an accurate representation of how the current-voltage relationship of the one or more pixels has aged.

[0248] In some embodiments, an aged current-voltage curve 1026 may be generated for each batch of displays manufactured (e.g., by or at a manufacturer). In alternative or additional embodiments, an aged current-voltage curve 1026 may be generated for each display 18. For example, the digital-to-analog converter 572 may stress one or more pixels in a less active and / or less focused (e.g., by a user) area of ​​the display 18 (such as along a perimeter or border of the display 18) for a period of time, and generate an aged current-voltage curve 1026 based at least in part on the stressed one or more pixels. The aged current-voltage curve 1026 may be stored in any suitable storage device, such as the local memory 14, the main memory storage device 16, etc.

[0249] The graph includes two pairs of sensed current-voltage values ​​1028, 1030 for the pixel received from the sensing circuit 576. The voltage comparator circuit 584 may determine a first difference d1 1032 between the current of the first pair of sensed current-voltage values ​​1028 at the corresponding voltage 1034 and the current of the reference current-voltage curve 1024 at the corresponding voltage 1034. The voltage comparator circuit 584 may also determine a first total difference D1 1036 between the current of the reference current-voltage curve 1024 at the corresponding voltage 1034 and the current of the aged current-voltage curve 1026 at the corresponding voltage 1034. The voltage comparator circuit 584 may then determine a first degradation ratio r1 (e.g., r1=d1 / D1) between the first difference 1032 and the first total difference 1036.

[0250] The voltage comparator circuit 584 may also determine a second difference d2 1038 between the current of the second pair of sensed current-voltage values ​​1030 at the corresponding voltage 1040 and the current of the reference current-voltage curve 1024 at the corresponding voltage 1040. The voltage comparator circuit 584 may also determine a second total difference D2 1042 between the current of the reference current-voltage curve 1024 at the corresponding voltage 1040 and the current of the aged current-voltage curve 1026 at the corresponding voltage 1040. The voltage comparator circuit 584 may then determine a second degradation ratio r2 (e.g., r2=d2 / D2) between the second difference 1038 and the second total difference 1042.

[0251] Using the interpolation-based model 1022, the voltage comparator circuit 584 may then determine a linear relationship between the first ratio and the second ratio, and apply the linear relationship to the reference current-voltage curve 1024 to reconstruct the current-voltage curve 1020. The current-voltage compensation circuit 586 may then instruct the digital-to-analog converter 572 to compensate for the voltage degradation as provided and based at least in part on the current-voltage 1020. For example, the current-voltage compensation circuit 586 may determine a set of voltage differences between the current-voltage curve 1020 and the reference current-voltage curve 1024, and increase the data voltage or current for the pixel at the corresponding current value based at least in part on the set of voltage differences.

[0252] Using degradation ratios rather than linear voltage differences to reconstruct the current-voltage curve can reduce or remove the dependence of the current-voltage relationship on the material and / or temperature of the display 18. That is, sensing is typically performed at lower temperatures because the device 10 is inactive, while applying compensation based at least in part on the sensing results is performed at higher temperatures because the device is active. Because the use of degradation ratios is more generally applicable (e.g., as opposed to using linear voltage differences), the reconstruction of the current-voltage curve based on interpolation may be more accurate. This is at least in part because when expressed using degradation ratios, the current-voltage curve of the pixel appears to degrade the voltage linearly.

[0253] Fig.61 A method for determining a degradation current-voltage curve to drive a Figure 7 18. Method 1043 may be performed by any suitable device or combination of devices that can generate a current-voltage curve, determine a degradation ratio, and drive a pixel. Although method 1043 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in an order different from that shown, and that certain described steps may be skipped or not performed at all. In some embodiments, at least some of the steps of method 1043 may be performed by Fig.31 The current-voltage compensation circuit 586 of the embodiment is performed as described below. However, it should be understood that any suitable device or combination of devices is contemplated to perform method 1043, such as a digital-to-analog converter 572, a voltage comparator circuit 584, a processor core complex 12, a display 18, etc.

[0254] The current-voltage compensation circuit 586 receives (block 1044) a set of reference current-voltage values. The set of reference current-voltage values ​​may be received from a reference array control circuit and may include any suitable number (e.g., eight pairs) of reference current-voltage values. The current-voltage compensation circuit 586 then generates (block 1045) a reference current-voltage curve 1024 based at least in part on the set of reference current-voltage values.

[0255] The current-voltage compensation circuit 586 receives (block 1046) the aged current-voltage curve 1026. In some embodiments, the current-voltage compensation circuit 586 may receive a set of aged current-voltage values ​​from the sensing circuit 576 and / or any suitable storage device or mechanism (such as the local memory 14, the main memory storage device 16, the lookup table 582, etc.). The current-voltage compensation circuit 586 may then generate the aged current-voltage curve 1026 based at least in part on the set of aged current-voltage values.

[0256] The current-voltage compensation circuit 586 then receives (block 1047) a set of degraded current-voltage values ​​for the pixel. The set of degraded current-voltage values ​​may be received from the sensing circuit 576 and may degrade as the pixel operates for a period of time.

[0257] The current-voltage compensation circuit 586 determines (block 1048) a set of degradation ratios based at least in part on the set of degraded current-voltage values, the reference current-voltage curve 1024, and the aged current-voltage curve 1026. Specifically, for each degraded current-voltage value of the set of degraded current-voltage values, the current-voltage compensation circuit 586 may determine a difference d 1032 between the current of the corresponding degraded current-voltage value 1028 at the corresponding voltage 1034 and the current of the reference current-voltage curve 1024 at the corresponding voltage 1034. The voltage comparator circuit 584 may also determine a total difference D 1036 between the current of the reference current-voltage curve 1024 at the corresponding voltage 1034 and the current of the aged current-voltage curve 1026 at the corresponding voltage 1034. The voltage comparator circuit 584 may then determine a degradation ratio r (e.g., r=d / D) between the first difference 1032 and the first total difference 1036.

[0258] The current-voltage compensation circuit 586 generates (block 1049) a degraded current-voltage curve 1020 based at least in part on the set of degradation ratios. Specifically, the voltage comparator circuit 584 may then determine a linear relationship between the set of degradation ratios and apply the linear relationship to the reference current-voltage curve 1024 to reconstruct the degraded current-voltage curve 1020. The current-voltage compensation circuit 586 may then drive (block 1050) or instruct the digital-to-analog converter 572 to drive the pixel 574 based at least in part on the degraded current-voltage curve 1020. For example, the current-voltage compensation circuit 586 may determine a set of voltage differences between the current-voltage curve 1020 and the reference current-voltage curve 1024, and increase the data voltage or current for the pixel at the corresponding current value based at least in part on the set of voltage differences.

[0259] In some embodiments, the current step limiter circuit 72 of the active array control circuit 85 can limit the current compensation value corresponding to the set of voltage differences. Specifically, the current step limiter circuit 72 can be used to limit the current compensation value corresponding to the set of voltage differences to below a visibility threshold. The visibility threshold can correspond to a change in current value that may not be perceived by an observer of the display 18 when applied to drive the pixel 574 (compared to driving the pixel 574 before applying the current compensation value). In this way, the observer may not notice the applied compensation, thereby improving the overall viewing experience of the display 18.

[0260] Fig.62 According to the embodiments of the present disclosure Figure 7 A block diagram of a system 1051 for compensating for voltage degradation in a display 18 of a device 10. Part or all of the system 1051 may be included in the processor core complex 12, the timing controller 581, the display 18, or any other suitable component of the device 10. As shown, the system 1051 includes Fig.31 The current-voltage compensation circuit 586 receives the degradation ratio r1 1052, r2 1054, the input voltage V in 1056 and input current I in 1058 as input.

[0261] The degradation ratio r1 1052, r2 1054 of each pixel may be stored in any suitable storage device or mechanism, such as the local memory 14, the main memory storage device 16, the lookup table 582, etc. ... in 1062 receives the input voltage V from the gamma voltage converter 1060 in 1056. Input gamma G in1062 may be the target gamma intended to be displayed by the pixel, and the input voltage V in 1056 can be used to generate input gamma G before compensation in 1062 corresponding to the data voltage. The input current I can be received from the reference array lookup table 1064 in 1058, the reference array lookup table can store the data voltage and corresponding pixel current of one or more pixels of the reference array 64. The reference array lookup table 1064 can be a part of the lookup table 582 and is based at least in part on the input voltage V in 1056. Specifically, when an input voltage V is provided to the pixel in 1056 data voltage, input current I in 1058 may be the resulting current produced by the pixels of the reference array 64 .

[0262] The current-voltage compensation circuit 586 can output V based at least in part on the input out 1066, the V out The input current I may correspond to the compensated data voltage to generate an input current I at the pixel based at least in part on a current-voltage curve generated (eg, interpolated) using the degradation ratios r1 1052, r2 1054. in 1058. Output voltage V out 1066 can be converted into a gamma value G by a voltage gamma converter 1068 out 1070, the gamma value may be sent to the digital-to-analog converter 572 to drive the pixel 574. The pixel 574 is driven to emit the gamma value G out 1070 may cause pixel 574 to actually emit approximately the input gamma value G in 1062, thereby compensating for the current-voltage degradation in pixel 574.

[0263] Fig.63 is a diagram showing an embodiment according to the present disclosure Figure 7 1052, r2 1054, the current-to-voltage compensation circuit 586 can generate or extrapolate the linear relationship 1080 (e.g., with respect to voltage) using the two degradation ratios r1 1052, r2 1054. The current-to-voltage compensation circuit 586 can also determine or extrapolate the degradation ratio or tap point 1082 based at least in part on the linear relationship 1080.

[0264] Fig.64 1 is a graph showing a current-voltage curve I(V) 1090 reconstructed at least in part based on two extrapolated current-voltage values ​​1092, 1094 according to an embodiment of the present disclosure. As shown, the graph includes a reference current-voltage curve I T0(V)1024 and input current I in 1058, the input current is the reference current-voltage curve at V in The current at 1056 (e.g., I T0 (V in )). The current-voltage compensation circuit 586 may convert the extrapolated degradation ratio or tap point 1082 into an extrapolated current-voltage value. The current-voltage compensation circuit 586 may then determine two extrapolated current-voltage values ​​(V j ,I j )1092、(V k ,I k )1094, these two extrapolated current-voltage values ​​satisfy the following conditions: I(V j ) in <I(V k ).

[0265] Fig.65 is a diagram showing an output voltage V for driving a pixel and compensating for voltage degradation according to an embodiment of the present disclosure. out 1066. The current-voltage compensation circuit 586 can be composed of I(V j ) and I(V k )Internal output voltage V out 1066. For example, the current-voltage compensation circuit 586 may be configured to provide a current-voltage compensation circuit 586 at two extrapolated current-voltage values ​​(V j ,I j )1092 and (V k ,I k )1094 to generate a curve 1096, and select a value on the curve 1096 that corresponds approximately to the input current I in The output voltage of 1058 is V out 1066. Output voltage V out 1066 can be converted into a gamma value G by a voltage gamma converter 1068 out 1070, the gamma value may be sent to the digital-to-analog converter 572 to drive the pixel 574. The pixel 574 is driven to emit the gamma value G out 1070 may cause pixel 574 to actually emit approximately the input gamma value G in 1062, thereby compensating for the current-voltage degradation in pixel 574.

[0266] Fig.66 According to an embodiment of the present disclosure, a method for compensating for current-voltage degradation to drive a Figure 7 ​18. The method 1110 may be performed by any suitable device or combination of devices that can extrapolate data, generate current-voltage curves, and drive pixels. Although the method 1110 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in an order different from that shown, and that certain described steps may be skipped or not performed at all. In some embodiments, at least some of the steps of the method 1110 may be performed by Fig.31 The current-voltage compensation circuit 586 of the embodiment is performed as described below. However, it should be understood that any suitable device or combination of devices is contemplated to perform the method 1110, such as the digital-to-analog converter 572, the voltage comparator circuit 584, the processor core complex 12, the display 18, etc.

[0267] The current-voltage compensation circuit 586 receives (block 1112) a set of degradation ratios. A set of degradation ratios (e.g., 1052, 1054) may be received for each pixel and may be stored in any suitable storage device or mechanism, such as a local memory 14, a main memory storage device 16, a lookup table 582, etc.

[0268] The current-voltage compensation circuit 586 then extrapolates (block 1114) a set of extrapolated degradation ratios based at least in part on the set of degradation ratios. For example, the current-voltage compensation circuit 586 may generate or extrapolate a linear relationship 1080 (e.g., with respect to voltage) based at least in part on the set of degradation ratios. The current-voltage compensation circuit 586 may then determine or extrapolate the set of extrapolated degradation ratios or tap points 1082 based at least in part on the linear relationship 1080.

[0269] The current-voltage compensation circuit 586 may convert the set of extrapolated degradation ratios into a set of extrapolated current-voltage values ​​(block 1116). Specifically, the current-voltage relationship of the extrapolated degradation ratio may be expressed as I(V x )=I TO (V x )–r x D x , where I TO is the reference current-voltage curve 1024, r x is the degradation ratio at data voltage x, and D x is the current difference between the reference current-voltage curve 1024 and the aged current-voltage curve 1026 at the data voltage x.

[0270] The current-voltage compensation circuit 586 may receive (block 1118) an input reference current. The input current I may be received from a reference array lookup table, which may be part of the lookup table 582. in 1058, and the input current may be based at least in part on the input voltage V in 1056. Specifically, when an input voltage V is provided to the pixel in 1056 data voltage, input current I in 1058 may be the resulting current produced by the pixels of the reference array 64 .

[0271] The current-voltage compensation circuit 586 may determine (block 1120) a first extrapolated current-voltage value having a current less than the input reference current. The current-voltage compensation circuit 586 may also determine (block 1122) a second extrapolated current-voltage value having a current greater than the input reference current. Fig.65 The first extrapolated current-voltage value (V j ,I j )1092 and the second extrapolated current-voltage value (V k ,I k ) 1094. In some embodiments, the first extrapolated current-voltage value may be an extrapolated current-voltage value of the set of extrapolated current-voltage values ​​that is smaller than and closest to the input reference current. Similarly, the second extrapolated current-voltage value may be an extrapolated current-voltage value of the set of extrapolated current-voltage values ​​that is larger than and closest to the input reference current.

[0272] The current-voltage compensation circuit 586 may then generate (block 1124) an extrapolated current-voltage curve based at least in part on the first extrapolated current-voltage value and the second extrapolated current-voltage value. Fig.65 The current-voltage value (V j ,I j )1092 and the second extrapolated current-voltage value (V k ,I k ) An example of an extrapolated current-voltage curve 1096 of 1094.

[0273] The current-voltage compensation circuit 586 may determine (block 1126) a compensation voltage or current based at least in part on the extrapolated current-voltage curve and the input reference current. The current-voltage compensation circuit 586 may determine the compensation voltage or current as determined by the extrapolated current-voltage curve 1096 at the input reference current (e.g., I in 1058) given the compensation voltage (for example, the output voltage V out 1066) or current.

[0274] The current-voltage compensation circuit 586 may then use the compensation voltage or current to drive (block 1128) or instruct the digital-to-analog converter 572 to drive the pixel (e.g., 574). The compensation voltage or current may cause the digital-to-analog converter 572 to supply approximately the input reference current (e.g., I in 1058), thereby emitting a gamma that is closer to the input gamma 1062 (compared to uncompensated operation). In this way, the method 1110 can compensate for current-voltage degradation in the pixel.

[0275] In some embodiments, the current step limiter circuit 72 of the active array control circuit 85 can limit the compensation current or the current corresponding to the compensation voltage. Specifically, the current step limiter circuit 72 can be used to limit the compensation current or the current corresponding to the compensation voltage to below a visibility threshold. The visibility threshold can correspond to a change in current value that may not be perceived by an observer of the display 18 when applied to drive the pixel 574 (compared to driving the pixel 574 before applying the compensation current or the current corresponding to the compensation voltage). In this way, the observer may not notice the applied compensation, thereby improving the overall viewing experience of the display 18.

[0276] The above specific embodiments have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but are intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure.

[0277] The technology described and claimed herein is cited and applied to specific examples of a physical and practical nature that significantly improves the art and is therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", then those elements will be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, those elements will not be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A method comprising: instructing, via the processing circuit, a digital-to-analog converter of an active array of an electronic display to supply a first data voltage to pixels of the electronic display; instructing, via the processing circuit, the digital-to-analog converter to supply a zero data voltage to adjacent pixels of the pixel; instructing, via the processing circuit, a transmit power source of the electronic display to supply an operational transmit supply voltage to the pixel and the adjacent pixel; instructing, via the processing circuit, a sensing circuit of the active array to determine a first current in the pixel; instructing the transmit power source via the processing circuit to supply an increased transmit supply voltage to the pixel and the adjacent pixel; instructing the sensing circuit, via the processing circuit, to determine a second current in the pixel; and The digital-to-analog converter is instructed, via the processing circuit, to drive the pixel based at least in part on the first current and the second current. 2 . The method of claim 1 , wherein the increased emission supply voltage is configured to cause a diode of the adjacent pixel to be reverse biased. 3 . The method of claim 1 , wherein the first current comprises a leakage current, a bias current, and a diode current on a diode of the pixel. The method according to claim 1 , wherein the second current comprises a leakage current and a bias current.

5. An electronic display comprising: a first pixel including a first diode, a first data voltage line, a first topmost current source disposed on a first side of the first data voltage line, and a first bottommost current source disposed on a second side of the first data voltage line; a second pixel including a second diode, a second data voltage line, a second topmost current source disposed on a first side of the second data voltage line, and a second bottommost current source disposed on a second side of the second data voltage line; a topmost sense amplifier coupled to the first topmost current source and the second topmost current source; and A bottom-most sense amplifier is coupled to the first bottom-most current source and the second bottom-most current source.

6. The electronic display of claim 5, wherein the processing circuit is configured to: instructing the topmost sense amplifier and the bottommost sense amplifier to measure a first current on the first pixel and a second current on the second pixel; and A current on the first diode is determined based at least in part on a difference between the first current on the first pixel and the second current on the second pixel. 7 . The electronic display of claim 6 , wherein the difference between the first current and the second current is determined when current is flowing through the first diode and current is not flowing through the second diode.

8. The electronic display of claim 5, comprising one or more transistors coupled between the first pixel or the second pixel and the topmost sense amplifier or the bottommost sense amplifier, wherein the one or more transistors are configured to reduce a bias current mismatch between the first pixel and the second pixel.

9. The electronic display according to claim 5, comprising: a plurality of pixel columns, wherein each pixel comprises a plurality of sub-pixels; a plurality of power wiring lines coupled to at least the topmost sensing amplifier, wherein each of the plurality of power wiring lines is disposed between two of the plurality of pixel columns, wherein the plurality of power wiring lines are configured to couple one or more of the plurality of power wiring lines to at least the topmost sensing amplifier, the one or more power wiring lines supplying a power signal to a sub-pixel that receives a leakage current when a current is sensed in a first sub-pixel.

10. The electronic display of claim 9, wherein the one or more power routing lines include the two power routing lines closest to the first subpixel.

11. The electronic display of claim 9 , comprising a plurality of multiplexers configured such that each of the plurality of power wiring lines is coupled to at least the topmost sense amplifier, wherein the processing circuit is configured to instruct one or more of the plurality of multiplexers to couple the one or more power wiring lines to at least the topmost sense amplifier, the one or more power wiring lines supplying a power signal to the sub-pixel that receives the leakage current when current is sensed in the first sub-pixel.

12. A method comprising: disabling a first signal current in the first pixel and a second signal current in the second pixel; determining a bias mismatch current between the first pixel and the second pixel; enabling the first signal current in the first pixel; determining a difference between a first current through the first pixel and a second current through the second pixel; and The bias mismatch current is extracted from the difference between the first current and the second current to determine a current through a diode of the first pixel. 13 . The method of claim 12 , wherein the first pixel and the second pixel each include a data voltage line, a first current source disposed on one side of the data voltage line, and a second current source disposed on an opposite side of the data voltage line.

14. The method of claim 12, wherein the first pixel and the second pixel each comprise a class AB amplifier pixel.

15. A mobile electronic device, comprising: a display comprising an active array and a reference array, wherein the active array comprises pixels and the reference array comprises reference pixels; and a processing circuit communicatively coupled to the display, wherein the processing circuit is configured to drive the pixel based at least in part on a degradation current-voltage relationship for the pixel, a reference current-voltage relationship for the reference pixel, and an aged current-voltage relationship, wherein the aged current-voltage relationship is determined based on a stress applied to one or more pixels of an additional display, and wherein the aged current-voltage relationship is stored in a storage component accessible to the processing circuit.

16. The mobile electronic device of claim 15, wherein the aged current-voltage relationship is based at least in part on peripheral pixels of an additional active array of the additional display.

17. The mobile electronic device of claim 15, wherein the processing circuit comprises one or more lookup tables configured to store a set of degraded current-voltage values ​​for the pixel associated with the degraded current-voltage relationship.

18. The mobile electronic device of claim 17, wherein the processing circuit comprises a voltage comparator circuit configured to generate the degraded current-voltage relationship based at least in part on the set of degraded current-voltage values.

19. The mobile electronic device of claim 17, wherein the processing circuit comprises a voltage comparator circuit configured to: determining a set of degradation ratios based at least in part on the set of degraded current-voltage values, the reference current-voltage relationship, and the aged current-voltage relationship; and The degraded current-voltage relationship is generated based at least in part on the set of degradation ratios.

20. The mobile electronic device of claim 19, wherein each degradation ratio in the set of degradation ratios is based at least in part on: a first current difference between a respective reference current-voltage value associated with the reference current-voltage relationship and a respective degraded current-voltage value of the set of degraded current-voltage values; and A second current difference between the respective reference current-voltage values ​​and respective degraded current-voltage values ​​of the set of degraded current-voltage values ​​and an aged current-voltage value associated with the aged current-voltage relationship.

21. A method comprising: extrapolating, via processing circuitry, a set of extrapolated degradation ratios based at least in part on the set of received degradation ratios; determining, via the processing circuit, a first extrapolated current-voltage value including a first current less than a reference current based at least in part on a first extrapolated degradation ratio in the set of extrapolated degradation ratios; determining, via the processing circuit, a second extrapolated current-voltage value including a second current greater than the reference current based at least in part on a second extrapolated degradation ratio in the set of extrapolated degradation ratios; generating, via the processing circuit, an extrapolated current-voltage curve between the first extrapolated current-voltage value and the second extrapolated current-voltage value; determining, via the processing circuit, a compensation voltage based at least in part on the extrapolated current-voltage curve and the reference current; and The processing circuit instructs a digital-to-analog converter to drive a pixel using the compensation voltage.

22. The method of claim 21, comprising converting the set of extrapolated degradation ratios into a set of extrapolated current-voltage values, wherein the set of extrapolated current-voltage values ​​comprises the first extrapolated current-voltage value and the second extrapolated current-voltage value.

23. The method of claim 22, wherein the first current is the closest current among the set of extrapolated current-voltage values ​​that is less than the reference current.

24. The method of claim 22, wherein the second current is the closest current among the set of extrapolated current-voltage values ​​that is greater than the reference current.

25. The method of claim 21, wherein the reference current is configured to be generated at a reference pixel of a reference array when a reference voltage is supplied.

26. The method of claim 25, wherein a diode of the reference pixel is configured to emit a target gray level when the reference voltage is supplied to the pixel.

27. The method of claim 26, wherein instructing the digital-to-analog converter via the processing circuit to drive the pixel using the compensation voltage approximately produces the target gray level at a second diode of the pixel.

28. The method of claim 25, wherein driving the pixel using the compensation voltage via the processing circuit is configured to approximately produce the reference current at the pixel.

29. The method of claim 21, wherein the extrapolated current-voltage curve is linear.

30. A mobile electronic device comprising: a display comprising an active array, a reference array, and a digital-to-analog converter, wherein the active array comprises pixels; and a processing circuit communicatively coupled to the display, wherein the processing circuit comprises: A current-voltage compensation circuit, wherein the current-voltage compensation circuit is configured as follows: receiving a plurality of degradation ratios, an input voltage, and an input reference current; as well as outputting a compensation voltage based at least in part on the plurality of degradation ratios, the input voltage, and the input reference current, Wherein the digital-to-analog converter drives the pixel based at least in part on the compensation voltage.

31. The mobile electronic device of claim 30, wherein the processing circuit comprises a gamma voltage converter configured to convert an input grayscale level into the input voltage.

32. The mobile electronic device of claim 31, wherein the processing circuit comprises a voltage gamma converter configured to convert the compensation voltage into an output gray level.

33. The mobile electronic device of claim 32, wherein the diode of the pixel is configured to emit approximately the input gray level when the digital-to-analog converter drives the pixel to output the output gray level.

34. The mobile electronic device of claim 30, wherein the processing circuit comprises a reference array lookup table configured to store the input voltage and the input reference current.

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