Buck converter and power manager

Abstract

The invention provides a buck converter and a power manager, and the buck converter comprises a phase-locked loop circuit which is used for generating a frequency modulation current signal and a synchronous clock signal according to a received external clock signal and a frequency adjustment value outputted by a frequency modulation element; and the at least one channel circuit outputs the voltage accessed by the external power supply at the corresponding output frequency according to the synchronous clock signal and the frequency modulation current signal. The buck converter comprises a phase-locked loop circuit and a channel circuit, and the channel circuit outputs voltage accessed by an external power supply at a corresponding output frequency according to a frequency modulation current signal and a synchronous clock signal generated by the phase-locked loop circuit, so that the working frequency of the buck converter is not limited to one frequency, but can be adjusted in a very wide range. And at the determined working frequency, the working frequency is not influenced by the working conditions such as the input voltage and the output voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and in particular to a step-down converter and a power manager. Background Art

[0002] The constant on-time control mode is widely used in DC-DC buck converters because of its simple structure and fast transient response speed. The traditional control method is to keep the on-time constant. When the input voltage or output voltage changes, the duty cycle will also change, resulting in a large change in the switching frequency, which cannot be applied to circuits with fixed frequency requirements. In order to achieve the purpose of fixed switching frequency, the adaptive on-time control method is applied to the buck converter. The circuit can automatically adjust the on-time according to the input voltage and output voltage, thereby keeping the duty cycle constant, and thus making the switching frequency basically unchanged.

[0003] In the existing adaptive on-time circuit, since the switching frequency is related to the specific values ​​of electronic components such as internal resistors and capacitors, once integrated into the circuit, its switching frequency can only be maintained at a fixed value, and the switching frequency cannot be adjusted to adapt to various scenarios. Therefore, a buck converter with adjustable switching frequency is needed. Summary of the invention

[0004] The main purpose of the present invention is to provide a buck converter and a power manager, aiming to solve the problem that the traditional buck converter cannot adjust the switching frequency.

[0005] In view of the above problems, the present invention provides a buck converter, comprising: A phase-locked loop circuit, wherein the external clock access terminal of the phase-locked loop circuit is used to access an external clock signal, and the frequency adjustment input terminal of the phase-locked loop circuit is used to access a frequency modulation element; the phase-locked loop circuit is used to generate a frequency modulation current signal and a synchronous clock signal according to the received external clock signal and the frequency adjustment value output by the frequency modulation element; At least one channel circuit, the clock signal input end of the channel circuit is connected to the synchronous clock output end of the phase-locked loop circuit, the voltage input end of the channel circuit is used to access an external power supply, and the voltage output end is used to access a load; the channel circuit is used to receive and output the voltage connected to the external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency-modulated current signal.

[0006] Optionally, the number of the channel circuits is two; The phase-locked loop circuit is specifically used to output a first synchronous clock signal and a second synchronous clock signal; the first synchronous clock signal and the second synchronous clock signal are received by two channel circuits respectively; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 180°.

[0007] Optionally, a plurality of the buck converters operate in parallel. The synchronous clock output terminal of the phase-locked loop circuit in the previous buck converter is electrically connected to the external clock input terminal of the next buck converter.

[0008] Alternatively, the external clock input terminal of the phase-locked loop circuit in each of the buck converters is used to access the same external clock signal.

[0009] Optionally, the phase-locked loop circuit includes: A selection switch, one end of which is electrically connected to an external clock access terminal or a frequency modulation element, and the other end of which is electrically connected to an oscillator and a frequency modulation current generating circuit; the selection switch is used to select a frequency adjustment value for the phase-locked loop circuit to access an external clock signal or an output of the frequency modulation element; An oscillator, used to receive the frequency adjustment value output by the frequency modulation element, and output a synchronous clock signal or output a synchronous clock signal according to an external clock signal; The frequency modulated current generating circuit is used to receive the frequency adjustment value output by the frequency modulated element and output a frequency modulated current signal or output a frequency modulated current signal according to an external clock signal.

[0010] Optionally, the phase-locked loop circuit further includes: A frequency and phase detector is electrically connected to the external clock access terminal, and is used to receive an external clock signal and compare the frequency error between the external clock signal and the synchronous clock signal, and output it to a low-pass filter; A low-pass filter, wherein the input end of the low-pass filter is electrically connected to the frequency and phase detector, and the output end is connected to the selection switch; the low-pass filter is used to convert the received frequency error into a voltage; The frequency divider is electrically connected to the frequency detector and the phase detector and the oscillator; the frequency divider is used to divide the synchronous clock signal output by the oscillator into multiple synchronous clock signals.

[0011] Optionally, the channel circuit includes: A switch circuit, wherein the input end of the switch circuit is used to connect to an external power supply; the switch circuit is used to turn on / off the connection between the external power supply and the voltage output end; A feedback loop, wherein the feedback loop input end is electrically connected to the voltage output end; the feedback loop is used to output a feedback signal; A conduction time generating circuit, wherein the input end of the conduction time generating circuit is connected to a synchronous clock signal, a frequency modulated current signal, a voltage of an external power supply, and an output voltage of a voltage output end; the conduction time generating circuit is used to receive and output a conduction time signal according to the synchronous clock signal, the frequency modulated current signal, the voltage of an external power supply, and the output voltage of the voltage output end; The logic circuit and the driving circuit are electrically connected to the switch circuit, the feedback loop and the on-time generating circuit; the logic circuit and the driving circuit are used to receive and output a control signal according to the on-time signal and the feedback signal to control the switch circuit to turn on / off the connection between the external power supply and the voltage output terminal.

[0012] Optionally, the on-time generating circuit includes: An input voltage-to-current circuit, wherein an input end of the input voltage-to-current circuit is electrically connected to a voltage of an external power supply; the input voltage-to-current circuit is used to convert an input voltage into a first current signal; An error current generating circuit, wherein the input end of the error current generating circuit is connected to the synchronous clock signal and the conduction time signal; the error current generating circuit is used to compare the conduction time signal and the synchronous clock signal and output the error current; A current multiplier, the current multiplier is electrically connected to the error current generating circuit, the voltage-to-current circuit and the conduction signal flipping circuit; the current multiplier is used to receive and output a second current signal according to the frequency modulated current signal, the error current and the first current signal; A conduction signal flipping circuit, wherein the input end of the conduction signal flipping circuit is electrically connected to the output voltage of the current multiplier and the voltage output end; the conduction signal flipping circuit is used to receive and output a conduction time signal according to the second current signal and the output voltage.

[0013] Optionally, the switching circuit includes a first switching tube and a second switching tube, the source of the first switching tube is connected to an external power supply, the drain is connected to the drain of the second switching tube and one end of the inductor as a SW node, the other end of the inductor is electrically connected to the output end of the channel circuit, the gates of the first switching tube and the second switching tube are electrically connected to the logic circuit and the drive circuit, and the source of the second switching tube is grounded.

[0014] Optionally, the feedback loop includes an error comparator and a current comparator, the input end of the error comparator is electrically connected to a reference voltage and a feedback voltage, the output end is electrically connected to the current comparator, the input end of the current comparator is electrically connected to a SW node, and the output end is electrically connected to a logic circuit and a drive circuit; The error comparator is used to compare the reference voltage with the feedback voltage, and output the error between the reference voltage and the feedback voltage to the current comparator; The current comparator is used to output a feedback signal when the inductor discharge ends according to the error between the inductor current signal at the SW node and the reference voltage and the feedback voltage.

[0015] The present invention also provides a power manager, comprising the buck converter as described above.

[0016] The present invention includes a phase-locked loop circuit and a channel circuit. The channel circuit generates a frequency-modulated current signal and a synchronous clock signal according to the phase-locked loop circuit, and outputs the voltage connected to the external power supply at a corresponding output frequency, so that the working frequency of the buck converter is not limited to one frequency, but can be adjusted within a wide range. At a determined working frequency, its working frequency will not be affected by working conditions such as input voltage and output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0018] Figure 1 A circuit diagram of a buck converter according to the present invention; Figure 2 A phase-locked loop circuit diagram of a buck converter of the present invention; Figure 3 A channel circuit diagram of a buck converter of the present invention; Figure 4 The present invention is a conduction time control circuit diagram of a buck converter.

[0019] A first dual-channel buck converter 200, a first PLL circuit 101, a frequency detector 11, a low-pass filter 12, a selection switch 13, an oscillator 14, a frequency divider 15, a frequency modulation current generating circuit 16, a channel one 201, a channel two 202, a switch module 21, a logic circuit and a drive circuit 22, a feedback loop 23, a conduction time generating circuit 24, a second dual-channel buck converter 300, a second PLL circuit 102, a channel three 301, a channel four 302, an input voltage to current conversion module 501, a conduction signal flipping module 502, an error current generating module 503, and a current multiplier 54.

[0020] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0023] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0025] The constant on-time control mode is widely used in DC-DC buck converters because of its simple structure and fast transient response speed. The traditional control method is to keep the on-time unchanged. When the input voltage or output voltage changes, the duty cycle will also change, resulting in a large change in the switching frequency, which cannot be applied to circuits with fixed frequency requirements. In order to achieve the purpose of fixed switching frequency, the adaptive on-time control method is applied to the buck converter. The circuit can automatically adjust the on-time according to the input voltage and output voltage, thereby keeping the duty cycle unchanged, and thus keeping the switching frequency basically unchanged. In the existing adaptive on-time circuit, since the switching frequency is related to the specific values ​​of electronic components such as internal resistors and capacitors, once integrated in the circuit, its switching frequency can only be maintained at a fixed value, and the switching frequency cannot be adjusted to adapt to various scenarios. In addition, due to the influence of process, voltage, and temperature, its actual switching frequency has a certain deviation.

[0026] A multiphase buck converter is a group of step-down power devices connected in parallel. A single-channel buck converter has only a single output and can only power a single load. Compared with a single-phase buck converter, a multiphase buck converter has the advantages of reducing input capacitance, output capacitance, and improving thermal performance under high load, making it the default choice for high-power, high-performance applications. A multichannel buck converter has multiple outputs and can have independent input and output voltages, powering each module separately without affecting each other. Different channels can also be connected to each other, with a higher performance mode of operation. For example, when a dual-channel buck converter is coupled to the same output, ensuring that the switching frequency phase of the two channels is 180° can increase the load capacity and reduce the output voltage ripple. In a higher phase working mode, more channels are required. Due to circuit area considerations, the number of channels of a single buck converter will not be too many, so it is necessary for multiple buck converters to be able to output in parallel to further improve the load capacity and reduce the output voltage ripple.

[0027] To this end, the present invention provides a buck converter, comprising: A phase-locked loop circuit, wherein an external clock access terminal of the phase-locked loop circuit is used to access an external clock signal, and a frequency adjustment input terminal of the phase-locked loop circuit is used to access a frequency modulation element; the phase-locked loop circuit is used to generate a frequency modulation current signal and a synchronous clock signal according to the received external clock signal and the frequency adjustment value output by the frequency modulation element; At least one channel circuit, the clock signal input end of the channel circuit is connected to the synchronous clock output end of the phase-locked loop circuit, the voltage input end of the channel circuit is used to access an external power supply, and the voltage output end of the channel circuit is used to access a load; the channel circuit is used to receive and output the voltage connected to the external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency-modulated current signal.

[0028] More specifically, in order to enable the buck converter to adjust the operating frequency over a wide frequency and have the ability to adjust to reduce the influence of factors such as process, voltage, temperature, etc., the present invention proposes a DC-DC buck converter, which includes a phase-locked loop circuit (PLL) and at least one channel (n channels, n is an integer greater than or equal to 1).

[0029] The first PLL circuit 101 generates a frequency-modulated current signal IPLL and synchronous clock signals CLK1, CLK2...CLKn required by each channel, and a certain phase difference is maintained between the synchronous clock signals CLK1, CLK2...CLKn of different channels; each channel receives the synchronous clock signal, the frequency-modulated current signal IPLL and the input voltage VIN of the external power supply, and the output voltage signal VOUT of the voltage output terminal.

[0030] The first PLL circuit 101 has an external clock access terminal (port MODE) connected to an external clock signal or directly grounded, and a frequency adjustment input terminal (port RT) connected to a frequency modulation element, thereby generating a clock signal CLK and a frequency modulation current signal IPLL. Port MODE can be connected to an external clock or to ground. When connected to an external clock, the output clock signal is synchronized with the external clock. When grounded, the output clock is controlled by the frequency modulation element connected to port RT.

[0031] The port MODE is grounded, and the switching frequency is controlled by an external frequency modulation element. The oscillator 14 in the first PLL circuit 101 generates a synchronous clock signal CLK according to the port RT, and the frequency modulation current generating module in the first PLL circuit 101 receives the RT signal to generate a frequency modulation current signal IPLL, which is inversely proportional to the frequency modulation element RT (the frequency modulation element is preferably a resistor), and the frequency modulation current signal IPLL is proportional to the frequency of the output synchronous clock signal CLK.

[0032] PLL is a feedback control system that locks the phase of the input signal and generates an output signal that is synchronized with the input signal frequency and phase. It mainly consists of three parts: phase detector, filter and oscillator. When the phase difference between the input signal and the VCO output signal is not zero, the phase detector will generate an error signal. After the error signal is filtered by the loop filter, a smooth DC control voltage is obtained.

[0033] This control voltage acts on the VCO, causing the frequency and phase of its output signal to change to reduce the phase difference with the input signal. When the phase difference is reduced to zero, the system reaches a locked state, at which point the frequency and phase of the VCO output signal are completely synchronized with the input signal.

[0034] In the present invention, a selection switch 13, a frequency divider 15 and a frequency modulation current generating circuit 16 are additionally provided in the first PLL circuit 101. The establishment of the selection switch 13 enables the first PLL circuit 101 to select whether the switching frequency is controlled by an external frequency modulation element or an external clock signal. When the switching frequency of the PLL circuit needs to be precisely controlled, the external frequency modulation element control mode can be selected, and when synchronization with an external clock signal needs to be achieved, the external clock signal control mode can be selected.

[0035] The frequency divider 15 can divide the synchronous clock signal output by the oscillator into several synchronous clock signals. The buck converter can form a multi-channel buck converter (one synchronous clock signal for one channel) or connect multiple buck converters in parallel (the synchronous clock signal of the previous buck converter is input to the clock signal of the next buck converter) based on the frequency division.

[0036] The frequency modulated current generating circuit 16 generates a frequency modulated current signal IPLL through an operational amplifier based on the frequency adjustment value output by the selection switch 13. When the selection switch 13 selects the phase-locked loop circuit to access the external clock signal, the frequency adjustment value is a fixed voltage after passing through the LPF; when the selection switch 13 selects the external frequency modulating element, the frequency modulated current generating circuit 16 receives the RT signal to generate, which is inversely proportional to the frequency modulating element RT, and the frequency modulated current signal IPLL is proportional to the frequency of the output synchronous clock signal CLK. The frequency modulated current signal IPLL is used for the switching frequency of the channel circuit, so that the operating frequency of the buck converter is not limited to one frequency.

[0037] The channel circuit receives and outputs the voltage connected to the external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency-modulated current signal. It includes a logic circuit, a switch circuit for turning on / off the connection between the external power supply and the output voltage, and a signal processing circuit that receives the synchronous clock signal and the frequency-modulated current signal. The signal processing circuit processes the synchronous clock signal and the frequency-modulated current signal and feeds them back to the logic circuit. The logic circuit sends a signal to the switch circuit according to the received signal to turn on / off the connection between the external power supply and the output voltage, thereby controlling the switching frequency of the buck converter.

[0038] The present invention includes a phase-locked loop circuit and a channel circuit. The channel circuit generates a frequency-modulated current signal and a synchronous clock signal according to the phase-locked loop circuit, and outputs the voltage connected to the external power supply at a corresponding output frequency, so that the working frequency of the buck converter is not limited to one frequency, but can be adjusted within a wide range. At a determined working frequency, its working frequency will not be affected by working conditions such as input voltage and output voltage.

[0039] In one embodiment, if Figure 1 As shown, Figure 1 The number of channel circuits of the first dual-channel buck converter 200 is two; The phase-locked loop circuit is specifically used to output a first synchronous clock signal and a second synchronous clock signal; the first synchronous clock signal and the second synchronous clock signal are received by two channel circuits respectively; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 180°.

[0040] The first dual-channel buck converter 200 includes a first PLL circuit 101, a channel 1 201, and a channel 2 202; the port MODE of the first PLL circuit 101 receives an external synchronization clock, and the port RT is externally connected to an external resistance element; the channel 1 201 and the channel 2 202 respectively have input ports for receiving a first input voltage VIN1 and a second input voltage VIN2, and output ports VOUT1 and VOUT2 respectively output a first output voltage and a second output voltage, and are connected to a load.

[0041] Ports VFB1 and VFB2 detect the first output voltage and the second output voltage respectively, and ports SW1 and SW2 are connected to the outputs of inductors L1 and L2 respectively. Channel 1 201 has an input terminal receiving a first input voltage VIN1, a first clock signal CLK1, a current frequency modulation signal IPLL, and an output port VOUT1, a port SW1, and VFB1. The first clock signal CLK1 is used as a synchronous clock signal of channel 1 201, and the current frequency modulation signal IPLL regulates the conduction time to control the switching frequency of channel 1 201. Similarly, channel 2 202 has an input terminal receiving a second input voltage VIN2, a second clock signal CLK2, a current frequency modulation signal IPLL, and an output port VOUT2, a port SW2, and VFB2. The second clock signal CLK2 is used as a synchronous clock of channel 2 202, and the current frequency modulation signal IPLL regulates the conduction time to control the switching frequency of channel 2 202.

[0042] Those skilled in the art will appreciate that the dual-channel buck converter illustrated here is only an example, and a multi-channel buck converter may have n channels, where n is an integer greater than or equal to 1.

[0043] In the first dual-channel buck converter 200, each channel can independently receive input voltage and output voltage. The values ​​and sources of different input voltages VIN1 and VIN2 can be independent and different, which is very important when energy needs to be shared between two power supplies. The values ​​of the output voltages VOUT1 and VOUT2 and the load current can be different, and multiple circuit modules can be powered independently to meet different needs.

[0044] In one embodiment, the outputs of the first dual-channel buck converter 200 are coupled together to operate in two phases to supply power to a load. Figure 1As shown, the circuit is composed of a first dual-channel buck converter 200 and an output load. The values ​​and sources of different input voltages VIN1 and VIN2 can be independent and different, the input port MODE is grounded, the port RT is externally connected to a resistor element, the frequency is controlled by the external resistor element, and is inversely proportional to the resistance. The frequency-modulated current signal IPLL is proportional to the frequency. The output voltages VOUT1 and VOUT2 are coupled together at the same node, and multiple channels have only one output. When working in two phases, the first PLL circuit 101 outputs clock signals CLK1 and CLK2 with the same frequency and a phase difference of 180°. The operating frequency of channel one 201 is synchronized with the first clock signal CLK1, and the operating frequency of channel two 202 is synchronized with the second clock signal CLK2. Therefore, the operating frequency of channel one 201 is the same as the operating frequency of channel two 202, and the phase difference is 180°. Since the operating frequencies differ by 180° in phase, when the first dual-channel buck converter 200 operates in two phases, channel one 201 is charging the load while channel two 202 is discharging, and vice versa when channel one 201 is discharging the load while channel two 202 is charging, the voltage ripple is greatly reduced, and the load capacity is doubled, thereby improving the performance.

[0045] Therefore, even when powering a single circuit, each channel can be coupled to work in multiple phases, greatly improving performance. In addition, energy can be shared between the two channels, and the power of the input voltage VIN1 is output to the load through channel one 201, and can also be coupled to channel two 202 through the output.

[0046] In one embodiment, multiple buck converters are connected in parallel to operate. The synchronous clock output terminal of the phase-locked loop circuit in the previous first dual-channel buck converter 200 is electrically connected to the external clock input terminal of the next second dual-channel buck converter 300. The first PLL circuit 101 in the previous first dual-channel buck converter 200 outputs a clock signal CLKOUT which is transmitted to the second PLL circuit 102 in the next second dual-channel buck converter 300 connected in parallel. The clock signal CLKOUT maintains a consistent operating frequency while having a certain phase difference, so that different buck converters can synchronize operating frequencies and adjust phases to achieve parallel multi-phase operation.

[0047] Alternatively, the external clock input terminal of the phase-locked loop circuit in each buck converter is used to access the same external clock signal.

[0048] The output port of the first PLL circuit 101 outputs a clock signal CLKOUT, which has the same frequency as the MODE input clock and a constant phase difference. Figure 1As shown, the first dual-channel buck converter 200 has the same structure as the second dual-channel buck converter 300, and the second dual-channel buck converter 300 includes a second PLL circuit 102, a channel three 301, and a channel four 302. In one embodiment, two first dual-channel buck converters 200 and second dual-channel buck converters 300 are connected in parallel to work in four phases, supplying power to the same load, and the phase difference between CLKOUT and MODE is 90°. The circuit is composed of the first dual-channel buck converter 200 and the output load. The input signal MODE of the first dual-channel buck converter 200 is coupled to the external synchronous clock signal, and the frequency is controlled by the external synchronous clock. At the same time, the output clock signal CLKOUT is coupled to the input port MODE of the second dual-channel buck converter 300. The clock frequency of CLKOUT is the same as that of CLK, and the phase difference is 90°. Since the clock signals CLK1 and CLK2 differ by 180° inside the second dual-channel buck converter 300 and the clock signals CLK3 and CLK4 differ by 180° inside the second dual-channel buck converter 300, CLK1, CLK3, CLK2, CLK4 have the same frequency and differ by 90° in phase with each other.

[0049] Each channel has an input port to receive input voltages VIN1, VIN2, VIN3, and VIN4 respectively. The output ports VOUT1~VOUT4, ports VFB1~VFB4, and inductors L1~L4 of each channel are coupled together to power the same load. Energy is shared among the four channels. In the four-phase working mode, since the four channels are connected in parallel, the outputs are coupled together, the switching clock frequencies are the same and the phases are 90° apart, and the charging and discharging times of different channels are staggered, the output voltage ripple is reduced to one-fourth of the original, the load capacity is four times the original, and the performance is greatly improved.

[0050] In one embodiment, the phase-locked loop circuit comprises: A selection switch 13, one end of which is electrically connected to an external clock access terminal or a frequency modulation element, and the other end of which is electrically connected to an oscillator 14 and a frequency modulation current generating circuit 16; the selection switch 13 is used to select a frequency adjustment value for the phase-locked loop circuit to access an external clock signal or an output of a frequency modulation element; An oscillator 14 is used to receive the frequency adjustment value output by the frequency modulation element and output a synchronous clock signal or output a synchronous clock signal according to an external clock signal; The frequency modulated current generating circuit 16 is used to receive the frequency adjustment value output by the frequency modulating element and output a frequency modulated current signal or output a frequency modulated current signal according to an external clock signal.

[0051] The phase and frequency detector 11 is electrically connected to the external clock access terminal, and is used to receive the external clock signal and compare the frequency error between the external clock signal and the synchronous clock signal, and output it to the low-pass filter 12; A low-pass filter 12, the input end of the low-pass filter 12 is electrically connected to the frequency and phase detector 11, and the output end is connected to the selection switch 13; the low-pass filter 12 is used to convert the received frequency error into a voltage; The frequency divider 15 is electrically connected to the frequency detector 11 and the oscillator 14. The frequency divider 15 is used to divide the synchronous clock signal output by the oscillator 14 into multiple synchronous clock signals.

[0052] Figure 2 for Figure 1 Detailed circuit diagram of the first PLL circuit 101 in FIG. Figure 2 As shown, the first PLL circuit 101 includes a phase frequency detector (PFD) 11 , a low pass filter (LC) 12 , a selection switch 13 , an oscillator 14 , a frequency divider 15 , and a frequency modulation current generating circuit 16 .

[0053] The first PLL circuit 101 has two paths, namely a MODE path and an RT path, wherein the MODE path includes a phase frequency detector 11 (PFD), a low-pass filter 12 (LC), a selection switch 13, an oscillator 14, a frequency divider 15, and a frequency modulation current generating circuit 16; The RT path includes a resistor element, a selection switch 13, an oscillator 14, a frequency divider 15, and a frequency modulation current generating circuit 16. The path is controlled by the selection switch 13, and the port MODE access signal is used as a control signal. When the port MODE is connected to an external clock, the selection switch 13 is connected to the MODE path, and when the port MODE is grounded, the selection switch 13 is connected to the RT path.

[0054] In one embodiment, the outputs of the first dual-channel buck converter 200 are coupled together for two-phase operation, the port MODE is grounded, and the switching frequency is controlled by an external resistor element. The port MODE is grounded, and the selection switch 13 is connected to the RT path. The oscillator 14 generates a clock signal f according to the port RT, which is input to the frequency divider 15 to generate the signal CLK and the output signals CLK1, CLK2, and CLKOUT. The frequency modulated current generating module 16 receives the RT signal to generate a frequency modulated current signal IPLL, which is inversely proportional to the resistor RT, and IPLL is proportional to the frequency of the output signals CLK1, CLK2, and CLKOUT.

[0055] In one embodiment, the outputs of the first dual-channel buck converter 200 and the second dual-channel buck converter 300 are coupled together, and the four-phase operation is paralleled. The port MODE is connected to the external synchronous clock, and the operating frequency of each buck converter is synchronized with the external clock. When the port MODE is connected to the external synchronous clock, the selection switch 13 is connected to the MODE path. The frequency detector 11 compares the frequency error between the external signal and the clock signal CLK output by the frequency divider 15, and converts it into a voltage through the low-pass filter 12 and outputs it to the selection switch 13. The oscillator 14 receives the voltage to generate the clock signal f, which is input to the frequency divider 15 to generate the signal CLK and the output signals CLK1, CLK2, and CLKOUT. The frequency-modulated current generating module 16 receives the output voltage of the low-pass filter 12 to generate the frequency-modulated current signal IPLL, which is proportional to the frequency.

[0056] In one embodiment, if Figure 3 As shown, the channel circuit includes: A switch circuit, wherein the input end of the switch circuit is used to connect to an external power supply; the switch circuit is used to turn on / off the connection between the external power supply and the voltage output end; A feedback loop 23, wherein the input end of the feedback loop 23 is electrically connected to the voltage output end; the feedback loop 23 is used to output a feedback signal; The on-time generating circuit 24 has an input terminal connected to the synchronous clock signal, the frequency modulated current signal, the voltage of the external power supply, and the output voltage of the voltage output terminal; the on-time generating circuit 24 is used to receive and output the on-time signal according to the synchronous clock signal, the frequency modulated current signal, the voltage of the external power supply, and the output voltage of the voltage output terminal; The logic circuit and the driving circuit 22 are electrically connected to the switch circuit, the feedback loop 23 and the on-time generating circuit 24; the logic circuit and the driving circuit 22 are used to receive and output a control signal according to the on-time signal and the feedback signal to control the switch circuit to turn on / off the connection between the external power supply and the voltage output terminal.

[0057] Figure 3 Schematic diagram of channel 1 201 of a buck converter. Each channel includes a switch module 21, a logic circuit and a driving circuit 22, a feedback loop 23, and an on-time generating circuit 24. The logic circuit and the driving circuit 22 receive a feedback signal Toff from the feedback loop 23 and an on-time signal Ton output by the on-time generating circuit 24, and drive the switch module 21 to convert the input voltage VIN into a constant output voltage VOUT by controlling the on and off of the tube.

[0058] The switch module 21 converts the input voltage VIN into a constant output voltage VOUT by controlling the on and off of the tube. The logic circuit and the driving circuit 22 receive the feedback signal Toff of the feedback loop 23 and the output signal Ton of the on-time generating circuit 24, and drive the on and off of the first switch tube 41 and the second switch tube 42 of the switch module 21. The on-time generating circuit 24 has an input port for receiving the input voltage VIN, the output voltage VOUT, the frequency modulation current signal IPLL, and the synchronous clock CLK1. The synchronous clock CLK1 is generated by the first PLL circuit 101, and the on-time signal Ton is a square wave signal output by the on-time generating circuit 24. The output on-time signal Ton determines the length of the charging time.

[0059] In one embodiment, the on-time generating circuit 24 includes: An input voltage-to-current circuit, wherein an input end of the input voltage-to-current circuit is electrically connected to a voltage of an external power supply; the input voltage-to-current circuit is used to convert an input voltage into a first current signal; An error current generating circuit, wherein the input end of the error current generating circuit is connected to the synchronous clock signal and the conduction time signal; the error current generating circuit is used to compare the conduction time signal and the synchronous clock signal and output the error current; A current multiplier 54, the current multiplier 54 is electrically connected to the error current generating circuit, the voltage-to-current circuit and the conduction signal flipping circuit; the current multiplier 54 is used to receive and output a second current signal according to the frequency-modulated current signal, the error current and the first current signal; The conduction signal flip circuit has an input terminal electrically connected to the current multiplier 54 and the output voltage of the voltage output terminal; the conduction signal flip circuit is used to receive and output a conduction time signal according to the second current signal and the output voltage.

[0060] The on-time generating circuit 24 has an input port for receiving an input voltage VIN, an output voltage VOUT, a frequency-modulated current signal IPLL, and a synchronous clock CLK1. The synchronous clock CLK1 is generated by the first PLL circuit 101. The on-time signal Ton is a square wave signal output by the on-time generating circuit 24. The output on-time signal Ton determines the length of the charging time.

[0061] Figure 4 FIG. 2 is a circuit schematic diagram of the conduction time generating circuit 24. Figure 4 As shown, the on-time generating circuit 24 includes an input voltage-to-current conversion module 501 , a conduction signal flipping module 502 , an error current generating module 503 and a current multiplier 54 .

[0062] The input voltage-to-current module 501 includes voltage-dividing resistors R1 and R2, and a voltage feedback structure. The voltage feedback structure includes an operational amplifier, a MOS tube M1, a resistor R3, and a current mirror. The positive end of the operational amplifier inputs the voltage obtained by voltage division of VIN, the negative end input is coupled to the first end of the resistor R3 and the source of the MOS tube M1, the output end is coupled to the gate of the MOS tube, the second end of the resistor R3 is grounded, and the MOS tube M1, the resistor R3, and the current mirror form an output branch; the voltage-dividing resistors R1 and R2 are connected in series to divide the input voltage VIN to obtain , and input to the operational amplifier, the voltage feedback structure ensures that the voltage drop across the resistor R3 is equal to the voltage input to the operational amplifier. Specifically, the input voltage to current module 501 outputs a current signal proportional to the input voltage VIN .

[0063] The conduction signal flip module 502 includes a charging capacitor CTON, a switch and a voltage comparator. The positive input of the voltage comparator is connected to the output voltage VOUT, the negative input is connected to the first end of the charging capacitor CTON, and the output signal Ton. The switch is controlled by the output signal Ton. When charging, the switch is disconnected, the current I charges the charging capacitor CTON, and the voltage at the first end of the charging capacitor CTON rises. When the voltage is higher than VOUT, the voltage comparator output signal Ton flips, the switch closes, and the voltage at the first end of the charging capacitor CTON drops to zero. The flipped Ton signal is input to the logic circuit and the drive circuit 22 to control the switch module 21 from charging to discharging. The conduction time signal Ton controls the charging time, and the specific time Where I is the charging current, VOUT is the output voltage, and CTON is the charging capacitor.

[0064] The error current generating module 503 includes a phase detector 11, a charge pump module (PFD / CP), and a voltage feedback structure. The voltage feedback structure includes an operational amplifier, a MOS tube M2, and a resistor R4. The positive input of the operational amplifier is connected to the output of the phase detector 11 and the charge pump module, the negative input is coupled to the first end of the resistor R4 and the source of the MOS tube M2, the output end is coupled to the gate of the MOS tube, the second end of the resistor R3 is grounded, and the MOS tube M2 and the resistor R4 form an output branch; the phase detector 11 and the charge pump module compare the on-time signal Ton and the synchronous clock signal CLK1, and output the error voltage VCO. The voltage feedback structure ensures that the voltage drop at the resistor R4 is equal to the error signal VCO, and the error current generating module 503 outputs an error current proportional to the error signal VCO. .

[0065] The frequency modulated current signal IPLL comes from the first PLL circuit 101 and is synchronized with the frequency of the external clock. is proportional to * , where k1 is a constant, The current multiplier 54 multiplies the input current (IPLL+ICO) and Ivin and outputs the multiplied current.

[0066] The conventional conduction circuit module only includes an input voltage-to-current conversion module 501 and a conduction signal flip module 502. Charging current I=Ivin, conduction time , where k2 is a constant related to the internal resistance and capacitance components, is the duty cycle. Therefore, the switching frequency , the switching frequency is determined by internal components. For the integrated conduction circuit module, its switching frequency cannot be adjusted by external components or signals. Due to the influence of process, power supply voltage and temperature, the actual operating frequency also has deviations. Some circuits only use charge pumps to modulate the charging current ICO to adjust the operating frequency, but this structure has a limited adjustable frequency range and cannot guarantee high-precision channel synchronization.

[0067] The conduction time generating circuit 24 of the present invention includes, in addition to the input voltage-to-current module 501 and the conduction signal flipping module 502, an error current generating module 503 and a current multiplier 54. The frequency modulated current signal IPLL and the error current output by the error current generating module 503 are The two currents are added and input to the current multiplier 54. The current multiplier 54 multiplies the two input currents to output the current I = Ivin*(IPLL+ ), as the charging current of the conduction signal flip module 502.

[0068] On time ; The on-time is proportional to the duty cycle D and the external synchronous clock frequency Inversely proportional to the switching frequency .

[0069] In general, k1*k2≈1, Numerically greater than , the operating frequency of the buck converter , the switching frequency is modulated in a large amplitude so that the switching frequency is substantially equal to the synchronous clock. The error voltage VCO output by the frequency detector 11 and the charge pump module detects the error between the switching frequency and the synchronous clock frequency, and further fine-tunes the switching frequency within a small amplitude so that the switching frequency of the channel is the same as the synchronous clock frequency, while ensuring phase lock. The switching frequency is the same as the synchronous clock frequency and the phase lock enables the buck converter to operate in multiple phases. In one embodiment, two channels of a single buck converter are coupled to operate in two phases. In one embodiment, two buck converters are coupled in parallel and output, and synchronized with the external clock signal to operate in four phases.

[0070] In one embodiment, the switching circuit includes a first switching tube and a second switching tube, the source of the first switching tube is connected to an external power supply, the drain is connected to the drain of the second switching tube and one end of the inductor as a SW node, the other end of the inductor is electrically connected to the output end of the channel circuit, the gates of the first switching tube and the second switching tube are electrically connected to the logic circuit and the drive circuit 22, and the source of the second switching tube is grounded.

[0071] The switch module 21 converts the input voltage VIN into a constant output voltage VOUT by controlling the on and off of the tube. The switch module 21 includes a first switch tube 41 and a second switch tube 42. The source of the first switch tube 41 is connected to the input voltage VIN, the drain of the first switch tube 41 is connected to the drain of the second switch tube 42 and the first end of the inductor L as a SW node, the second end of the inductor L is connected to the first end of the resistor Rfb2 and generates an output voltage VOUT, the second end of the resistor Rfb2 is connected to the first end of the resistor Rfb1 to generate a feedback voltage VFB, and the second end of the resistor Rfb1 is grounded; the gates of the first switch tube 41 and the second switch tube 42 are both connected to the logic circuit and the drive circuit 22.

[0072] Specifically, when the switch module 21 receives the charge-on signal from the logic circuit and the drive circuit 22, the first switch tube 41 is turned on, the second switch tube 42 is turned off, the voltage at the SW node is ≈VIN, and the inductor current and the output voltage rise. When the switch module 21 receives the discharge-off signal from the logic circuit and the drive circuit 22, the first switch tube 41 is turned off, the second switch tube 42 is turned on, the voltage at the SW node is ≈0, and the inductor current and the output voltage decrease.

[0073] The logic circuit and driving circuit 22 receives the feedback signal Toff of the feedback loop 23 and the output on-time signal Ton of the on-time generating circuit 24 , and drives the first switch tube 41 and the second switch tube 42 of the switch module 21 to be turned on and off.

[0074] In one embodiment, the feedback loop 23 includes an error comparator and a current comparator, the input end of the error comparator is electrically connected to the reference voltage and the feedback voltage, the output end is electrically connected to the current comparator, the input end of the current comparator is electrically connected to the SW node, and the output end is electrically connected to the logic circuit and the driving circuit 22; An error comparator is used to compare a reference voltage with a feedback voltage, and output an error between the reference voltage and the feedback voltage to a current comparator; The current comparator is used for outputting a feedback signal when the inductor discharge ends according to the error between the inductor current signal at the SW node and the reference voltage and the feedback voltage.

[0075] The feedback loop 23 includes an error comparator (EA) 31 and a current comparator (ICMP) 32. The positive input of the error comparator 31 is connected to the reference voltage VREF, the negative input is connected to the feedback voltage VFB, and the error between the reference voltage and the feedback voltage is output. The reference voltage can come from a bandgap reference or an external signal, and the feedback voltage detects the output voltage. The positive input of the current comparator 32 is connected to the output of the error comparator 31, and the negative input is connected to the inductor current signal of the SW node. When the inductor L is discharged, the current comparator 32 outputs a high level Toff. The feedback loop 23 is turned on when the switch module 21 is in discharge, and the high level Toff is output when the threshold is reached, and the switch module 21 is switched from discharge to charging state.

[0076] The present invention also provides a power manager, including the buck converter as described above. The buck converter reduces the input voltage to the required output voltage to supply the load. The operating frequency of the buck converter included in the power manager of the present invention is not limited to one frequency, but can be adjusted within a wide range. At a determined operating frequency, the operating frequency will not be affected by operating conditions such as input voltage and output voltage.

[0077] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A buck converter, characterized in that: include: A phase-locked loop circuit, wherein an external clock input terminal of the phase-locked loop circuit is used to access an external clock signal, and a frequency adjustment input terminal of the phase-locked loop circuit is used to access a frequency modulation element; The phase-locked loop circuit is used to generate a frequency-modulated current signal and a synchronous clock signal according to the received external clock signal and the frequency adjustment value output by the frequency modulation element; At least one channel circuit, the clock signal input end of the channel circuit is connected to the synchronous clock output end of the phase-locked loop circuit, the voltage input end of the channel circuit is used to access an external power supply, and the voltage output end is used to access a load; the channel circuit is used to receive and output the voltage connected to the external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency-modulated current signal.

2. The buck converter according to claim 1, characterized in that: The number of the channel circuits is two; The phase-locked loop circuit is specifically used to output a first synchronous clock signal and a second synchronous clock signal; the first synchronous clock signal and the second synchronous clock signal are received by two channel circuits respectively; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 180°.

3. The buck converter according to claim 1, characterized in that: The buck converters are connected in parallel to work in multiple The synchronous clock output terminal of the phase-locked loop circuit in the previous buck converter is electrically connected to the external clock input terminal of the next buck converter; Alternatively, the external clock input terminal of the phase-locked loop circuit in each of the buck converters is used to access the same external clock signal.

4. The buck converter according to any one of claims 1 to 3, characterized in that: The phase-locked loop circuit comprises: A selection switch, one end of which is electrically connected to an external clock access terminal or a frequency modulation element, and the other end of which is electrically connected to an oscillator and a frequency modulation current generating circuit; the selection switch is used to select a frequency adjustment value for the phase-locked loop circuit to access an external clock signal or an output of the frequency modulation element; An oscillator, used to receive the frequency adjustment value output by the frequency modulation element, and output a synchronous clock signal or output a synchronous clock signal according to an external clock signal; The frequency modulated current generating circuit is used to receive the frequency adjustment value output by the frequency modulated element and output a frequency modulated current signal or output a frequency modulated current signal according to an external clock signal.

5. The buck converter according to claim 4, characterized in that: The phase-locked loop circuit also includes: A frequency and phase detector is electrically connected to the external clock access terminal, and is used to receive an external clock signal and compare the frequency error between the external clock signal and the synchronous clock signal, and output it to a low-pass filter; A low-pass filter, wherein the input end of the low-pass filter is electrically connected to the frequency and phase detector, and the output end is connected to the selection switch; the low-pass filter is used to convert the received frequency error into a voltage; The frequency divider is electrically connected to the frequency detector and the phase detector and the oscillator; the frequency divider is used to divide the synchronous clock signal output by the oscillator into multiple synchronous clock signals.

6. The buck converter according to any one of claims 1 to 3, characterized in that: The channel circuit comprises: A switch circuit, wherein the input end of the switch circuit is used to connect to an external power supply; the switch circuit is used to turn on / off the connection between the external power supply and the voltage output end; A feedback loop, wherein the feedback loop input end is electrically connected to the voltage output end; the feedback loop is used to output a feedback signal; A conduction time generating circuit, wherein the input end of the conduction time generating circuit is connected to a synchronous clock signal, a frequency modulated current signal, a voltage of an external power supply, and an output voltage of a voltage output end; the conduction time generating circuit is used to receive and output a conduction time signal according to the synchronous clock signal, the frequency modulated current signal, the voltage of an external power supply, and the output voltage of the voltage output end; The logic circuit and the driving circuit are electrically connected to the switch circuit, the feedback loop and the on-time generating circuit; the logic circuit and the driving circuit are used to receive and output a control signal according to the on-time signal and the feedback signal to control the switch circuit to turn on / off the connection between the external power supply and the voltage output terminal.

7. The buck converter according to claim 6, characterized in that: The on-time generating circuit comprises: An input voltage-to-current circuit, wherein an input end of the input voltage-to-current circuit is electrically connected to a voltage of an external power supply; the input voltage-to-current circuit is used to convert an input voltage into a first current signal; An error current generating circuit, wherein the input end of the error current generating circuit is connected to the synchronous clock signal and the conduction time signal; the error current generating circuit is used to compare the conduction time signal and the synchronous clock signal and output the error current; A current multiplier, the current multiplier is electrically connected to the error current generating circuit, the voltage-to-current circuit and the conduction signal flipping circuit; the current multiplier is used to receive and output a second current signal according to the frequency modulated current signal, the error current and the first current signal; A conduction signal flipping circuit, wherein the input end of the conduction signal flipping circuit is electrically connected to the output voltage of the current multiplier and the voltage output end; the conduction signal flipping circuit is used to receive and output a conduction time signal according to the second current signal and the output voltage.

8. The buck converter according to claim 6, characterized in that: The switch circuit includes a first switch tube and a second switch tube, the source of the first switch tube is connected to an external power supply, the drain is connected to the drain of the second switch tube and one end of the inductor as a SW node, the other end of the inductor is electrically connected to the output end of the channel circuit, the gates of the first switch tube and the second switch tube are electrically connected to the logic circuit and the drive circuit, and the source of the second switch tube is grounded.

9. The buck converter according to claim 6, characterized in that: The feedback loop includes an error comparator and a current comparator, the error comparator input terminal is electrically connected to a reference voltage and a feedback voltage, the output terminal is electrically connected to the current comparator, the current comparator input terminal is electrically connected to a SW node, and the output terminal is electrically connected to a logic circuit and a driving circuit; The error comparator is used to compare the reference voltage with the feedback voltage, and output the error between the reference voltage and the feedback voltage to the current comparator; The current comparator is used to output a feedback signal when the inductor discharge ends according to the error between the inductor current signal at the SW node and the reference voltage and the feedback voltage.

10. A power manager, characterized in that: Comprising a buck converter as claimed in any one of claims 1 to 9.

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