Enabling regeneration circuit, radio frequency chip and enabling regeneration routing method
By designing an enable regeneration circuit including an out-of-order enable regeneration receiver, a delay logic circuit and a signal detection filter circuit in the RF chip, the problem of large power consumption and inability to filter in the prior art is solved, and low power consumption and signal stable output is achieved.
Patent Information
- Application Number
- CN202311297306.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-08
- Publication Date
- 2025-04-15
AI Technical Summary
The enable regeneration circuits in existing RF chips consume a large power and cannot filter the output signal, resulting in the incompatibility of the input signal being sent to the output terminal.
An enable regeneration circuit is designed, including an out-of-order enable regeneration receiver, a delay logic circuit and a signal detection filter circuit. The out-of-order enable regeneration receiver is used to select multiple out-of-order enable signals, the delay logic circuit is used to delay processing of the selected signals, and the signal detection filtering circuit is used to filter the output signal.
Through this design, the power consumption of enabling regeneration circuits is reduced, and invalid glitch signals are avoided to be transmitted to the subsequent circuit, ensuring the effectiveness and stability of the output signal.
Smart Images
Figure CN119834818A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of communications, and in particular to a regeneration-enabled circuit, a radio frequency chip, and a regeneration-enabled routing method. Background Art
[0002] The RF chip needs to perform on-chip communication for multi-channel signals. In the related technology, the enabling regeneration circuit in the common multi-channel RF chip lacks a low-power structure, and the regeneration circuit cannot be turned off when not working. It also has no filtering function, and there is a problem that the input signal that does not meet the requirements is sent to the output end. Summary of the invention
[0003] The embodiments of the present invention provide a regeneration enabling circuit, a radio frequency chip and a regeneration enabling routing method, so as to at least solve the problem in the related art that the regeneration enabling circuit has high power consumption and cannot filter the output signal.
[0004] According to one embodiment of the present invention, there is provided an enabling regeneration circuit, comprising: an out-of-order enabling regeneration receiver, used to select multiple out-of-order enabling signals; a delay logic circuit, used to perform delay processing on the out-of-order enabling signal selected by the out-of-order enabling regeneration receiver to obtain an enabling regeneration routing signal; and a signal detection filter circuit, used to perform filtering processing on the enabling regeneration routing signal to obtain an enabling regeneration output signal.
[0005] According to another embodiment of the present invention, a radio frequency chip is provided, comprising the enabling regeneration circuit described in any one of the above embodiments, wherein the enabling regeneration circuit performs selection processing, delay processing, and filtering processing on the input signal of the radio frequency chip to obtain an enabling regeneration output signal.
[0006] According to another embodiment of the present invention, there is also provided a method for enabling regeneration routing, which adopts the enabling regeneration circuit described in any of the above embodiments, including: the out-of-order enabling regeneration receiver selects and conducts multiple out-of-order enabling signals of the chip under the enable control of the selection configuration register; the out-of-order enabling signal selected by the out-of-order enabling regeneration receiver enters the delay logic circuit through the switch control logic circuit; the delay logic circuit delays the out-of-order enabling signal to obtain an enabling regeneration routing signal; the signal detection filter circuit filters the enabling regeneration routing signal to obtain an enabling regeneration output signal.
[0007] The present invention provides an enabling regeneration circuit, comprising: an out-of-order enabling regeneration receiver for selecting multiple out-of-order enabling signals; a time delay logic circuit for delaying the out-of-order enabling signals selected by the out-of-order enabling regeneration receiver to obtain an enabling regeneration routing signal; and a signal detection filter circuit for filtering the enabling regeneration routing signal to obtain an enabling regeneration output signal. The invention solves the problem that the enabling regeneration circuit in the related art has high power consumption and cannot filter the output signal, and achieves the effect of reducing the power consumption of the enabling regeneration circuit and preventing invalid burr signals from being transmitted to the subsequent circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 is a schematic diagram of the structural principle of a regeneration enabling circuit according to an embodiment of the present invention;
[0009] Figure 2 is a schematic diagram of a single channel selection principle according to an embodiment of the present invention;
[0010] Figure 3 is a schematic diagram of the structure of a signal detection filter circuit according to an embodiment of the present invention;
[0011] Figure 4 is a flow chart of a method for enabling regenerative routing according to an embodiment of the present invention;
[0012] Figure 5 is a schematic diagram of a signal output principle of a switch configuration register according to a scenario embodiment of the present invention;
[0013] Figure 6 is a schematic diagram of the delay configuration principle according to a scenario embodiment of the present invention;
[0014] Figure 7 It is a schematic diagram of the configuration principle of the detection configuration register in the related art;
[0015] Figure 8 is a schematic diagram of the configuration principle of the detection configuration register implemented according to the scenario of the present invention;
[0016] Fig. 9 This is an example of enabling regeneration circuit application according to an embodiment of the present invention. Figure 1 ;
[0017] Fig.10 This is an example of enabling regeneration circuit application according to an embodiment of the present invention. Figure 2 . DETAILED DESCRIPTION
[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.
[0019] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0020] The embodiment of the present invention provides a regeneration enabling circuit. Figure 1 is a schematic diagram of the structural principle of the enabling regeneration circuit according to an embodiment of the present invention. Figure 1 As shown, it includes: an out-of-order enabling regeneration receiver, which is used to select multiple out-of-order enabling signals; a delay logic circuit, which is used to delay the out-of-order enabling signal selected by the out-of-order enabling regeneration receiver to obtain an enabling regeneration routing signal; a signal detection filter circuit, which is used to filter the enabling regeneration routing signal to obtain an enabling regeneration output signal.
[0021] In the actual implementation process, Figure 1 As shown, the low-power out-of-order enabled regenerative receiver (i.e., the above-mentioned out-of-order enabled regenerative receiver) selects multiple user-defined enable signals or baseband device signals, and cooperates with the mask configuration register (i.e. Figure 1 Mask0~N in the mask configuration register represent the mask configuration signals generated by the mask configuration register, which are used to mask the channels that do not need to be processed, and the mask polarity can be selected to avoid invalid flipping of subsequent circuits.
[0022] In an exemplary embodiment, the enable regeneration circuit provided by the embodiment of the present invention also includes: a synchronization circuit and an arbitrator, wherein the synchronization circuit is used to synchronize the out-of-order enable signal; the arbitrator is used to arbitrate the priorities of multiple transmission channels corresponding to the out-of-order enable signal to select a high-priority transmission channel to transmit the corresponding out-of-order enable signal.
[0023] In the actual implementation process, the out-of-order enabled regeneration receiver has built-in synchronization circuits and arbiters to switch multiple out-of-order inputs to prevent glitch signals generated during the switching process; it can also select a specified channel and automatically shield the inputs of other channels, directly reducing invalid channel signal flips.
[0024] In an exemplary embodiment, the enable regeneration circuit provided by the embodiment of the present invention further includes: further including: a selection configuration register for selectively shielding multiple transmission channels corresponding to the out-of-order enable signal.
[0025] Figure 2 is a schematic diagram of a single channel selection principle according to an embodiment of the present invention. Figure 2 As shown, in the actual implementation process, the mask configuration signal mask0 generated by the mask configuration register can be turned on or off by the selection configuration information number sel0 generated by the selection configuration register, and then the out-of-order enabled regeneration receiver is configured and controlled according to the selection situation. Figure 2 What is shown is only a single-channel structure. In the actual implementation process, there will be multiple channels, that is, multiple masking configuration signals mask0~N are generated in the above embodiment. In this case, one selection configuration register can be used to select and mask multiple transmission channels, or a corresponding number of selection configuration registers can be used to select and mask multiple transmission channels. No specific restrictions are made here.
[0026] In an exemplary embodiment, Figure 1 As shown, the enabling regeneration circuit provided by the embodiment of the present invention further includes: a switch control logic circuit, which is used to perform circuit processing operations on the out-of-order enabling signal selected by the out-of-order enabling regeneration receiver.
[0027] In the actual implementation process, the switch control logic circuit transmits, shuts down, sets to zero, and sets to 1 the signal selected by the multi-channel decoding selector (i.e., the above-mentioned out-of-order enabled regeneration receiver) according to the switch signal of the switch controller, thereby realizing the independent configuration of each channel, especially the independent shutdown function, which can reduce the power consumption of unnecessary channels.
[0028] In an exemplary embodiment, Figure 1 As shown, the enabling regeneration circuit provided in the embodiment of the present invention also includes: a switch controller and a switch configuration register, wherein the switch controller is used to provide a configuration effectiveness signal to the switch control logic circuit to configure the configuration instructions of the switch configuration register to be effective or isolated; the switch configuration register is used to provide switch enable configuration and switch polarity configuration to control the conduction and shutdown of the switch control logic circuit.
[0029] In actual implementation, the switch controller can control switch properties through software, and provides a configuration validation signal to release or isolate the global configuration. After isolation, the software configuration is no longer effective for the switch controller.
[0030] In an exemplary embodiment, Figure 1 As shown, the enabling regeneration circuit provided by the embodiment of the present invention also includes: a positive edge configuration register, which is used to perform positive edge delay processing on the out-of-order enable signal selected by the out-of-order enable regeneration receiver; and a negative edge configuration register, which is used to perform negative edge delay processing on the out-of-order enable signal selected by the out-of-order enable regeneration receiver.
[0031] In the actual implementation process, the delay logic circuit realizes the delayed transmission of the signal, and the rising edge and the falling edge are configured separately through the positive edge configuration register and the negative edge configuration register, and the rising edge and the falling edge can be delayed independently. In the actual implementation process, the delay configuration is divided into coarse delay configuration and fine delay configuration. The coarse delay configuration uses a divided clock for processing, and the delay accuracy is lower than that of the fine delay configuration, but it can achieve low-power timing.
[0032] In an exemplary embodiment, Figure 1 As shown, the enabling regeneration circuit provided in the embodiment of the present invention further includes: a detection configuration register, which is used to provide a detection threshold for the signal detection filter circuit to filter and shield the enabling regeneration routing signal that does not meet the detection threshold.
[0033] In the actual implementation process, the signal detection filter circuit detects the signal that finally completes the delay. The required detection threshold is configured in the detection configuration register. This component also uses the frequency division counting method to detect the pulse width output by the regeneration circuit, and shields the pulse that is less than the pre-configured filter width of the software to prevent invalid glitch signals from being transmitted to the subsequent circuit and introducing functional problems.
[0034] In an exemplary embodiment, the signal detection and filtering circuit for enabling a regeneration circuit provided in an embodiment of the present invention includes: a delay filter controller and a delay filter logic circuit, wherein the delay filter controller is used to generate a delay filter configuration signal according to the delay processing configuration signal of the positive edge configuration register and / or the negative edge configuration register; the delay filter logic circuit is used to perform delay processing and filtering processing on the enable regeneration routing signal according to the delay filter configuration signal.
[0035] Figure 3 is a schematic diagram of the structure of a signal detection filter circuit according to an embodiment of the present invention. Figure 3 As shown, the detection filter circuit includes a time delay filter controller and a time delay filter logic circuit, which has a time delay function and completes a filtering function without introducing an extra time delay, and has a filtering function while still maintaining the accuracy of the time delay function.
[0036] An embodiment of the present invention further provides a radio frequency chip, comprising the enabling regeneration circuit described in any of the above embodiments, wherein the enabling regeneration circuit performs selection processing, time delay processing, and filtering processing on the input signal of the radio frequency chip to obtain an enabling regeneration output signal.
[0037] It should be noted that the above-mentioned circuit structures can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above-mentioned circuit structures are integrated and designed in the same chip structure; or, the above-mentioned circuit structures are located in different chip structures in the form of any combination.
[0038] The embodiment of the present invention further provides a method for enabling regeneration routing, which is implemented by the enabling regeneration circuit described in any one of the above embodiments. Figure 4 is a flow chart of a method for enabling regenerative routing according to an embodiment of the present invention. Figure 4 As shown, including:
[0039] Step S402, the out-of-order enable regeneration receiver selects and turns on multiple out-of-order enable signals of the chip under the enable control of the selection configuration register;
[0040] Step S404, the out-of-order enable signal selected by the out-of-order enable regeneration receiver enters the delay logic circuit through the switch control logic circuit;
[0041] Step S406, the delay logic circuit performs delay processing on the out-of-order enable signal to obtain an enable regeneration routing signal;
[0042] Step S408: the signal detection filter circuit performs filtering processing on the regeneration-enabled routing signal to obtain a regeneration-enabled output signal.
[0043] In an exemplary embodiment, after the signal detection filter circuit filters the enable regeneration routing signal to obtain the enable regeneration output signal, the method further includes: the signal detection filter circuit detects the pulse width of the enable regeneration output signal using a frequency division counting method according to a detection threshold provided by a detection configuration register, and shields the enable regeneration output signal whose pulse width is less than the detection threshold.
[0044] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.
[0045] In order to enable those skilled in the art to better understand the technical solution of the present invention, it is described below in conjunction with specific scenario embodiments.
[0046] Scenario Example 1
[0047] The above-mentioned enabling regeneration circuit provided by the embodiment of the present invention can configure multiple configuration registers, including multiple selection configuration registers, switch configuration registers, positive edge configuration registers, negative edge configuration registers, detection configuration registers, etc. through software, and then implement the function by hardware circuit according to the configuration characteristics. The specific configuration method and configuration examples are as follows:
[0048] (1) Out-of-order enable regenerative receiver
[0049] It receives and processes multiple out-of-order enable signals, and shields the signals that do not meet the requirements, reducing the subsequent logic circuit flipping to reduce power consumption. The shielding mode is divided into active mode, passive mode and out-of-order mode. The active mode directly configures the mask signal of the channel, and the polarity of the shield can be selected by configuration to reduce the flipping of subsequent logic devices; the passive mode is when the sel configuration of the configuration register fixes the specified channel, other channels are shielded, and the polarity is determined by the mask of the specified channel transmitted to all channels; the out-of-order mode will turn on the arbitrator and arbitrate in the order of priority 0 to N. When the enable signal of the high-priority channel enters the routing, the logical effect is equivalent to turning on the channel designation function, which can shield other channels and complete the glitches that may be generated by shielding switching.
[0050] (2) Switch Configuration Register
[0051] The switch configuration register includes a switch enable configuration and a switch polarity configuration, and its configuration acts on the output out_sw of the switch control logic circuit. An example of the switch configuration register reg_sw is shown in Table 1.
[0052] Table 1 Switch configuration register reg_sw example table
[0053] reg_sw[1]=reg_sw_va reg_sw[0]=reg_sw_en out_sw not care 0 in 0 1 0 1 1 1
[0054] Figure 5 is a schematic diagram of the signal output principle of the switch configuration register according to a scenario embodiment of the present invention, such as Figure 5 As shown, when reg_sw_en is configured to 0, out_sw is equal to the value of the input signal in regardless of the value of reg_sw_va; when reg_sw_en is configured to 1, the value of out_sw will switch to the value equal to reg_sw_va, regardless of the value of the input signal in.
[0055] (3) Positive edge configuration register and negative edge configuration register
[0056] The positive edge configuration register and the negative edge configuration register can respectively delay the positive edge and the negative edge of the input signal of the delay logic circuit through the configured selected values Tpos and Tneg, and then output them. Figure 6 Schematic diagram of the delay configuration principle according to the scenario embodiment of the present invention. Figure 6As shown, when Tpos is configured, the rising edge of the output signal out will be delayed by the time represented by the Tpos configuration value relative to the rising edge of the input signal in; when Tneg is configured, the falling edge of the output signal out will be delayed by the time represented by the Tneg configuration value relative to the falling edge of the input signal in. The configuration register is divided into coarse delay configuration and fine delay configuration, and different frequency clocks are used for delay logic processing. When the delay requirement is not high, the coarse delay configuration can automatically start and switch to the divided frequency clock instead of the high frequency clock, which can greatly reduce the power consumption of the circuit.
[0057] (4) Detection configuration register
[0058] Figure 7 It is a schematic diagram of the configuration principle of the detection configuration register in the related technology, such as Figure 7 As shown, the detection configuration register is configured, the corresponding preset value Tlp is selected, the signal detection and filtering logic circuit input is detected and the filtering function is completed, and finally the filtered signal is output, such as Figure 7 As shown, the rising edge of the input signal in is delayed by Tpos (and Tneg) and converted to in_dly (its behavior is already described in Figure 6 Description), and then according to the Tlp configuration, the time length represented by the Tlp configuration value is filtered. In the figure, the left pulse width on the in_dly waveform is lower than the time represented by the Tlp configuration value. On the output signal out, this pulse will be filtered out and no longer output; the right pulse width on the in_dly waveform is greater than the time represented by the Tlp configuration value, then on the output signal out, this pulse will be output, and at the same time, this output pulse signal on the output signal out is delayed by the time represented by Tlp relative to the corresponding pulse signal of in_dly.
[0059] In the embodiment of the present invention, the filter and the delay circuit are connected as follows: Figure 3 Redesign shown. Figure 8 Schematic diagram of the configuration principle of the detection configuration register implemented according to the scenario of the present invention, such as Figure 8 As shown in the figure, the rising edge of the input signal in is delayed by Tpos (and Tneg) and converted to in_dly (dummy). Dummy means an abstract logical signal and is not necessarily actually generated. It is intended to indicate that the delay processing will be completed and is convenient for Figure 7 Contrast (its behavior has been Figure 6Description); then according to the Tlp configuration, the time length represented by the Tlp configuration value is filtered. If the left pulse width on the in_dly(dummy) waveform is lower than the time represented by the Tlp configuration value, this pulse will be filtered out on the output signal out and will no longer be output; if the right pulse width on the in_dly(dummy) waveform is greater than the time represented by the Tlp configuration value, this pulse will be output on the output signal out; this output pulse signal on the output signal out will not be delayed by the time represented by Tlp relative to the corresponding pulse signal of in_dly(dummy).
[0060] In the case of completing the delay and filtering functions, Figure 7 The configuration of the detection configuration register shown in the figure introduces a delay of the time represented by the Tlp configuration value between the output signal out and in_dly when processing the filtering function. In addition to the delay configured by Tpos and other configurations, an additional delay of the time represented by the Tlp configuration value is introduced between the output signal out and the input signal in. The overall delay time will no longer be determined by and only by Tpos (and Tneg); Figure 8 The configuration of the detection configuration register shown in the figure processes the filtering function simultaneously with the delay function, and no additional delay is introduced between the output signal out and in_dly (dummy), nor is an additional delay introduced between the output signal out and the input signal in. The overall delay time is determined by and only by Tpos (and Tneg).
[0061] Scenario Example 2
[0062] The enabling regeneration circuit provided in the embodiment of the present invention can be applied to a radio frequency chip to perform selection processing, time delay processing, and filtering processing on an input signal of the radio frequency chip to obtain an enabling regeneration output signal.
[0063] In actual implementation, there is no restriction on the application of the enabling regeneration circuit. Fig. 9 This is an example of enabling regeneration circuit application according to an embodiment of the present invention. Figure 1 ,like Fig. 9 As shown, the signal detection filter circuit part is replicated to obtain multiple branches, each of which has an independent configuration register group and function. Fig.10 This is an example of enabling regeneration circuit application according to an embodiment of the present invention. Figure 2 ,like Fig.10 As shown, the enabling regeneration circuit is replicated as a whole, and multiple enabling regeneration circuits are combined to achieve the overall function.
[0064] In summary, the enabling regeneration circuit provided in the embodiment of the present invention adopts a multi-channel decoding selector, that is, an out-of-order enabling regeneration receiver to increase the flexibility of system control, and is combined with software-controllable configuration registers to perform multiple configurations of different priorities to achieve transmission or polarity control from the input end to the output end. The polarity control can perform input shielding when the system does not need to respond to the input signal to achieve low power consumption characteristics; at the same time, the present invention adds a signal delay logic module to respectively realize the delay of the rising edge and the falling edge of the signal, and can regenerate the signal required by the system; a signal de-burring logic module is added to distinguish signals less than a preset time length and eliminate them, and the preset time length can be configured separately by software; in summary, the present invention provides a signal transmission scheme, which significantly improves its transmission convenience and configuration diversity, reduces power consumption, and provides a signal delay function. Finally, a filtering function is provided to solve the problem of burr transmission of the signal. The enabling regeneration routing scheme of the present invention can generate various enabling signals and baseband device signals for internal use according to the user-defined enabling signals and baseband device signals received on the user identity identification number (PIN), and can flexibly select the enabling regeneration routing direction of the signal on the chip.
[0065] The enabling regeneration circuit provided in the embodiment of the present invention can filter the burrs, especially in the process of switching from TDD to FDD in the radio frequency chip, the signal stability is required, and the removal of burrs can provide stability to the greatest extent. The present invention detects the output of the regeneration circuit through a signal detection and filtering unit, and uses a frequency division counting method to detect the pulse width of the regeneration circuit output, and shields the pulses that are less than the pre-configured filtering width of the software to avoid invalid burr signals from being transmitted to the subsequent circuit and introducing functional problems. The embodiment of the present invention can independently configure each output branch, and control the polarity of the input signal through a polarity control unit. According to the system setting, it can flexibly choose to shield the input signal that does not meet the polarity requirements, avoid invalid flipping of the subsequent circuit, and reduce the power consumption of the enabling regeneration circuit as a whole.
[0066] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A regeneration enabling circuit, characterized in that: include: An out-of-order enable regeneration receiver for selecting multiple out-of-order enable signals; A time delay logic circuit, used for delaying the out-of-order enable signal selected by the out-of-order enable regeneration receiver to obtain an enable regeneration routing signal; The signal detection filter circuit is used to filter the regeneration-enabled routing signal to obtain a regeneration-enabled output signal.
2. The enabling regeneration circuit according to claim 1, characterized in that: Also includes: A switch control logic circuit is used to perform circuit processing operations on the out-of-order enable signal selected by the out-of-order enable regenerative receiver.
3. The enabling regeneration circuit according to claim 2, characterized in that: Also includes: Switch controller, switch configuration register, where The switch controller is used to provide a configuration validation signal to the switch control logic circuit to validate or isolate the configuration instruction of the switch configuration register; The switch configuration register is used to provide switch enable configuration and switch polarity configuration to control the on and off of the switch control logic circuit.
4. The enabling regeneration circuit according to claim 1, characterized in that: The out-of-order enabled regeneration receiver further includes: a synchronization circuit and an arbitrator, wherein: The synchronization circuit is used to synchronize the out-of-order enable signal; The arbiter is used to arbitrate the priorities of multiple transmission channels corresponding to the out-of-order enable signal, so as to select a transmission channel with a high priority to transmit the corresponding out-of-order enable signal.
5. The enabling regeneration circuit according to claim 1, characterized in that: Also includes: The selection configuration register is used to select and shield multiple transmission channels corresponding to the out-of-order enable signal.
6. The enabling regeneration circuit according to claim 1, characterized in that: Also includes: A positive edge configuration register, used for performing positive edge delay processing on the out-of-order enable signal selected by the out-of-order enable regeneration receiver; A negative edge configuration register is used to perform negative edge delay processing on the out-of-order enable signal selected by the out-of-order enable regeneration receiver.
7. The enabling regeneration circuit according to claim 1, characterized in that: Also includes: The detection configuration register is used to provide a detection threshold for the signal detection filter circuit so as to filter and shield the regeneration routing enable signal that does not meet the detection threshold.
8. The enabling regeneration circuit according to claim 1, characterized in that: The signal detection filter circuit includes: a time delay filter controller and a time delay filter logic circuit, wherein: The delay filter controller is used to generate a delay filter configuration signal according to the delay processing configuration signal of the positive edge configuration register and / or the negative edge configuration register; The time delay filtering logic circuit is used to perform time delay processing and filtering processing on the regeneration routing enable signal according to the time delay filtering configuration signal.
9. A radio frequency chip, characterized in that: It comprises the enabling regeneration circuit described in any one of claims 1-8, and the enabling regeneration circuit performs selection processing, delay processing, and filtering processing on the input signal of the radio frequency chip to obtain an enabling regeneration output signal.
10. A method for enabling regenerative routing, characterized in that: The enabling regeneration circuit according to any one of claims 1 to 8 comprises: The out-of-order enable regeneration receiver selects and conducts multiple out-of-order enable signals of the chip under the enable control of the selection configuration register; The out-of-order enable signal selected by the out-of-order enable regeneration receiver enters the delay logic circuit through the switch control logic circuit; The delay logic circuit performs delay processing on the out-of-order enable signal to obtain an enable regeneration routing signal; The signal detection filter circuit performs filtering processing on the regeneration enabling routing signal to obtain a regeneration enabling output signal.
11. The method according to claim 10, characterized in that After the signal detection filter circuit performs filtering processing on the regeneration-enabled routing signal to obtain the regeneration-enabled output signal, the method further includes: The signal detection filter circuit detects the pulse width of the regeneration-enabling output signal using a frequency division counting method according to the detection threshold provided by the detection configuration register, and shields the regeneration-enabling output signal whose pulse width is smaller than the detection threshold.