Dynamically changing time slice cycles in computer processor unit

Abstract

Exemplary aspects include dynamically changing thread execution time slices in a processor in response to a change in detected FPS (Frame per second) QoS (Quality of Service) requirements. A computer processor and / or an operating system (OS) is configured to generate a scheduler interrupt in response to a timer signal. The scheduler service routine executes in response to the scheduler interrupt to schedule pending threads for execution. The frequency of the timer signal controls the frequency or time slice allocated to the current thread being executed before the thread is interrupted for the scheduler service routine. To avoid having a fixed timer signal at a frequency that achieves maximum FPS QoS requirements, which results in frequent and unnecessary scheduling interruptions, the frequency of the timer signal is dynamically changed to control the duration of a thread time slice to be still sufficient to serve the current FPS QoS.

Description

[0001] Priority application

[0002] This application claims priority to international patent application serial No. PCT / CN2022 / 117994 filed on September 9, 2022 and entitled “DYNAMICALLY VARYING TIME SLICEPERIODS IN A COMPUTER PROCESSOR UNIT”, the entire text of which is incorporated herein by reference. Background Art

[0003] I. Technical field

[0004] The techniques of this disclosure generally relate to modifying processor time slices allocated to software threads and processes.

[0005] II. Background Technology

[0006] The computer processor unit (CPU) time slice assigned to software threads and processes is the time period during which such threads and processes run on the processor without being interrupted by the processor's scheduler. When the processor time slice is relatively long, more time is allocated on the processor to run instructions associated with the corresponding thread or process before periodic interruptions will force the processor's scheduler to check whether other threads / processes need to be dispatched to execute on the processor. The longer the time slice assigned to the thread / process, the longer the time that other pending threads / processes must wait before being dispatched. In addition, the longer the time slice assigned to the thread / process, the thread / process will complete its processing in a shorter amount of elapsed time (also referred to as higher application throughput). When the processor time slice is relatively short, interruptions are generated more frequently, resulting in more interruptions without dispatching waiting threads, which consumes power. In addition, the shorter the processor time slice, the shorter the amount of time that pending threads / processes must wait to be served by the processor, and the longer the amount of elapsed time spent by the thread / process is completed, which is also referred to as lower application throughput. Summary of the invention

[0007] Exemplary aspects include dynamically changing thread execution time slices in a processor in response to a detected change in FPS (frames per second) QoS (quality of service) requirements. In an exemplary aspect, a computer processor unit is included in a processor-based system that includes other peripheral devices, such as memory and input / output (I / O) devices, such as a display, as an example. The computer processor and / or an operating system (OS) is configured to generate a scheduler interrupt in response to a timer signal generated by a timer circuit. The computer processor and / or its operating system is configured to execute a scheduler service routine in response to the scheduler interrupt to schedule pending threads for execution. Therefore, the frequency of the timer signal controls the frequency or time slice assigned to the current thread being executed before the thread is interrupted for the scheduler service routine to determine whether to reschedule the pending thread. In a computer processor employed by an application that controls display functions, certain threads involved in display operations (e.g., rendering, compositing, refreshing) have FPS QoS requirements so that those threads complete their work without dropping frames. In an exemplary aspect, in order to avoid having a fixed timer signal at a frequency that achieves the maximum FPS QoS requirement (which in turn results in higher power consumption due to more frequent scheduling interrupts), the processor or its operating system may dynamically change the frequency of the timer signal to control the duration of the thread time slice to reduce the frequency of scheduling interrupts while still being sufficient to serve the current FPS QoS. In this way, the thread time slice is shortened or extended to a time frame corresponding to serving the current FPS QoS requirement.

[0008] In this regard, in one exemplary aspect, a device is provided. The device includes a computer processor unit (CPU), a display unit; a scheduler timer circuit; and an FPS control circuit, the FPS control circuit being configured to receive a signal indicating a new frame rate QoS requirement from a current frame rate QoS requirement, and in response to the signal indicating the new frame rate QoS requirement, the FPS control circuit being configured to determine a corresponding time slice period and set the scheduler timer circuit to the corresponding time slice period, wherein the computer processor unit is configured to interrupt the execution of a thread on the computer processor unit when the scheduler timer circuit expires to determine whether to schedule one or more pending threads.

[0009] The apparatus may further include a frame rate source circuit configured to generate a signal indicative of a new frame rate quality of service requirement.

[0010] The frame rate source circuit may be a thermal sensor configured to generate a signal indicative of a new frame rate quality of service requirement when the thermal sensor senses a temperature exceeding a temperature threshold.

[0011] The frame rate source circuit may be a user interface circuit configured to generate a signal indicative of a new frame rate quality of service requirement in response to input from a user.

[0012] The frame rate source circuit may be an application configured to generate a signal indicative of a new frame rate quality of service requirement based on a requirement of the application.

[0013] The apparatus may further include a preconfigured table of FPS rate QoS requirements and corresponding time slice periods, wherein the frames per second control circuit determines the corresponding time slice period by retrieving the corresponding time slice period associated with the new frame rate quality of service requirement from the preconfigured table of FPS rate QoS requirements.

[0014] The frames per second control circuit may determine the corresponding time slice period by dividing the period of the new frame rate quality of service requirement by x, where x is less than 3 and greater than or equal to 2.

[0015] The frames per second control circuit can determine the corresponding time slice period through the AI ​​engine.

[0016] In another exemplary aspect, a method for dynamically changing a time slice period in a computer processor unit is provided. The method includes receiving a signal indicating a change from a current frame rate QoS requirement. The method also includes determining a corresponding time slice period in response to the signal indicating a new frame rate QoS requirement. The method also includes setting a scheduler timer circuit to the corresponding time slice period. The method also includes interrupting execution of a thread on the computer processor unit to determine whether to schedule one or more pending threads upon expiration of the scheduler timer circuit.

[0017] The method may also include generating a signal indicating a change in the quality of service requirement from the current frame rate.

[0018] Determining the corresponding time slice period may include retrieving the corresponding time slice period associated with the new frame rate quality of service requirement from a table.

[0019] Determining the corresponding time slice period may include dividing the period of the new frame rate quality of service requirement by x, where x is less than three and greater than or equal to two.

[0020] Determining the corresponding time slice period may include receiving the corresponding time slice period from the AI ​​engine.

[0021] In another exemplary aspect, a non-transitory computer-readable storage medium is provided that includes instructions that can be executed by a processor, which instructions, when executed by the processor, cause the processor to periodically interrupt a running thread to schedule one or more pending threads, the non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium includes code for receiving a signal indicating a change from a current frame rate QoS requirement. The non-transitory computer-readable storage medium also includes code for determining a corresponding time slice period in response to the signal indicating a new frame rate QoS requirement. The non-transitory computer-readable storage medium also includes code for setting a scheduler timer circuit to a corresponding time slice period. The non-transitory computer-readable storage medium also includes code for interrupting the execution of a thread on a computer processor unit to determine whether to schedule one or more pending threads when the scheduler timer circuit expires.

[0022] The non-transitory computer-readable storage medium may also include code for generating a signal indicating a change in quality of service requirement from a current frame rate.

[0023] The code for determining a corresponding time slice period may also include code for retrieving from a table a corresponding time slice period associated with the new frame rate quality of service requirement.

[0024] The code for determining the corresponding time slice period may also include code for dividing the period of the new frame rate quality of service requirement by x, where x is less than 3 and greater than or equal to 2.

[0025] The code for determining the corresponding time slice period may also include code for receiving the corresponding time slice period from the AI ​​engine.

[0026] In another exemplary aspect, an apparatus is provided. The apparatus includes components for receiving a signal indicating a change from a current frame rate QoS requirement. The apparatus also includes components for determining a corresponding interrupt time slice period in response to the signal indicating a new frame rate QoS requirement. The apparatus also includes components for setting a scheduler timer circuit to the corresponding interrupt time slice period. The apparatus also includes components for interrupting execution of a thread on a computer processor unit to determine whether to schedule one or more pending threads upon expiration of the scheduler timer circuit.

[0027] The apparatus may also include means for generating a signal indicating a change in quality of service requirement from a current frame rate.

[0028] The means for determining the corresponding time slice period may include means for retrieving the corresponding time slice period associated with the new frame rate quality of service requirement from a table.

[0029] The means for determining the corresponding time slice period may include means for dividing the period of the new frame rate quality of service requirement by x, where x is less than 3 and greater than or equal to 2.

[0030] The means for determining the corresponding time slice period may include means for receiving the corresponding time slice period from the AI ​​engine. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is an exemplary timing diagram for a time slice of a computer processor unit that is less than an FPS (frames per second) rate QoS (Quality of Service) requirement;

[0032] Figure 2 is a block diagram of an exemplary consumer device that dynamically changes a scheduler timer circuit in response to a new frame rate QoS requirement;

[0033] Figure 3 is a block diagram of exemplary threads running on a computer processor deployed in a consumer electronic device;

[0034] Figure 4 It is shown Figure 2 Block diagrams of various implementations of frame rate source circuits in;

[0035] Figure 5 is a block diagram illustrating various alternatives for determining corresponding time slice periods;

[0036] Figure 6 is a flow chart illustrating an exemplary process for dynamically changing time slices in a CPU;

[0037] Figure 7 is a timing diagram when the time slice varies in response to different FPS rate QoS requirements; and

[0038] Figure 8 Yes, it can include Figure 3 A block diagram of an exemplary processor-based system of a system. DETAILED DESCRIPTION

[0039] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0040] In response to the discussion Figure 2 Before describing an example of dynamically changing the time slice of a central processing unit (CPU) according to a change in FPS (frames per second) QoS (quality of service) requirement starting at Figure 1An example of a computer processor unit that is set to a fixed clock rate to generate a scheduler interrupt in response to a maximum FPS QoS requirement supported by a display is described.

[0041] Today's computer processor units (including CPUs and graphics processing units (GPUs)) render text and images for physical displays. With the development of physical displays, they have been able to support variable FPS QoS requirements. Applications (such as games) where scenes change and are frequently updated have high FPS QoS requirements. Because the screen changes less than video games and updates occur much less, applications such as word processing have relatively low FPS QoS requirements. In order to render text and images for physical displays, real-time rendering threads / processes, threads / processes with high priorities, must complete their work within a fixed time period so that video frames are not discarded. In many consumer electronic devices (including PCs, laptops, and mobile phones), the operating system requires a static system FPS rate setting that the display will run.

[0042] However, since today's physical displays can support running at different FPS rates, users usually set the static system FPS QoS to the highest supported frame rate to support applications that require these high FPS rates during operation. Correspondingly, the CPU time slice (also known as the time slice period assigned to the running thread before generating a scheduler interrupt) is set according to the highest FPS QoS requirement. It is possible to support variable FPS QoS requirements in other operating systems without changing the CPU time slice. Therefore, in these two types of existing operating systems, when a consumer electronic device is running an application that does not require the highest FPS QoS and a correspondingly relatively short time slice, unnecessary energy is consumed due to the overly frequent interrupts generated, and the time it takes to complete the thread / processor is longer than the time it takes.

[0043] For example, a user may switch from playing games on their mobile device to reading the news. In many current operating systems, the FPS rate will be fixedly set to the highest FPS rate supported by the display to support the game, and the CPU time slice will be correspondingly set to a shorter relative time period to serve the real-time, high-priority rendering thread / process that needs to be scheduled more frequently to complete its work. When the user switches to reading the news, the news application (non-real-time application thread) will continue to be interrupted at the same rate as the previously running game application that the user no longer plays. Therefore, unnecessary energy will be consumed due to the frequent interruptions generated by the short CPU time slice.

[0044] Figure 11 is an exemplary timing diagram 100 where the CPU time slice 102 is less than the frame period requirement 104, which is the inverse of the FPS rate QoS requirement. For simplicity, all real-time threads that need to be completed within the frame period requirement 104 are aggregated in a real-time thread timeline 106, and all non-real-time threads that are independent of the FPS rate QoS requirement are aggregated in a non-real-time thread timeline 108. Non-real-time threads are independent of the FPS rate QoS requirement. However, real-time and non-real-time threads, timelines 106 and timelines 108, respectively, depend on the CPU time slice 102. The CPU time slice 102 is the period during which the CPU is interrupted by the scheduler when the scheduler timer expires. This timing diagram 100 occurs when the FPS rate QoS requirement is reduced from a more stringent requirement and the CPU time slice 102 is initialized to support a faster FPS rate QoS requirement. In the timing diagram 100, the real-time thread is interrupted at time t 0 With time t 5 is executed on the CPU. At time t 5 At time t, the scheduler is called and recognizes that the real-time thread is waiting for resources. 5 The non-real-time thread was previously scheduled and dispatched as a pending thread. The non-real-time thread was exactly at time t 9 In other words, the non-real-time thread can be slotted to run on the CPU during the waiting time of the real-time thread waiting for resources. When the scheduler 8 When called, the scheduler will continue to allow non-real-time threads to execute on the CPU. 8 Soon after, the resource that the real-time thread is waiting for becomes available, causing the scheduler to schedule the thread to execute at time t 9 The real-time thread is scheduled and dispatched to execute on the CPU. In addition, at time t 9 Before that, the non-real-time thread completes its work. At time t 10 At this point, the real-time thread completes in time to meet the FPS rate requirement. In this case where the CPU time slice 102 is less than the inverse of the FPS rate requirement, there are many scheduler interrupts where there is no change in the execution of the thread (e.g., t 1 -t 4 , t 6 -t 7 ). Figure 1 The poor relationship shown between CPU time slice 102 and frame period requirement 104 results in wasteful power consumption due to overly frequent scheduler interrupts.

[0045] and Figure 1Unlike the timing diagram 100 of FIG. 1 , an exemplary aspect includes dynamically changing a thread execution time slice in a processor in response to a detected change in the FPS QoS requirement. In an exemplary aspect, a computer processor is included in a processor-based system that includes other peripheral devices, such as memory and input / output (I / O) devices, such as a display. The computer processor and / or an operating system (OS) are configured to generate a scheduler interrupt in response to a timer signal generated by a timer circuit. The computer processor and / or its operating system are configured to execute a scheduler service routine in response to the scheduler interrupt to schedule pending threads for execution. Therefore, the frequency of the timer signal controls the frequency or time slice assigned to the current thread being executed before the thread is interrupted, so that the scheduler service routine determines whether to reschedule the pending thread. In a computer processor used by an application that controls display functions, certain threads involved in display operations (e.g., rendering, compositing, refreshing) have FPS QoS requirements so that those threads complete their work without dropping frames. In an exemplary aspect, in order to avoid having a fixed timer signal at a frequency that achieves the maximum FPS QoS requirement (which in turn results in higher power consumption due to more frequent scheduler interrupts), the processor or its operating system may dynamically change the frequency of the timer signal to control the duration of the thread time slice to still be sufficient to serve the current FPS QoS. In this way, the thread time slice is shortened or extended to a time frame corresponding to serving the current FPS QoS requirement.

[0046] In this regard, Figure 2 is a block diagram of an exemplary consumer device 200 that dynamically changes a scheduler timer in response to a new frame rate QoS requirement. The consumer device 200 includes at least a computer processor unit 202 (CPU), an instruction memory 204, and a display unit 206. An operating system 208 runs on the CPU 202, including real-time threads / processes 210 and non-real-time threads / processes 212. The operating system 208 may include Android, iOS, Windows, or any other operating system that would run on a consumer electronic device. The real-time threads / processes 210 include threads that need to complete their work in advance of the FPS rate QoS requirement to render text and graphics on the display unit 206. Both the real-time threads / processes 210 and the non-real-time threads / processes 212 execute on the CPU (202). The real-time threads / processes 210 and the non-real-time threads / processes 212 are combined to execute on the CPU (202). Figure 3 Let's discuss some examples of real-time and non-real-time threads.

[0047] CPU 202 includes at least instruction processor 213, frame rate source circuit 214, frame number per second (FPS) control circuit 216, scheduler timer circuit 218 and clock circuit 220. Frame rate source circuit 214 signals FPS control circuit 216 with new FPS rate QoS requirement. Figure 4 An alternative embodiment of the frame rate source circuit 214 is discussed. When a signal 217 indicating a new FPS rate QoS requirement is received, the FPS control circuit 216 will determine a corresponding time slice period 222 based on the new FPS rate QoS requirement and set the scheduler timer circuit 218 to the corresponding time slice period. The clock circuit 220 generates a tick to the scheduler timer circuit 218. Once the number of ticks is equal to the corresponding time slice period, the scheduler timer circuit 218 interrupts the instruction processor 213, which in turn loads a scheduler service routine (SSR) 224 from the instruction memory 204. The instruction processor 213 runs the SSR 224 to determine whether the currently running thread should be switched out to run a higher priority pending thread that is already waiting. When the SSR 224 is run, the real-time thread / process 210 and the non-real-time thread / process 212 will run according to the corresponding time slice period 222. The same SSR 224 can also run on other CPUs in a multi-processor system and thus control the time slice periods of threads and processes running on other CPUs. By utilizing the corresponding time slice period 222 based on the FPS rate QoS requirement, the Figure 1 Unnecessary scheduler interrupts shown.

[0048] In consumer devices running the Android operating system, the scheduler timer circuit 218 includes a jiffie timer running in the kernel of the Android operating system. In addition, the FPS control circuit 216 is implemented in software as a device driver or service running in Android.

[0049] Figure 3 300 is a block diagram of an exemplary, non-exhaustive set of threads running on a CPU deployed in a consumer electronic device. Real-time threads 302A to 302E should complete within the FPS rate QoS requirement. Non-real-time threads 304A to 304F are not subject to the FPS rate QoS requirement. Real-time threads 302A to 302E and non-real-time threads 304A to 304F will run when dispatched with the current setting of the time slice period 222.

[0050] Application services 304A are one or more threads that run in the background and run applications such as games, word processors, or web browsers. Network 304B are one or more threads responsible for managing network connectivity, including WiFi, Bluetooth, and cellular networks. File manager 304C are one or more threads responsible for managing access to storage on consumer electronic devices. Security 304D are one or more threads responsible for monitoring and preventing security breaches. Camera service 304F are one or more threads responsible for controlling the camera on a consumer electronic device.

[0051] Real-time threads 302A to 302E depending on FPS rate QoS requirements include application rendering 302A, OS surface rendering service 302B, OS surface synthesis service 302C, display frame refresh control 302D, and frame layer rendering 302E. Application rendering 302A includes one or more threads associated with application service 304A, and is responsible for providing access to the display to application service 304A. OS surface rendering service 302B includes one or more threads associated with various applications running on the CPU, and its responsibility is to provide display services to various applications running on the CPU. OS surface synthesis service 302C includes one or more threads responsible for aggregating multiple application renderings. Display frame refresh control 302D and frame layer rendering 302E are traditionally device driver-level threads that control hardware associated with the display. Display frame refresh control 302D includes one or more threads that control display refresh. Frame layer rendering 302E includes one or more threads to control the CPU to perform actual rendering tasks at the physical display.

[0052] Figure 4 It is shown Figure 2 400 of various embodiments of the frame rate source circuit 214 in FIG. The frame rate source circuit 214 may include a user interface circuit 402 for receiving an end-user request for a new FPS rate QoS requirement. In this embodiment, the frame rate source circuit 214 receives the end-user request to signal the FPS control circuit 216 to determine a new time slice period corresponding to the new FPS rate QoS requirement. The frame rate source circuit 214 may also include a thermal sensor 404 that reports the new FPS rate QoS requirement in response to the temperature of the CPU 202 crossing a temperature threshold. The frame rate source circuit 214 may also include a software application 406 that runs on the CPU 202 and reports the new FPS rate QoS requirement. The frame rate source circuit 214 may also include a battery sensor 408 that reports the new FPS rate QoS requirement in response to the energy level of the battery crossing a battery level threshold. One or more of these embodiments may be deployed simultaneously in the same frame rate source circuit 214 in any combination.

[0053] Figure 5 5 is a block diagram 500 illustrating various alternatives for determining the corresponding time slice period 222. At alternative 502, the FPS control circuit 216 calculates the time slice period 222 by dividing the period of the new FPS rate QoS requirement by 2. Although this calculation is preferred, dividing the period of the new FPS rate QoS requirement by any real number between 2 and 3 will achieve a sufficient time slice period to correspond to the new FPS rate QoS requirement.

[0054] In alternative 504, the FPS control circuit 216 refers to the pre-configured table 506 of FPS rate QoS requirements to retrieve the corresponding time slice period 222. When the battery level ("BAT") and the temperature level ("TMP") are in the normal operating range ("Normal"), the FPS control circuit 216 looks up the new FPS rate QoS requirement ("FPS rate QoS request") in the pre-configured table 506 to retrieve the corresponding "time slice period" and sets the scheduler timer circuit 218 to the retrieved "time slice period". If the battery sensor reports that the battery level is low or the temperature sensor reports that the temperature level is high, the FPS control circuit 216 matches the "BAT" and "TMP" fields and matches the "FPS rate QoS Req" field in the pre-configured table 506 to determine the corresponding "time slice period". For example, if the battery level is reported as "low", the temperature level is reported as "normal", and the new FPS rate QoS requirement is 120Hz, the FPS control circuit 216 sets the time slice period 222 to 8.3msec.

[0055] In an alternative embodiment 508, the FPS control circuit 216 includes an AI engine 510. The AI ​​engine 510 monitors the performance of the CPU 202, the battery level, the temperature level, and unnecessary interrupts from the scheduler timer circuit 218 to determine the appropriate match between the FPS rate QoS requirements and the time slice period 222 for various combinations of battery level and temperature level. In other words, the FPS control circuit 216 dynamically creates a table similar to the preconfigured table 506, which is used to look up the corresponding time slice period in response to receiving a new FPS rate QoS requirement.

[0056] Figure 6 6 is a flow chart illustrating an exemplary process 600 for dynamically changing the time slice period 222 in the CPU 202. At block 602, the process 600 receives a signal indicating a change from a current frame rate QoS requirement to a new frame rate QoS requirement. At block 604, the process 600 determines whether the new frame rate QoS requirement is different from the current frame rate QoS requirement, or at least within a certain tolerance level. At block 606, the process 600 determines a corresponding time slice period based on the new FPS rate QoS requirement. At block 608, the process 600 sets a scheduler timer to a time slice period associated with the new FPS rate QoS requirement. At block 610, the process 600 interrupts the thread currently running on the CPU 202 when the updated scheduler timer expires.

[0057] Figure 7700 is a timing diagram when the time slice period changes in response to different FPS rate QoS requirements. The timing diagram 700 shows a scenario where three different FPS rate QoS requirements are reported to the FPS control circuit 216. The periods of the three different FPS rate QoS requirements correspond to time periods 702, 704, and 706. In response to the FPS rate QoS requirements, the three different FPS rate QoS requirements, the FPS control circuit 216 sets the time slice period 222 to time slice periods 708, 710, and 712, respectively. Figure 7 As shown, for three different FPS rate QoS requirements, time slice periods 708, 710, and 712 are approximately half of time periods 702, 704, and 706, respectively. Time periods 714, 716, and 718 show that the real-time threads are completed within their respective time periods 702, 704, and 706, which correspond to the three different FPS rate QoS requirements. 2 Previously, timing diagram 700 illustrates setting scheduler timer circuit 218 to a time slice period 710 in response to receiving a new FPS rate QoS requirement corresponding to time period 704. 2 At t, the real-time thread begins to be interrupted by the CPU 202 at each time slice period 710. 4 Previously, timing diagram 700 illustrates setting scheduler timer circuit 218 to time slice period 712 in response to receiving a new FPS rate QoS requirement corresponding to time period 706. 4 At , the real-time thread begins to be interrupted by the CPU 202 at each time slice cycle 712. Figure 7 As shown, the time slice period is matched with the changing FPS rate QoS requirement to reduce unnecessary task switching, thereby saving power consumption, while ensuring that the real-time thread completes its work within the FPS rate QoS requirement, thereby avoiding frame dropping.

[0058] According to aspects disclosed herein, dynamically changing time slice periods in a CPU may be provided or integrated into any processor-based consumer device. Examples, not limiting, include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, tablet phones, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotors.

[0059] In this regard, Figure 8 An example of a processor-based system 800 is shown that can employ dynamically changing time slice cycles in CPU 202, such as Figure 2 In this example, the processor-based system 800 includes processors 804, each of which includes one or more CPUs 806. The CPUs 806 may have a cache memory 816 coupled to the processors 804 for fast access to temporarily stored data. The CPUs 806 are combined with Figure 2 The CPU 806 is similar to the CPU 202 shown and discussed above. The CPU 806 is coupled to the system bus 810 and may be inter-coupled with devices included in the processor-based system 800. As is well known, the CPU 806 communicates with these other devices by exchanging address information, control information, and data information over the system bus 810. For example, the CPU 806 may communicate a bus transaction request to the memory controller 812. Although in Figure 8 Although not shown, a plurality of system buses 810 may be provided, wherein each system bus 810 constitutes a different configuration.

[0060] Other devices may be connected to the system bus 810. Figure 8As shown, as examples, these devices may include a memory system 814, one or more input devices 818, one or more output devices 820, one or more network interface devices 822, and one or more display controllers 824. The input device 818 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device 820 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 822 may be any device configured to allow data exchange to and from the network 826. The network 826 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth TM Network and Internet. The network interface device 822 can be configured to support any type of communication protocol desired. The memory system 814 can include one or more memory arrays 832.

[0061] The CPU 806 may also be configured to access a display controller 824 over the system bus 810 to control information sent to one or more displays 828. The display controller 824 sends information to be displayed to the display 828 via one or more video processors 830, which processes the information to be displayed into a format suitable for the display 828. The display 828 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0062] It will be further understood by those skilled in the art that the various exemplary logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of the two. As an example, the CPU described herein can be used for any circuit, hardware component, integrated circuit (IC) or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various exemplary components, blocks, modules, circuits and steps has been generally described above. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing departure from the scope of the present disclosure.

[0063] According to aspects disclosed herein, the time slice period that changes dynamically in the CPU can be implemented or executed in a graphics processing unit (GPU) digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof, which is designed to perform the functions described herein. The CPU can be a microprocessor, but in an alternative, the CPU can be a controller, a microcontroller, or a state machine. The CPU can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0064] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. In an alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0065] It is also noted that the operation steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operation can be performed in many different orders except for the illustrated order. In addition, the operation described in a single operation step can actually be performed in multiple different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications can be made to the operation steps illustrated in the flow chart. Those skilled in the art will also understand that any of a variety of different technologies and processes can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles or any combination thereof.

[0066] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device, comprising: Computer processor unit; and Display unit; The computer processor unit comprises: Scheduler timer circuit; and A frames per second control circuit configured to receive a signal indicating a new frame rate quality of service requirement, wherein in response to the signal indicating the new frame rate quality of service requirement, the frames per second control circuit is configured to determine a corresponding time slice period and set the scheduler timer circuit to the corresponding time slice period, and wherein the computer processor unit is configured to interrupt execution of threads on the computer processor unit upon expiration of the scheduler timer circuit to determine whether to schedule one or more pending threads.

2. The device according to claim 1, further comprising: A frame rate source circuit is configured to generate the signal indicative of the new frame rate quality of service requirement.

3. The apparatus of claim 2, wherein the frame rate source circuit is a thermal sensor, the thermal sensor configured to generate the signal indicative of the new frame rate quality of service requirement when the thermal sensor senses a temperature exceeding a temperature threshold.

4. The apparatus of claim 2, wherein the frame rate source circuit is a user interface circuit configured to generate the signal indicative of the new frame rate quality of service requirement in response to input from a user.

5. The apparatus of claim 2, wherein the frame rate source circuit is the application configured to generate the signal indicative of the new frame rate quality of service requirement based on a requirement of the application.

6. The device according to claim 1, further comprising: A preconfigured table of frames per second (FPS) rate QoS requirements and corresponding time slice periods, wherein the frames per second control circuit determines the corresponding time slice period by retrieving the corresponding time slice period associated with the new frame rate quality of service requirement from the preconfigured table of FPS rate QoS requirements.

7. The apparatus of claim 1, wherein the frames per second control circuit determines the corresponding time slice period by dividing the period of the new frame rate quality of service requirement by x, where x is less than 3 and greater than or equal to 2.

8. The device according to claim 1, wherein the frames per second control circuit determines the corresponding time slice period through an artificial intelligence (AI) engine.

9. A method for dynamically changing a time slice period in a computer processor unit, the method comprising: receiving a signal indicating a change in quality of service requirement from a current frame rate; determining a corresponding time slice period in response to the signal indicating a new frame rate quality of service requirement; setting a scheduler timer circuit of the computer processor unit to the corresponding time slice period; as well as Execution of a thread on the computer processor unit is interrupted to determine whether to schedule one or more pending threads upon expiration of the scheduler timer circuit.

10. The method according to claim 9, further comprising: The signal is generated indicating the change in quality of service requirement from the current frame rate.

11. The method of claim 9, wherein determining the corresponding time slice period comprises retrieving the corresponding time slice period associated with the new frame rate quality of service requirement from a table. 12 . The method of claim 9 , wherein determining the corresponding time slice period comprises dividing the period of the new frame rate quality of service requirement by x, wherein x is less than 3 and greater than or equal to 2.

13. The method of claim 9, wherein determining the corresponding time slice period comprises receiving the corresponding time slice period from an artificial intelligence (AI) engine.

14. The method of claim 9, wherein receiving the signal indicating a change in quality of service requirement from a current frame rate, the method further comprising: A determination is made as to whether the new frame rate quality of service requirement is different from the current frame rate quality of service requirement.

15. A non-transitory computer-readable storage medium comprising instructions executable by a processor, the instructions, when executed by the processor, causing the processor to periodically interrupt a running thread, the non-transitory computer-readable storage medium comprising: code for receiving a signal indicating a change in quality of service requirement from a current frame rate; code for determining a corresponding time slice period in response to the signal indicating a new frame rate quality of service requirement; code for setting a scheduler timer circuit to the corresponding time slice period; and Code for interrupting execution of threads on a computer processor unit to determine whether to schedule one or more pending threads upon expiration of the scheduler timer circuit.

16. The non-transitory computer-readable storage medium of claim 15, further comprising: Code for generating the signal indicating the change in quality of service requirement from the current frame rate.

17. The non-transitory computer-readable storage medium of claim 15, wherein the code for determining the corresponding time slice period further comprises: Code for retrieving from a table the corresponding time slice period associated with the new frame rate quality of service requirement.

18. The non-transitory computer-readable storage medium of claim 15, wherein the code for determining the corresponding time slice period further comprises: Code for dividing the period of the new frame rate quality of service requirement by x, where x is less than 3 and greater than or equal to 2.

19. The non-transitory computer-readable storage medium of claim 15, wherein the code for determining the corresponding time slice period further comprises: Code for receiving the corresponding time slice period from an artificial intelligence (AI) engine.

20. A device, comprising: means for receiving a signal indicative of a change in quality of service requirement from a current frame rate; means for determining a time slice period in response to the signal indicating a new frame rate quality of service requirement; means for setting a scheduler timer circuit to said time slice period; and Means for interrupting execution of threads on a computer processor unit to determine whether to schedule one or more pending threads upon expiration of said scheduler timer circuit.

21. The apparatus according to claim 20, further comprising: Means for generating said signal indicative of said change in quality of service requirement from said current frame rate.

22. The apparatus of claim 20, wherein the means for determining the time slice period comprises: Means for retrieving from a table said time slice period associated with said new frame rate quality of service requirement.

23. The apparatus of claim 20, wherein the means for determining the time slice period comprises: Means for dividing said time slice period of said new frame rate quality of service requirement by x, wherein x is less than 3 and greater than or equal to 2.

24. The apparatus of claim 20, wherein the means for determining a corresponding time slice period comprises: A component for receiving the corresponding time slice period from an artificial intelligence AI engine.

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