Decoupling capacitor architecture

Abstract

In certain aspects, a chip includes first source / drain contacts and first gates formed over a first oxide diffusion (OD), where each of the first gates is disposed between a respective pair of the first source / drain contacts. The chip also includes a first bridge coupling a first one of the first source / drain contacts, a first one of the first gates, and a second one of the first source / drain contacts. The chip further includes: a first metal wiring coupled to the first one of the first source / drain contacts; and a second metal wiring coupled to the second one of the first source / drain contacts.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application serial number 17 / 940,911 filed in the U.S. Patent Office on September 8, 2022, the entire contents of which are incorporated herein as if set forth in its entirety below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure relate generally to capacitors, and more particularly, to capacitors integrated on a chip. Background Art

[0004] The capacitor may be integrated on a chip (ie, a bare die). For example, the integrated capacitor may be used as a decoupling capacitor. The decoupling capacitor may be used, for example, as a charge storage device to support instantaneous current demands in a power delivery network. Summary of the invention

[0005] A simplified overview of one or more implementations is presented below in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is neither intended to identify key or important elements of all implementations nor to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to a more detailed description presented later.

[0006] One aspect relates to a chip. The chip includes first source / drain contacts and first gates formed above a first oxide diffusion (OD), wherein each of the first gates is disposed between corresponding pairs of first source / drain contacts. The chip also includes a first bridge coupling a first first source / drain contact of the first source / drain contacts, a first first gate of the first gates, and a second first source / drain contact of the first source / drain contacts. The chip also includes: a first metal wiring coupled to the first first source / drain contact of the first source / drain contacts; and a second metal wiring coupled to the second first source / drain contact of the first source / drain contacts.

[0007] A second aspect relates to a chip. The chip includes a power rail and a low rail, the low rail having a lower potential than the power rail. The chip also includes a decoupling capacitor, which is coupled between the power rail and the low rail. The decoupling capacitor includes a first source / drain contact and a first gate formed on a first oxide diffusion (OD), wherein each first gate of the first gate is arranged between corresponding pairs of first source / drain contacts. The decoupling capacitor also includes a first bridge, which couples a first first source / drain contact in the first source / drain contact, a first first gate in the first gate, and a second first source / drain contact in the first source / drain contact. The decoupling capacitor also includes: a first metal wiring coupled to the first first source / drain contact in the first source / drain contact; and a second metal wiring coupled to the second first source / drain contact in the first source / drain contact, wherein the first metal wiring and the second wiring are coupled to the power rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A side view of an example of a chip including metal layers and vias according to certain aspects of the present disclosure is shown.

[0009] Figure 2 An example of an n-type device according to certain aspects of the present disclosure is shown.

[0010] Figure 3 An example of a p-type device according to certain aspects of the present disclosure is shown.

[0011] Figure 4 Examples of n-type devices and p-type devices according to certain aspects of the present disclosure are shown.

[0012] Figure 5 An example of a reverse biased diode formed using n-type devices and p-type devices and the capacitance of the diode is shown in accordance with certain aspects of the present disclosure.

[0013] Fig. 6A Examples of a gate, a first OD, and a second OD are shown according to certain aspects of the present disclosure.

[0014] Figure 6B Examples of source / drain contacts according to certain aspects of the present disclosure are shown.

[0015] Figure 6C Examples of first and second bridges are shown, wherein each of the first and second bridges couples a respective gate to a respective source / drain, in accordance with certain aspects of the present disclosure.

[0016] Fig.6D Examples of vias disposed on source / drain contacts and gate contacts are shown in accordance with certain aspects of the present disclosure.

[0017] Fig. 6E An example of a layout including multiple n-type devices and multiple p-type devices forming a capacitor is shown in accordance with certain aspects of the present disclosure.

[0018] Figure 7 A circuit diagram showing an example of a decoupling capacitor in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0019] The specific embodiments described below in conjunction with the drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein may be practiced. The specific embodiments include specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, in order to avoid confusing these concepts, well-known structures and components are shown in block diagram form.

[0020] Figure 1 1 shows a side view of an example of a chip 100 (ie, a bare die) according to certain aspects. The chip 100 may include many devices integrated on the chip 100. In this aspect, Figure 1 An example of a device 110 integrated on a chip 100 is shown. Figure 1 1 , but it should be understood that chip 100 may include many devices. Device 110 may be used as a transistor on chip 100. Device 110 may also be used to form a capacitor (eg, a decoupling capacitor), as discussed further below.

[0021] exist Figure 1 In the example shown in , the device 110 includes a gate 115, a first source / drain 120-1, and a second source / drain 120-2. As used herein, the term "source / drain" refers to a source and / or a drain. The gate 115 is formed over a channel between the first source / drain 120-1 and the second source / drain 120-2. The device 110 may also include a thin gate oxide 118 between the gate 115 and the channel. The gate 115 may be a polysilicon gate, a metal gate, or another type of gate. Figure 1 In the example shown in FIG. 1 , the device 110 is depicted as a planar device. However, it should be understood that the device 110 may be implemented using a fin field effect transistor (FinFET) process.

[0022] The chip 100 may further include a first source / drain contact 130-1 formed on the first source / drain 120-1, and a second source / drain contact 130-2 formed on the second source / drain 120-2. The source / drain contacts 130-1 and 130-2 may be formed by forming a source / drain contact layer (at the top) using, for example, a photolithography process and an etching process. Figure 1 Although Figure 1 In the example of FIG. 1 , the source / drain contact layer is marked as “MD”, but it should be understood that the source / drain contact layer may also be marked as “CA” or other marks. The source / drain contact layer may include one or more metals and / or one or more other conductive materials.

[0023] The chip 100 may further include a gate contact 135 formed on the gate 115. The gate contact 135 may be formed by forming a gate contact layer (in the embodiment of FIG. 1 ) using, for example, a photolithography process and an etching process. Figure 1 Marked as "MP" in the Figure 1 In the example of FIG. 1 , the gate contact layer is labeled as “MP”, but it should be understood that the gate contact layer may also be labeled with another label. The gate contact layer may include one or more metals and / or one or more other conductive materials.

[0024] The chip 100 may also include a stack of metal layers 150. The metal layers 150 are patterned (e.g., using photolithography and etching) to provide metal wiring for the devices 110 and other devices (not shown) on the chip 100. The metal wiring can be used, for example, to interconnect the devices on the chip 100, couple the devices to a power delivery network, couple the devices to one or more input / output (I / O) pins, etc. One or more metal layers may also be used to provide local wiring within a device or unit. The metal layer 150 may also be referred to as a metallization layer or another term.

[0025] exist Figure 1 In the example of , the bottom metal layer may be designated as metal layer M0 (also referred to as metal 0), the metal layer directly above metal layer M0 may be designated as metal layer M1 (also referred to as metal 1), the metal layer directly above metal layer M1 may be designated as metal layer M2 (also referred to as metal 2), and so on. Although for ease of explanation, in Figure 1 , but it should be understood that chip 100 may include additional metal layers (e.g., five or more metal layers, including metal layer M3, metal layer M4, etc.). It should be understood that the present disclosure is not limited to the nomenclature in which the bottom-most metal layer is designated as metal layer M0. For example, in another example, the bottom-most metal layer may be designated as metal layer M1 instead of metal layer M0.

[0026] Chip 100 also includes vias 160, which provide electrical coupling between metal layers 150 and between metal layer M0 and contacts 130-1, 130-2, and 135. In this example, vias VD provide electrical coupling between source / drain contacts 130-1 and 130-2 and metal layer M0, and vias VG provide electrical coupling between gate contact 135 and metal layer M0. It should be understood that vias VD and vias VG can be formed by the same via layer (e.g., using photolithography and etching). Via V0 provides electrical coupling between metal layer M0 and metal layer M1, and vias V1 provides electrical coupling between metal layer M1 and metal layer M2.

[0027] Figure 1 The device 110 shown in FIG. 1 can be used to implement an n-type device (e.g., an n-type field effect transistor (NFET)) or a p-type device (e.g., a p-type field effect transistor (PFET)). In this regard, Figure 2 2 shows an example of an n-type device 210 implementation of the device 110 according to certain aspects. Figure 2 One n-type device 210 is shown in FIG. 1 , but it should be understood that the chip 100 may include multiple instances of the n-type device 210. It should also be understood that the chip 100 may include p-type devices, as discussed further below.

[0028] exist Figure 2 In the example shown in FIG. 1 , the n-type device 210 includes a gate 215, a first source / drain 220-1, and a second source / drain 220-2. Figure 2 As shown in , the first source / drain 220-1 and the second source / drain 220-2 can be formed in a p-substrate (i.e., a p-type substrate). In addition, each of the first source / drain 220-1 and the second source / drain 220-2 can be an n+ source / drain, which can be formed using n+ diffusion, p+ implantation, or another process. The gate 215 is formed over the channel between the first source / drain 220-1 and the second source / drain 220-2. The n-type device 210 may also include a thin gate oxide 218 between the gate 215 and the channel. The gate 215 may be a polysilicon gate, a metal gate, or another type of gate. In Figure 2 In the example shown in FIG. 1 , the n-type device 210 is depicted as a planar device. However, it should be understood that the n-type device 210 may be implemented using a fin field effect transistor (FinFET) process.

[0029] The chip 100 may also include a first source / drain contact 230-1 formed on the first source / drain 220-1, and a second source / drain contact 230-2 formed on the second source / drain 220-2. The source / drain contacts 230-1 and 230-2 may be formed from the source / drain contact layer discussed above using, for example, a photolithography process and an etching process. The chip 100 may also include a gate contact 235 formed on the gate 215. The gate contact 235 may be formed from the gate contact layer discussed above using, for example, a photolithography process and an etching process. In some aspects, the source / drain contact layer and the gate contact layer may be the same contact layer or different contact layers.

[0030] Figure 2 Also shown is a stack of metal layers 150 (also referred to as a metal layer stack), which, as discussed above, may be patterned (eg, using photolithography and etching) to provide metal wiring for n-type device 210 and other devices (not shown) on chip 100 . Figure 2 Also shown are vias 160 , which, as discussed above, provide electrical coupling between metal layers 150 and between metal layer M0 and contacts 230 - 1 , 230 - 2 , and 235 .

[0031] Figure 3 1 shows an example of a p-type device 310 implementation of the device 110 according to certain aspects. Figure 3 One p-type device 310 is shown in FIG. 1 , but it should be understood that the chip 100 may include multiple instances of the p-type device 310. It should also be understood that the chip 100 may also include multiple instances of the n-type device 210 discussed above.

[0032] exist Figure 3 In the example shown in FIG. 1 , the p-type device 310 includes a gate 315, a first source / drain 320-1, and a second source / drain 320-2. Figure 3 As shown in , the first source / drain 320-1 and the second source / drain 320-2 can be formed in an N-well 350 in a p-substrate. In addition, each of the first source / drain 320-1 and the second source / drain 320-2 can be a p+ source / drain, which can be formed using p+ diffusion, p+ implantation, or another process. The gate 315 is formed over the channel between the first source / drain 320-1 and the second source / drain 320-2. The p-type device 310 may also include a thin gate oxide 318 between the gate 315 and the channel. The gate 315 may be a polysilicon gate, a metal gate, or another type of gate. In Figure 3In the example shown in FIG. 3 , the p-type device 310 is depicted as a planar device. However, it should be understood that the p-type device 310 may be implemented using a fin field effect transistor (FinFET) process.

[0033] The chip 100 may also include a first source / drain contact 330-1 formed on the first source / drain 320-1, and a second source / drain contact 330-2 formed on the second source / drain 320-2. The source / drain contacts 330-1 and 330-2 may be formed from the source / drain contact layer discussed above using, for example, a photolithography process and an etching process. The chip 100 may also include a gate contact 335 formed on the gate 315. The gate contact 335 may be formed from the gate contact layer discussed above using, for example, a photolithography process and an etching process. In some aspects, the source / drain contact layer and the gate contact layer may be the same contact layer or different contact layers.

[0034] Figure 3 Also shown is a stack of metal layers 150 (also referred to as a metal layer stack), which, as discussed above, may be patterned (eg, using photolithography and etching) to provide metal wiring for p-type device 310 and other devices (not shown) on chip 100 . Figure 3 Also shown are vias 160 , which, as discussed above, provide electrical coupling between metal layers 150 and between metal layer M0 and contacts 330 - 1 , 330 - 2 , and 335 .

[0035] According to certain aspects, n-type device 210 and / or p-type device 310 may be used to form a capacitor (eg, a decoupling capacitor). For example, a decoupling capacitor may be integrated on chip 100 using one or more instances of n-type device 210 and / or one or more instances of p-type device 310.

[0036] Decoupling capacitors can be used, for example, as charge storage devices to support transient current demands in a power delivery network. Transient current demands may have various causes. For example, a circuit receiving power from a power delivery network may draw a large transient current when the circuit is first powered on (e.g., due to the charging of capacitors in the circuit). If there are no adequate provisions to meet the transient current requirements, large voltage drops or ground bounces may occur, which may cause circuit functional failures (e.g., timing violations in logic devices). To support the transient current demands of the power delivery network, decoupling capacitors may be inserted throughout the power delivery network.

[0037] Figure 4 1 shows an example in which n-type device 210 and p-type device 310 can be used to form capacitor 410 (eg, decoupling capacitor) on chip 100. Although for simplicity, in Figure 4 4. In the example, one n-type device 210 and one p-type device 310 are shown, but it should be understood that multiple n-type devices and / or multiple p-type devices may be used (e.g., to increase capacitance). In this example, capacitor 410 is coupled between power rail 435 and low rail 415 and may be used as a decoupling capacitor. Power rail 435 (also referred to as a voltage supply rail) may provide power (e.g., supply voltage) to one or more circuits (not shown). Low rail 415 has a lower potential than power rail 435. In one example, low rail 415 is a ground rail coupled to ground, but is not limited to this example.

[0038] exist Figure 4 In the example of , the n-type device 210 and the p-type device 310 are adjacent to each other on the chip 100. In this example, the gate 215, the first source / drain 220-1 and the second source / drain 220-2 of the n-type device 210 are coupled to each other and to the low rail 415 (e.g., the ground rail). For example, the gate 215, the first source / drain 220-1 and the second source / drain 220-2 can be coupled to each other and to the low rail 415 via contacts 230-1, 230-2 and 235, vias (e.g., VD and VG), and one or more metal layers 150. It should be noted that for ease of illustration, Figure 4 Vias and one or more metal layers 150 are not explicitly shown.

[0039] Furthermore, in this example, the gate 315, the first source / drain 320-1, and the second source / drain 320-2 of the p-type device 310 are coupled to each other and to the power rail 435. For example, the gate 315, the first source / drain 320-1, and the second source / drain 320-2 may be coupled to each other and to the power rail 435 via contacts 330-1, 330-2, and 335, vias (e.g., VD and VG), and one or more metal layers 150. Note that for ease of illustration, Figure 4 Vias and one or more metal layers 150 are not explicitly shown.

[0040] In this example, the p-substrate and N-well between p-type device 210 and p-type device 310 form a diode that is reverse biased because N-type device 210 is coupled to low rail 415 and p-type device 310 is coupled to power rail 435 (which is at a higher potential than low rail 415). Figure 5 A circuit diagram of diode 510 is shown in FIG. Figure 5 As shown in , diode 510 is reverse biased between power rail 435 and low rail 415 .

[0041] In this example, the capacitance of diode 510 provides the capacitance for capacitor 410. In this regard, Figure 5 Also shown is a capacitor 520 representing the capacitance of the diode 510. Figure 5 As shown in FIG. 4 , capacitor 520 is coupled between power rail 435 and low rail 415 and can therefore function as a decoupling capacitor.

[0042] Various aspects of the present disclosure provide new layout techniques for integrating capacitors (e.g., decoupling capacitors) on chip 100 using n-type devices and p-type devices. Compared to current layout techniques, layout techniques according to aspects of the present disclosure accommodate more n-type devices and p-type devices in a given area, thereby increasing the capacitance for a given area. In addition, compared to current layout techniques, layout techniques according to aspects of the present disclosure eliminate or reduce the number of polysilicon diffusion edge (PODE) devices, thereby reducing leakage current caused by PODE devices. The above-mentioned features and other features of the present disclosure are further discussed below.

[0043] According to some aspects, reference will now be made to FIG. 6A to FIG. 6E Exemplary layouts of capacitors (eg, decoupling capacitors) are described.

[0044] Fig. 6A A top view of a gate array including a plurality of gates 620-1 to 620-7 (eg, polysilicon gates) is shown, wherein each of the gates 620-1 to 620-7 is elongated and extends in a lateral direction 615. As used herein, a "lateral direction" is a direction parallel to a substrate (eg, a p-substrate) of the chip 100. Fig. 6A In the example of , gates 620-1 to 620-7 are evenly spaced apart in lateral direction 610, wherein lateral direction 610 is perpendicular to lateral direction 615. However, it should be understood that the disclosure is not limited to this example. In one example, the gate array corresponds to a cell, as discussed further below.

[0045] Fig. 6A Also shown are source / drain electrodes 622-1 to 622-6 corresponding to a first oxide diffusion (OD), which may be a p-type OD. OD may also be referred to as an active region, active diffusion, active area, or another term. Source / drain electrodes 622-1 to 622-6 may be p+ source / drain electrodes formed using p+ diffusion, p+ implantation, or other processes. In this example, each of source / drain electrodes 622-1 to 622-6 is located between corresponding pairs of gate electrodes 620-1 to 620-7.

[0046] Fig. 6AAlso shown are source / drain electrodes 625-1 to 625-6 corresponding to a second OD, which may be an n-type OD. The second OD is spaced apart from the first OD in the lateral direction 615. The source / drain electrodes 625-1 to 625-6 may be n+ source / drain electrodes formed using n+ diffusion, n+ implantation, or other processes. In this example, each of the source / drain electrodes 625-1 to 625-6 is located between corresponding pairs of gate electrodes 620-1 to 620-7.

[0047] Figure 6B Shown cutting between the first OD and the second OD Fig. 6A 6. More specifically, gate 620-2 is cut into gates 630-1 and 632-1, gate 620-3 is cut into gates 630-2 and 632-2, gate 620-5 is cut into gates 630-3 and 632-3, and gate 620-6 is cut into gates 630-4 and 632-4. Gates 630-1 to 630-4 and 632-1 to 632-4 can be used as gates of the device. The center gate 620-4 can be a dummy gate.

[0048] Figure 6B Also shown are examples of source / drain contacts 635-1 to 635-6, where each of the source / drain contacts 635-1 to 635-6 is formed at Fig. 6A On top of a corresponding one of the source / drain electrodes 622-1 to 622-6 shown in FIG. Figure 6B Also shown are examples of source / drain contacts 638-1 to 638-6, where each of the source / drain contacts 638-1 to 638-6 is formed at Fig. 6A The source / drain contacts 635-1 to 635-6 and 638-1 to 638-6 may be formed of the same contact layer (eg, MD layer) using, for example, photolithography and etching.

[0049] like Figure 6BAs shown in , each of the gates 630-1 to 630-4 is disposed between corresponding pairs of source / drain contacts 635-1 to 635-6, and each of the gates 632-1 to 632-4 is disposed between corresponding pairs of source / drain contacts 638-1 to 638-6. It should be noted that two pairs of source / drain contacts can have a common source / drain. For example, gate 630-1 is located between corresponding pairs of source / drain contacts 635-1 and 635-2, and gate 630-2 is located between corresponding pairs of source / drain contacts 635-2 and 635-3, wherein source / drain contact 635-2 is common to both pairs.

[0050] Figure 6C Examples of gate contacts 642-1 and 642-2 formed on gates 630-1 and 630-2, respectively, and gate contacts 647-1 and 647-2 formed on gates 632-3 and 632-4, respectively, are shown. Gate contacts 642-1, 642-2, 647-1, and 647-2 may be formed from a gate contact layer (eg, MP layer) using, for example, photolithography and etching.

[0051] Figure 6C Also shown is an example of a first bridge 645 extending in the lateral direction 610 over the gate 630-3 and the source / drain contacts 635-4 and 635-5. The first bridge 645 can be formed from a gate contact layer (e.g., an MP layer) using, for example, photolithography and etching. In other words, in this example, the source / drain 622-4, the gate 630-3, and the source / drain 622-5 are coupled to each other (i.e., coupled to the same potential through the first bridge 645) via the first bridge 645. In this example, the source / drain 622-4, the gate 630-3, and the source / drain 622-5 can form a first p-type device. As used herein, a "bridge" can be a conductor (e.g., formed by a contact layer) that couples one or more source / drains to a gate.

[0052] Figure 6C Also shown is an example of a second bridge 650 extending in the lateral direction 610 over the gate 632-2 and the source / drain contacts 638-2 and 638-3. The second bridge 650 can be formed from a gate contact layer (e.g., an MP layer) using, for example, photolithography and etching. In other words, in this example, the source / drain 625-2, the gate 632-2, and the source / drain 625-3 are coupled to each other (i.e., coupled to the same potential through the second bridge 650) via the second bridge 650. In this example, the source / drain 625-2, the gate 632-2, and the source / drain 625-3 can form a first n-type device.

[0053] In some aspects, the first bridge 645 and the second bridge 650 are formed by a gate contact layer (e.g., MP layer), which can be at the same level as the source / drain contact layer (e.g., MD layer). However, it should be understood that the present disclosure is not limited to this example. The gate contact layer and the source / drain contact layer can be the same contact layer or different contact layers. In general, the first bridge 645 and the second bridge 650 are formed by contact layers, for example, using photolithography and etching.

[0054] Fig.6D An example of vias 655-1 to 655-6 disposed on source / drain contacts 635-1 to 635-6, respectively, is shown. Vias 655-1 to 655-4 are aligned in a lateral direction 610, and vias 655-5 and 655-6 are aligned in a lateral direction 610. Vias 655-1 to 655-4 are spaced apart from vias 655-5 and 655-6 in a lateral direction 615. Fig.6D Also shown are vias 660-1 and 660-2 disposed on gate contacts 642-1 and 642-2, respectively. Vias 660-1 and 660-2 are aligned with vias 655-5 and 655-6 in lateral direction 610. Vias 655-1 to 655-6, 660-1 and 660-2 may be formed from a via layer, for example, using photolithography and etching.

[0055] Fig.6D Also shown are examples of vias 665-1 to 665-6 disposed on source / drain contacts 638-1 to 635-6, respectively. Vias 665-3 to 665-6 are aligned in lateral direction 610, and vias 665-1 and 665-2 are aligned in lateral direction 610. Vias 665-3 to 665-6 are spaced apart from vias 665-1 and 665-2 in lateral direction 615. Fig.6D Also shown are vias 670-1 and 670-2 disposed on gate contacts 647-1 and 647-2, respectively. Vias 670-1 and 670-2 are aligned with vias 665-1 and 665-2 in lateral direction 610. Vias 665-1 to 665-6, 670-1 and 670-2 may be formed from a via layer, for example, using photolithography and etching.

[0056] Fig. 6E An example of a first metal wiring 680, a second metal wiring 682, a third metal wiring 684, and a fourth metal wiring 686 is shown. The metal wirings 680, 682, 684, and 686 extend in a lateral direction 610 and are spaced apart in a lateral direction 615. Fig. 6EIn the example of FIG. 1 , each of metal wirings 680, 682, 684, and 686 is shown as a continuous metal line. However, it should be understood that the present disclosure is not limited to this example. In some aspects, metal wirings 680, 682, 684, and 686 are formed from metal layer M0, for example, using photolithography and etching. It should be noted that for ease of illustration, Fig. 6E Reference numerals of the source / drain contacts 635 - 1 to 635 - 6 and 638 - 1 to 638 - 6 are not explicitly illustrated in FIG. As used herein, “wiring” may be a conductive path formed by one of the metal layers 150 .

[0057] exist Fig. 6E In the example of FIG. 1 , the first metal wiring 680 is coupled to the source / drain contacts 635-1 to 635-4 via the vias 655-1 to 655-4. In other words, each of the vias 655-1 to 655-4 is coupled between a corresponding one of the source / drain contacts 635-1 to 635-4 and the first metal wiring 680. The vias 655-1 to 655-4 are connected to the source / drain contacts 635-1 to 635-4. Fig. 6E A dashed line is shown in FIG. 6 to indicate that a via is below the first metal wiring 680 .

[0058] The second metal wiring 682 is coupled to the source / drain contacts 635-5 and 635-6 via vias 655-5 and 655-6, and is coupled to the gates 630-1 and 630-2 via vias 660-1 and 660-2. In other words, each of the vias 655-5 and 655-6 is coupled between a corresponding one of the source / drain contacts 635-5 and 635-6 and the second metal wiring 682, and each of the vias 660-1 and 660-2 is coupled between the corresponding gates 630-1 and 630-2 and the second metal wiring 682. The vias 655-5, 655-6, 660-1, and 660-2 are connected to the gates 630-1 and 630-2. Fig. 6E A dashed line is shown in FIG. 6 to indicate that a via is below the second metal wiring 682 .

[0059] In this example, the first metal wiring 680 and the second metal wiring 682 are coupled through the first bridge 645, which couples the source / drain contact 635-4, the gate 630-3, and the source / drain contact 635-5 together. Therefore, the first metal wiring 680 and the second metal wiring 682 are at approximately the same potential. This exemplary layout forms three p-type devices coupled to a common potential. In some aspects, the first metal wiring 680 and the second metal wiring 682 can be coupled to Figure 4 4. Thus, in this example, the layout forms three p-type devices coupled to the power rail 435.

[0060] exist Fig. 6E In the example of FIG. 1 , the fourth metal wiring 686 is coupled to the source / drain contacts 638-3 to 638-6 via the vias 665-3 to 665-6. In other words, each of the vias 665-3 to 665-6 is coupled between a corresponding one of the source / drain contacts 638-3 to 638-6 and the fourth metal wiring 686. The vias 665-3 to 665-6 are connected to the source / drain contacts 638-3 to 638-6. Fig. 6E A dashed line is shown in FIG. 6 to indicate that the via is below the fourth metal wiring 686 .

[0061] The third metal wiring 684 is coupled to the source / drain contacts 638-1 and 638-2 via vias 665-1 and 665-2, and is coupled to the gates 632-3 and 632-4 via vias 670-1 and 670-2. In other words, each of the vias 665-1 and 665-2 is coupled between a corresponding one of the source / drain contacts 638-1 and 638-2 and the third metal wiring 684, and each of the vias 670-1 and 670-2 is coupled between the corresponding gates 632-3 and 632-4 and the third metal wiring 684. The vias 665-1, 665-2, 670-1, and 670-2 are connected to the gates 632-3 and 632-4. Fig. 6E A dashed line is shown in FIG. 6 to indicate that the via is below the third metal wiring 684 .

[0062] In this example, the third metal wiring 684 and the fourth metal wiring 686 are coupled through the second bridge 650, which couples the source / drain contact 638-2, the gate 632-2, and the source / drain contact 638-3 together. Therefore, the third metal wiring 684 and the fourth metal wiring 686 are at approximately the same potential. This exemplary layout forms three n-type devices coupled to a common potential. In some aspects, the third metal wiring 684 and the fourth metal wiring 686 can be coupled to Figure 4 Thus, in this example, the layout forms three n-type devices coupled to the low rail 415 (which is at a lower potential than the power rail 435).

[0063] therefore, Fig. 6E The exemplary layout shown in FIG. 4 forms three p-type devices coupled to power rail 435 and three n-type devices coupled to low rail 415. The p-type devices and the n-type devices form reverse biased diodes (e.g., diode 510) between power rail 435 and low rail 415, where the capacitance of the diodes provides a decoupling capacitor between power rail 435 and low rail 415.

[0064] It should be understood that Fig. 6EThe number of gates and the number of source / drain contacts shown in are merely exemplary, and layout techniques according to aspects of the present disclosure are not limited to a specific number of gates and a specific number of source / drain contacts.

[0065] Fig. 6E The exemplary layout shown in FIG. 1 can be used to define a decoupling capacitor cell (also referred to as a decapacitor cell) in a standard cell library. In the layout of chip 100, the decapacitor cell can be inserted into the entire power delivery network to provide a decoupling capacitor in the entire power delivery network. Other implementations of the decoupling capacitor cell may include different numbers of p-type devices and / or n-type devices.

[0066] Figure 7 Shows that it can be used Fig. 6E . A circuit diagram of an example of a decoupling capacitor 735 implemented with the exemplary layout shown in FIG. One terminal 740 of the decoupling capacitor 735 is coupled to the power rail 435 (also referred to as the power supply voltage rail) that provides the supply voltage Vdd, and the other terminal 745 of the decoupling capacitor 735 is coupled to the low rail 415, which is at a lower potential than the power rail 435. For example, the low rail 415 can be a ground rail coupled to ground, but is not limited to this example. Terminal 740 can correspond to Fig. 6E The first metal wiring 680 and the second metal wiring 682 are shown in FIG. 4 , which are coupled to the power rail 435 in this example. The terminal 745 may correspond to Fig. 6E 4. The third metal wiring 684 and the fourth metal wiring 686 are shown in FIG. 4, and in this example, the third metal wiring 684 and the fourth metal wiring 686 are coupled to the lower rail 415.

[0067] Example implementations are described in the following numbered clauses:]

[0068] 1. A chip, comprising:

[0069] a first source / drain contact formed on the first oxide diffusion (OD);

[0070] first gates, wherein each of the first gates is disposed between a corresponding pair of first source / drain contacts;

[0071] a first bridge coupling a first one of the first source / drain contacts, a first one of the first gates, and a second one of the first source / drain contacts;

[0072] a first metal wiring coupled to a first one of the first source / drain contacts; and

[0073] A second metal wiring is coupled to a second one of the first source / drain contacts.

[0074] 2. The chip of clause 1, wherein the first OD is a p-type OD, and the first metal wiring and the second metal wiring are coupled to a power rail.

[0075] 3. The chip according to clause 1 or 2, wherein the first metal wiring is coupled to a third first source / drain contact among the first source / drain contacts, and the second metal wiring is coupled to a second first gate among the first gates.

[0076] 4. The chip of clause 3, wherein the first metal wiring is coupled to a fourth first source / drain contact of the first source / drain contacts, and the second metal wiring is coupled to a third first gate of the first gates.

[0077] 5. The chip according to any one of clauses 1 to 4, wherein each of the first gates extends in a first direction, and each of the first metal wiring and the second metal wiring extends in a second direction perpendicular to the first direction.

[0078] 6. The chip according to any of clauses 1 to 5, wherein the first bridge is formed by a contact layer.

[0079] 7. The chip according to clause 6, wherein the contact layer is a gate contact layer.

[0080] 8. The chip according to clause 6 or 7, wherein each of the first metal wiring and the second metal wiring is formed of an M0 metal layer or an M1 metal layer.

[0081] 9. A chip according to any one of clauses 1 to 8, further comprising:

[0082] a second source / drain contact formed on the second OD;

[0083] second gates, wherein each of the second gates is disposed between a corresponding pair of second source / drain contacts;

[0084] a second bridge coupling a first second source / drain contact of the second source / drain contacts, a first second gate of the second gates, and a second second source / drain contact of the second source / drain contacts;

[0085] a third metal wiring coupled to a first one of the second source / drain contacts; and

[0086] A fourth metal wiring is coupled to a second one of the second source / drain contacts.

[0087] 10. The chip of clause 9, wherein the first OD is a p-type OD, and the first metal wiring and the second metal wiring are coupled to a power rail.

[0088] 11. The chip of clause 10, wherein the second OD is an n-type OD, the third metal wiring and the fourth metal wiring are coupled to a low rail, and the low rail has a lower potential than the power rail.

[0089] 12. The chip of clause 11, wherein the low rail is coupled to ground.

[0090] 13. The chip according to any of clauses 9 to 12, wherein the first metal wiring is coupled to a third first source / drain contact of the first source / drain contacts, and the second metal wiring is coupled to a second first gate of the first gates.

[0091] 14. The chip of clause 13, wherein the third metal wiring is coupled to a third of the second source / drain contacts, and the fourth metal wiring is coupled to a second of the second gates.

[0092] 15. A chip according to any one of clauses 9 to 14, wherein each of the first gate and the second gate extends in a first direction, and each of the first metal wiring, the second metal wiring, the third metal wiring and the fourth metal wiring extends in a second direction perpendicular to the first direction.

[0093] 16. The chip according to any of clauses 9 to 15, wherein each of the first bridge and the second bridge is formed by a contact layer.

[0094] 17. The chip according to clause 16, wherein the contact layer is a gate contact layer.

[0095] 18. The chip according to clause 16 or 17, wherein each of the first metal wiring, the second metal wiring, the third metal wiring, and the fourth metal wiring is formed of an M0 metal layer or an M1 metal layer.

[0096] 19. A chip, comprising:

[0097] Power rails;

[0098] a low rail having a lower potential than the power rail; and

[0099] A decoupling capacitor is coupled between the power rail and the low rail. The decoupling capacitor includes:

[0100] a first source / drain contact formed on the first oxide diffusion (OD);

[0101] first gates, wherein each of the first gates is disposed between a corresponding pair of first source / drain contacts;

[0102] a first bridge coupling a first one of the first source / drain contacts, a first one of the first gates, and a second one of the first source / drain contacts;

[0103] a first metal wiring coupled to a first one of the first source / drain contacts; and

[0104] A second metal wiring is coupled to a second one of the first source / drain contacts, wherein the first metal wiring and the second metal wiring are coupled to a power rail.

[0105] 20. The chip according to clause 19, wherein the decoupling capacitor further comprises:

[0106] a second source / drain contact formed on the second OD;

[0107] second gates, wherein each of the second gates is disposed between a corresponding pair of second source / drain contacts;

[0108] a second bridge coupling a first second source / drain contact of the second source / drain contacts, a first second gate of the second gates, and a second second source / drain contact of the second source / drain contacts;

[0109] a third metal wiring coupled to a first one of the second source / drain contacts; and

[0110] A fourth metal wiring is coupled to a second one of the second source / drain contacts, wherein the third metal wiring and the fourth metal wiring are coupled to the low rail.

[0111] 21. The chip of clause 20, wherein the first OD is a p-type OD and the second OD is an n-type OD.

[0112] 22. The chip according to clause 20 or 21, wherein the first metal wiring is coupled to a third first source / drain contact of the first source / drain contacts, and the second metal wiring is coupled to a second first gate of the first gates.

[0113] 23. The chip of clause 22, wherein the third metal wiring is coupled to a third of the second source / drain contacts, and the fourth metal wiring is coupled to a second of the second gates.

[0114] 24. The chip according to any of clauses 20 to 23, wherein each of the first bridge and the second bridge is formed by a contact layer.

[0115] 25. The chip according to clause 24, wherein the contact layer is a gate contact layer.

[0116] 26. The chip according to any one of clauses 20 to 25, wherein each of the first metal wiring, the second metal wiring, the third metal wiring and the fourth metal wiring is formed of an M0 metal layer or an M1 metal layer.

[0117] 27. A chip according to any of clauses 19 to 26, wherein the low rail is coupled to ground.

[0118] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled," as used herein, refers to a direct or indirect electrical coupling between two structures.

[0119] Any reference to an element using names such as "first", "second", etc. herein generally does not limit the number or order of these elements. Rather, these names are used herein as a convenient way to distinguish between two or more elements or examples of elements. Therefore, referring to a first element and a second element does not mean that only two elements can be used, or that the first element must be before the second element.

[0120] The foregoing description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip, comprising: a first source / drain contact formed on the first oxide diffusion (OD); first gates, wherein each of the first gates is disposed between a corresponding pair of the first source / drain contacts; a first bridge coupling a first one of the first source / drain contacts, a first one of the first gates, and a second one of the first source / drain contacts; a first metal wiring coupled to the first of the first source / drain contacts; as well as A second metal wiring is coupled to the second first source / drain contact of the first source / drain contacts. 2 . The chip of claim 1 , wherein the first OD is a p-type OD, and the first metal wiring and the second metal wiring are coupled to a power rail. 3 . The chip according to claim 1 , wherein the first metal wiring is coupled to a third first source / drain contact among the first source / drain contacts, and the second metal wiring is coupled to a second first gate among the first gates. 4 . The chip according to claim 3 , wherein the first metal wiring is coupled to a fourth first source / drain contact among the first source / drain contacts, and the second metal wiring is coupled to a third first gate among the first gates. 5 . The chip according to claim 1 , wherein each of the first gates extends in a first direction, and each of the first metal wiring and the second metal wiring extends in a second direction perpendicular to the first direction. The chip according to claim 1 , wherein the first bridge is formed by a contact layer. The chip according to claim 6 , wherein the contact layer is a gate contact layer. 8 . The chip according to claim 6 , wherein each of the first metal wiring and the second metal wiring is formed of an M0 metal layer or an M1 metal layer.

9. The chip according to claim 1, further comprising: a second source / drain contact formed on the second OD; a second gate, wherein each of the second gates is disposed between a corresponding pair of the second source / drain contacts; a second bridge coupling a first second source / drain contact of the second source / drain contacts, a first second gate of the second gates, and a second second source / drain contact of the second source / drain contacts; a third metal wiring coupled to the first of the second source / drain contacts; as well as A fourth metal wiring is coupled to the second of the second source / drain contacts. 10 . The chip of claim 9 , wherein the first OD is a p-type OD, and the first metal wiring and the second metal wiring are coupled to a power rail. 11 . The chip according to claim 10 , wherein the second OD is an n-type OD, the third metal wiring and the fourth metal wiring are coupled to a low rail, and the low rail has a lower potential than the power rail.

12. The chip of claim 11, wherein the low rail is coupled to ground. 13 . The chip according to claim 9 , wherein the first metal wiring is coupled to a third first source / drain contact among the first source / drain contacts, and the second metal wiring is coupled to a second first gate among the first gates. 14 . The chip according to claim 13 , wherein the third metal wiring is coupled to a third second source / drain contact of the second source / drain contacts, and the fourth metal wiring is coupled to a second second gate of the second gates.

15. The chip according to claim 9, wherein each of the first gate and the second gate extends in a first direction, and each of the first metal wiring, the second metal wiring, the third metal wiring, and the fourth metal wiring extends in a second direction perpendicular to the first direction. 16 . The chip according to claim 9 , wherein each of the first bridge and the second bridge is formed of a contact layer. The chip according to claim 16 , wherein the contact layer is a gate contact layer. 18 . The chip according to claim 16 , wherein each of the first metal wiring, the second metal wiring, the third metal wiring, and the fourth metal wiring is formed of an M0 metal layer or an M1 metal layer.

19. A chip, comprising: Power rails; a low rail having a lower potential than the power rail; as well as A decoupling capacitor coupled between the power rail and the low rail, the decoupling capacitor comprising: a first source / drain contact formed on the first oxide diffusion (OD); first gates, wherein each of the first gates is disposed between a corresponding pair of the first source / drain contacts; a first bridge coupling a first one of the first source / drain contacts, a first one of the first gates, and a second one of the first source / drain contacts; a first metal wiring coupled to the first of the first source / drain contacts; and A second metal wiring is coupled to the second of the first source / drain contacts, wherein the first metal wiring and the second metal wiring are coupled to the power rail.

20. The chip according to claim 19, wherein the decoupling capacitor further comprises: a second source / drain contact formed on the second OD; second gates, wherein each of the second gates is disposed between a corresponding pair of the second source / drain contacts; a second bridge coupling a first second source / drain contact of the second source / drain contacts, a first second gate of the second gates, and a second second source / drain contact of the second source / drain contacts; a third metal wiring coupled to the first of the second source / drain contacts; as well as A fourth metal wiring is coupled to a second one of the second source / drain contacts, wherein the third metal wiring and the fourth metal wiring are coupled to the lower rail. The chip according to claim 20 , wherein the first OD is a p-type OD, and the second OD is an n-type OD. 22 . The chip of claim 20 , wherein the first metal wiring is coupled to a third first source / drain contact among the first source / drain contacts, and the second metal wiring is coupled to a second first gate among the first gates. 23 . The chip of claim 22 , wherein the third metal wiring is coupled to a third one of the second source / drain contacts, and the fourth metal wiring is coupled to a second one of the second gates. 24 . The chip according to claim 20 , wherein each of the first bridge and the second bridge is formed of a contact layer. The chip according to claim 24 , wherein the contact layer is a gate contact layer. 26 . The chip according to claim 20 , wherein each of the first metal wiring, the second metal wiring, the third metal wiring, and the fourth metal wiring is formed of an M0 metal layer or an M1 metal layer.

27. The chip of claim 19, wherein the low rail is coupled to ground.

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