Primary side current monitoring device and system
By designing a primary current monitoring device including a central processing module, a control module and a data sampling module, the problem of difficult recording of harmonic interference transient signals in the EMU is solved, real-time data recording and analysis are realized, and fault analysis capabilities are improved.
Patent Information
- Application Number
- CN202411836238.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-18
AI Technical Summary
During the real-time monitoring and control of primary current of EMUs, it is difficult for the prior art to accurately locate and record the harmonic interference transient spike signals in the contact network current, affecting fault traceability and analysis.
A primary current monitoring device is designed, including a central processing module, a control module and a data sampling module. By adding hardware acquisition paths and flexible configuration channels, real-time calibration of the acquisition circuit and data recording, exporting and parsing of the fault moments are realized.
Real-time recording and analysis of key data is realized, transient signals can be accurately positioned and recorded, the ability to trace faults and analyze problems is improved, and the safety and stability of the EMU operation is ensured.
Smart Images
Figure CN119846288A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of EMU control, and in particular to a primary current monitoring device and system. Background Art
[0002] The real-time monitoring and control of the primary current of the EMU is mainly completed by the primary current monitoring board (PCM). In the existing control strategy, current monitoring and rapid protection are performed by hardware circuits, and the configuration is relatively fixed, which only judges and executes the corresponding protection actions. During the operation of the EMU, the contact network current and the primary current value of the traction transformer are the key parameters of the vehicle operation. The size of the primary current value affects the safety and stability of the whole vehicle operation. Therefore, it is particularly important to monitor the contact network current and the primary current of the transformer, control it in real time, and record and analyze it. Summary of the invention
[0003] The purpose of this application is to provide a primary current monitoring device and system. On the basis of the original scheme of 4 acquisition channels, a hardware acquisition channel is added, and at the same time, flexible configuration of the channel is realized, real-time calibration of the acquisition circuit is increased, and data recording, exporting and analysis at the time of fault are added, so as to solve the problem that transient spike signals of harmonic interference during driving cannot be accurately located and recorded, which is not conducive to tracing and analyzing the fundamental problem.
[0004] To achieve the above-mentioned purpose, the primary current monitoring device provided in the present application comprises a central processing module, a control module and a data sampling module; the central processing module is connected to the data sampling module, and is used to perform timing control on the data sampling module, and analyze and calculate the data collected by the data sampling module using a preset algorithm to obtain a real-time value and an effective value, and, through a state machine conversion, provides communication between baseboard components and a data channel between the control module and an external system; the control module is connected to the central processing module, and is used to call a preset control strategy according to the matching of the real-time value and the effective value, and, according to the received communication request, controls the central processing module to perform a state machine conversion; the data sampling module uses a preset processing chip to collect the contact network current and the primary current data of the traction transformer through an operational amplifier conditioning circuit.
[0005] In the above-mentioned primary current monitoring device, optionally, the device also includes a storage module and a serial interface; the storage module and the serial interface are respectively connected to the control module; wherein the storage unit is used to store preset calibration parameters; the serial interface is used to provide remote IAP calls between the control module and an external host computer.
[0006] In the above-mentioned primary current monitoring device, optionally, the control module also includes a verification unit; the verification unit is connected to the storage module, and is used to obtain the calibration parameters pre-stored in the storage module during the analog channel calibration stage, calculate the actual physical value according to the linearity calibration formula, and perform channel calibration on the analog channel through the actual physical value.
[0007] In the above-mentioned primary current monitoring device, optionally, the central processing module includes a comparison unit, and the comparison unit is used to compare the data collected by the data sampling module for multiple times to obtain a maximum value, and record the maximum value in a latch.
[0008] In the above-mentioned primary current monitoring device, optionally, the central processing module includes a state machine unit and a bus unit; the bus unit includes the backplane ISA bus of the central processing module, the FMC bus of the control module and the parallel bus of the data sampling module of the central processing module; the state machine unit is used to execute corresponding bus occupancy control according to the interrupt requests received from the backplane bus, the data sampling module and the control module.
[0009] In the above-mentioned primary current monitoring device, optionally, the state machine unit is also used to determine the occupancy status of the bus unit according to the received interrupt request, and when the bus unit is occupied, respond to the terminal request through a preset processing function and use the currently occupied bus unit.
[0010] In the above-mentioned primary current monitoring device, optionally, the state machine unit is also used to compare the priorities corresponding to the interrupt requests when receiving multiple interrupt requests, and respond to the interrupt requests in sequence according to the comparison results.
[0011] In the above-mentioned primary current monitoring device, optionally, the central processing module further includes a watchdog unit, and the watchdog unit is communicatively connected to the control module, and is used to reset the control module when the feeding information provided by the control module is not received within a preset period.
[0012] In the above-mentioned primary current monitoring device, optionally, the device further includes a watchdog module, which is communicatively connected to the central processing module and is used to reset the central processing module when the feeding information provided by the central processing module is not received within a preset period.
[0013] The present application also provides a control system, which includes the above-mentioned primary current monitoring device.
[0014] The beneficial technical effects of this application are: Data calibration: During the analog channel calibration phase, there is a certain linear error in the analog acquisition link. Channel calibration is used to ensure that the error is reduced to the allowable range. First, the E2PROM is tested. If it is normal, the calibration parameters are read from the E2PROM, and the actual physical value is calculated according to the linearity calibration formula. If it does not exist, the default value is used as the calibration parameter. Prevent the problem of channel value distortion caused by failure to read the calibration parameters. Control strategy optimization: Compared with the previous pure hardware circuit design, this design adopts a control strategy of software and hardware. The algorithm is more flexible and convenient. The control strategy can be flexibly configured through software, such as channel threshold setting, time parameter setting for triggering fault latching, setting of statistical value of triggering over-limit times, setting of effective value dynamic response speed, setting of integral depth, dynamic setting of sampling frequency, etc. The specific parameters can be configured according to the actual working conditions to achieve a better control strategy effect. Data recording and analysis: During the operation of the EMU, the transient spike signal of the harmonic interference of the contact network cannot be accurately located and recorded, which is not conducive to the tracing and analysis of the fundamental problem. This design realizes the real-time recording, data export and analysis functions of key data. It plays a vital role in fault tracing and analysis. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The drawings described herein are used to provide a further understanding of the present application, constitute a part of the present application, and do not constitute a limitation of the present application. In the drawings:
[0016] Figure 1 A schematic diagram of the structure of a primary current monitoring device provided in one embodiment of the present application;
[0017] Figure 2A A schematic diagram of the structure of a primary current monitoring device provided in one embodiment of the present application;
[0018] Figure 2B A schematic diagram of the application logic of a primary current monitoring device provided by an embodiment of the present application;
[0019] Figure 3 A schematic diagram of an analog channel calibration process provided in an embodiment of the present application;
[0020] Figure 4 A schematic diagram of a control module processing flow provided in an embodiment of the present application;
[0021] Figure 5 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION
[0022] The following will describe the implementation methods of the present application in detail in conjunction with the accompanying drawings and embodiments, so that the implementation process of how the present application applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that as long as there is no conflict, the various embodiments in the present application and the various features in the embodiments can be combined with each other, and the technical solutions formed are all within the protection scope of the present application.
[0023] In addition, the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be performed in an order different from that shown here.
[0024] Please refer to Figure 1 As shown, the primary current monitoring device 100 provided in the present application may include a central processing module 1001, a control module 1002 and a data sampling module 1003; the central processing module 1001 is connected to the data sampling module 1003, and is used to perform timing control on the data sampling module, analyze and calculate the data collected by the data sampling module using a preset algorithm to obtain a real-time value and an effective value, and provide communication between baseboard components and a data channel between the control module 1002 and an external system through a state machine conversion; the control module 1002 is connected to the central processing module 1001, and is used to call a preset control strategy according to the matching of the real-time value and the effective value, and control the central processing module to perform a state machine conversion according to the received communication request; the data sampling module 1003 uses a preset processing chip to collect the contact network current and the primary current data of the traction transformer through an operational amplifier conditioning circuit.
[0025] The timing control can control the acquisition frequency of the data acquisition module through the result obtained by the root mean square operation of high-speed sampling; the algorithm used for analyzing and calculating the data collected by the data sampling module can be the following function:
[0026]
[0027] In the above formula, T is the integration time, u(t) is the response of the AC input signal to time, and U is the effective value calculation result.
[0028] Specifically, in actual work, the monitoring of the primary current and contact network current of the present application is mainly completed by the primary current monitoring board (PCM), and the calibration data collected by each channel is compared with the benchmark in the software algorithm to obtain the compensation coefficient, and then the compensation coefficient is used to correct the subsequent real-time data for real-time calibration, that is, the data collection and real-time calibration, monitoring and protection strategy, real-time recording of data, data export and analysis of 6 channels such as contact network side current and traction transformer primary current are newly added, and the change curve of abnormal data is formed by analyzing the host computer software. Among them, the control module 1002 can use STM32F107 as the main controller, that is, the control module MCU, which is mainly responsible for the selection and configuration of the board channel, data calibration, access to the on-chip memory, power-on initialization configuration and host computer serial data transmission, and interacts with other control systems through the backplane bus. In terms of data sampling, a high-speed AD chip with 8 parallel inputs is used as the data sampling module 1003, and its maximum sampling frequency is 200K, which supports continuous conversion of analog sampling and parallel bus reading, and provides a strong guarantee for high-speed sampling. The FPGA chip is used as the central processing module 1001 to realize the timing control of the AD chip, and the real-time value processing and effective value calculation of the analog AC signal are realized through the software algorithm, and sent to the MCU for corresponding control strategy.
[0029] For further information, please refer to Figure 2A As shown, the device may also include a storage module 1004 and a serial interface 1005; the storage module 1004 and the serial interface 1005 are respectively connected to the control module 1002; wherein the storage module 1004 is used to store preset calibration parameters; the serial interface 1005 is used to provide remote IAP calls between the control module and an external host computer.
[0030] Specifically, in actual work, Figure 2B As shown, the storage module is the memory on the board. The on-board memory of the board can use FM25V20 non-volatile NVRAM, support SPI serial communication, and have a storage space size of 4Mbit. The front connector of the board is equipped with an RS232 serial interface to realize the remote IAP function between the controller and the host computer.
[0031] In one embodiment of the present application, the control module further includes a verification unit; the verification unit is connected to the storage module, and is used to obtain the calibration parameters pre-stored in the storage module during the analog channel calibration stage, calculate the actual physical value according to the linearity calibration formula, and perform channel calibration on the analog channel through the actual physical value.
[0032] Specifically, Figure 3As shown in the figure, during the analog channel calibration stage, there is a certain linear error in the analog acquisition link. Channel calibration is used to ensure that the error is reduced to the allowable range. First, the storage module, namely the E2PROM, is tested. If it is normal, the calibration parameters are read from the E2PROM, and the actual physical value is calculated according to the linearity calibration formula. If it does not exist, the default value is used as the calibration parameter to prevent the problem of channel value distortion caused by failure to read the calibration parameters.
[0033] In the above embodiment, the storage module can use the storage chip FM25V10, which is a non-volatile NVRAM chip. The chip supports SPI serial access, with a speed of nanoseconds and unlimited reading and writing. The power-off storage is maintained for more than 15 years. Three recording areas are set in the storage chip. Each time the power is turned on, the single-chip microcomputer reads the address of the last record from the NVRAM, records it cyclically, and writes it into the register. The data area information is shown in Table 1 below:
[0034] Table 1
[0035] Offset Recording period Recording duration illustrate 0x000~0x20000 1ms 2s Recording area 1 status indication 0x20000~0x40000 1ms 2s Recording area 2 status indication 0x40000~0x60000 1ms 2s Recording area 3 status indication 0x80000~0x90000 1ms 2s Event log area
[0036] The size of each data area is set to 20000Byte, where information is stored starting from the offset address, storing the high voltage analog data of 5 channels. The status information of the event recording area will save the log information of all trigger states.
[0037] In one embodiment of the present application, the central processing module includes a comparison unit, which is used to compare the data collected by the data sampling module for multiple comparisons to obtain a maximum value, and record the maximum value in a latch.
[0038] Specifically, in actual work, the central processing module, i.e., FPGA, is responsible for realizing the high-speed AD sampling function of the data sampling module, i.e., ADC chip, completing the initialization configuration of important parameters such as ADC sampling frequency, oversampling rate, gain, etc., completing the management and data access of the AD acquisition channel, and comparing the collected data N times to select the maximum value and record it in the latch. ADC sampling frequency setting method, Sample Rate = 50000 / (500+VALUE), unit kHz.
[0039] In the above embodiment, the ADC chip can adopt the high-speed parallel processing chip AD7606. The ADC is equipped with 8-way parallel synchronous acquisition, 16-bit data width, bipolar input impedance up to 1MΩ, and has a programmable filtering function. There are two ways of output: 16-bit parallel bus read and write and SPI high-speed serial read and write to meet the access requirements of various controllers. The interface configuration is simple and the program writing is convenient and fast. The acquisition range is -10V to +10V, and 10V corresponds to the full scale. A high-precision, low-noise 2.5V reference chip is provided outside the ADC chip. The voltage accuracy is 3mV, and the temperature drift is 10 parts per million / degree.
[0040] In the primary current monitoring device, the central processing module acts as a transfer hub to achieve high-speed sampling and data processing of high-voltage analog signals, and is responsible for the backplane communication and the interaction of key data between the MCU, playing a connecting role. The ECP5U series high-performance general-purpose processor can be used, and a large number of logic units are integrated internally, which is very suitable for data processing of alternating signals. In one embodiment, the central processing module includes a state machine unit and a bus unit; the bus unit includes the backplane ISA bus of the central processing module, the FMC bus of the control module, and the parallel bus of the central processing module data sampling module; the state machine unit is used to perform corresponding bus occupancy control according to the interrupt requests received from the backplane bus, the data sampling module, and the control module.
[0041] In the above embodiment, the specific implementation of the bus occupancy control is controlled by the state machine unit. Specifically, the state machine unit is used to determine the occupancy state of the bus unit according to the received interrupt request. When the bus unit is occupied, the terminal request is responded to through a preset processing function and the currently occupied bus unit is used. Further, the state machine unit is also used to compare the priorities corresponding to the interrupt requests when multiple interrupt requests are received, and respond to the interrupt requests in order according to the comparison results.
[0042] Specifically, the central processing module, i.e., FPGA, needs to take into account the CPU's backplane ISA bus, the MCU's FMC bus, and the FPGA's parallel bus for collecting AD data. At a certain moment, only one of the above buses can be occupied, so an arbitration function needs to be implemented. The solution to this is that FPGA responds to interrupt requests from the backplane bus, ADC chip, and single-chip microcomputer through state machine conversion. When the internal state machine detects the corresponding bus occupation application, the FPGA state machine will jump to the corresponding processing function to respond. After the response is completed, the bus occupation is released, and the state machine returns to the idle state to continue detecting real-time requests. When there are multiple applications, in order to avoid bus conflicts, the FPGA assigns interrupt priority to each application and responds in order of priority.
[0043] In one embodiment of the present application, the central processing module further includes a watchdog unit, which is in communication with the control module and is used to reset the control module when the feeding information provided by the control module is not received in a preset period. Further, the device further includes a watchdog module, which is in communication with the central processing module and is used to reset the central processing module when the feeding information provided by the central processing module is not received in a preset period.
[0044] Specifically, in order to facilitate monitoring of the operating status of the entire primary current monitoring device and automatically restart and recover when an abnormality is detected, this application provides a hardware watchdog reset function. The FPGA can implement the watchdog function through a software algorithm. When the control module MCU periodically feeds the dog and the FPGA fails, the control module MCU is reset. At the same time, an external watchdog chip is configured. When the FPGA fails, the external watchdog chip resets the FPGA. The watchdog chip can use the TPS3823 high-performance chip, which has a counter 200ms watchdog function, which is used to monitor the operating status of the FPGA. Once the hardware freezes or the software program runs away, the FPGA is reset.
[0045] Please refer to Figure 4 As shown, in the primary current monitoring device provided by the present application, the processing logic of the control module includes the following steps:
[0046] 1. Initialization: complete the operation parameter configuration of the entire system, including clock configuration, IO configuration, communication module configuration, ADC mode configuration, etc.;
[0047] 2. Calibration parameter acquisition: obtain the preset calibration parameters or default calibration parameters in the storage module for subsequent error compensation and acquisition value correction of actual acquisition channel data;
[0048] 3. Channel acquisition: complete channel data acquisition according to calibration parameters;
[0049] 4. Communication reset: reset the communication request to the ready state;
[0050] 5. Main loop:
[0051] 1) Perform channel data acquisition;
[0052] 2) Feed your dog regularly;
[0053] 3) Execute over-limit protection logic;
[0054] 4) Monitor and confirm the version and heartbeat of external boards;
[0055] 5) Execute fault recovery logic;
[0056] 6) Execute data logging;
[0057] 7) Return to the main loop header to continue execution.
[0058] The present application also provides a control system, which includes the above-mentioned primary current monitoring device. Specifically, in actual work, the control system is adjusted from the functions of undervoltage monitoring, fast discharge, delayed start, and voltage backflow prevention. The control system as a whole adopts 5V±5% power supply, and the board power inlet has a power monitoring chip. The voltage monitoring threshold can be configured through the hardware circuit. The present application adopts a monitoring threshold of 4.5V. If the input voltage is greater than 4.5V, the chip turns on the enable signal to drive the subsequent switch after the set delay, and the voltage is input to the board after the switch is turned on. Inside the board, the power supply has a MOS tube that discharges the voltage to the ground. When the board is powered on, the MOS is in a closed state and does not discharge the voltage to the ground. When the board is powered off, the MOS is turned on to the ground and the remaining voltage is discharged to the ground. Since the principle of solving the problem of the control system is similar to that of the primary current monitoring device, the implementation of the system can refer to the implementation of the primary current monitoring device, and the repeated parts will not be repeated.
[0059] The beneficial technical effects of this application are: Data calibration: During the analog channel calibration phase, there is a certain linear error in the analog acquisition link. Channel calibration is used to ensure that the error is reduced to the allowable range. First, the E2PROM is tested. If it is normal, the calibration parameters are read from the E2PROM, and the actual physical value is calculated according to the linearity calibration formula. If it does not exist, the default value is used as the calibration parameter. Prevent the problem of channel value distortion caused by failure to read the calibration parameters. Control strategy optimization: Compared with the previous pure hardware circuit design, this design adopts a control strategy of software and hardware. The algorithm is more flexible and convenient. The control strategy can be flexibly configured through software, such as channel threshold setting, time parameter setting for triggering fault latching, setting of statistical value of triggering over-limit times, setting of effective value dynamic response speed, setting of integral depth, dynamic setting of sampling frequency, etc. The specific parameters can be configured according to the actual working conditions to achieve a better control strategy effect. Data recording and analysis: During the operation of the EMU, the transient spike signal of the harmonic interference of the contact network cannot be accurately located and recorded, which is not conducive to the tracing and analysis of the fundamental problem. This design realizes the real-time recording, data export and analysis functions of key data. It plays a vital role in fault tracing and analysis.
[0060] Figure 5 A schematic diagram of the physical structure of an electronic device provided in an embodiment of the present invention, such as Figure 5 As shown, the electronic device includes: a processor (processor) 501, a memory (memory) 502 and a bus 503.
[0061] The processor 501 and the memory 502 communicate with each other via a bus 503 .
[0062] The processor 501 is used to call the program instructions in the memory 502 to execute the methods provided by the above method embodiments.
[0063] The embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above Figure 4 The processing logic method shown.
[0064] The embodiment of the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program being executed by a processor to implement the above Figure 4 The processing logic method shown.
[0065] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.
[0066] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0067] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0068] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0069] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.
Claims
1. A primary current monitoring device, characterized in that: The device comprises a central processing module, a control module and a data sampling module; The central processing module is connected to the data sampling module, and is used to perform timing control on the data sampling module, analyze and calculate the data collected by the data sampling module using a preset algorithm to obtain real-time values and effective values, and provide communication between the backplane components and data channels between the control module and the external system through state machine conversion; The control module is connected to the central processing module, and is used to call a preset control strategy according to the matching of the real-time value and the effective value, and to control the central processing module to perform state machine conversion according to the received communication request; The data sampling module uses a preset processing chip to collect the contact network current and the primary current data of the traction transformer through an operational amplifier conditioning circuit.
2. The primary current monitoring device according to claim 1, characterized in that: The device also includes a storage module and a serial interface; The storage module and the serial interface are respectively connected to the control module; Wherein, the storage module is used to store preset calibration parameters; the serial interface is used to provide remote IAP calling between the control module and an external host computer.
3. The primary current monitoring device according to claim 2, characterized in that: The control module also includes a verification unit; the verification unit is connected to the storage module, and is used to obtain the calibration parameters pre-stored in the storage module during the analog channel calibration stage, calculate the actual physical value according to the linearity calibration formula, and perform channel calibration on the analog channel through the actual physical value.
4. The primary current monitoring device according to claim 1, characterized in that: The central processing module comprises a comparison unit, and the comparison unit is used to compare the data collected by the data sampling module for multiple times to obtain a maximum value, and record the maximum value in a latch.
5. The primary current monitoring device according to claim 1, characterized in that: The central processing module includes a state machine unit and a bus unit; The bus unit includes a backplane ISA bus of the central processing module, an FMC bus of the control module and a parallel bus of a data acquisition sampling module of the central processing module; The state machine unit is used to execute corresponding bus occupancy control according to the received interrupt requests of the backplane bus, the data sampling module and the control module.
6. The primary current monitoring device according to claim 5, characterized in that: The state machine unit is also used to determine the occupation state of the bus unit according to the received interrupt request, and when the bus unit is occupied, respond to the interrupt request through a preset processing function and use the currently occupied bus unit.
7. The primary current monitoring device according to claim 5, characterized in that: The state machine unit is further configured to compare priorities corresponding to the interrupt requests when receiving multiple interrupt requests, and respond to the interrupt requests in sequence according to the comparison results.
8. The primary current monitoring device according to claim 1, characterized in that: The central processing module further includes a watchdog unit, which is communicatively connected to the control module and is used to reset the control module when the feeding information provided by the control module is not received within a preset period.
9. The primary current monitoring device according to claim 1, characterized in that: The device further comprises a watchdog module, which is communicatively connected with the central processing module and is used for resetting the central processing module when the feeding information provided by the central processing module is not received within a preset period.
10. A control system, characterized in that: The control system comprises the primary current monitoring device according to any one of claims 1 to 9.