A Multi-Chip Fair Scheduling Method Based on ZNS SSD

Abstract

This invention relates to a multi-chip fairness scheduling method based on ZNS SSDs, comprising: calculating the latency penalty ratio of each current data flow in each chip queue for all current data flows of the ZNS SSD; calculating the fairness of each chip queue based on the latency penalty ratio of each current data flow in each chip queue; for each chip queue, taking the latest transaction allocated to each chip queue as the transaction to be scheduled, and scheduling the transaction to be scheduled forward in the chip queue based on the latency penalty ratio of the current data flows related to each chip queue in the chip queue, with the optimization objective of maximizing the fairness of the chip queue; and scheduling all transactions related to the request of the transaction to be scheduled to the maximum position in the corresponding chip queue according to the maximum position of all transactions in the corresponding chip queue, thereby improving the response time of the request. This invention improves the performance of ZNS SSDs.

Description

Technical Field

[0001] This invention belongs to the field of computer storage technology, and in particular relates to a multi-chip fairness scheduling method based on ZNS SSD. Background Technology

[0002] With the rapid development of information technology, storage systems have become an indispensable and important component of computer architecture. Although traditional SATA solid-state drives (HDDs) and NVMe solid-state drives (SSDs) have made significant achievements in improving storage performance and speed, these traditional solutions still fall short when facing the severe challenges of big data processing and cloud computing applications. The mismatch between traditional block interfaces and flash memory media leads to a series of problems such as write amplification, performance fluctuations, and high latency.

[0003] To address these challenges, ZNS SSD (Zone Namespaced SSD) emerged as an innovative storage solution. ZNS SSD divides the SSD into multiple independent Zones, stipulating that only sequential write operations are allowed within each Zone. This significantly reduces the size of the address mapping table, effectively mitigating write amplification and thus improving the overall performance of the storage system. This design not only preserves a standardized ecosystem but also grants the host side more flexible control over data placement, thereby optimizing storage management and improving storage efficiency.

[0004] However, ZNS SSDs divide the logical address space into multiple partitions and map them to multiple flash memory chips, introducing the concept of multi-chip queues. In practical applications, a request issued by the host is often split into transactions in multiple chip-level queues for parallel execution. However, current research mainly focuses on fair scheduling on a single queue, neglecting the overall request scheduling strategy, resulting in limited overall performance improvements. Summary of the Invention

[0005] To address the problems existing in the background art, this invention provides a multi-chip fairness scheduling method based on ZNS SSD, comprising:

[0006] S1: For all current data streams of the ZNS SSD, calculate the latency loss ratio of each data stream in each chip queue;

[0007] S2: Calculate the fairness of each chip queue based on the latency penalty ratio of each data stream in each chip queue;

[0008] S3: For each chip queue, the latest transaction allocated to each chip queue is taken as the transaction to be scheduled. Based on the latency loss ratio of the data stream currently associated with each chip queue in the chip queue, the transaction to be scheduled is advanced in the chip queue with the goal of maximizing the fairness of the chip queue. The data stream associated with each chip queue includes: when a requested transaction is allocated to a chip queue in the data stream, then the data stream is associated with the chip queue; otherwise, it is not associated.

[0009] S4: Based on the maximum position of all transactions in the corresponding chip queue that belong to the request to be scheduled, schedule all transactions in the corresponding chip queue to the maximum position to optimize the response time of the request.

[0010] The present invention has at least the following beneficial effects

[0011] This invention significantly improves the overall performance of ZNS SSDs by comprehensively considering the performance differences of different data streams on different chip queues and optimizing transaction scheduling strategies accordingly. By identifying chip queues with performance bottlenecks or uneven resource allocation and optimizing them specifically, this invention optimizes resource utilization and improves the resource efficiency of the storage system. The scheduling method of this invention can flexibly address the challenges brought by large-scale data processing and cloud computing applications, providing a useful reference for innovative development in the storage system field. In summary, the multi-chip fairness scheduling method based on ZNS SSDs proposed in this invention optimizes storage system performance and resource utilization by comprehensively considering factors such as data stream performance differences, chip queue fairness, and request response time, providing strong support for large-scale data processing and cloud computing applications. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the method flow according to an embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram illustrating the I / O access workflow and partition mapping of the ZNS SSD according to an embodiment of the present invention;

[0014] Figure 3 This is an overall architecture diagram and implementation principle diagram of an embodiment of the present invention;

[0015] Figure 4 This is a schematic diagram of transaction scheduling according to an embodiment of the present invention;

[0016] Figure 5 This is a schematic diagram of multi-chip collaborative scheduling according to an embodiment of the present invention. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0018] Please see Figure 1 This invention provides a multi-chip fairness scheduling method based on ZNS SSD, comprising:

[0019] S1: For all current data streams of the ZNS SSD, calculate the latency loss ratio of each data stream in each chip queue;

[0020] S2: Calculate the fairness of each chip queue based on the latency penalty ratio of each data stream in each chip queue;

[0021] S3: For each chip queue, the latest transaction allocated to each chip queue is taken as the transaction to be scheduled. Based on the latency loss ratio of the data stream currently associated with each chip queue in the chip queue, the transaction to be scheduled is advanced in the chip queue with the goal of maximizing the fairness of the chip queue. The data stream associated with each chip queue includes: when a requested transaction is allocated to a chip queue in the data stream, then the data stream is associated with the chip queue; otherwise, it is not associated.

[0022] S4: Based on the maximum position of all transactions in the corresponding chip queue that belong to the request to be scheduled, schedule all transactions in the corresponding chip queue to the maximum position to optimize the response time of the request.

[0023] Please see Figure 2 and Figure 3 In this embodiment, Figure 2 For the I / O access workflow and partition mapping of ZNS SSD, from Figure 2As can be seen from the diagram, an I / O access workflow consists of four steps: First, I / O streams from different applications are submitted to the host-side DRAM, forming multiple submission queues. Second, the host interface logic on the device side cyclically retrieves requests from these queues and parses them into a series of 4KB page-sized transactions. Third, the partitioned flash translation layer provides address translation and transaction scheduling functions to insert transactions into multiple chip queues, with each transaction corresponding to one chip and each chip having its own queue. Fourth, the flash channel controller schedules transactions to the backend, executing them in the order they are scheduled. From the partition mapping diagram, we can see that a zone is typically mapped to multiple chips; therefore, a request will be executed in parallel on multiple chips. The request is considered complete only after all transactions are finished. Therefore, fair scheduling should consider the coordinated scheduling of transactions on multiple chips. Chips need time to respond to transactions; transactions that cannot be responded to in time are temporarily stored in the corresponding chip queue, waiting for a response. For transactions waiting for a response in the chip queue, the transaction scheduling module can schedule certain transactions forward or backward according to pre-agreed rules.

[0024] The multi-chip fairness scheduling method based on ZNS SSDs provided in this invention optimizes storage system performance and resource utilization by comprehensively considering factors such as data flow performance differences, chip queue fairness, and request response time. This method not only improves the overall performance of ZNS SSDs but also optimizes resource utilization, meeting the needs of large-scale data processing and cloud computing applications.

[0025] Preferably, the calculation of the latency penalty ratio for each current data stream in each chip queue includes:

[0026] S11: Based on the processing time of each transaction in each data stream on each chip, calculate the start time of each transaction in each data stream running independently on each chip, and the start time of each transaction in each data stream running together with transactions in other data streams on each chip.

[0027] In this embodiment, based on the processing time of each data stream's transactions on each chip, the start time of each data stream's transactions if they were running alone on that chip is calculated. This helps us understand the potential execution time of each data stream's transactions in the absence of interference from other data streams. Next, the start time of each data stream's transactions running concurrently with transactions from other data streams on each chip is calculated. This reflects the actual execution time of each data stream's transactions in a real multi-data stream environment.

[0028] Preferably, the calculation of the start time of the transaction for each current data stream running individually on each chip includes:

[0029] Assuming the q-th transaction of the current f-th data stream is running independently on the c-th chip, using PT c,f,q Let represent the processing time of the q-th transaction in the current f-th data stream on the c-th chip. Then, the start time of the i-th transaction in the current f-th data stream on the c-th chip is:

[0030]

[0031] in, This represents the start time of the i-th transaction in the current f-th data stream running independently on the c-th chip. NAT c This represents the next idle time for the c-th chip;

[0032] Preferably, the calculation of the start time for the current transaction of each data stream to run together with the transactions of other data streams on each chip includes:

[0033] Assuming that the q-th transaction of the current f-th data stream and transactions of other data streams are running together on the c-th chip, PT′ c,f,q Let represent the processing time of the q-th transaction in the current f-th data stream on the c-th chip. Then, the start time of the i′-th transaction in the current f-th data stream on the c-th chip is:

[0034]

[0035] in, This represents the start time of the i′-th transaction in the current f-th data stream, which runs concurrently with transactions in other data streams on the c-th chip. NAT′ c This represents the next idle time for the c-th chip;

[0036] In this embodiment, by comparing the start times of individual and joint operation, the degree of mutual influence between data streams can be preliminarily determined, providing a basis for subsequent calculation of latency loss ratio.

[0037] S12: Calculate the average response time of each data stream when it runs individually on each chip, based on the start time of each transaction in each data stream running on each chip alone and the time when each transaction in each data stream enters the chip queue.

[0038] Preferably, the response time for each data stream running individually on each chip includes:

[0039]

[0040] in, This represents the average response time of the current f-th data stream when it is run alone on the c-th chip; PT represents the start time of the i-th transaction in the current f-th data stream when it runs independently on the c-th chip. c,f,i AT represents the processing time of the i-th transaction in the f-th data stream on the c-th chip. c,f,i N represents the time when the i-th transaction of the f-th data stream enters the c-th chip queue. c,f This represents the number of transactions in the f-th data stream within the c-th chip queue.

[0041] S13: Calculate the average response time of each data stream when it runs together with other data streams on each chip, based on the start time of each data stream's transaction and the time when each data stream's transaction enters the chip queue.

[0042] Preferably, calculating the average response time of each data stream when it runs together with other data streams on each chip includes:

[0043]

[0044] in, This represents the average response time when the current f-th data stream and other data streams are running together on the c-th chip; PT′ represents the start time of the i′-th transaction in the current f-th data stream, which is running concurrently with transactions in other data streams on the c-th chip. c,f,i AT represents the processing time of the i-th transaction in the f-th data stream on the c-th chip. c,f,i ′ represents the time when the i′-th transaction of the f-th data stream enters the c-th chip-level queue, N c,f This represents the number of transactions in the f-th data stream within the c-th chip queue.

[0045] S14: Calculate the latency loss ratio of each data stream in each chip queue based on the average response time of each data stream running alone on each chip, and the average response time of the transactions of each data stream and the transactions of other data streams running together on each chip.

[0046] Preferably, the latency penalty ratio for each data stream in each chip queue includes:

[0047]

[0048] Among them, SD c,f This represents the latency penalty ratio of the f-th data stream in the c-th chip queue. This represents the average response time when the current f-th data stream and other data streams are running together on the c-th chip. This represents the average response time of the current f-th data stream when it is run alone on the c-th chip;

[0049] Preferably, the fairness of each chip queue includes:

[0050]

[0051] Among them, SD c,f This represents the latency loss ratio of the current f-th data stream in the c-th chip queue; min() represents the minimum value function; max() represents the maximum value function, f∈{1,2,…,f,…,F}, where F represents the number of current data streams.

[0052] In this embodiment, by calculating the start time and average response time of each data stream running independently on each chip and running concurrently with other data streams, the mutual impact between data streams can be accurately assessed. This helps to understand the latency loss caused by resource contention among various data streams in a multi-data-stream environment. By calculating the latency loss ratio of each data stream in each chip queue, the degree of latency loss suffered by the data stream due to shared resources in different chip queues can be quantitatively represented. Using the latency loss ratio of each chip queue, the fairness index of that queue can be calculated. This index reflects whether the system treats each data stream fairly when multiple data streams share the same chip resource, ensuring they receive a relatively balanced processing opportunity. Fairness assessment is crucial for improving overall system performance and user experience.

[0053] Please see Figure 4 Preferably, step S3 includes:

[0054] S31: Based on the fairness of each chip queue and the latency loss ratio of each data stream in each chip queue, divide the data streams associated with the chip queues into fair data streams and unfair data streams;

[0055] S32: For each chip queue, define the latest transaction to be scheduled assigned to the chip-level queue as N. First, determine whether there is an empty slot in the chip queue. If there is, schedule transaction N to the empty slot closest to the head of the chip queue.

[0056] S33: Determine whether the data stream to which transaction N belongs is an unfair data stream. If yes, proceed to step S34; otherwise, proceed to step S37.

[0057] S34: Determine the position of transaction W before transaction N in the chip queue. If transaction R and transaction N do not belong to the same data stream, then execute step S35; otherwise, execute step S37.

[0058] S35: Determine whether the latency loss ratio of the data stream to which transaction W belongs is less than that of the data stream to which transaction N belongs after scheduling transaction N to the position before transaction W. If yes, schedule transaction N to the position before transaction W; otherwise, execute step S37.

[0059] S36: Repeat steps S34 to S35;

[0060] S37: End the scheduling of transaction N.

[0061] In this embodiment, by considering the fairness of each chip queue and the latency loss ratio of each data stream in the chip queue, this step achieves intelligent scheduling of transactions to be scheduled. This scheduling strategy not only focuses on the performance of individual data streams but also aims to improve the fairness and efficiency of the entire system. Step S31 divides the relevant data streams into fair data streams and unfair data streams, which helps to identify those data streams that suffer greater latency loss due to uneven resource allocation. Through priority scheduling in subsequent steps, the performance of these unfair data streams can be gradually improved. Step S32 first checks whether there are empty slots in the chip queue. If so, transaction N is directly scheduled to the empty slot closest to the head of the queue. This strategy reduces unnecessary scheduling latency and improves the system's response speed. For transaction N identified as an unfair data stream, steps S33 to S35 attempt to schedule transaction N to a position that can better reduce the latency loss ratio of its data stream through a series of judgments and adjustments. This intelligent adjustment helps to balance the performance differences between different data streams and improve the overall fairness of the system. By comprehensively considering the fairness of the chip queue and the latency loss ratio of the data stream, intelligent scheduling of transactions to be scheduled is achieved. This scheduling strategy not only improves the efficiency and fairness of the system, but also helps to optimize resource allocation and enhance overall performance.

[0062] Preferably, step S31 includes:

[0063] S311: When the fairness of the chip-level queue is less than a set threshold, the data stream related to the chip queue is divided into a fair data stream; otherwise, step S312 is executed.

[0064] S312: Set the two cluster centers of the k-means algorithm to be the minimum and maximum latency loss ratios of the data streams related to the chip queue, respectively;

[0065] S313: For each data stream associated with the chip queue, calculate its latency loss ratio and the distance to the two cluster centers respectively, and assign the data stream to the cluster to which the nearest cluster center belongs;

[0066] S314: For each cluster, calculate the average of the latency loss ratios of all data streams within the cluster, and use this average as the new cluster center.

[0067] S315: Repeat steps S313 and S314 until the cluster centroids no longer change or the maximum number of iterations is reached. The data flow in the cluster with the smaller cluster centroid is taken as the fair data flow, and the data flow in the other cluster is taken as the unfair data flow.

[0068] In this embodiment, the k-means clustering algorithm dynamically divides the data streams related to the chip queue into fair and unfair data streams, providing a foundation for subsequent optimized scheduling. This division method not only improves the accuracy of clustering but also helps to enhance the fairness and overall performance of the system. By classifying data streams with smaller latency losses as fair data streams and data streams with larger latency losses as unfair data streams, step S31 provides a basis for subsequent optimized scheduling. During the scheduling process, transactions in unfair data streams can be given priority to reduce their latency loss ratio, thereby improving the fairness of the entire system.

[0069] Please see Figure 5 Preferably, step S4 includes:

[0070] S41: Define all transactions to which the latest transaction N assigned to the chip-level queue belongs as a set P = {P1, P2, ..., P...} i ,…,P n}, N∈P, where n represents the number of requests to which transaction N belongs;

[0071] S42: For each transaction P in set P, ... i Its position in the corresponding chip queue is defined as L i ;

[0072] S43: Calculation All transactions in set P are scheduled to L at their corresponding chip queue positions.

[0073] In this embodiment, by scheduling all transactions (set P) belonging to the transaction N most recently assigned to the chip-level queue to the same position L in their corresponding chip queues, centralized transaction processing is achieved. This optimizes the scheduling order, reduces transaction dispersion, improves transaction processing fairness, simplifies the scheduling strategy, and exhibits strong adaptability. These effects collectively improve the overall performance and stability of the system. By scheduling all transactions (set P) belonging to the transaction N most recently assigned to the chip-level queue to the same position L in their corresponding chip queues, it is ensured that these transactions can be processed in a more orderly manner. This helps reduce waiting time and processing latency between transactions, improving the overall processing efficiency of the system.

[0074] Please see Figure 4 ,according to Figure 4 As shown in the diagram, the newly arrived request is divided into four transactions located on chip 0, chip 1, chip 2, and chip 3 for execution. After the fairness check section above, the transaction is classified as an unfair flow and will therefore be scheduled forward. According to the principle of forward scheduling of unfair flows, transactions N located on chip 0 and chip 1 will be scheduled after transaction T_3, while transactions N located on chip 2 and chip 3 will remain at their current positions.

[0075] Please see Figure 5 , Figure 5 (a) shows how transactions that arrive in a new flow are scheduled if they belong to an unfair flow. The four transactions N on chip 0, chip 1, chip 2, and chip 3 all originate from the same request that belongs to flow 3. For new transactions on chip 0 and chip 1, transactions N on chip 2 and chip 3 will be aligned to improve the fairness of flow 3 while reducing the impact on ZNS SSD performance.

[0076] Figure 5 (b), Figure 5 (c) shows how fair flows should be scheduled. Figure 5 In (a), according to the unfair flow transaction scheduling method, transaction N should be scheduled and Figure 5 (a) Same position, such as Figure 5 (b) is the position, but since it is a fair flow, it cannot be forward-scheduled, so it is treated as follows: Figure 5 (c) shows the backward scheduling method, which aligns new transactions on chip 2 and chip 3 with new transactions on chip 0 and chip 1, leaving space R for subsequent new transactions to be scheduled, thus reducing the response time of subsequent new transactions.

[0077] In summary, this invention significantly improves the overall performance of ZNS SSDs by comprehensively considering the performance differences of different data streams on different chip queues and optimizing transaction scheduling strategies accordingly. By identifying chip queues with performance bottlenecks or uneven resource allocation and optimizing them specifically, this invention optimizes resource utilization and improves the resource efficiency of the storage system. The scheduling method of this invention can flexibly address the challenges brought by large-scale data processing and cloud computing applications, providing a useful reference for innovative development in the storage system field. In conclusion, the multi-chip fairness scheduling method based on ZNS SSDs proposed in this invention optimizes storage system performance and resource utilization by comprehensively considering factors such as data stream performance differences, chip queue fairness, and request response time, providing strong support for large-scale data processing and cloud computing applications.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A multi-chip fairness scheduling method based on ZNS SSD, characterized in that, include: S1: For all current data streams of the ZNS SSD, calculate the latency loss ratio of each data stream in each chip queue; The calculation of the latency penalty ratio for each current data stream in each chip queue includes: S11: Based on the processing time of each transaction in each data stream on each chip, calculate the start time of each transaction in each data stream running independently on each chip, and the start time of each transaction in each data stream running together with transactions in other data streams on each chip. S12: Calculate the average response time of each data stream when it runs individually on each chip, based on the start time of each transaction in each data stream running on each chip alone and the time when each transaction in each data stream enters the chip queue. S13: Calculate the average response time of each data stream when it runs together with other data streams on each chip, based on the start time of each data stream's transaction and the time when each data stream's transaction enters the chip queue. S14: Calculate the latency loss ratio of each data stream in each chip queue based on the response time of each data stream running alone on each chip and the response time of the transaction of each data stream and the transactions of other data streams running together on each chip; S2: Calculate the fairness of each chip queue based on the latency penalty ratio of each data stream in each chip queue; S3: For each chip queue, the latest transaction allocated to each chip queue is taken as the transaction to be scheduled. Based on the latency loss ratio of the data stream currently associated with each chip queue in the chip queue, the transaction to be scheduled is advanced in the chip queue with the goal of maximizing the fairness of the chip queue. The data stream associated with each chip queue includes: when a requested transaction is allocated to a chip queue in the data stream, then the data stream is associated with the chip queue; otherwise, it is not associated. S4: Based on the maximum position of all transactions in the corresponding chip queue that belong to the request to be scheduled, schedule all transactions in the corresponding chip queue to the maximum position to optimize the response time of the request.

2. The multi-chip fairness scheduling method based on ZNS SSD according to claim 1, characterized in that, The fairness of each chip queue includes: in, Indicates the current number The data stream in the first... The latency loss ratio of each chip queue; This represents a function that takes the minimum value. This represents the function that takes the maximum value. , This indicates the number of data streams currently in operation.

3. The multi-chip fairness scheduling method based on ZNS SSD according to claim 1, characterized in that, Step S3 includes: S31: Based on the fairness of each chip queue and the latency loss ratio of each data stream in each chip queue, divide the data streams associated with the chip queues into fair data streams and unfair data streams; S32: For each chip queue, define the latest scheduled transaction assigned to the chip-level queue as... First, determine if there is an empty slot in the chip queue. If there is, schedule transaction N to the empty slot closest to the head of the chip queue. S33: Determine the transaction Is the data stream to which it belongs an unfair data stream? If so, proceed to step S34; otherwise, proceed to step S37. S34: Determine the transaction The transaction preceding the one in the chip queue If transaction With transactions If they do not belong to the same data stream, proceed to step S35; otherwise, proceed to step S37. S35: Determine whether the latency loss ratio of the data stream to which transaction W belongs is less than that of the data stream to which transaction N belongs after scheduling transaction N to the position before transaction W. If yes, schedule transaction N to the position before transaction W; otherwise, execute step S37. S36: Repeat steps S34~S35; S37: End the scheduling of transaction N.

4. The multi-chip fairness scheduling method based on ZNS SSD according to claim 3, characterized in that, Step S31 includes: S311: When the fairness of the chip-level queue is less than a set threshold, the data stream related to the chip queue is divided into a fair data stream; otherwise, step S312 is executed. S312: Set the two cluster centers of the k-means algorithm to be the minimum and maximum latency loss ratios of the data streams related to the chip queue, respectively; S313: For each data stream associated with the chip queue, calculate its latency loss ratio and the distance to the two cluster centers respectively, and assign the data stream to the cluster to which the nearest cluster center belongs; S314: For each cluster, calculate the average of the latency loss ratios of all data streams within the cluster, and use this average as the new cluster center. S315: Repeat steps S313 and S314 until the cluster centroids no longer change or the maximum number of iterations is reached. The data flow in the cluster with the smaller cluster centroid is taken as the fair data flow, and the data flow in the other cluster is taken as the unfair data flow.

5. The multi-chip fairness scheduling method based on ZNS SSD according to claim 1, characterized in that, Step S4 includes: S41: Define all transactions to which the latest transaction N assigned to the chip-level queue belongs as a set. , Indicates the number of requests to which transaction N belongs; S42: Set Each transaction Its position in the corresponding chip queue is defined as ; S43: Calculation , will set All transactions are scheduled to their corresponding chip queue positions. Place.

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