Method for expanding EMMC interface based on parallel bus
By setting up a logic circuit for extending the EMMC interface in the embedded system, the problem of the data processing module lacking an EMMC controller is solved, and large-capacity storage data recording is realized, which improves the universality and portability of the EMMC interface.
Patent Information
- Application Number
- CN202411712709.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-04-18
AI Technical Summary
In embedded systems, some data processing modules lack EMMC controllers, and cannot realize mass storage data processing and recording. Traditional memory cannot meet capacity, read and write rates and packaging size requirements.
Using the method of extending the EMMC interface based on parallel bus, portable logic circuits are set up, including EMMC initialization, data cache and control modules, and the initialization, data transmission and reception and control of the EMMC interface are realized through Verilog language simulation test.
It improves the versatility and portability of the EMMC interface, realizes the modular large-capacity storage data recording function, and enhances the flexibility and expansion of the interface circuit.
Smart Images
Figure CN119847952A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of embedded system design, and in particular relates to a method for extending an EMMC interface based on a parallel bus. Background Art
[0002] In the embedded field, the demand for data processing and large-capacity storage functions is increasing, mainly for big data processing, acquisition and recording. Traditional data storage FLASH, ROM and single-chip SSD cannot meet the demand in terms of capacity, read and write speed, package size and circuit design. EMMC (Embedded Multi Media Card) is mainly a standard format for embedded storage in products such as mobile phones or tablets, and has great advantages for embedded system data processing and large-capacity storage.
[0003] In embedded system design, some data processing module processor chips do not have EMMC controllers and cannot achieve large-capacity storage data processing and recording by connecting EMMC chips. Summary of the invention
[0004] In view of this, the present invention provides a method for extending an EMMC interface based on a parallel bus, and implements a large-capacity storage data recording function of an embedded system data processing module based on the method for extending an EMMC interface based on a parallel bus.
[0005] The technical solution of the present invention is:
[0006] A method for extending the EMMC interface based on a parallel bus:
[0007] A portable parallel bus expansion EMMC interface logic circuit is provided to realize the communication between the parallel bus and the EMMC interface of the EMMC chip;
[0008] The interface logic circuit comprises an EMMC initialization module, an EMMC data cache module and an EMMC control module.
[0009] The interface logic circuit and the EMMC chip communicate with the EMMC interface based on CMD, DATA and CLK signals.
[0010] Furthermore, the interface logic circuit is connected to the local parallel bus of the CPU, and the interface logic circuit implements the control of the EMMC interface and the data transmission and reception based on the instructions of the CPU.
[0011] Furthermore, the EMMC initialization module is used to implement the initialization of the EMMC interface, including: chip ID acquisition, address space allocation, clock configuration, CSD register acquisition, and working mode configuration.
[0012] Furthermore, the EMMC data cache module is used for caching the data received and sent by the EMMC interface, including: FIFO working mode configuration and receiving and sending data bit width configuration.
[0013] Furthermore, the EMMC control module is used to implement read and write control, erase control and bus test of the EMMC interface.
[0014] Furthermore, the EMMC initialization module is also used for configuring the data bit width.
[0015] Furthermore, the method for extending the EMMC interface based on a parallel bus verifies the interface logic circuit in the following manner:
[0016] Verilog language is used to simulate the test code, simulate the CPU local parallel bus and EMMC interface excitation signal, and test the function of the interface logic circuit.
[0017] Beneficial effects of the present invention:
[0018] The present invention adopts Verilog language to implement EMMC controller design, realizes the conversion from parallel bus to EMMC protocol, forms modular standard EMMC interface, improves the versatility and portability of large-capacity storage EMMC interface logic. Through design, simulation and verification, modular products are formed, which have strong flexibility and can realize the expansion of large-capacity storage data recording function of embedded system data processing module. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0020] Figure 1 Design a block diagram for expanding the EMMC interface based on a parallel bus. DETAILED DESCRIPTION
[0021] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
[0022] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
[0023] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.
[0024] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0025] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.
[0026] In one embodiment of the present invention, a method for extending an EMMC interface based on a parallel bus is proposed:
[0027] A portable parallel bus expansion EMMC interface logic circuit is provided to realize the communication between the parallel bus and the EMMC interface of the EMMC chip;
[0028] The interface logic circuit comprises an EMMC initialization module, an EMMC data cache module and an EMMC control module.
[0029] The interface logic circuit and the EMMC chip communicate with the EMMC interface based on CMD, DATA and CLK signals.
[0030] The interface logic circuit is connected to the local parallel bus of the CPU, and the interface logic circuit realizes the control of the EMMC interface and the data transmission and reception based on the instructions of the CPU.
[0031] The EMMC initialization module is used to implement the initialization of the EMMC interface, including: chip ID acquisition, address space allocation, clock configuration, CSD register acquisition, and working mode configuration.
[0032] The EMMC data cache module is used for caching the data received and sent by the EMMC interface, including: FIFO working mode configuration and receiving and sending data bit width configuration.
[0033] In this embodiment, the EMMC control module is used to implement read and write control, erase control and bus test of the EMMC interface.
[0034] In this embodiment, the EMMC initialization module is also used for configuring the data bit width.
[0035] In this embodiment, the method for extending the EMMC interface based on a parallel bus verifies the interface logic circuit in the following manner:
[0036] Verilog language is used to simulate the test code, simulate the CPU local parallel bus and EMMC interface excitation signal, and test the function of the interface logic circuit.
[0037] This embodiment realizes the conversion from a parallel bus to an EMMC protocol, forms a modular standard EMMC interface, and improves the versatility and portability of the large-capacity storage EMMC interface logic.
[0038] This embodiment is implemented using standard Verilog language and a modular design method, thereby improving the flexibility and scalability of the interface circuit.
[0039] The interface design framework of this embodiment includes an EMMC initialization module, an EMMC data cache module and an EMMC control module.
[0040] The EMMC initialization module completes the EMMC logic controller configuration parameters through the parallel bus, including: chip ID acquisition, address space allocation, clock configuration, csd register acquisition, working mode configuration and data bit width.
[0041] The EMMC data cache module implements data caching through parallel bus extended FIFO, including FIFO depth and data bit width configuration.
[0042] The EMMC control module realizes EMMC read and write control, EMMC erase control and EMMC bus communication test functions through a parallel bus.
[0043] The EMMC initialization module, EMMC data cache module and EMMC control module mentioned above are all implemented through Verilog code.
[0044] The functional block diagram of EMMC interface expansion based on parallel bus is as follows Figure 1 As shown, a design framework based on parallel bus expansion EMMC interface includes an EMMC initialization module, an EMMC data cache module and an EMMC control module.
[0045] 1.EMMC initialization module
[0046] The EMMC initialization module realizes the initialization of the EMMC controller through the parallel bus, including: chip ID acquisition, address space allocation, clock configuration, CSD register acquisition, configuration of working mode and data bit width. The module is implemented through Verilog code.
[0047] 2.EMMC data cache module
[0048] The EMMC data cache module implements data transmission and reception cache through parallel bus extended FIFO, including FIFO transmission and reception data depth and data bit width configuration. The module is implemented through Verilog code.
[0049] 3.EMMC control module
[0050] The EMMC control module realizes EMMC read and write control, chip erase control and EMMC bus test functions through a parallel bus. This module is implemented through Verilog code.
[0051] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A method for extending an EMMC interface based on a parallel bus, characterized in that: A portable parallel bus expansion EMMC interface logic circuit is provided to realize the communication between the parallel bus and the EMMC interface of the EMMC chip; The interface logic circuit includes an EMMC initialization module, an EMMC data cache module and an EMMC control module; The interface logic circuit and the EMMC chip communicate with the EMMC interface based on CMD, DATA and CLK signals.
2. The method for extending the EMMC interface based on a parallel bus according to claim 1, characterized in that: The interface logic circuit is connected to the local parallel bus of the CPU, and the interface logic circuit realizes the control of the EMMC interface and the data transmission and reception based on the instructions of the CPU.
3. The method for extending the EMMC interface based on a parallel bus according to claim 2, characterized in that: The EMMC initialization module is used to implement the initialization of the EMMC interface, including: chip ID acquisition, address space allocation, clock configuration, CSD register acquisition, and working mode configuration.
4. The method for extending the EMMC interface based on a parallel bus according to claim 3, characterized in that: The EMMC data cache module is used for caching the data received and sent by the EMMC interface, including: FIFO working mode configuration and receiving and sending data bit width configuration.
5. The method for extending the EMMC interface based on a parallel bus according to claim 4, characterized in that: The EMMC control module is used to implement read and write control, erase control and bus test of the EMMC interface.
6. The method for extending the EMMC interface based on a parallel bus according to claim 5, characterized in that: The EMMC initialization module is also used to configure the data bit width.
7. The method for extending the EMMC interface based on a parallel bus according to claim 6, characterized in that: The method for extending the EMMC interface based on a parallel bus verifies the interface logic circuit in the following manner: Verilog language is used to simulate the test code, simulate the CPU local parallel bus and EMMC interface excitation signal, and test the function of the interface logic circuit.