Circuit and chip for enabling CXL protocol to support low-rate serial link

Abstract

The invention discloses a circuit and a chip for enabling a CXL protocol to support a low-rate serial link. The circuit provided by the invention comprises a link management state machine containing a sending SDS state, a 4-byte clock skew compensation character SKP4B generation circuit and an analysis circuit, an encoder and a decoder supporting a data stream start character SDS, a 128b / 130b encoder and a decoder, a data stream start detection circuit, a 40: 1 parallel-serial conversion circuit, a 32: 1 parallel-serial conversion circuit, a multiplexer, a 1: 40 serial-parallel conversion circuit and a 1: 1 parallel-serial conversion circuit, the output end of the multiplexer is connected with the input end of the demultiplexer through a serial link, and the output end of the demultiplexer is connected with the input end of the demultiplexer through a serial link. The invention aims to enable the CXL protocol to extend and support PCIe Gen1 and Gen2 rates, so that the FPGA chip can use the CXL protocol, and the ASIC chip can use the CXL protocol at a low rate.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed interconnection interfaces between chiplets, and in particular to a circuit and a chip for enabling a CXL protocol to support a low-rate serial link. Background Art

[0002] The CXL protocol standard is a protocol standard proposed by Intel for the next generation of chip-to-chip interconnection, supporting two types of transactions: CXL.io and CXL.mc. Its main feature is that it is based on the traditional PCIe Gen3 and higher-speed (Gen4 and Gen5, etc.) PCIe Serdes. On the basis of supporting the traditional inter-chip master-to-slave IO access (implemented through CXL.io transactions), it extends support for master-to-slave storage and cache consistency access (implemented through CXL.mc transactions). The goal of the CXL protocol is not only to meet the access from the CPU to external IO peripherals, but also to meet the efficient interconnection in various rich scenarios such as CPU to CPU, CPU to GPU, and CPU to memory. Intel intends to unify various communication requirements within and between cabinets in application scenarios such as data centers through the CXL protocol standard, establish standards and build an ecosystem. Since the CXL protocol standard is compatible with PCIeGen3 and higher-speed physical links, it has been supported by a large number of chip and system manufacturers and has broad application prospects.

[0003] The CXL protocol specifies that the physical link does not support low-rate (PCIe Gen1 and Gen2) serial links, which limits some application scenarios of the CXL protocol. One scenario is to use the CXL protocol in FPGA chips. As a prototype verification chip or a dedicated acceleration chip for high-performance chips, FPGAs need to integrate interconnect interfaces that support the CXL protocol. When the FPGA chip supports the CXL protocol, the physical link can use the standard PCIe PHY, but the digital circuits such as the MAC layer, data link layer, and protocol layer specified in the CXL protocol specification need to be implemented through the lookup table (LUT) in the FPGA. Due to the large scale of this part of the digital circuit, it is very difficult to achieve a higher main frequency. Usually, this part of the digital circuit can only achieve a frequency of more than 100 megahertz, which does not reach 200MHz. Taking the PCIe PHY supporting 16 lanes as an example, if the transmission rate of 8Gbps per lane specified by PCIe Gen3 is to be achieved, when the PIPE interface between the MAC layer and PHY in the CXL controller has a data width of 512 bits, the operating frequency of the MAC layer and the digital circuits above it needs to reach 16*8G / 512=250MHz to achieve bandwidth balance, and the operating frequency of 250MHz is difficult to achieve in FPGA. Therefore, in FPGA, when the PIPE interface between the MAC layer and PHY has a data width of 512 bits, the PCIe PHY must operate at the Gen1 or Gen2 rate. Taking the Gen2 rate as an example, at this time, the operating frequency of the MAC layer and the layers above the CXL controller only needs to reach 16*5G / 512=156.25Mhz; at the Gen1 rate, the operating frequency only needs to reach 16*2.5G / 512=78.125MHz. The above frequencies are feasible for the implementation of the CXL controller in FPGA. Another scenario is when the ASIC chip cannot reach Gen3 or higher speeds due to serial link reliability and other issues, and it is decelerated to work at Gen1 or Gen2 speeds. According to Intel's current CXL protocol specification, once the physical link works at a speed lower than Gen3, CXL.mc transactions are not supported, and the functions of accessing memory and other chips' caches through the CXL protocol interface will be invalid. In order to enable the ASIC chip to still use the full functionality of the CXL protocol when the physical link rate is Gen1 or Gen2, the CXL protocol specification must be optimized to support PCIe Gen1 and Gen2 rates.

[0004] In summary, due to the lack of support for low-rate serial links in the current CXL protocol specification, the application scenarios of FPGA chips and ASIC chips are restricted. Therefore, making the CXL protocol physical link support low-rate serial links has become a key technical issue that needs to be solved urgently. Summary of the invention

[0005] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a circuit and chip are provided to enable the CXL protocol to support low-speed serial links. The present invention aims to extend the CXL protocol specification to support PCIe Gen1 and Gen2 rates, so that FPGA chips can use the CXL protocol and ASIC chips can still work normally with the CXL protocol interface when the physical link speed is reduced to Gen1 and Gen2.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A circuit that enables a CXL protocol to support a low-rate serial link, comprising a transmitting end and a receiving end, wherein the transmitting end comprises a link management state machine including a "sending SDS" state, a 4-byte clock deviation compensation symbol SKP_4B generating circuit, an encoder supporting a data stream start symbol SDS, a 128b / 130b encoder, a 40:1 parallel-to-serial conversion circuit, a 32:1 parallel-to-serial conversion circuit and a multiplexer, wherein the encoder supporting the data stream start symbol SDS is used to perform 8b / 10b encoding on data of a PCIe physical link at Gen1 and Gen2 rates, and insert the 4-byte clock deviation compensation symbol SKP_4B generated by the 4-byte clock deviation compensation symbol SKP_4B generating circuit into a message, and the receiving end comprises a data stream start detection circuit, a 4-byte clock deviation compensation symbol SKP_4B parsing circuit, a decoder supporting the data stream start symbol SDS, a 128b / 130b decoder, a 1:40 serial-to-parallel conversion circuit, and a multiplexer. The invention relates to a converter circuit, a 1:32 serial-to-parallel conversion circuit and a demultiplexer, wherein the decoder supporting the data stream start character SDS is used to perform 10b / 8b decoding on the data of the PCIe physical link at the Gen1 and Gen2 rates, and after decoding, the decoder is sent to the 4-byte clock deviation compensation character SKP_4B parsing circuit to parse out the 4-byte clock deviation compensation character SKP_4B in the message, the input end of the multiplexer is respectively connected to the output end of the encoder supporting the data stream start character SDS through a 40:1 parallel-to-serial conversion circuit, and is connected to the output end of the 128b / 130b encoder through a 32:1 parallel-to-serial conversion circuit, the output end of the multiplexer is connected to the input end of the demultiplexer through a serial communication link, and the output end of the demultiplexer is respectively connected to the input end of the 128b / 130b decoder through a 1:32 serial-to-parallel conversion circuit, and is connected to the input end of the decoder supporting the data stream start character SDS through a 1:40 serial-to-parallel conversion circuit.

[0007] Optionally, the encoder supporting the data stream start character SDS adopts 8b / 10b encoding rules with an added SDS control character to perform 8b / 10b encoding on data of the PCIe physical link at Gen1 and Gen2 rates, wherein the SDS control character is a code group identifier K28.4 reserved in the 8b / 10b encoding table of the CXL protocol.

[0008] Optionally, the encoder supporting the data stream start symbol SDS includes: The first judgment module is used to judge whether the high 3 bits data_in[7:5] of the input 8-bit to-be-encoded data data_in are 3'd4 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; The first NOT gate is used to generate a bitwise inverted value of the fixed code data_abcdei_sds, wherein the code value of the fixed code data_abcdei_sds is fixed to 6'b001101; The first selector is used to select and output between the fixed code data_abcdei_sds and the bitwise inverted value of the fixed code data_abcdei_sds generated by the first NOT gate according to the 1-bit polarity signal disp_in; wherein the 1-bit polarity signal disp_in is 1, indicating that the current clock cycle is positive polarity RD+, and is 0, indicating that the current clock cycle is negative polarity RD-; A second selector, used for selecting and generating a 6-bit code value data_abcdei between the output value of the first selector and the 0 code value according to the selection signal generated by the first judgment module; The second judgment module is used to judge whether the lower 5 bits data_in[4:0] of the input 8-bit to-be-encoded data data_in are 5'd28 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; The second NOT gate is used to generate a bitwise inverted value of the fixed code data_fghj_sds, wherein the code value of the fixed code data_fghj_sds is fixed to 4'b1100; A third selector is used to select and output between the fixed code data_fghj_sds and the bitwise inverted value of the fixed code data_fghj_sds generated by the second NOT gate according to the 1-bit polarity signal disp_in; A fourth selector is used to select between the output value of the third selector and the 0 encoding value to generate a 4-bit encoding value data_fghj according to the selection signal generated by the second judgment module, and together with the 6-bit encoding value data_abcdei, form an encoding result data_out={data_fghj, data_abcdei} output; The third judgment module is used to judge whether the encoding result data_out is equal to 10'h0, and use the judgment result as the generated error signal sds_err. If the error signal sds_err is 1, it means that the SDS control character encoding is incorrect.

[0009] Optionally, the decoder supporting the data stream start character SDS uses a 10b / 8b decoding rule with an SDS control character added to perform 10b / 8b decoding on data of the PCIe physical link at Gen1 and Gen2 rates, wherein the SDS control character is a code group identifier K28.4 reserved in a 10b / 8b decoding table of the CXL protocol.

[0010] Optionally, the decoder supporting the data stream start symbol SDS includes: A fourth judgment module is used to judge whether the upper 4 bits data_in[9:6] of the input 10-bit to-be-decoded data data_in are 4'b1100 or 4'b0011, and use the judgment result as the generated selection signal; a fifth selector, configured to select the fixed code data_EDCBA_sds or 5'd0 as the 5-bit decoded value data_EDCBA according to the selection signal generated by the fourth determination module; A fifth judgment module, used for judging whether the first, third and fourth bits of the 10-bit input data to be decoded data_in are all 1 at the same time, and outputting the judgment result as a signal; A sixth judgment module, used to judge whether any one of the 1st, 3rd and 4th bits of the 10-bit input data to be decoded data_in is 1, and output the judgment result as a signal; An OR gate, used for performing an OR operation on the signals output by the fifth judgment module and the sixth judgment module; a sixth selector, for selecting the fixed code data_HGF_sds or 3'd0 as the 3-bit decoding value data_HGF according to the OR operation result of the OR gate, and the 3-bit decoding value data_HGF and the 5-bit decoding value data_EDCBA together constitute the decoding result data_out={data_HGF, data_EDCBA}, wherein the code value of the fixed code data_HGF_sds is fixed to 3'd4; A first AND gate, used for performing an AND operation on the selection signal generated by the fourth judgment module and the OR operation result of the OR gate to output a 1-bit K code k_out to indicate whether the decoding result data_out is an SDS control character; The seventh judgment module is used to judge whether the decoding result data_out is equal to 8'h0, and use the judgment result as the generated error signal sds_err. If the error signal sds_err is 1, it means that the SDS control character decoding is wrong.

[0011] Optionally, the encoder supporting the data stream start symbol SDS adopts a link management state machine with an added "send SDS" state to perform link management, and the link management state machine with an added "send SDS" state includes the following states: "Reset / Idle" state, which is the initial state of the link and is entered after power-on; "Link Training" state, which is the state in which the link is initialized and trained; "L0 / Active" state, which is a normal working state, in which the link sends and receives messages normally, and enters this state after the link training is completed; "L0s" state, which is a first-level low-power state; "Retrain" state, which is the state in which the link is re-initialized and trained, and after the link exits the "L1" state, it needs to go through this state for retraining, and can enter the "L0 / Active" state after the training is completed; "L1" state, which is a second-level low-power state; "L2" state, which is a third-level low-power state. The "Send SDS" state is the state of sending SDS control characters; the "Reset / Idle" state is exited to enter the "Link Training" state; the "Link Training" state is exited to enter the "Send SDS" state; under the control of the "Send SDS" state, the encoding circuit that supports the data stream start character SDS on the sending end starts to send SDS control characters. After the receiving end recognizes the SDS control characters and detects the start of the data stream, the link management state machine jumps from the "Send SDS" state to the "L0 / Active" state; the "L0 / Active" state and the "L0s" state can switch to each other, and the "L0 / Active" state can switch unidirectionally to the "L1" state and the "L2" state; the "Reset / Idle" state is entered when the "L2" state is exited; the "Retrain" state is entered when the "L1" state is exited; the "Send SDS" state is re-entered when the "Retrain" state is exited.

[0012] Optionally, when the PCIe physical link is at Gen1 and Gen2 rates, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, COMMA_1B}, and when the PCIe physical link is at Gen3 and above rates, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, SKP_1B}, wherein SKP_1B is a single-byte clock deviation compensation symbol, and COMMA_1B is a single-byte synchronization symbol; the 4-byte clock deviation compensation symbol SKP_4B parsing circuit for parsing out two types of 4-byte clock deviation compensation symbols SKP_4B in the message includes: An eighth judgment module is used to judge whether the result of an AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A ninth judgment module, used to judge whether the result of an AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A tenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; An eleventh judgment module is used to judge whether the result of an AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A twelfth judgment module is used to judge whether the AND operation result of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the synchronization symbol COMMA_1B; a seventh selector, configured to select the judgment result of the twelfth judgment module when the PCIe physical link is at the rate of Gen1 and Gen2, and to select the judgment result of the eleventh judgment module otherwise; The second AND gate is used to perform a logic AND operation on the output results of the eighth judgment module, the ninth judgment module, the tenth judgment module, and the eleventh multiplexer to obtain a 4-byte clock deviation compensation symbol parsing result SKP_OUT; The first counter is used to output 1 every time a SKP_4B sequence {SKP_1B, SKP_1B, SKP_1B, SKP_1B} is received at the rate of Gen3 and above; The second counter is used to output 3 for each SKP sequence {SKP_1B, SKP_1B, SKP_1B, COMMA_1B} received at the Gen1 and Gen2 rates; an eighth selector, for selecting to output the output result of the second counter at the Gen1 and Gen2 rates, and otherwise selecting to output the output result of the first counter; The SKP counter is used to accumulate the output result of the eighth selector to obtain the clock deviation compensation symbol count value SKP_COUNT.

[0013] Optionally, the data stream start detection circuit is used to generate a data stream start mark for Gen1 and Gen2 rates, and Gen3 and above rates at the same time, and uses the Gen1 / Gen2 signal representing the Gen1 and Gen2 rates as a decoding enable signal to enable a decoder supporting the data stream start symbol SDS and a 128b / 130b decoder. The data stream start detection circuit includes a Gen3 and above rate SDS detection circuit, a Gen1 / Gen2 rate SDS detection circuit and a ninth selector. The Gen3 and above rate SDS detection circuit is used The decoding result of the 128b / 130b decoder is subjected to data stream start mark detection to obtain the output result SDS_OUT_GEN3. The Gen1 / Gen2 rate SDS detection circuit is used to perform data stream start mark detection on the decoding result of the decoder supporting the data stream start symbol SDS to obtain the output result SDS_OUT_GEN1. The ninth selector is used to select one from the output result SDS_OUT_GEN3 and the output result SDS_OUT_GEN1 as the final data stream start mark based on the control of the Gen1 / Gen2 signal.

[0014] Optionally, the Gen1 / Gen2 rate SDS detection circuit includes: The thirteenth judgment module is used to judge whether the result of the AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the SDS control character SDS_1B; A fourteenth judgment module is used to judge whether the result of the AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the SDS control character SDS_1B; The fifteenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the SDS control character SDS_1B; A sixteenth judgment module is used to judge whether the result of the AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the SDS control character SDS_1B; The third AND gate is used for performing a logic AND operation on the output results of the thirteenth judgment module, the fourteenth judgment module, the fifteenth judgment module and the sixteenth judgment module to obtain a result SDS_OUT_GEN1 of whether the received data is an SDS control character.

[0015] In addition, the present invention also provides a chip, comprising a plurality of core particles interconnected by a high-speed interconnect interface, wherein the high-speed interconnect interface comprises the circuit for enabling the CXL protocol to support a low-rate serial link.

[0016] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: 1. The present invention solves the problem that the CXL protocol specification does not support PCIe Gen1 and Gen2 rates. Currently, whether it is the CXL protocol specification or the commercial CXL protocol controller, when the physical link works at Gen1 and Gen2 rates, it cannot support the CXL protocol interface circuit to access the memory and cache in other chips. The present invention can achieve that when the physical link works at PCIeGen1 and Gen2 rates, the CXL controller can still support normal access to CXL.mc transactions, ensuring the functional integrity and correctness of the CXL protocol.

[0017] 2. The present invention realizes the independence of CXL controller and physical layer serial link rate by supporting PCIe Gen1 and Gen2 rates, further realizes the "decoupling" of CXL controller and physical layer link, supports the adaptation of CXL controller to richer physical link types, greatly improves the practicality of CXL protocol in chip and core particle interconnection, and is of great significance for expanding the CXL ecosystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the circuit structure in an embodiment of the present invention.

[0019] Figure 2 4 is a circuit diagram of an 8b / 10b encoder for SDS control characters in an embodiment of the present invention.

[0020] Figure 3 4 is a circuit diagram of an 8b / 10b decoder for SDS control characters in an embodiment of the present invention.

[0021] Figure 4 Schematic diagram of the improvement of the link management state machine in the embodiment of the present invention, wherein (a) is the original link management state machine, and (b) is the link management state machine after adding the "SDS state" in the embodiment of the present invention.

[0022] Figure 5 4 is a circuit schematic diagram of a 4-byte clock deviation compensation symbol SKP_4B parsing circuit in an embodiment of the present invention.

[0023] Figure 6 4 is a circuit schematic diagram of a data stream start detection circuit in an embodiment of the present invention.

[0024] Figure 7 4 is a circuit schematic diagram of a Gen1 / Gen2 SDS detection circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0026] like Figure 1 As shown, in this embodiment, the circuit that enables the CXL protocol to support a low-rate serial link includes a transmitting end and a receiving end. The transmitting end includes a link management state machine including a "sending SDS" state, a 4-byte clock deviation compensation symbol SKP_4B generating circuit, an encoder supporting a data stream start symbol SDS, a 128b / 130b encoder, a 40:1 parallel-to-serial conversion circuit, a 32:1 parallel-to-serial conversion circuit and a multiplexer. The encoder supporting the data stream start symbol SDS is used to perform 8b / 10b encoding on the data of the PCIe physical link at the Gen1 and Gen2 rates, and insert the 4-byte clock deviation compensation symbol SKP_4B generated by the 4-byte clock deviation compensation symbol SKP_4B generating circuit into the message. The receiving end includes a data stream start detection circuit, a 4-byte clock deviation compensation symbol SKP_4B parsing circuit, a decoder supporting the data stream start symbol SDS, a 128b / 130b decoder, a 1:40 serial-to-parallel converter, and a 32:1 serial-to-serial converter. A conversion circuit, a 1:32 serial-to-parallel conversion circuit and a demultiplexer, wherein the decoder supporting the data stream start character SDS is used to perform 10b / 8b decoding on the data of the PCIe physical link at the Gen1 and Gen2 rates, and after decoding, the decoder is sent to a 4-byte clock deviation compensation character SKP_4B analysis circuit to parse out the 4-byte clock deviation compensation character SKP_4B in the message, the input end of the multiplexer is respectively connected to the output end of the encoder supporting the data stream start character SDS through a 40:1 parallel-to-serial conversion circuit, and is connected to the output end of the 128b / 130b encoder through a 32:1 parallel-to-serial conversion circuit, the output end of the multiplexer is connected to the input end of the demultiplexer through a serial communication link, and the output end of the demultiplexer is respectively connected to the input end of the 128b / 130b decoder through a 1:32 serial-to-parallel conversion circuit, and is connected to the input end of the decoder supporting the data stream start character SDS through a 1:40 serial-to-parallel conversion circuit. The 128b / 130b encoder, the 128b / 130b decoder, and the 4-byte clock skew compensator SKP_4B generating circuit are existing well-known circuits.

[0027] See also Figure 1When the link is at the Gen1 / Gen2 rate, if the link management state machine is in the "send SDS" state, the sender's encoder that supports the data start character SDS sends the SDS control character, and through 8b / 10b encoding, 8 bits are encoded into 10 bits, and 512 bits of data (the interface width is 512 bits) are encoded into 640 bits of data and output to the electrical physical layer; after the receiver receives the 640 bits of data from the electrical physical layer, the decoder that supports the data start character SDS decodes the data into 512 bits and parses out the SDS control character. The data stream start detection circuit determines the start of the data stream based on the SDS control character and outputs the information. When the link is at Gen3 and above, if the link management state machine is in the "send SDS" state, the sender's 128b130b encoder sends the SDS control character and outputs 512 bits of data to the electrical physical layer; after the receiver receives the 512 bits of data from the electrical physical layer, the 128b / 130b decoder parses the SDS control character, and the data stream start detection circuit determines the start of the data stream based on the SDS control character and outputs the information.

[0028] Based on the need to increase bandwidth, PCIe Gen3 and above versions replace 8b / 10b encoding with 128b / 130b encoding. The CXL protocol requires the Start of Data Stream (SDS) in the 128b / 130b encoding to identify the start of the data stream, so that the position of the first Protocol ID (PID) can be correctly parsed. Since the physical link of PCIe does not support 128 / 130b encoding at Gen1 and Gen2 rates, but only supports 8b / 10b encoding, and there is no SDS required by the CXL protocol in the 8b / 10b encoding, the CXL protocol cannot determine the start of the data stream at the Gen1 and Gen2 rates, and thus cannot parse the PID, which in turn causes the CXL.mc protocol to not work properly. In response to the above problems, this embodiment expands the 8b / 10b encoding rules in the CXL protocol and adds SDS control characters. Table 1 shows the 8b / 10b encoding table of the CXL protocol, in which the control character part retains two groups of codes K28.4 and K28.6, which do not represent any control characters; based on the 8b / 10b encoding rules of the CXL protocol, this embodiment defines the original reserved code K28.4 as an SDS control character, and the encoding and meaning of other control characters remain unchanged; Tables 2 and 3 are SDS control character 8b / 10b encoding and 10b / 8b decoding comparison tables respectively.

[0029] Table 1: Extended SDS control characters in the 8b / 10b encoding table of the CXL protocol

[0030] Table 2: SDS control character 8b / 10b encoding comparison table

[0031] Table 3: SDS control character 10b / 8b decoding comparison table

[0032] Among them, 8'h9C is an 8-digit hexadecimal number, and its hexadecimal value is 9C.

[0033] Therefore, the encoder supporting the data stream start character SDS in this embodiment adopts the 8b / 10b encoding rule with the SDS control character added to perform 8b / 10b encoding on the data of the PCIe physical link at the Gen1 and Gen2 rates, and the SDS control character is the code group identifier K28.4 reserved in the 8b / 10b encoding table of the CXL protocol. The decoder supporting the data stream start character SDS in this embodiment adopts the 10b / 8b decoding rule with the SDS control character added to perform 10b / 8b decoding on the data of the PCIe physical link at the Gen1 and Gen2 rates, and the SDS control character is the code group identifier K28.4 reserved in the 10b / 8b decoding table of the CXL protocol.

[0034] The 8b / 10b encoding circuit and decoding circuit corresponding to the 8b / 10b encoding table are known circuits, so their detailed implementation will not be described in detail here. Figure 2 As shown, in order to perform 8b / 10b encoding on the SDS control character, the encoder supporting the data stream start character SDS in this embodiment includes: The first judgment module is used to judge whether the high 3 bits data_in[7:5] of the input 8-bit to-be-encoded data data_in are 3'd4 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; wherein 3'd4 represents a 3-bit binary, and its value is 4 (the binary value is 100); The first NOT gate is used to generate a bitwise inversion value of the fixed code data_abcdei_sds, wherein the code value of the fixed code data_abcdei_sds is fixed to 6'b001101; wherein 6'b001101 represents a 6-bit binary, and its binary value is 001101; The first selector is used to select and output between the fixed code data_abcdei_sds and the bitwise inverted value of the fixed code data_abcdei_sds generated by the first NOT gate according to the 1-bit polarity signal disp_in; wherein the 1-bit polarity signal disp_in is 1, indicating that the current clock cycle is positive polarity RD+, and is 0, indicating that the current clock cycle is negative polarity RD-; A second selector, used for selecting and generating a 6-bit code value data_abcdei between the output value of the first selector and the 0 code value according to the selection signal generated by the first judgment module; The second judgment module is used to judge whether the lower 5 bits data_in[4:0] of the input 8-bit to-be-encoded data data_in are 5'd28 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; The second NOT gate is used to generate a bitwise inverted value of the fixed code data_fghj_sds, wherein the code value of the fixed code data_fghj_sds is fixed to 4'b1100; A third selector is used to select and output between the fixed code data_fghj_sds and the bitwise inverted value of the fixed code data_fghj_sds generated by the second NOT gate according to the 1-bit polarity signal disp_in; A fourth selector is used to select between the output value of the third selector and the 0 encoding value to generate a 4-bit encoding value data_fghj according to the selection signal generated by the second judgment module, and together with the 6-bit encoding value data_abcdei, form an encoding result data_out={data_fghj, data_abcdei} output; The third judgment module is used to judge whether the encoding result data_out is equal to 10'h0, and use the judgment result as the generated error signal sds_err. If the error signal sds_err is 1, it means that the SDS control character encoding is incorrect. Among them, 10'h0 represents 10 hexadecimal codes and the value is 0; See also Figure 2 , the input signal of the encoder supporting the data stream start symbol SDS in this embodiment is: 1) 8 bits of data to be encoded (data_in); 2) 1-bit K code (k_in), k_in is 1, indicating that data_in of this clock cycle is a control character, and k_in is 0, indicating that data_in of this clock cycle is data; 3) 1-bit polarity signal (disp_in). If disp_in is 1, it indicates that the current clock cycle is positive polarity (RD+). If it is 0, it indicates that the current clock cycle is negative polarity (RD-).

[0035] See also Figure 2 , the output signal of the encoder supporting the data stream start symbol SDS in this embodiment is: 1) 10 bits of encoded data (data_out); 2) 1-bit error signal (sds_err). sds_err is 1, indicating that the SDS control character encoding is incorrect, and 0, indicating that the SDS control character encoding is correct.

[0036] See also Figure 2 In this embodiment, the intermediate signals other than the input signal and output signal of the encoder supporting the start of data stream (SDS) include: 1) data_abcdei_sds, fixed value 6'b001101; 2) data_fghj_sds, fixed value 4'b1100; 3) data_abcdei, which is a 6-bit coded value; 4) data_fghj, which is a 4-bit coded value.

[0037] According to the coding rules of the SDS control characters in Table 2, the encoder proposed in this embodiment divides data_in into the upper 3 bits (data_in[7:5]) and the lower 5 bits (data_in[4:0]) for coding. For the SDS control characters, the coding under the positive and negative polarities is a negation relationship, so two NOT gates are used in the circuit to generate the bitwise inverted values ​​of data_abcdei_sds and data_fghj_sds, and the disp_in signal is used to select whether to output the original value or the bitwise inverted value. If data_in[7:5] is 3'd4 and the k_in corresponding to data_in is 1, it means that the code group identifier of data_in[7:5] is Kxx.4 (where xx represents an unknown value); at the same time, if disp_in=1 (positive polarity), select data_abcdei_sds (6'b001101), otherwise select the bitwise inversion value of data_abcdei_sds 6'b0110010 and assign it to data_abcdei. The encoding logic of data_in[4:0] is similar. If data_in[4:0] is 5'd28 and the k_in corresponding to data_in is 1, it means that the code group identifier of data_in[4:0] is K28.x (where x represents an unknown value); combined with the above data_in[7:5] code group identifier Kxx.4, it can be obtained that the code group identifier of data_in is K28.4, that is, the SDS control character. At the same time, if disp_in=1, select data_fghj_sds (4'b1100), otherwise select the bitwise inverted value of data_fghj_sds 4'b0011 and assign it to data_fghj. data_fghj and data_abcdei are combined into the output signal data_out, data_out = {data_fghj, data_abcdei}, that is, 10'b001111 0010 or 10'b 110000 1101. If data_out is 0, the error signal sds_err is 1, indicating that the SDS control character encoding is incorrect.

[0038] like Figure 3 As shown, in order to perform 8b / 10b encoding on the SDS control character, the decoder supporting the data stream start character SDS in this embodiment includes: A fourth judgment module is used to judge whether the upper 4 bits data_in[9:6] of the input 10-bit to-be-decoded data data_in are 4'b1100 or 4'b0011, and use the judgment result as the generated selection signal; a fifth selector, configured to select the fixed code data_EDCBA_sds or 5'd0 as the 5-bit decoded value data_EDCBA according to the selection signal generated by the fourth determination module; A fifth judgment module, used for judging whether the first, third and fourth bits of the 10-bit input data to be decoded data_in are all 1 at the same time, and outputting the judgment result as a signal; A sixth judgment module, used to judge whether any one of the 1st, 3rd and 4th bits of the 10-bit input data to be decoded data_in is 1, and output the judgment result as a signal; An OR gate, used for performing an OR operation on the signals output by the fifth judgment module and the sixth judgment module; a sixth selector, for selecting the fixed code data_HGF_sds or 3'd0 as the 3-bit decoding value data_HGF according to the OR operation result of the OR gate, and the 3-bit decoding value data_HGF and the 5-bit decoding value data_EDCBA together constitute the decoding result data_out={data_HGF, data_EDCBA}, wherein the code value of the fixed code data_HGF_sds is fixed to 3'd4; A first AND gate, used for performing an AND operation on the selection signal generated by the fourth judgment module and the OR operation result of the OR gate to output a 1-bit K code k_out to indicate whether the decoding result data_out is an SDS control character; The seventh judgment module is used to judge whether the decoding result data_out is equal to 8'h0, and use the judgment result as the generated error signal sds_err. If the error signal sds_err is 1, it means that the SDS control character decoding is wrong.

[0039] 10b / 8b decoding is the inverse process of 8b / 10b encoding, see Figure 3 In this embodiment, the input signal of the decoder supporting the start of data stream (SDS) is: 10 bits of data to be decoded (data_in).

[0040] See also Figure 3 , the input signal of the decoder supporting the start of data stream (SDS) in this embodiment is: 1) 8 bits of decoded data (data_out); 2) 1-bit K code (k_out), k_out is 1, indicating that the decoded data data_out of this clock cycle is a control character, and k_out is 0, indicating that data_out is data; 3) 1-bit error signal (sds_err). sds_err is 1, indicating that the SDS control character decoding is wrong. 0 indicates that the SDS control character decoding is correct.

[0041] See also Figure 3 In this embodiment, the intermediate signals other than the decoder input signal and output signal of the data stream start symbol (SDS) supported by the present embodiment include: 1) data_EDCBA _sds, fixed value 5'd28; 2) data_HGF_sds, fixed value 3'd4; 3) data_EDCBA, which is a 5-bit decoded value; 4) data_HGF, which is a 3-bit decoded value.

[0042] According to the decoding rules of the SDS control characters in Table 3, data_in is divided into the upper 4 bits (data_in[9:6]) and the lower 6 bits (data_in[5:0]) for decoding. The lower 6 bits can be decoded into data_HGF according to the rules of bits 0 / 2 / 3. If data_in[9:6] is 4'b1100 or 4'b0011, it means that the decoded code group identifier is K28.x (where x represents an unknown value), so the selector selects data_EDCBA _sds (5'd28), otherwise it selects 5'd0; the selected value is assigned to data_EDCBA. The decoding logic of data_in[5:0] is similar. If data_in[3]&data_in[2]&data_in[0] = 1 or data_in[3]| data_in[2] | data_in[0]= 0, it means that the decoded code group identifier is Kxx.4 (where xx represents an unknown value). Combined with the above data_in[9:6] decoded code group identifier K28.x, it can be obtained that the code group identifier of data_out is K28.4, which is the SDS control character. Therefore, the selector selects data_HGF_sds (3'd4), otherwise it selects 3'd0; the selected value is assigned to data_HGF. data_HGF and data_EDCBA are combined into the output signal data_out, data_out = {data_HGF, data_EDCBA}, that is, 8'h9C. If the decoding result of data_in[9:6] is K28.x and the decoding result of data_in[5:0] is Kxx.4, it means that the decoding result is a control character, k_out = 1, otherwise k_out = 0. If data_out is 0, the output signal sds_err is 1, indicating that the SDS control character is decoded incorrectly.

[0043] See also Figure 4 The improved schematic diagram of the link management state machine shown in the figure is Figure 4 (a) in the figure is a traditional link management state machine, which includes the following states: 1) "Reset / Idle" state is the initial state of the link and is entered after power-on; 2) "Link training" state, which is the state of link initialization and training; 3) "L0 / Active" state is a normal working state. The link sends and receives messages normally in this state. After the link training is completed, it enters this state; 4) "L0s" state, which is the first-level low power consumption state; 5) "Retraining" state is the state where the link is re-initialized and trained. After the link exits the "L1" state, it needs to go through this state for retraining. Only after the training is completed can it enter the "L0 / Active" state; 6) "L1" state is the second-level low power consumption state; 7) "L2" state is the third level low power consumption state.

[0044] like Figure 4 As shown in (b) in the figure, the encoder that supports the data stream start symbol SDS in this embodiment adopts a link management state machine with an added "send SDS" state to perform link management. The link management state machine with an added "send SDS" state includes the following states: "Reset / Idle" state, which is the initial state of the link and is entered after power-on; "Link Training" state, which is the state in which the link is initialized and trained; "L0 / Active" state, which is the normal working state, in which the link normally sends and receives messages, and enters this state after the link training is completed; "L0s" state, which is the first-level low-power state; "Retrain" state, which is the state in which the link is re-initialized and trained, and after the link exits the "L1" state, it needs to go through this state for retraining, and can enter the "L0 / Active" state after the training is completed; "L1" state, which is the second-level low-power state; "L2" state, which is Three-level low power consumption state; "Send SDS" state is the state of sending SDS control characters; "Reset / Idle" state exits to enter "Link Training" state; "Link Training" state exits to enter "Send SDS" state; under the control of "Send SDS" state, the encoding circuit that supports the data stream start character SDS at the sending end starts to send SDS control characters, and after the receiving end recognizes the SDS control characters and detects the start of the data stream, the link management state machine jumps from the "Send SDS" state to the "L0 / Active" state; "L0 / Active" state and "L0s" state can switch to each other, and "L0s" state can switch unidirectionally to "L1" state and "L2" state; "L2" state exits to enter "Reset / Idle" state; "L1" state exits to enter "Retrain" state; "Retrain" state exits to re-enter "Send SDS" state.

[0045] See also Figure 4In (b), in this embodiment, on the basis of the traditional link management state machine, a "Send SDS" state is added, and the state transition direction and conditions of other states are modified. First, when the link exits from the "Link Training" state, it no longer directly enters the "L0 / Active" state, but enters the "Send SDS" state. Under the control of the "Send SDS" state, the encoder that supports the data stream start character SDS on the transmitting end begins to send SDS control characters. After the receiving end recognizes the SDS control characters and detects the start of the data stream, the state machine jumps from the "Send SDS" state to the "L0 / Active" state. Secondly, when the traditional link management state machine exits from the "L1" state, it first enters the "Retraining" state; after the retraining is completed, it directly enters the "L0 / Active" state. The state machine proposed in this embodiment needs to first enter the "Send SDS" state after the retraining is completed ( Figure 4 The bold state transition arrow in the right figure) can only jump from the "Send SDS" state to the "L0 / Active" state after repeating and completing the above process of sending SDS control characters. Because the "L1" state is a low-power state, no messages are sent or received on the link in this state, so after exiting from the "L1" state, it is necessary to relocate the start of the data stream (i.e., the message). However, the "Retraining" state only trains the number of lanes, rate and other parameters of the link, and does not locate the start of the data stream. Therefore, before entering the "L0 / Active" state, it is necessary to pass through the "Send SDS" state. Finally, in the process of the state machine proposed in this embodiment exiting from the "L2" state and entering the "L0 / Active" state again, in addition to passing through the "Reset / Idle" state and the "Link Training" state, it is also necessary to pass through the "Send SDS" state. After repeating and completing the above process of sending SDS control characters, it jumps from the "Send SDS" state to the "L0 / Active" state.

[0046] Since the CXL protocol stipulates that the micropacket from the data link layer is 512 bits wide, and each link in the physical layer under x16 uses a 32:1 parallel-to-serial conversion circuit, the control character must use a 4-byte (32-bit) mode, that is, the clock deviation compensation symbol is in a 4-byte format (SKP_4B). According to the PCIe protocol, when the PCIe physical link works in Gen1 and Gen2 modes, the clock deviation compensation symbol is specified as a single-byte format (SKP_1B), and the clock deviation compensation symbol is followed by the synchronization symbol (COMMA), where the synchronization symbol is also in a single-byte format (COMMA_1B). Therefore, in this embodiment, when the PCIe physical link is at the rate of Gen1 and Gen2, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, COMMA_1B}, and when the PCIe physical link is at the rate of Gen3 and above, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, SKP_1B}, where SKP_1B is a single-byte clock deviation compensation symbol, and COMMA_1B is a single-byte synchronization symbol; Figure 5 As shown, the 4-byte clock deviation compensation symbol SKP_4B parsing circuit for parsing out two types of 4-byte clock deviation compensation symbols SKP_4B in the message in this embodiment includes: An eighth judgment module is used to judge whether the result of an AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A ninth judgment module, used to judge whether the result of an AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A tenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; An eleventh judgment module is used to judge whether the result of an AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; The twelfth judgment module is used to judge whether the AND operation result of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the synchronization symbol COMMA_1B; a seventh selector, configured to select the judgment result of the twelfth judgment module when the PCIe physical link is at the rate of Gen1 and Gen2, and otherwise select the judgment result of the eleventh judgment module; The second AND gate is used to perform a logic AND operation on the output results of the eighth judgment module, the ninth judgment module, the tenth judgment module, and the eleventh multiplexer to obtain a 4-byte clock deviation compensation symbol parsing result SKP_OUT; The first counter is used to output 1 every time a SKP_4B sequence {SKP_1B, SKP_1B, SKP_1B, SKP_1B} is received at the rate of Gen3 and above; The second counter is used to output 3 for each SKP sequence {SKP_1B, SKP_1B, SKP_1B, COMMA_1B} received at the Gen1 and Gen2 rates; an eighth selector, for selecting to output the output result of the second counter at the rate of Gen1 or Gen2, and otherwise selecting to output the output result of the first counter; The SKP counter is used to accumulate the output result of the eighth selector to obtain the clock deviation compensation symbol count value SKP_COUNT.

[0047] See also Figure 5In this embodiment, the logic of the 4-byte clock deviation compensation symbol SKP_4B parsing circuit to determine whether it is SKP_1B is: (rx_datak[i]&(rx_data[(i+1)*8-1:i*8] == SKP_1B)), where i is 0~3. The logic of determining whether it is COMMA_1B is: (rx_datak[0]&(rx_data[7:0] == COMMA_1B)). When the physical link works in the Gen1 / Gen2 rate mode, the multiplexer selects the result of "determining whether it is COMMA_1B"; when the physical link works in the Gen3 and above rate modes, the multiplexer selects the result of "determining whether it is SKP_1B". Finally, the judgment results of each byte of the received data are obtained through logical AND (&) to obtain the 4-byte clock deviation compensation symbol parsing result SKP_OUT. When calculating the accumulated SKP, in Gen3 and above rate modes, each time a SKP_4B sequence {SKP_1B, SKP_1B, SKP_1B, SKP_1B} is received, the accumulated SKP counter increases by 1; in Gen1 / 2 mode, each time a SKP sequence {SKP_1B, SKP_1B, SKP_1B, COMMA_1B} is received, the accumulated SKP counter increases by 3, indicating that 3 SKP_1Bs have been received. The multiplexer is used to select whether the SKP counter value increases by 1 or 3.

[0048] like Figure 1 and Figure 6As shown, in this embodiment, the data stream start detection circuit generates data stream start marks for Gen1 and Gen2 rates and Gen3 and above rates at the same time, and uses the Gen1 / Gen2 signal representing the Gen1 and Gen2 rates as a decoding enable signal to enable the decoder supporting the data stream start symbol SDS and the 128b / 130b decoder. The data stream start detection circuit includes a Gen3 and above rate SDS detection circuit, a Gen1 / Gen2 rate SDS detection circuit and a ninth selector. The Gen3 and above rate SDS detection circuit is used to The decoding result of the 128b / 130b decoder is subjected to data stream start mark detection to obtain the output result SDS_OUT_GEN3. The Gen1 / Gen2 rate SDS detection circuit is used to detect the data stream start mark of the decoding result of the decoder supporting the data stream start symbol SDS to obtain the output result SDS_OUT_GEN1. The ninth selector is used to select one path from the output result SDS_OUT_GEN3 and the output result SDS_OUT_GEN1 as the final generated data stream start mark based on the control of the Gen1 / Gen2 signal. The 40-bit or 32-bit data obtained from the data link serial-to-parallel conversion circuit is sent to the 128b / 130b decoder and the 8b / 10b decoder. The Gen1 / Gen2 signal is used to control the decoding enable of the two decoders. When Gen1 / Gen2 is valid, the 8b / 10b decoder is enabled, and when Gen1 / Gen2 is invalid, the 128b / 130b decoder is enabled. When Gen1 / Gen2 is valid, the output result SDS_OUT_GEN3 of the Gen1 / Gen2 SDS detection logic is selected to generate a data stream start mark; when Gen1 / Gen2 is invalid, the output result SDS_OUT_GEN1 of the Gen3 rate SDS detection logic is selected to generate a data stream start mark. Among them, the 128b130b decoder and the Gen3 and above rate SDS detection circuit are existing well-known circuits, so their detailed implementation is not described in detail here.

[0049] like Figure 7 As shown, in this embodiment, the Gen1 / Gen2 rate SDS detection circuit includes: The thirteenth judgment module is used to judge whether the result of the AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the SDS control character SDS_1B; A fourteenth judgment module is used to judge whether the result of the AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the SDS control character SDS_1B; The fifteenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the SDS control character SDS_1B; A sixteenth judgment module is used to judge whether the result of the AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the SDS control character SDS_1B; The third AND gate is used to perform a logical AND operation on the output results of the thirteenth judgment module, the fourteenth judgment module, the fifteenth judgment module, and the sixteenth judgment module to obtain the result SDS_OUT_GEN1 of whether the received data is an SDS control character. The logic of the Gen1 / Gen2 rate SDS detection circuit to determine whether it is SDS_1B is: (rx_datak[i]&(rx_data[(i+1)*8-1:i*8] == SDS_1B)), where i is 0~3. The judgment result of each byte of the received data is obtained through the logical AND (&) logic to obtain the result SDS_OUT_GEN1 of whether the received data is an SDS control character. The SDS_OUT_GEN1 valid signal will be used as the start mark of the data stream.

[0050] In summary, a major difference between the Gen1 / Gen2 rate version of the PCIe physical link and the Gen3 and higher rate version is that the physical layer uses 8b / 10b encoding at the Gen1 / Gen2 rate, while the physical layer uses 128b / 130b encoding at the Gen3 and higher rates. The two encodings differ in the types of control characters and even the encoding of the same control characters, and the CXL protocol only supports Gen3 and higher rates, so its data stream start detection, clock deviation compensation and other logic are only based on the 128b / 130b encoding mechanism. When supporting Gen1 / Gen2 rates, due to the use of 8b / 10b encoding, some logic of the CXL protocol cannot work properly, which in turn causes the CXL protocol to be unable to support Gen1 / Gen2 rates. If you want the CXL protocol to support Gen1 / Gen2 rates, you need to unify the data stream start symbol (SDS) generation and parsing logic and the 4-byte clock deviation compensation symbol SKP_4B parsing logic under 8b / 10b encoding and 128b / 130b encoding. Therefore, the circuit that enables the CXL protocol to support low-rate serial links in this embodiment mainly includes four parts: the first part is an encoder and decoder that supports the data stream start symbol (SDS); the second part is a link management state machine circuit containing the "send SDS" state at the protocol sending end; the third part is a 4-byte clock deviation compensation symbol SKP_4B parsing circuit at the protocol receiving end; and the fourth part is a data stream start detection circuit at the protocol receiving end. The circuit that enables the CXL protocol to support low-rate serial links in this embodiment enables the CXL protocol specification to be extended to support PCIe Gen1 and Gen2 rates, so that FPGA chips can use the CXL protocol and ASIC chips can still work normally when the physical link is reduced to Gen1 and Gen2.

[0051] In addition, this embodiment also provides a chip, including a plurality of core particles interconnected by a high-speed interconnect interface, wherein the high-speed interconnect interface includes the circuit for enabling the CXL protocol to support a low-rate serial link.

[0052] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A circuit for enabling the CXL protocol to support a low-rate serial link, characterized in that: The invention comprises a transmitting end and a receiving end, wherein the transmitting end comprises a link management state machine including a "sending SDS" state, a 4-byte clock deviation compensation symbol SKP_4B generating circuit, an encoder supporting a data stream start symbol SDS, a 128b / 130b encoder, a 40:1 parallel-to-serial conversion circuit, a 32:1 parallel-to-serial conversion circuit and a multiplexer, wherein the encoder supporting the data stream start symbol SDS is used to perform 8b / 10b encoding on data of a PCIe physical link at Gen1 and Gen2 rates, and insert the 4-byte clock deviation compensation symbol SKP_4B generated by the 4-byte clock deviation compensation symbol SKP_4B generating circuit into a message, and the receiving end comprises a data stream start detection circuit, a 4-byte clock deviation compensation symbol SKP_4B parsing circuit, a decoder supporting the data stream start symbol SDS, a 128b / 130b decoder, a 1:40 serial-to-parallel conversion circuit, a 1:32 serial-to-parallel conversion circuit, and a multiplexer. The conversion circuit and demultiplexer are used for performing 10b / 8b decoding on the data of the PCIe physical link at the rates of Gen1 and Gen2, and sending the decoded data to the 4-byte clock deviation compensation symbol SKP_4B analysis circuit to parse out the 4-byte clock deviation compensation symbol SKP_4B in the message. The input end of the multiplexer is respectively connected to the output end of the encoder supporting the data stream start symbol SDS through a 40:1 parallel-serial conversion circuit and to the output end of the 128b / 130b encoder through a 32:1 parallel-serial conversion circuit. The output end of the multiplexer is connected to the input end of the demultiplexer through a serial communication link. The output end of the demultiplexer is respectively connected to the input end of the 128b / 130b decoder through a 1:32 serial-to-parallel conversion circuit and to the input end of the decoder supporting the data stream start symbol SDS through a 1:40 serial-to-parallel conversion circuit.

2. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: The encoder supporting the data stream start character SDS uses the 8b / 10b encoding rule with an added SDS control character to perform 8b / 10b encoding on the data of the PCIe physical link at the Gen1 and Gen2 rates. The SDS control character is a code group identifier K28.4 reserved in the 8b / 10b encoding table of the CXL protocol.

3. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 2, characterized in that: The encoder supporting the data stream start symbol SDS comprises: The first judgment module is used to judge whether the high 3 bits data_in[7:5] of the input 8-bit to-be-encoded data data_in are 3'd4 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; The first NOT gate is used to generate a bitwise inverted value of the fixed code data_abcdei_sds, wherein the code value of the fixed code data_abcdei_sds is fixed to 6'b001101; The first selector is used to select and output between the fixed code data_abcdei_sds and the bitwise inverted value of the fixed code data_abcdei_sds generated by the first NOT gate according to the 1-bit polarity signal disp_in; wherein the 1-bit polarity signal disp_in is 1, indicating that the current clock cycle is positive polarity RD+, and is 0, indicating that the current clock cycle is negative polarity RD-; A second selector, used for selecting and generating a 6-bit code value data_abcdei between the output value of the first selector and the 0 code value according to the selection signal generated by the first judgment module; The second judgment module is used to judge whether the lower 5 bits data_in[4:0] of the input 8-bit to-be-encoded data data_in are 5'd28 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; The second NOT gate is used to generate a bitwise inverted value of the fixed code data_fghj_sds, wherein the code value of the fixed code data_fghj_sds is fixed to 4'b1100; A third selector is used to select and output between the fixed code data_fghj_sds and the bitwise inverted value of the fixed code data_fghj_sds generated by the second NOT gate according to the 1-bit polarity signal disp_in; A fourth selector is used to select between the output value of the third selector and the 0 encoding value to generate a 4-bit encoding value data_fghj according to the selection signal generated by the second judgment module, and together with the 6-bit encoding value data_abcdei, form an encoding result data_out={data_fghj, data_abcdei} output; The third judgment module is used to judge whether the encoding result data_out is equal to 10'h0, and use the judgment result as the generated error signal sds_err. If the error signal sds_err is 1, it means that the SDS control character encoding is incorrect.

4. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: The decoder supporting the data stream start character SDS uses a 10b / 8b decoding rule with an added SDS control character to perform 10b / 8b decoding on data of the PCIe physical link at Gen1 and Gen2 rates. The SDS control character is a code group identifier K28.4 reserved in a 10b / 8b decoding table of the CXL protocol.

5. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 4, characterized in that: The decoder supporting the data stream start symbol SDS comprises: A fourth judgment module is used to judge whether the upper 4 bits data_in[9:6] of the input 10-bit to-be-decoded data data_in are 4'b1100 or 4'b0011, and use the judgment result as the generated selection signal; a fifth selector, configured to select the fixed code data_EDCBA_sds or 5'd0 as the 5-bit decoded value data_EDCBA according to the selection signal generated by the fourth determination module; A fifth judgment module, used for judging whether the first, third and fourth bits of the 10-bit input data to be decoded data_in are all 1 at the same time, and using the judgment result as an output signal; A sixth judgment module, used to judge whether any one of the 1st, 3rd and 4th bits of the 10-bit input data to be decoded data_in is 1, and output the judgment result as a signal; An OR gate, used for performing an OR operation on the signals output by the fifth judgment module and the sixth judgment module; a sixth selector, for selecting the fixed code data_HGF_sds or 3'd0 as the 3-bit decoding value data_HGF according to the OR operation result of the OR gate, and the 3-bit decoding value data_HGF and the 5-bit decoding value data_EDCBA together constitute the decoding result data_out={data_HGF, data_EDCBA}, wherein the code value of the fixed code data_HGF_sds is fixed to 3'd4; A first AND gate, used for performing an AND operation on the selection signal generated by the fourth judgment module and the OR operation result of the OR gate to output a 1-bit K code k_out to indicate whether the decoding result data_out is an SDS control character; The seventh judgment module is used to judge whether the decoding result data_out is equal to 8'h0, and use the judgment result as the generated error signal sds_err. If the error signal sds_err is 1, it means that the SDS control character decoding is wrong.

6. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: The encoder supporting the data stream start character SDS adopts a link management state machine with an added "send SDS" state to perform link management. The link management state machine with an added "send SDS" state includes the following states: "reset / idle" state, which is the initial state of the link and is entered after power-on; "link training" state, which is the state in which the link is initialized and trained; "L0 / active" state, which is a normal working state, in which the link normally sends and receives messages, and enters this state after the link training is completed; "L0s" state, which is a first-level low-power state; "retraining" state, which is a state in which the link is reinitialized and trained, and the link needs to be retrained in this state after exiting from the "L1" state, and can enter the "L0 / active" state after the training is completed; "L1" state, which is a second-level low-power state; "L2" state, which is a third-level low-power state state; "send SDS" state is the state of sending SDS control characters; exiting the "reset / idle" state enters the "link training" state; exiting the "link training" state enters the "send SDS" state; under the control of the "send SDS" state, the encoding circuit that supports the data stream start character SDS on the sending end starts to send SDS control characters. After the receiving end recognizes the SDS control characters and detects the start of the data stream, the link management state machine jumps from the "send SDS" state to the "L0 / active" state; the "L0 / active" state and the "L0s" state can switch to each other, and the "L0 / active" state can switch unidirectionally to the "L1" state and the "L2" state; exiting the "L2" state enters the "reset / idle" state; exiting the "L1" state enters the "retraining" state; exiting the "retraining" state re-enters the "send SDS" state.

7. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: When the PCIe physical link is at the rate of Gen1 and Gen2, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, COMMA_1B}; when the PCIe physical link is at the rate of Gen3 and above, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, SKP_1B}, wherein SKP_1B is a single-byte clock deviation compensation symbol, and COMMA_1B is a single-byte synchronization symbol; the 4-byte clock deviation compensation symbol SKP_4B parsing circuit for parsing out two types of 4-byte clock deviation compensation symbols SKP_4B in the message includes: An eighth judgment module is used to judge whether the result of an AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A ninth judgment module, used to judge whether the result of an AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A tenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; An eleventh judgment module is used to judge whether the result of an AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A twelfth judgment module is used to judge whether the AND operation result of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the synchronization symbol COMMA_1B; a seventh selector, configured to select the judgment result of the twelfth judgment module when the PCIe physical link is at the rate of Gen1 and Gen2, and to select the judgment result of the eleventh judgment module otherwise; The second AND gate is used to perform a logic AND operation on the output results of the eighth judgment module, the ninth judgment module, the tenth judgment module, and the eleventh multiplexer to obtain a 4-byte clock deviation compensation symbol parsing result SKP_OUT; The first counter is used to output 1 every time a SKP_4B sequence {SKP_1B, SKP_1B, SKP_1B, SKP_1B} is received at the rate of Gen3 and above; The second counter is used to output 3 for each SKP sequence {SKP_1B, SKP_1B, SKP_1B, COMMA_1B} received at the Gen1 and Gen2 rates; an eighth selector, for selecting to output the output result of the second counter at the Gen1 and Gen2 rates, and otherwise selecting to output the output result of the first counter; The SKP counter is used to accumulate the output result of the eighth selector to obtain the clock deviation compensation symbol count value SKP_COUNT.

8. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: The data stream start detection circuit is used to generate data stream start marks for Gen1 and Gen2 rates and Gen3 and above rates at the same time, and uses the Gen1 / Gen2 signal representing the Gen1 and Gen2 rates as a decoding enable signal to enable either a decoder supporting the data stream start symbol SDS or a 128b / 130b decoder. The data stream start detection circuit includes a Gen3 and above rate SDS detection circuit, a Gen1 / Gen2 rate SDS detection circuit and a ninth selector. The Gen3 and above rate SDS detection circuit is used to detect the 1 The decoding result of the 28b / 130b decoder is used to perform data stream start mark detection to obtain the output result SDS_OUT_GEN3, the Gen1 / Gen2 rate SDS detection circuit is used to perform data stream start mark detection on the decoding result of the decoder that supports the data stream start symbol SDS to obtain the output result SDS_OUT_GEN1, and the ninth selector is used to select one from the output result SDS_OUT_GEN3 and the output result SDS_OUT_GEN1 as the final data stream start mark based on the control of the Gen1 / Gen2 signal.

9. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 8, characterized in that: The Gen1 / Gen2 rate SDS detection circuit comprises: The thirteenth judgment module is used to judge whether the result of the AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the SDS control character SDS_1B; A fourteenth judgment module is used to judge whether the result of the AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the SDS control character SDS_1B; The fifteenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the SDS control character SDS_1B; A sixteenth judgment module is used to judge whether the result of the AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the SDS control character SDS_1B; The third AND gate is used for performing a logic AND operation on the output results of the thirteenth judgment module, the fourteenth judgment module, the fifteenth judgment module and the sixteenth judgment module to obtain a result SDS_OUT_GEN1 of whether the received data is an SDS control character.

10. A chip comprising a plurality of core particles interconnected by a high-speed interconnect interface, characterized in that: The high-speed interconnect interface includes the circuit described in any one of claims 1 to 9 for enabling the CXL protocol to support a low-rate serial link.

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