Method, device and equipment for detecting via hole abnormity in PCB (Printed Circuit Board) and storage medium

Abstract

The invention provides a via hole abnormity detection method and device in a PCB, equipment and a storage medium, and relates to the technical field of circuit board design. The method comprises the following steps: in response to a via hole anomaly detection instruction for a generated PCB, grabbing via holes of the PCB, and obtaining a hole pitch between a first via hole and a second via hole belonging to the same network relationship in the via holes; and if the hole pitch is smaller than the process capability threshold, determining that the first via hole and the second via hole in the PCB are abnormal. According to the method and the device, the via holes of the PCB are automatically grabbed in response to the via hole anomaly detection instruction for the generated PCB, and whether the via holes are abnormal or not is judged according to the hole pitch of the via holes and the process capability threshold value, so that the detection efficiency is greatly improved. Besides, the automatic detection method can systematize and standardize the detection process and fully cover the via holes in the PCB, so that the problems of missing detection and false detection possibly occurring in manual detection are reduced, and the accuracy and reliability of via hole anomaly detection are further improved.

Description

Technical Field

[0001] The present application relates to the technical field of circuit board design, and in particular to a method, device, equipment and storage medium for detecting abnormal vias in a PCB. Background Art

[0002] In the design and manufacturing process of electronic products, the design of printed circuit boards (PCBs) is a crucial link, and its design quality directly affects the performance, reliability and production efficiency of the products. In the PCB design process, there are usually two kinds of misoperations: one is that when punching holes in the whole board, the designer may accidentally overlap or intersect the holes together. Although the design software does not prompt errors when the holes belonging to the same network relationship are overlapped or intersected, this may lead to poor electrical performance or other manufacturing problems during the manufacturing process; the other is that when punching holes in an area with extremely limited space, the designer may need to design the holes of the same network to intersect to meet the wiring requirements. However, the distance of these intersecting holes must be precisely controlled to meet the process capabilities of the PCB manufacturer. If these design problems fail to meet the manufacturing capacity requirements, they may flow into the production link and lead to frequent communication of engineering quality issues and repeated modifications of PCB design data, which will eventually affect the delivery time of the product. Therefore, before the PCB is put into production, it is necessary to detect abnormalities in the holes in the PCB.

[0003] In the related art, abnormal detection of vias in PCB is usually performed manually, but the efficiency of manual detection is low and there is a problem of missed detection. Summary of the invention

[0004] The present application provides a method, device, equipment and storage medium for detecting abnormal vias in a PCB, so as to reduce the problem of low efficiency and missed detection when manual abnormal detection of vias in a PCB is performed in the related art.

[0005] In a first aspect, the present application provides a method for detecting abnormal vias in a PCB, comprising:

[0006] In response to a via abnormality detection instruction for the generated PCB, the vias of the PCB are captured;

[0007] Obtain the hole spacing between the first via and the second via in the vias, the first via and the second via belong to vias of the same network relationship, the hole spacing is the difference between the first distance and the second distance, the first distance is the distance between the center of the first via and the center of the second via, and the second distance is the sum of the radius of the first via and the radius of the second via;

[0008] If the hole spacing is less than the process capability threshold, it is determined that there is an abnormality in the first via and the second via in the PCB.

[0009] In a possible implementation, the via types of the vias include blind vias, buried vias, and through holes. After obtaining the hole spacing between the first via and the second via, it also includes: obtaining a first via type for the first via and a second via type for the second via; and determining a process capability threshold based on the first via type and the second via type.

[0010] In a possible implementation, determining a process capability threshold based on a via type of a first via and a via type of a second via includes: obtaining a first aperture parameter of the first via type and a second aperture parameter of the second via type; and determining the process capability threshold based on the first aperture parameter and the second aperture parameter.

[0011] In a possible implementation, grabbing vias of a PCB includes: for each layer in a multi-layer structure of the PCB, based on a frame selection instruction, selecting a target area containing vias; based on a grabbing instruction, grabbing the vias in the target area.

[0012] In one possible implementation, obtaining the hole spacing between a first via and a second via in the vias includes: obtaining the name of a first electrical network to which the first via belongs; obtaining the name of a second electrical network to which the second via belongs; if the first electrical network name is consistent with the second electrical network name, determining that the first via and the second via belong to the same network relationship; and obtaining the hole spacing between the first via and the second via based on a spacing measurement instruction.

[0013] In a possible implementation, the method for detecting abnormal vias in a PCB further includes: if an abnormality exists in the first via and the second via in the PCB, adding abnormal warning marks for the first via and the second via.

[0014] In a possible implementation, the method for detecting abnormal vias in a PCB further includes: if there is no abnormality in the vias in the PCB, outputting prompt information indicating that the via detection in the PCB has passed, the prompt information indicating that the via design in the PCB is normal.

[0015] In a possible implementation, the method for detecting abnormal vias in a PCB further includes: if there are abnormal vias in the vias of the PCB, outputting an abnormal detection report of the PCB, the abnormal detection report including the location of the abnormal via and modification suggestions for the abnormal via.

[0016] In a second aspect, the present application provides a device for detecting abnormal vias in a PCB, comprising:

[0017] A capture module, used for responding to a via abnormality detection instruction for the generated PCB and capturing the vias of the PCB;

[0018] An acquisition module, used to acquire a hole spacing between a first via hole and a second via hole in the via hole, the first via hole and the second via hole being via holes of the same network relationship, the hole spacing being a difference between a first distance and a second distance, the first distance being a distance between a center of the first via hole and a center of the second via hole, and the second distance being a sum of a radius of the first via hole and a radius of the second via hole;

[0019] The processing module is used to determine that there is an abnormality between the first via hole and the second via hole in the PCB when the hole spacing is less than the process capability threshold.

[0020] In a third aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor;

[0021] Memory for storing computer-executable instructions;

[0022] A processor, configured to execute computer-executable instructions stored in a memory to implement any one of the methods described in the first aspect.

[0023] In a fourth aspect, the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed, they are used to implement any of the methods in the first aspect.

[0024] In a fifth aspect, the present application provides a computer program product, including a computer program, which implements any method in the first aspect when executed.

[0025] The present application provides a method, device, equipment and storage medium for detecting abnormal vias in a PCB. In response to an abnormal via detection instruction for a generated PCB, the vias of the PCB are captured, and the hole spacing between the first via and the second via in the via is obtained. The first via and the second via belong to vias of the same network relationship. The hole spacing is the difference between the first distance and the second distance. The first distance is the distance between the center of the first via and the center of the second via, and the second distance is the sum of the radius of the first via and the radius of the second via. If the hole spacing is less than the process capability threshold, it is determined that the first via and the second via in the PCB are abnormal. In this process, by responding to the abnormal via detection instruction for the generated PCB, the vias of the PCB are automatically captured, and according to the hole spacing of the via and the process capability threshold, it is determined whether the via is abnormal, thereby greatly improving the detection efficiency, reducing the problem of low manual detection efficiency, and reducing the cost of manpower input. In addition, the automated detection method can systematize and standardize the detection process, and comprehensively cover all vias in the PCB, thereby reducing the problems of missed detection and false detection that may occur in manual detection, thereby improving the accuracy and reliability of abnormal via detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0027] Figure 1 A schematic diagram of an application scenario of a method for detecting abnormal vias in a PCB provided by an exemplary embodiment of the present application;

[0028] Figure 2 A schematic diagram of a flow chart of a method for detecting abnormal vias in a PCB provided by an exemplary embodiment of the present application;

[0029] Figure 3 A schematic diagram of a first via hole and a second via hole in a via hole provided by an exemplary embodiment of the present application;

[0030] Figure 4 A schematic diagram of adding an abnormal warning mark provided for an exemplary embodiment of the present application;

[0031] Figure 5 Another schematic diagram of a flow chart of a method for detecting abnormal vias in a PCB provided by an exemplary embodiment of the present application;

[0032] Figure 6 A schematic diagram of a structure of a device for detecting abnormal via holes in a PCB provided by an exemplary embodiment of the present application;

[0033] Figure 7 A schematic diagram of the structure of an electronic device provided for an exemplary embodiment of the present application.

[0034] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0035] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0036] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, products or equipment.

[0037] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0038] In the related art, when relying on manual abnormal detection of vias in PCB, the inspectors usually check the vias of each layer of PCB one by one with naked eyes, manually judge whether there are vias with a hole spacing less than the process capability threshold among the vias of the same network relationship, and review the preliminary detection results by another inspector or senior engineer to ensure the accuracy of the detection results. However, since manual detection requires checking each via of each layer of PCB one by one, the process is cumbersome and time-consuming, especially in mass production, the efficiency is extremely low and the manpower investment cost is high; due to the different experience and skill levels of different inspectors during manual detection, and the large amount of repetitive workload of manual detection, it is easy to cause fatigue and decreased attention of the inspectors, making it easy for manual detection to miss detection, resulting in some abnormal vias not being discovered, thereby affecting the performance and reliability of the product; in addition, manual detection relies on the subjective judgment of the inspectors, and there may be differences in the detection results, which makes it difficult to ensure the consistency and reliability of the detection results, and as the complexity of PCB design increases, the difficulty of manual detection also increases, further reducing the detection efficiency and the accuracy of the detection results.

[0039] In order to solve the above problems, the embodiment of the present application provides a via abnormality detection solution in PCB, by designing an automated detection tool or automated detection program for one-click inspection of via abnormalities in PCB, in response to the via abnormality detection instruction for the generated PCB, all vias of PCB are automatically captured, and the hole spacing between vias of the same network relationship is obtained, and the vias of the same network relationship are judged according to the hole spacing and process capability threshold whether there are abnormal vias, and the automated detection of via abnormalities in PCB is realized, thereby greatly improving the detection efficiency, reducing the problem of low efficiency of manual detection, and reducing the cost of manpower input. In addition, automated detection can systematize and standardize the detection process, and comprehensively cover all vias in PCB, thereby reducing the problems of missed detection and false detection that may occur during manual detection, and thus improving the accuracy and reliability of via abnormality detection in PCB.

[0040] Figure 1 Schematic diagram of an application scenario of the method for detecting abnormal vias in a PCB provided by an exemplary embodiment of the present application. Figure 1 As shown, the application scenario includes a client 11 and a server 12, wherein the number of the client 11 may be at least one, and a PCB design tool is deployed in the server 12. In actual applications, when the server 12 detects a via abnormality detection instruction for a generated PCB submitted by the client 11, the server 12 executes the via abnormality detection method in the PCB provided by the present application to determine whether there is an abnormality in the via in the PCB.

[0041] It should be noted that the server 12 can also be replaced by a server cluster or other computing devices with certain computing power. The client 11 can be a computer and a notebook, etc.; the PCB design tool can be, for example, Cadence, Mentor Graphics, Eagle, PADS or Zuken, etc., and the PCB design tool deployed in the server 12 is not limited here.

[0042] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0043] Figure 2 A schematic diagram of a flow chart of a method for detecting abnormal vias in a PCB provided by an exemplary embodiment of the present application. Figure 2 As shown, the method for detecting abnormal vias in a PCB includes the following steps:

[0044] S201, responding to a via abnormality detection instruction for a generated PCB, capturing vias of the PCB.

[0045] For example, in one implementation, Figure 1 As shown, a pre-designed one-click automatic detection program for checking PCB via anomalies, such as a Skill program, is installed under the pcbenv path of the PCB design tool. Further, a new menu item such as Check VIA is added under the MANUFACTURE menu of the PCB design tool, and Check VIA is used to start the Skill program. Correspondingly, the user submits a via anomaly detection instruction for the generated PCB through the client 11, and the server 12 responds to the via anomaly detection instruction for the generated PCB, clicks the Check VIA menu, starts the Skill program, and automatically captures the vias of the PCB based on the preset judgment logic in the Skill program. Among them, the Skill program refers to a program written in the Skill language. Skill is a scripting language specifically used for electronic design automation tools and is widely used in PCB design tools. It should be noted that the Skill program here is only an example of an automatic detection program. In actual applications, it can also be a program written in other programming languages. The type of automatic detection program is not limited here.

[0046] In another implementation, still refer to Figure 1 , a pre-designed one-click automatic detection tool for checking PCB via abnormalities is deployed on the server 12. Correspondingly, Figure 1 As shown, the user submits a wiring anomaly detection instruction for the generated PCB through the client 11, and the server 12 responds to the via anomaly detection instruction for the generated PCB, runs the automated detection tool, and automatically captures the vias of the PCB based on the judgment logic preset in the automated detection tool.

[0047] It should be noted that the above-mentioned vias may be vias in the target area, or may be all vias in all layers of the generated PCB, and the number of vias is not limited here.

[0048] S202. Obtain a hole spacing between a first via and a second via in the vias, where the first via and the second via are vias of the same network relationship, and the hole spacing is a difference between a first distance and a second distance, where the first distance is a distance between a center of the first via and a center of the second via, and the second distance is a sum of a radius of the first via and a radius of the second via.

[0049] Among them, the same network relationship in PCB refers to the relationship between electrical connection points with the same network name in PCB design. These connection points can be pads, vias or pins of other components, and such connection points are electrically connected.

[0050] For example, Figure 3Schematic diagram of a first via hole and a second via hole in the via hole provided by the exemplary embodiment of the present application. Figure 3 As shown, the first distance is the distance L between the center of the first via hole and the center of the second via hole. ad , the second distance is the radius L of the first via hole ab The radius L of the second via cd The sum of the hole spacing L bc The first distance L ad and the second distance (L ab +L cd ), namely L bc =L ad -(L ab +L cd ).

[0051] S203: If the hole spacing is less than the process capability threshold, it is determined that there is an abnormality in the first via hole and the second via hole in the PCB.

[0052] The process capability threshold is set according to the process capability of the PCB manufacturer, and the threshold represents the minimum safe spacing allowed in the manufacturing process. For example, a data comparison instruction such as lessp is used to compare the hole spacing and the process capability threshold. If the hole spacing is greater than or equal to the process capability threshold, it is determined that there is no abnormality in the first via and the second via in the PCB; if the hole spacing is less than the process capability threshold, it is determined that there is an abnormality in the first via and the second via in the PCB.

[0053] It should be noted that the first via and the second via are merely any two vias in the same network relationship of the PCB, and the abnormality detection method for other vias in the same network relationship is the same as the abnormality detection method for the first via and the second via, which will not be repeated here.

[0054] The method, device, equipment and storage medium for detecting abnormal vias in PCB provided in the embodiments of the present application automatically capture the vias of PCB by responding to the abnormal via detection instruction for the generated PCB, and judge whether the vias are abnormal based on the hole spacing and process capability threshold of the vias, thereby greatly improving the detection efficiency, reducing the problem of low efficiency of manual detection, and reducing the cost of manpower input. In addition, the automated detection method can systematize and standardize the detection process, reduce the influence and limitation of factors such as the complexity of PCB design, the experience, skill level, subjective judgment, human eye fatigue and attention of the detection personnel, and comprehensively cover all vias in PCB, thereby reducing the problems of missed detection and false detection that may occur in manual detection, and thus improving the accuracy and reliability of abnormal via detection.

[0055] In some embodiments, the via types of the vias include blind vias, buried vias, and through holes. After obtaining the hole spacing between the first via and the second via, it also includes: obtaining a first via type for the first via and a second via type for the second via; and determining a process capability threshold based on the first via type and the second via type.

[0056] Among them, blind vias are vias that connect the surface layer (usually the top or bottom layer) and the inner layer of a PCB. This type of via extends from an outer layer of the PCB to one or more inner layers, but does not penetrate the entire board. It is used to connect the outer and inner layers without affecting other layers. It is often used in high-density interconnect (HDI) design to save space and increase wiring density; buried vias are vias that are completely located between the inner layers of the PCB and are not connected to any outer layer. This type of via is "buried" inside during the manufacturing process of the PCB and is used to connect between inner layers without affecting the wiring and component placement of the outer layer. It is suitable for situations where complex connections are required in multi-layer board design; through holes are vias that run through the entire thickness of the PCB, from the top layer to the bottom layer, and are used to provide electrical connections between all layers. They are the most common and traditional type of vias and are usually used in relatively simple multi-layer board designs.

[0057] For example, the first via type of the first via and the second via type of the second via are obtained. Optionally, the first via type and the second via type can be any one of a blind hole, a buried hole or a through hole. Among them, the first via type and the second via type can be the same or different, for example, the first via type and the second via type are both through holes or both blind holes, etc.; or, the first via type is a blind hole, and the second via type is a through hole, etc.; the first via type and the second via type are not specifically limited here. Further, according to the first via type and the second via type, the manufacturing process specification or database can be consulted to determine the applicable process capability threshold. Accordingly, if the first via type and the second via type are both blind holes, the corresponding process capability threshold is determined to be, for example, 0.075mm; if the first via type and the second via type are both through holes, the corresponding process capability threshold is determined to be, for example, 0.1mm. It should be noted that the above-mentioned process capability threshold is only an example, and the specific value of the process capability threshold is not limited here.

[0058] In some embodiments, a process capability threshold is determined based on a via type of a first via and a via type of a second via, including: obtaining a first aperture parameter of the first via type and a second aperture parameter of the second via type; and determining the process capability threshold based on the first aperture parameter and the second aperture parameter.

[0059] For example, in one implementation, a front-end page of an automated detection program or automated detection tool for one-click inspection of PCB via anomalies is provided, and the front-end page displays the aperture parameter configuration input boxes of each via type, such as blind vias, buried vias, and through holes, such as the aperture parameter input box of blind vias, the aperture parameter input box of buried vias, and the aperture parameter input box of through holes. Correspondingly, before starting the inspection, the inspection personnel can enter the aperture parameter in the aperture parameter input box corresponding to each via type, for example, the aperture parameter corresponding to the blind hole is 0.2mm, the aperture parameter corresponding to the buried hole is 0.4mm, and the aperture parameter corresponding to the through hole is 0.4mm. Among them, the aperture parameter can be the diameter of the via, or the radius of the via, etc., which is not limited here. Correspondingly, after obtaining the hole spacing between the first via and the second via, the aperture parameter in the aperture parameter input box corresponding to each via type is obtained, and the process capability threshold is determined based on the preset rules according to the first aperture parameter corresponding to the first via type and the second aperture parameter corresponding to the second via type.

[0060] In another implementation, after obtaining the hole spacing between the first via and the second via, the aperture parameters corresponding to the first via type and the second via type are automatically read from a preset configuration file, and the process capability threshold is further determined based on a preset rule according to the first aperture parameter corresponding to the first via type and the second aperture parameter corresponding to the second via type. The file format of the configuration file may be Extensible Markup Language (XML), JSON (JavaScript Object Notation), Comma-Separated Values ​​(CSV), and YAML (YAML Ain't Markup Language), etc., and the configuration files of each file format contain the aperture parameters corresponding to each via type.

[0061] It should be noted that the preset rule can be a comparison relationship between a preset aperture parameter and a process capability threshold, for example, by referring to a manufacturing process specification or a database to match an applicable process capability threshold; or the preset rule can also be a preset calculation algorithm, etc.; there is no limitation on the preset rules for determining the process capability threshold here.

[0062] It should also be noted that the aperture parameters in the input box and the aperture parameters in the configured file can be flexibly adjusted according to the process capabilities and specific production requirements of the PCB manufacturer, and are not limited here.

[0063] In the embodiment of the present application, by obtaining the specific via types of the first via and the second via and the aperture parameters corresponding to the via types, the corresponding process capability threshold can be determined more accurately, making the abnormal detection of the vias more precise, thereby effectively reducing errors and rework in production and further improving production efficiency.

[0064] In some implementations, grabbing the vias of the PCB includes: for each layer in the multi-layer structure of the PCB, based on a frame selection instruction, selecting a target area containing the vias; based on the grabbing instruction, grabbing the vias in the target area.

[0065] For example, all PCB layers in the PCB design file workspace are scanned, and the target area containing vias in each PCB layer is selected based on a selection instruction such as axlSingleSelectBox, and all objects in the selected area are obtained. Among all the obtained objects, the vias are further captured based on a capture instruction such as axlGetSelSet.

[0066] In some implementations, obtaining the hole spacing between a first via and a second via in the vias includes: obtaining the name of a first electrical network to which the first via belongs; obtaining the name of a second electrical network to which the second via belongs; if the first electrical network name is consistent with the second electrical network name, determining that the first via and the second via belong to the same network relationship; and obtaining the hole spacing between the first via and the second via based on a spacing measurement instruction.

[0067] For example, in the PCB design software, select the first via, and use the property viewing function to obtain the name of the first electrical network to which the via belongs; select the second via, and use the property viewing function to obtain the name of the second electrical network to which the via belongs; compare the first electrical network name and the second electrical network name; if the first electrical network name is consistent with the second electrical network name, it is determined that the first via and the second via belong to the same network relationship; if the first electrical network name is inconsistent with the second electrical network name, it is determined that the first via and the second via do not belong to the same network relationship.

[0068] Further, refer to Figure 3 For the first via and the second via that belong to the same network relationship, the distance L between the center of the first via and the center of the second via is measured based on the spacing measurement instruction such as axlAirGap ad , the radius of the first via hole L ab and the radius L of the second via cd , correspondingly, based on L bc =L ad -(L ab +L cd ), the hole spacing L between the first via hole and the second via hole is obtained bc .

[0069] The embodiments of the present application reduce the risk of mismeasuring the spacing of unrelated vias by measuring only the spacing of vias in the same electrical network, thereby improving the accuracy and reliability of the measurement. In addition, by automatically identifying and processing the via spacing measurements of the same electrical network, the workload of manual inspection and verification is reduced, the process of abnormal via detection in the PCB is simplified, and the efficiency of abnormal via detection in the PCB is improved.

[0070] Considering that in the related technology, when the abnormal detection of vias in PCB is carried out manually, if an abnormality is detected, the abnormal via position needs to be recorded manually without relevant warning signs, which is not conducive to finding and handling problems. This manual recording method is not only inefficient, but also prone to omissions or errors, resulting in potential electrical failures or safety hazards that cannot be eliminated in time, thus affecting the stability and safety of PCB design. In addition, the repetitive workload of manual inspection is large, which can easily lead to fatigue and decreased concentration of inspectors, further increasing the unreliability of the inspection results.

[0071] Therefore, based on the above embodiments, in some implementations, the method for detecting abnormal vias in a PCB further includes: if there are abnormalities in the first via and the second via in the PCB, adding abnormal warning marks for the first via and the second via.

[0072] For example, if there is an abnormality in the first via and the second via in the PCB, an abnormality warning mark is added to the first via and the second via. Optionally, the abnormality warning mark can be a visual mark, such as red highlight, or a warning icon is added near the first via and the second via. For example, Figure 4 A schematic diagram of adding an abnormal warning mark provided by an exemplary embodiment of the present application. Figure 4 As shown, when the first via and the second via are tangent, if the hole spacing between them is greater than or equal to the process capability threshold, then there is no abnormality in the first via and the second via; when the first via and the second via intersect, if the hole spacing is greater than or equal to the process capability threshold, then there is no abnormality in the corresponding first via and the second via; when the first via and the second via intersect, if the hole spacing is less than the process capability threshold, then there is an abnormality in the corresponding first via and the second via; correspondingly, an abnormal warning mark is added above the via with the abnormality, and the location of the abnormal via can be intuitively displayed through the abnormal warning mark.

[0073] In the embodiment of the present application, by adding abnormal warning marks to abnormal vias in the PCB, designers can be reminded of potential problems in a timely manner, which facilitates rapid repair measures, thereby effectively preventing potential electrical failures and safety hazards, and further improving the stability and safety of PCB design. In addition, the automated marking method is not affected or limited by factors such as the complexity of the PCB design, the experience, skill level, subjective judgment, eye fatigue and attention of the inspection personnel, further increasing the reliability of the inspection results.

[0074] In some implementations, the method for detecting abnormal vias in a PCB further includes: if there is no abnormality in the vias in the PCB, outputting a prompt message indicating that the via detection in the PCB has passed, the prompt message indicating that the via design in the PCB is normal.

[0075] For example, still refer to Figure 4 If there are no abnormal vias in the designed PCB among the vias belonging to the same network relationship, that is, there are no vias whose hole spacing is smaller than the process capability threshold, then the PCB via detection pass prompt information is output through an output command such as axlUIWPrint, and the inspector can determine that the design of the vias in the PCB is normal through the prompt information.

[0076] In the embodiment of the present application, by outputting a detection pass prompt message for the PCB that has passed the via detection, the detection result can be fed back in time, so that the designer can confirm the correctness of the PCB design in time.

[0077] In some implementations, the method for detecting abnormal vias in a PCB further includes: if there are abnormal vias in the vias of the PCB, outputting an abnormal detection report of the PCB, the abnormal detection report including the location of the abnormal via and modification suggestions for the abnormal via.

[0078] For example, if there are abnormal vias in the vias of the PCB, an abnormal detection report of the PCB is automatically generated. The abnormal detection report records the specific location of the abnormal vias, such as the coordinates of the abnormal vias or the PCB layer where they are located, and provides specific modification suggestions for each abnormal via. Among them, the modification suggestions may include, but are not limited to, adjusting the via spacing to meet the design standards, modifying the via size to meet the tolerance requirements, confirming whether the electrical network connection of the via is correct, increasing the distance between the via and other components, etc., and summarizing the information and modification suggestions of all abnormal vias into an abnormal detection report. Furthermore, the abnormal detection report is stored in the target path or sent to the target device to facilitate designers to view and analyze the problem; and the abnormal detection report is used as a process management file for PCB design.

[0079] In the embodiment of the present application, through the relevant information recorded in the abnormal detection report, the designer can quickly and accurately identify and process abnormal vias in the PCB design, thereby improving the processing efficiency of abnormal vias and further improving the reliability and safety of the PCB design.

[0080] Figure 5 Another flow chart of the method for detecting abnormal vias in a PCB provided by the exemplary embodiment of the present application is shown in FIG. Figure 5 As shown, the method for detecting abnormal vias in a PCB includes the following steps:

[0081] S501, responding to a via abnormality detection instruction for a generated PCB, capturing vias of the PCB.

[0082] S502. Obtain a hole spacing between a first via and a second via in the vias, where the first via and the second via are vias of the same network relationship, and the hole spacing is a difference between a first distance and a second distance, where the first distance is a distance between a center of the first via and a center of the second via, and the second distance is a sum of a radius of the first via and a radius of the second via.

[0083] S503 : Obtain a first via type of the first via and a second via type of the second via.

[0084] Optionally, the first via type and the second via type can be any one of a blind hole, a buried hole or a through hole. The first via type and the second via type can be the same or different, for example, the first via type and the second via type are both through holes or both blind holes, or the first via type is a blind hole and the second via type is a through hole, etc. The first via type and the second via type are not specifically limited here.

[0085] S504 , obtaining a first aperture parameter of the first via type and a second aperture parameter of the second via type.

[0086] For example, a front-end page of an automated detection program or automated detection tool for one-click inspection of PCB via anomalies is provided, and the aperture parameter configuration input boxes of each via type, such as blind vias, buried vias and through holes, are displayed on the front-end page, such as the aperture parameter input box of the blind hole, the aperture parameter input box of the buried hole and the aperture parameter input box of the through hole. Correspondingly, before starting the inspection, the inspection personnel can enter the aperture parameter in the aperture parameter input box corresponding to each via type, for example, the aperture parameter corresponding to the blind hole is 0.2mm, the aperture parameter corresponding to the buried hole is 0.4mm, and the aperture parameter corresponding to the through hole is 0.4mm. Among them, the aperture parameter can be the diameter of the via, or the radius of the via, etc., which is not limited here. Correspondingly, after obtaining the hole spacing between the first via and the second via, the aperture parameters in the aperture parameter input box corresponding to each via type on the front-end page are read to obtain the first aperture parameter of the first via type and the second aperture parameter of the second via type.

[0087] S505 . Determine a process capability threshold according to the first aperture parameter and the second aperture parameter.

[0088] For example, the process capability threshold is determined based on a preset rule according to a first aperture parameter corresponding to the first via type and a second aperture parameter corresponding to the second via type. The preset rule may be a comparison relationship between a preset aperture parameter and a process capability threshold, such as matching an applicable process capability threshold by consulting a manufacturing process specification or a database; or the preset rule may be a preset calculation algorithm, etc.; the preset rule for determining the process capability threshold is not limited here.

[0089] S506 , determining whether there are vias with a hole spacing smaller than a process capability threshold among vias of the same network relationship on the PCB.

[0090] If yes, execute S507;

[0091] If not, execute S508.

[0092] S507 , adding an abnormal warning mark for the first via hole and the second via hole whose hole spacing is less than the process capability threshold.

[0093] For example, if there are abnormalities in the first via hole and the second via hole in the PCB, an abnormality warning mark is added to the first via hole and the second via hole. The abnormality warning mark is as follows: Figure 4 shown.

[0094] S508, outputting a prompt message indicating that the via hole detection of the PCB has passed.

[0095] For example, by outputting a prompt message indicating that the via detection of the PCB has passed through an output command such as axlUIWPrint, the inspector can determine that the design of the vias in the PCB is normal through the prompt message.

[0096] In summary, this application has at least the following advantages:

[0097] 1. By responding to the abnormal via detection instructions for the generated PCB, the PCB's vias are automatically captured, and the vias are judged to be abnormal based on the via spacing and process capability threshold, thereby greatly improving the detection efficiency, reducing the problem of low manual detection efficiency, and reducing the cost of manpower input. In addition, the automated detection method can systematize and standardize the detection process, reduce the influence and limitation of factors such as the complexity of PCB design, the experience, skill level, subjective judgment, human eye fatigue and attention of the detection personnel, and comprehensively cover all vias in the PCB, thereby reducing the problems of missed detection and false detection that may occur in manual detection, and thus improving the accuracy and reliability of abnormal via detection.

[0098] 2. By obtaining the specific via types of the first via and the second via and the aperture parameters corresponding to the via types, the corresponding process capability threshold can be determined more accurately, making the abnormal detection of vias more precise, thereby effectively reducing errors and rework in production and further improving production efficiency.

[0099] 3. By adding abnormal warning marks to abnormal vias in PCB, designers can be reminded of potential problems in time, which facilitates rapid repair measures, thus effectively preventing potential electrical failures and safety hazards, and further improving the stability and safety of PCB design. In addition, the automated marking method is not affected or limited by factors such as the complexity of PCB design, the experience, skill level, subjective judgment, eye fatigue and attention of the inspectors, further increasing the reliability of the inspection results.

[0100] Figure 6 A schematic diagram of a structure of a via abnormality detection device in a PCB provided by an exemplary embodiment of the present application. Figure 6 As shown, the via abnormality detection device 60 in the PCB includes a capture module 61, an acquisition module 62 and a processing module 63, wherein:

[0101] A capture module 61 is used to respond to a via abnormality detection instruction for the generated PCB and capture the vias of the PCB;

[0102] An acquisition module 62 is used to acquire a hole spacing between a first via hole and a second via hole in the via hole, the first via hole and the second via hole being via holes of the same network relationship, the hole spacing being a difference between a first distance and a second distance, the first distance being a distance between a center of the first via hole and a center of the second via hole, and the second distance being a sum of a radius of the first via hole and a radius of the second via hole;

[0103] The processing module 63 is used to determine that there is an abnormality between the first via hole and the second via hole in the PCB when the hole spacing is less than the process capability threshold.

[0104] In one possible implementation, the via types of the vias include blind vias, buried vias and through holes, and the acquisition module 62 can be specifically used to: obtain a first via type for the first via and a second via type for the second via; and determine a process capability threshold based on the first via type and the second via type.

[0105] In a possible implementation manner, the acquisition module 62 may also be used to: acquire a first aperture parameter of the first via type and a second aperture parameter of the second via type; and determine a process capability threshold according to the first aperture parameter and the second aperture parameter.

[0106] In a possible implementation, the capture module 61 may be specifically used to: for each layer in the multi-layer structure of the PCB, based on a frame selection instruction, frame a target area containing vias; based on a capture instruction, capture the vias in the target area.

[0107] In a possible implementation, the acquisition module 62 can also be used to: obtain the name of the first electrical network to which the first via belongs; obtain the name of the second electrical network to which the second via belongs; if the first electrical network name is consistent with the second electrical network name, determine that the first via and the second via belong to the same network relationship; based on the spacing measurement instruction, obtain the hole spacing between the first via and the second via.

[0108] In a possible implementation manner, the processing module 63 may be specifically configured to add abnormal warning marks to the first via and the second via when an abnormality exists in the first via and the second via in the PCB.

[0109] In a possible implementation manner, the processing module 63 may also be used to: when there is no abnormality in the via in the PCB, output a prompt message indicating that the via detection in the PCB has passed, the prompt message indicating that the via design in the PCB is normal.

[0110] In a possible implementation, the processing module 63 may also be used to: when there are abnormal vias in the vias of the PCB, output an abnormality detection report of the PCB, wherein the abnormality detection report includes the location of the abnormal via and modification suggestions for the abnormal via.

[0111] The device for detecting abnormal vias in a PCB provided in the embodiment of the present application can execute the technical solution shown in the embodiment of the method for detecting abnormal vias in a PCB mentioned above, and its implementation principle and beneficial effects are similar, so they will not be repeated here.

[0112] It should be noted that it should be understood that the division of the various modules of the above device is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. And these modules can all be implemented in the form of software called by processing elements; they can also be all implemented in the form of hardware; some modules can also be implemented in the form of software called by processing elements, and some modules can be implemented in the form of hardware. For example, the processing module can be a separately established processing element, or it can be integrated in a chip of the above device. In addition, it can also be stored in the memory of the above device in the form of program code, and called and executed by a processing element of the above device. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each module above can be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.

[0113] For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more microprocessors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module above is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0114] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer instructions on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, referred to as DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, Digital Video Discs (DVDs)), or semiconductor media (eg, solid state disks (SSDs)).

[0115] Figure 7 The schematic diagram of the structure of the electronic device provided by the exemplary embodiment of the present application. Figure 7 As shown, the electronic device 70 of this embodiment includes:

[0116] At least one processor 71; and a memory 72 communicatively connected to the at least one processor;

[0117] The memory 72 stores instructions that can be executed by the at least one processor 71, and the instructions are executed by the at least one processor 71 to enable the electronic device to execute the method described in any of the above embodiments.

[0118] Optionally, the memory 72 may be independent or integrated with the processor 71 .

[0119] The memory 72 may include a high-speed random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0120] The processor 71 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. Specifically, when implementing the method for detecting abnormal vias in a PCB described in the aforementioned method embodiment, the electronic device may be, for example, an electronic device with processing functions such as a server.

[0121] Optionally, the electronic device may further include a communication interface 73. In a specific implementation, if the communication interface 73, the memory 72 and the processor 71 are implemented independently, the communication interface 73, the memory 72 and the processor 71 may be interconnected through a bus and communicate with each other. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc., but it does not mean that there is only one bus or one type of bus.

[0122] Optionally, in a specific implementation, if the communication interface 73, the memory 72 and the processor 71 are integrated on a chip, the communication interface 73, the memory 72 and the processor 71 can communicate through an internal interface.

[0123] The implementation principle and technical effects of the electronic device provided in this embodiment can be found in the aforementioned embodiments and will not be described in detail here.

[0124] An embodiment of the present application also provides a computer-readable storage medium, in which computer execution instructions are stored. When the computer execution instructions are executed, they are used to implement the method steps in the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0125] The above-mentioned computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0126] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in a dedicated integrated circuit. Of course, the processor and the readable storage medium can also be present in the via abnormality detection device in the PCB as discrete components.

[0127] The embodiment of the present application also provides a computer program product, including a computer program. When the computer program is executed, the method steps in the above method embodiment are implemented. The specific implementation method and technical effect are similar and will not be repeated here.

[0128] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0129] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for detecting abnormal vias in a PCB, characterized in that: include: In response to a via abnormality detection instruction for a generated PCB, capture vias of the PCB; Obtaining a hole spacing between a first via hole and a second via hole in the via holes, wherein the first via hole and the second via hole belong to via holes of the same network relationship, the hole spacing is a difference between a first distance and a second distance, the first distance is a distance between a center of the first via hole and a center of the second via hole, and the second distance is a sum of a radius of the first via hole and a radius of the second via hole; If the hole spacing is less than the process capability threshold, it is determined that there is an abnormality in the first via hole and the second via hole in the PCB.

2. The method according to claim 1, characterized in that The via types of the vias include blind vias, buried vias and through holes. After obtaining the hole spacing between the first vias and the second vias, the method further includes: Obtain a first via type of the first via and a second via type of the second via; A process capability threshold is determined based on the first via type and the second via type.

3. The method according to claim 2, characterized in that The determining the process capability threshold according to the via type of the first via and the via type of the second via includes: Obtaining a first aperture parameter of the first via type and a second aperture parameter of the second via type; The process capability threshold is determined according to the first aperture parameter and the second aperture parameter.

4. The method according to any one of claims 1 to 3, characterized in that The step of grabbing the via hole of the PCB comprises: For each layer in the multi-layer structure of the PCB, based on the frame selection instruction, frame a target area including vias; Based on the grabbing instruction, the vias in the target area are grabbed.

5. The method according to any one of claims 1 to 3, characterized in that The obtaining the hole spacing between the first via hole and the second via hole in the via holes includes: Obtain a name of a first electrical network to which the first via belongs; Obtain a name of a second electrical network to which the second via belongs; If the first electrical network name is consistent with the second electrical network name, determining that the first via and the second via belong to the same network relationship; Based on the spacing measurement instruction, a hole spacing between the first via hole and the second via hole is obtained.

6. The method according to any one of claims 1 to 3, characterized in that Also includes: If there is an abnormality in the first via hole and the second via hole in the PCB, an abnormality warning mark is added to the first via hole and the second via hole.

7. The method according to any one of claims 1 to 3, characterized in that Also includes: If there is no abnormality in the vias in the PCB, a prompt message indicating that the via detection in the PCB has passed is output, and the prompt message indicates that the via design in the PCB is normal.

8. The method according to any one of claims 1 to 3, characterized in that Also includes: If there are abnormal vias in the vias of the PCB, an abnormality detection report of the PCB is output, and the abnormality detection report includes the location of the abnormal via and modification suggestions for the abnormal via.

9. A device for detecting abnormal vias in a PCB, characterized in that: include: A capture module, used for responding to a via abnormality detection instruction for a generated PCB and capturing vias of the PCB; an acquisition module, used to acquire a hole spacing between a first via hole and a second via hole in the via holes, wherein the first via hole and the second via hole are via holes of the same network relationship, and the hole spacing is a difference between a first distance and a second distance, wherein the first distance is a distance between a center of the first via hole and a center of the second via hole, and the second distance is a sum of a radius of the first via hole and a radius of the second via hole; A processing module is used to determine that there is an abnormality between the first via hole and the second via hole in the PCB when the hole spacing is less than a process capability threshold.

10. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory is used to store computer-executable instructions; The processor is used to execute the computer-executable instructions to implement the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 8 when executed.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed, the method according to any one of claims 1 to 8 is implemented.

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