Display panel and display device

Abstract

The invention discloses a display panel and a display device. Comprising a driving circuit, the driving circuit comprises N stages of shifting registers which are cascaded with one another, and each shifting register comprises a first control unit, a second control unit, a third control unit and a fourth control unit. The first control unit receives a signal of an input signal for controlling a first node in response to a first clock signal; the second control unit receives the first voltage signal and the second voltage signal, and responds to the signal of the first node, the first clock signal and the second clock signal to control the signal of the second node; the third control unit receives a signal of the first voltage signal in response to a third node, or the second voltage signal in response to a signal of the second node, and generates an output signal; the fourth control unit is connected to the third node and controls the potential of the third node to be a first low-level signal in at least a first time period when the first node is a low-level signal, and the potential of the first low-level signal is lower than that of the first voltage signal.

Description

[0001] This application is a divisional application of application number 202011621871.7, application date December 31, 2020, and invention name “Display panel and display device”. Technical Field

[0002] The present invention relates to the field of display panels, and in particular to a display panel and a display device. Background Art

[0003] In the display field, shift registers are often used to achieve scanning display or other functions. However, when the shift register is working, the voltage of its internal control node inevitably has threshold loss, which makes the transistor in the corresponding shift register unable to fully conduct, resulting in the level of the shift register output terminal failing to reach the target voltage, resulting in tailing phenomenon, affecting the display effect.

[0004] When the output signal of the PMOS transistor in the shift register jumps from a high level to a low level, the gate potential of the PMOS transistor is Vgl potential, and the source potential of the PMOS transistor is also Vgl potential, that is, the gate and source of the PMOS transistor are both Vgl potential, and the PMOS transistor operates in an unsaturated state, which will cause the voltage output at the drain to be |Vgl|-|Vth|, where Vth is the threshold voltage of the PMOS transistor.

[0005] Since the voltage outputted by the drain of the PMOS transistor cannot reach the predetermined output Vgl, the output pulse signal of the current shift register has a tailing phenomenon when the high level jumps to the low level. Summary of the invention

[0006] The embodiments of the present invention provide a display panel and a display device to solve the problem of tailing of output signals of a shift register.

[0007] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0008] A driving circuit, the driving circuit comprising N stages of shift registers cascaded to each other, N≥2;

[0009] The shift register comprises:

[0010] a first control unit configured to receive an input signal and control a signal of a first node in response to a first clock signal;

[0011] a second control unit, the second control unit being configured to receive the first voltage signal and the second voltage signal, and to control the signal of the second node in response to the signal of the first node, the first clock signal, and the second clock signal;

[0012] a third control unit, the third control unit being configured to receive the first voltage signal and respond to a signal of a third node, or to receive the second voltage signal and respond to a signal of the second node to generate an output signal, wherein the third node is connected to the first node, the first voltage signal is a low level signal, and the second voltage signal is a high level signal;

[0013] A fourth control unit, the fourth control unit is connected to the third node, and is used to control the potential of the third node to be a first low-level signal during at least a first time period when the first node is a low-level signal, wherein the potential of the first low-level signal is lower than the potential of the first voltage signal.

[0014] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the first aspect.

[0015] The display panel provided by the embodiment of the present invention includes a driving circuit, which includes N-stage shift registers cascaded to each other, and the shift register includes a first control unit, a second control unit, a third control unit and a fourth control unit. The third control unit is used to receive a first voltage signal and respond to a signal of a third node, or receive a second voltage signal and respond to a signal of a second node to generate an output signal. Since the fourth control unit is connected to the third node, and can control the potential of the third node to be a first low-level signal in at least a first time period when the first node is a low-level signal, the potential of the first low-level signal is lower than the potential of the first voltage signal, that is, the potential of the third node is lower than the potential of the first voltage signal, so that the transistor in the third control unit quickly tends to a saturated state, outputs the first voltage signal, and avoids the problem of tailing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of a shift register in the prior art;

[0017] Figure 2 for Figure 1 The timing diagram of the shift register shown;

[0018] Figure 3 A schematic diagram of the structure of a shift register of a display panel provided by an embodiment of the present invention;

[0019] Figure 4 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0020] Figure 5 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0021] Figure 6 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0022] Figure 7 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0023] Figure 8 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0024] Fig. 9 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0025] Fig.10 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0026] Fig.11 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0027] Fig.12 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0028] Fig.13 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0029] Fig.14 for Fig.13 Timing diagram of the circuit structure shown;

[0030] Fig.15 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0031] Fig.16 for Fig.15 Timing diagram of the circuit structure shown;

[0032] Fig.17 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0033] Fig.18 for Fig.17 Timing diagram of the circuit structure shown;

[0034] Fig.19 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0035] Fig. 20 for Fig.19 Timing diagram of the circuit structure shown;

[0036] Fig.21 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0037] Fig. 22 for Fig.21 Timing diagram of the circuit structure shown;

[0038] Fig.23 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0039] Fig.24 for Fig.23 Timing diagram of the circuit structure shown;

[0040] Fig.25 A schematic structural diagram of a shift register of another display panel provided by an embodiment of the present invention;

[0041] Fig.26 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0043] Figure 1 is a structural diagram of a shift register in the prior art, Figure 2 for Figure 1 The timing diagram of the shift register is shown in Figure 1. Figure 1 as well as Figure 2 , when the shift register needs to change from a high level to a low level, transistor P1 needs to be turned off and transistor P2 needs to be turned on. At this time, the gate potential of transistor P2 is Vgl, and the source potential of transistor P2 is also Vgl, that is, the gate and source of transistor P2 are both at Vgl, and transistor P2 works in an unsaturated state, which will cause the voltage output by the drain of transistor P2 to be |Vgl|-|Vth|, where Vth is the threshold voltage of transistor P2. Since the voltage output by the drain of transistor P2 cannot reach the predetermined output Vgl, Figure 2 As shown, the output pulse signal of the current shift register has a tailing phenomenon when the high level jumps to the low level (such as Figure 2 The position indicated by the arrow).

[0044] In view of this, an embodiment of the present invention provides a display panel, including a driving circuit, wherein the driving circuit includes N-stage shift registers cascaded to each other. N is a positive integer greater than or equal to 2. The driving circuit is used to output pulse signals to the display panel line by line. For example, a scanning pulse signal is output to each scanning line of the display panel, or a light-emitting control pulse signal is output to each row of the light-emitting control signal line of the display panel. Figure 3 A schematic diagram of the structure of a shift register of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the shift register of the display panel provided in the embodiment of the present invention includes a first control unit 01, a second control unit 02, a third control unit 03 and a fourth control unit 04. The first control unit 01 is used to receive an input signal IN and control the signal of the first node N1 in response to the first clock signal CK1. The second control unit 02 is used to receive a first voltage signal Vgl and a second voltage signal Vgh, and control the signal of the second node N2 in response to the signal of the first node N1, the first clock signal CK1, and the second clock signal CK2. The third control unit 03 is used to receive the first voltage signal Vgl and respond to the signal of the third node N3, or receive the second voltage signal Vgh and respond to the signal of the second node N2 to generate an output signal OUT. The third node N3 is connected to the first node N1, the first voltage signal Vgl is a low-level signal, and the second voltage signal Vgh is a high-level signal. The embodiment of the present invention is also provided with a fourth control unit 04, and the fourth control unit 04 is connected to the third node N3. During at least the first time period when the first node N1 is a low-level signal, the fourth control unit 04 can control the potential of the third node N3 to be the first low-level signal V1, wherein the potential of the first low-level signal V1 is lower than the potential of the first voltage signal Vgl. Therefore, the gate potential of the transistor that controls the generation of the output signal OUT in the third control unit 03 is lower than the potential of the first voltage signal Vgl, and the source potential is the potential of the first voltage signal Vgl, so that the transistor that controls the generation of the output signal OUT in the third control unit 03 quickly approaches the saturation state, so that the source voltage and drain voltage of the transistor that controls the generation of the output signal OUT in the third control unit 03 tend to be equal, thereby reducing the tailing phenomenon.

[0045] Optionally, based on the above embodiment, the fourth control unit may further include a first capacitor, wherein the first plate of the first capacitor is connected to the third node, and the second plate receives a first control signal; wherein, during the first time period, the first control signal is a low level signal. Figure 4The fourth control unit 04 is provided with a first capacitor C1, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives the first control signal A1. In the first time period, the first node N1 is at a low level, the first control signal A1 is a low level signal, and the first capacitor C1 is quickly charged, so that the potential of the third node N3 drops rapidly and is lower than the potential of the first voltage signal Vgl.

[0046] Optional, see for example Figure 5 , the fourth control unit 04 may also include a first transistor M1, the source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2; wherein, in the first time period, the second control signal A2 controls the first transistor M1 to turn on, and the first control signal A1 is transmitted to the first capacitor C1, and at this time, the first node N1 is at a low potential. Under the low level control of the first capacitor C1 and the first control signal A1, the potential of the third node N3 drops rapidly to below the first voltage signal Vgl. Since the third control unit 03 receives the second voltage signal Vgh and responds to the signal of the second node N2 to generate the output signal OUT, the third node N3 needs to maintain a high potential all the time. That is, the fourth control module 04 does not need to control the third node N3 to be less than the potential of the first voltage signal Vgl at all times. Therefore, the embodiment of the present invention sets the first transistor M1 so that in the first time period, the first transistor M1 is turned on to control the potential of the third node N3 to be less than the first voltage signal Vgl. In other time periods, the first transistor M1 can be turned off to avoid interfering with the potential of the third node N3 and affecting the output signal of the shift register.

[0047] Optionally, the first control signal and the second control signal may be set to be the same signal. Figure 6 As shown, the source and gate of the first transistor M1 are electrically connected, and both receive the first control signal A1 (or the second control signal A2). This arrangement can reduce the number of signal lines in the display panel.

[0048] Optionally, the first clock signal CK1 and the first control signal A1 may be set to be the same signal. Figure 7 As shown, the embodiment of the present invention can further reduce the number of signal lines in the display panel. By adjusting the timing of the shift register, it is ensured that the first clock signal CK1 is a low-level signal in the first time period, so that the fourth control unit can control the potential of the third node to be a first low-level signal, that is, a potential lower than the first voltage signal Vgl.

[0049] Optionally, the second control signal may also be set as a signal of the first node. Figure 8As shown, the gate of the first transistor M1 is connected to the first node N1, so the second control signal A2 is the signal of the first node N1. When the first node N1 is at a low level, the first transistor M1 is turned on, and the first control signal A1 is transmitted to the first capacitor C1, thereby controlling the potential of the third node N3 to be lower than the potential of the first voltage signal Vgl in the first time period.

[0050] Optionally, the fourth control unit in the embodiment of the present invention may further include a second capacitor, wherein the first plate of the second capacitor is connected to the gate of the first transistor, and the second plate receives the second voltage signal. Fig. 9 As shown, the fourth control unit 04 includes a second capacitor C2, a first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and a second plate receives a second voltage signal Vgh. When the second control signal A2 is a signal of the first node N1, the embodiment of the present invention can stabilize the potential of the first node N1 through the second voltage signal Vgh and the second capacitor C2, so as to prevent the floating of the potential of the first node N1 from affecting the potential of the third node N3.

[0051] Optionally, the capacitance value of the first capacitor is less than the capacitance value of the second capacitor. Since the first capacitor C1 is used to control the pull-down of the third node potential, according to the relationship between the capacitance C, the charge Q, and the voltage U, U=Q / C, it can be seen that, under the same charge, if the voltage is to drop rapidly, a smaller capacitance value is required. The smaller the capacitance, the faster the pull-down speed of the third node potential, and the easier it is to improve the effect of reducing the tailing phenomenon. Therefore, the first capacitor C1 requires a smaller capacitance value. The second capacitor C2 is mainly used to stabilize the potential of the first node N1 and the third node N3. Therefore, the second capacitor C2 requires a larger capacitance value to avoid causing too much change in the potential of the first node N1 during the process of capacitor charging and discharging, and improve the stability of the node potential. Therefore, the capacitance value of the first capacitor is set to be less than the capacitance value of the second capacitor in the embodiment of the present invention.

[0052] Optionally, the fourth control unit may further include a second transistor, the source of the second transistor is connected to the first node, the drain is connected to the third node, and the gate receives a first control signal; wherein, in the first time period, the first control signal controls the second transistor to turn on. Fig.10As shown, the fourth control unit 04 includes a first capacitor C1, a first transistor M1 and a second transistor M2. The source of the first transistor M1 receives the first control signal A1, the drain is connected to the third node N3, and the gate receives the second control signal A2; the first capacitor is located between the drain of the first transistor M1 and the third node N3. In the first time period, the second control signal A2 controls the first transistor M1 to turn on, and in the first time period, the first control signal A1 is a low level signal. The source of the second transistor M2 is connected to the first node N1, the drain is connected to the third node N3, and the gate receives the first control signal A1; wherein, in the first time period, the first control signal A1 controls the second transistor M2 to turn on.

[0053] If the potential of the first node N1 is transmitted to the third node N3 before the first control signal A1 drops to a low level, the tailing problem of the shift register cannot be avoided. In the embodiment of the present invention, a second transistor M2 is arranged between the first node N1 and the third node N3. Since the gate of the second transistor M2 receives the first control signal A1, only when the first control signal A1 is at a low level and the first transistor M1 is turned on, the second transistor M2 is turned on at the same time, thereby realizing the pull-down of the potential of the third node N3, which can prevent the potential of the first node N1 from being directly transmitted to the third control unit 03 without the pull-down effect of the fourth control unit 04, thereby causing the problem of output signal tailing.

[0054] Optionally, the fourth control unit may further include a third transistor, the source of the third transistor receives the second voltage signal, the drain is connected to the third node, and the gate is connected to the second node; wherein, in the first time period, the second node controls the third transistor to turn off. Fig.11 As shown, the fourth control unit 04 includes a first capacitor C1, a first transistor M1 and a third transistor M3. The source of the first transistor M1 receives the first control signal A1, the drain is connected to the third node N3, and the gate receives the second control signal A2; the first capacitor is located between the drain of the first transistor M1 and the third node N3. In the first time period, the second control signal A2 controls the first transistor M1 to turn on, and in the first time period, the first control signal A1 is a low level signal. The source of the third transistor M3 receives the second voltage signal Vgh, the drain is connected to the third node N3, and the gate is connected to the second node N2; wherein, in the first time period, the second node N2 controls the third transistor M3 to turn off.

[0055] Since each clock signal in the shift register undergoes multiple jumps, the potential of the first node N1 and the point node N3 will float during the jump process. The embodiment of the present invention sets the third transistor M3, and uses the potential of the second node N2 to control the potential of the third node N3, so as to ensure the signal stability of the third node N3 at a high level. For example, if the shift register is required to output a high level (the second voltage signal Vgh), then the second node N2 is at a low potential, and the third node N3 needs to maintain a stable high potential. The embodiment of the present invention sets the third transistor M3, the gate of the third transistor M3 is connected to the second node N2, the second node N2 is at a low potential, and the third transistor M3 is turned on, so that the third node N3 is stably maintained at the high potential of the second voltage signal Vgh, ensuring that the level of the third node N3 does not change before the second node N2 becomes a high level, and only when the second node N2 node becomes a high level, the third node N3 node becomes a low level signal lower than the first voltage signal Vgl, thereby weakening the tailing phenomenon.

[0056] Optionally, the first control unit may include a fourth transistor, the source of the fourth transistor is connected to the input signal, the drain is connected to the first node, and the gate receives the first clock signal. The second control unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a third capacitor and a fourth capacitor. Among them, the source of the fifth transistor receives the first clock signal, the drain is connected to the fourth node, and the gate is connected to the first node. The source of the sixth transistor receives the second clock signal, the drain is connected to the fifth node, and the gate is connected to the fourth node. The source of the seventh transistor receives the first voltage signal, the drain is connected to the fourth node, and the gate receives the first clock signal. The source of the eighth transistor receives the second voltage signal, the drain is connected to the second node, and the gate is connected to the first node. The source of the ninth transistor is connected to the fifth node, the drain is connected to the second node, and the gate receives the second clock signal. The first plate of the third capacitor is connected to the fourth node, and the second plate is connected to the fifth node. The first plate of the fourth capacitor receives the second voltage signal, and the second plate is connected to the second node. The third control unit includes the tenth transistor and the eleventh transistor fourth capacitor. The source of the tenth transistor receives the first voltage signal, the drain outputs the output signal, and the gate is connected to the third node. The source of the eleventh transistor receives the second voltage signal, the drain outputs the output signal, and the gate is connected to the second node.

[0057] See for example Fig.12As shown, the first control unit 01 may include a fourth transistor M4, the source of which receives the input signal IN, the drain of which is connected to the first node N1, and the gate of which receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain of which is connected to the fourth node N4, and the gate of which is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain of which is connected to the fifth node N5, and the gate of which is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain of which is connected to the fourth node N4, and the gate of which receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain of which is connected to the second node N2, and the gate of which is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain of which is connected to the second node N2, and the gate of which receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11 and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2.

[0058] Optionally, the capacitance value of the first capacitor C1 is less than the capacitance value of the third capacitor C3, or the capacitance value of the first capacitor C1 is less than the capacitance value of the fourth capacitor C4. Since the first capacitor C1 is used to control the pull-down of the potential of the third node N3, the smaller the capacitance, the faster the pull-down speed of the potential of the third node N3, and the easier it is to improve the effect of reducing the tailing phenomenon. Therefore, the first capacitor C1 is set to be less than the capacitance value of the third capacitor C3, or less than the capacitance value of the fourth capacitor C4. The third capacitor C3 is mainly used to stabilize the potential of the fourth node N4, and the fourth capacitor C4 is used to stabilize the potential of the second node N2, so the third capacitor C3 and the fourth capacitor C4 are set to have a larger capacitance value than the first capacitor C1.

[0059] The specific implementation principle of the present invention is described in detail below through several specific shift register circuit structure examples. Fig.13 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.13As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3 and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11 and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 also includes a first transistor M1, the source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. In this embodiment, the first clock signal, the first control signal A1 and the second control signal A2 are the same signal. In the first time period, the first control signal A1 is a low level signal, and the second control signal A2 controls the first transistor M1 to turn on. Fig.14 for Fig.13 The timing diagram of the circuit structure shown below. Fig.13 as well as Fig.14 Provide a detailed introduction.

[0060] The first stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the fourth transistor M4 is turned on, the first node N1 is at a high level, and the third node N3 is at a high level. The seventh transistor M7 is turned on, and the fourth node N4 is at a low level. The second clock signal CK2 is at a high level, the second node N2 remains at a high level, the eleventh transistor M11 is turned off, and the output signal OUT remains at a low level.

[0061] The second stage T2: the input signal IN is at a high level, the first clock signal CK1 is at a high level, the fourth transistor M4 is turned off, the first node N1 is kept at a high level, and the third node N3 is kept at a high level. The fourth node N4 is kept at a low level, the second clock signal CK2 is at a low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 becomes a low level, the eleventh transistor M11 is turned on, and the output signal OUT becomes a high level.

[0062] The third stage T3: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the seventh transistor M7 is turned on, the fourth node N4 is at a low level, the second clock signal CK2 is at a high level, the sixth transistor M6 is turned on, the fifth node N5 is at a high level, the ninth transistor M9 is turned off, the second node N2 remains at a low level, the eleventh transistor M11 is turned on, and the output signal OUT remains at a high level.

[0063] Fourth stage T4: the input signal IN is low, the first clock signal CK1 is high, the first node N1 remains high, the third node N3 remains high, the fourth node N4 remains low, the second clock signal CK2 is low, the second node N2 is low, and the output signal OUT remains high.

[0064] The fifth stage T5: the input signal IN is at a low level, the first clock signal CK1 is at a low level, and the first node N1 is at a low level. In the first time period X1, the first transistor M1 is turned on, and the first capacitor C1 is quickly charged, so that the potential of the third node N3 quickly drops to the first low-level signal V1. The fourth node N4 is at a low level, the second clock signal CK2 is at a high level, and the second node N2 is at a high level. Since the first low-level signal V1 is lower than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is lower than the source potential of the tenth transistor M10, so the tenth transistor M10 can quickly tend to a saturated state, the tenth transistor M10 is turned on, and the eleventh transistor M11 is turned off, and the output signal OUT of the shift register is basically consistent with the first voltage signal Vgl, avoiding the tailing phenomenon of the output signal.

[0065] Fig.15 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.15 As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3 and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11 and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 also includes a first transistor M1, a source of the first transistor M1 receives a first control signal A1, a drain is connected to the second plate of the first capacitor C1, and a gate receives a second control signal A2. In this embodiment, the second control signal A2 is a signal of the first node N1. The first clock signal CK1 and the first control signal A1 are the same signal. In the first time period, the first control signal A1 is a low level signal, and the second control signal A2 controls the first transistor M1 to turn on. Fig.16 for Fig.15 The timing diagram of the circuit structure shown below. Fig.15 as well as Fig.16 Provide a detailed introduction.

[0066] The first stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the third node N3 is at a high level, the seventh transistor M7 is turned on, and the fourth node N4 is at a low level. The second clock signal CK2 is at a high level, the second node N2 remains at a high level, the eleventh transistor M11 is turned off, and the output signal OUT remains at a low level.

[0067] The second stage T2: the input signal IN is at a high level, the first clock signal CK1 is at a high level, the fourth transistor M4 is turned off, the first node N1 is kept at a high level, and the third node N3 is kept at a high level. The fourth node N4 is kept at a low level, the second clock signal CK2 is at a low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 becomes a low level, the eleventh transistor M11 is turned on, and the output signal OUT becomes a high level.

[0068] The third stage T3: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the seventh transistor M7 is turned on, the fourth node N4 is at a low level, the second clock signal CK2 is at a high level, the sixth transistor M6 is turned on, the fifth node N5 is at a high level, the ninth transistor M9 is turned off, the second node N2 remains at a low level, the eleventh transistor M11 is turned on, and the output signal OUT remains at a high level.

[0069] Fourth stage T4: the input signal IN is low, the first clock signal CK1 is high, the first node N1 remains high, the third node N3 remains high, the fourth node N4 remains low, the second clock signal CK2 is low, the second node N2 is low, and the output signal OUT remains high.

[0070] The fifth stage T5: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the first node N1 is at a low level, the gate of the first transistor M1 is connected to the first node N1, and in the first time period X1, the first transistor M1 is turned on, the first capacitor C1 is quickly charged, and the potential of the third node N3 is rapidly reduced to the first low-level signal V1. The fourth node N4 is at a low level, the second clock signal CK2 is at a high level, and the second node N2 is at a high level. Since the first low-level signal V1 is lower than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is lower than the source potential of the tenth transistor M10, so the tenth transistor M10 can quickly tend to a saturated state, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned off, and the output signal OUT of the shift register is substantially consistent with the first voltage signal Vgl, avoiding the tailing phenomenon of the output signal.

[0071] Fig.17A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.17 As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3 and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11 and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, a first transistor M1 and a second capacitor C2. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, that is, the second control signal A2 is a potential signal of the first node N1. In this embodiment, the first clock signal CK1 and the first control signal A1 are the same signal. In the first time period, the first control signal A1 is a low level signal, and the second control signal A2 controls the first transistor M1 to turn on. Fig.18 for Fig.17 The timing diagram of the circuit structure shown below. Fig.17 as well as Fig.18 Provide a detailed introduction.

[0072] The first stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the third node N3 is at a high level, the seventh transistor M7 is turned on, and the fourth node N4 is at a low level. The second clock signal CK2 is at a high level, the second node N2 remains at a high level, the eleventh transistor M11 is turned off, and the output signal OUT remains at a low level.

[0073] The second stage T2: the input signal IN is at a high level, the first clock signal CK1 is at a high level, the fourth transistor M4 is turned off, the first node N1 is kept at a high level, and the third node N3 is kept at a high level. The fourth node N4 is kept at a low level, the second clock signal CK2 is at a low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 becomes a low level, the eleventh transistor M11 is turned on, and the output signal OUT becomes a high level.

[0074] The third stage T3: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the seventh transistor M7 is turned on, the fourth node N4 is at a low level, the second clock signal CK2 is at a high level, the sixth transistor M6 is turned on, the fifth node N5 is at a high level, the ninth transistor M9 is turned off, the second node N2 remains at a low level, the eleventh transistor M11 is turned on, and the output signal OUT remains at a high level.

[0075] Fourth stage T4: the input signal IN is low, the first clock signal CK1 is high, the first node N1 remains high, the third node N3 remains high, the fourth node N4 remains low, the second clock signal CK2 is low, the second node N2 is low, and the output signal OUT remains high.

[0076] The fifth stage T5: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the first node N1 is at a low level, and in the first time period X1, the gate of the first transistor M1 is connected to the first node N1, so the first transistor M1 is turned on, and the first capacitor C1 is quickly charged, so that the potential of the third node N3 is rapidly reduced to the first low-level signal V1. The fourth node N4 is at a low level, the second clock signal CK2 is at a high level, and the second node N2 is at a high level. Since the first low-level signal V1 is lower than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is lower than the source potential of the tenth transistor M10, so the tenth transistor M10 can quickly tend to a saturated state, the tenth transistor M10 is turned on, and the eleventh transistor M11 is turned off, and the output signal OUT of the shift register is basically consistent with the first voltage signal Vgl, avoiding the tailing phenomenon of the output signal. The fourth control unit 04 implemented in the present invention is provided with a second capacitor C2, which can stabilize the potential of the first node N1 through the second voltage signal Vgh and the second capacitor C2 to prevent the floating potential of the first node N1 from affecting the potential of the third node N3, thereby affecting the output signal OUT of the shift register.

[0077] Fig.19 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.19As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3 and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11 and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, a first transistor M1, a second capacitor C2 and a second transistor M2. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, that is, the second control signal A2 is a potential signal of the first node N1. The source of the second transistor M2 is connected to the first node N1, the drain is connected to the third node N3, and the gate receives the first control signal A1. In the first time period, the first control signal A1 controls the second transistor M2 to turn on. In the first time period, the first control signal A1 is a low level signal, and the second control signal A2 controls the first transistor M1 to turn on. Fig. 20 for Fig.19 The timing diagram of the circuit structure shown below. Fig.19 as well as Fig. 20 Provide a detailed introduction.

[0078] The first stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the fourth node N4 is at a low level, the first control signal A1 is at a high level, the second transistor M2 is turned off, the third node N3 remains at a low level, the second node N2 is at a high level, and the output signal OUT is at a low level.

[0079] Second stage T2: the input signal IN is high, the first control signal A1 is low, the second clock signal CK2 is high, the first node N1 is high, the second transistor M2 is turned on, the third node N3 is high, the fourth node N4 is low, the second node N2 is high, and the output signal OUT remains low.

[0080] The third stage T3: the input signal IN is at a high level, the second clock signal CK2 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 becomes a low level, the eleventh transistor M11 is turned on, and the output signal OUT is at a high level.

[0081] Fourth stage T4: the input signal IN is high, the second clock signal CK2 is high, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, and the output signal OUT remains high.

[0082] Fifth stage T5: the input signal IN is low, the first clock signal CK1 is high, the first control signal A1 is high, the second clock signal CK2 is low, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, and the output signal OUT remains high.

[0083] The sixth stage T6: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a low level, the fifth transistor M5 is turned on, the fourth node N4 is at a low level, the first control signal A1 is at a high level, the second transistor M2 is turned off, and the third node N3 is at a high level. Since the eighth transistor M8 is turned on, the second node N2 becomes a high level, the tenth transistor M10 and the eleventh transistor M11 are turned off, and the output signal OUT remains at a high level.

[0084] The seventh stage T7: the input signal IN is at a low level, the first control signal A1 is at a low level, the first node N1 is at a low level, and in the first time period X1, since the first capacitor C1 is quickly charged, the potential of the first node N1 is pulled down to the potential of the first low-level signal V1, the potential of the first low-level signal V1 is less than the potential of the first voltage signal Vgl, the second transistor M2 is turned on, and therefore the potential of the third node N3 is the potential of the first low-level signal V1. The fourth node N4 and the second node N2 are both at a high level, the eleventh transistor M11 is turned off, and since the potential of the third node N3 is less than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is less than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly tend to a saturated state, the tenth transistor M10 is turned on, and the output signal OUT of the shift register is substantially consistent with the first voltage signal Vgl, avoiding the tailing phenomenon of the output signal.

[0085] Fig.21 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.21As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3 and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11 and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 also includes a first transistor M1, the source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. In this embodiment, the second control signal A2 is a signal of the first node N1. In the first time period, the first control signal A1 is a low-level signal, and the second control signal A2 controls the first transistor M1 to turn on. In addition, the fourth control unit 04 also includes a second transistor M2, the source of the second transistor M2 is connected to the first node N1, the drain is connected to the third node N3, and the gate receives the first control signal A1; in the first time period, the first control signal A1 controls the second transistor M2 to turn on. Fig. 22 for Fig.21 The timing diagram of the circuit structure shown below. Fig.21 as well as Fig. 22 Provide a detailed introduction.

[0086] The first stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the first control signal A1 is at a high level, the second transistor M2 is turned off, the third node N3 maintains a low potential, the seventh transistor M7 is turned on, the fourth node N4 is at a low level. The second node N2 is at a high level, the eleventh transistor M11 is turned off, the tenth transistor M10 is turned on, and the output signal OUT is at a low level.

[0087] The second stage T2: the input signal IN is at a high level, the first clock signal CK1 is at a high level, the first control signal A1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a high level, the second transistor M2 is turned on, and the third node N3 is at a high level; the fourth node N4 is at a low level, the second node N2 is at a high level, and the output signal OUT remains at a low level.

[0088] The third stage T3: the input signal IN is at a high level, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the first control signal A1 is at a high level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 is at a low level, the eleventh transistor M11 is turned on, and the output signal OUT is at a high level.

[0089] Fourth stage T4: the input signal IN is high, the second clock signal CK2 is high, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, and the output signal OUT remains high.

[0090] Fifth stage T5: the input signal IN is low level, the second clock signal CK2 is low level, the first node N1 is high level, the third node N3 is high level, the fourth node N4 is low level, the second node N2 is low level, and the output signal OUT remains high level.

[0091] The sixth stage T6: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a low level, the fourth node N4 is at a low level, the first control signal A1 is at a high level, the second transistor M2 is turned off, and the third node N3 is at a high level. Since the eighth transistor M8 is turned on, the second node N2 becomes a high level, the tenth transistor M10 and the eleventh transistor M11 are turned off, and the output signal OUT remains at a high level.

[0092] The seventh stage T7: the input signal IN is at a low level, the first control signal A1 is at a low level, and in the first time period X1, since the first capacitor C1 is quickly charged, the potential of the first node N1 is pulled down to the potential of the first low-level signal V1, the potential of the first low-level signal V1 is less than the potential of the first voltage signal Vgl, the second transistor M2 is turned on, and therefore the potential of the third node N3 is the potential of the first low-level signal V1. The fourth node N4 is at a high level, the second node N2 is at a high level, the eleventh transistor M11 is turned off, and since the potential of the third node N3 is less than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is less than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly approach the saturation state, the tenth transistor M10 is turned on, and the output signal OUT of the shift register is substantially consistent with the first voltage signal Vgl, avoiding the tailing phenomenon of the output signal.

[0093] Fig.23 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.23As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3 and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11 and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 also includes a first transistor M1, the source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. In this embodiment, the first control signal A1 and the second control signal A2 are the same signal. In the first time period, the first control signal A1 is a low level signal, and the second control signal A2 controls the first transistor M1 to turn on. Fig.24 for Fig.23 The timing diagram of the circuit structure shown below. Fig.23 as well as Fig.24 Provide a detailed introduction.

[0094] The first stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the seventh transistor M7 is turned on, the fourth node N4 is at a low level, the first control signal A1 is at a high level, the third node N3 maintains a low potential, the second node N2 is at a high level, the eleventh transistor M11 is turned off, and the output signal OUT maintains an output low level.

[0095] Second stage T2: the input signal IN is high, the first control signal A1 is low, the second clock signal CK2 is high, the first node N1 is high, the fourth node N4 is low, the second transistor M2 is turned on, the third node N3 is high, the second node N2 is high, and the output signal OUT remains low.

[0096] The third stage T3: the input signal IN is high, the second clock signal CK2 is low, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, the eleventh transistor M11 is turned on, and the output signal OUT is high.

[0097] Fourth stage T4: the input signal IN is high, the second clock signal CK2 is high, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, and the output signal OUT remains high.

[0098] Fifth stage T5: the input signal IN is low level, the second clock signal CK2 is low level, the first node N1 is high level, the third node N3 is high level, the fourth node N4 is low level, the second node N2 is low level, and the output signal OUT remains high level.

[0099] The sixth stage T6: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a low level, the fourth node N4 is at a low level, the first control signal A1 is at a high level, the second transistor M2 is turned off, and the third node N3 is at a high level. Since the eighth transistor M8 is turned on, the second node N2 becomes a high level, the tenth transistor M10 and the eleventh transistor M11 are turned off, and the output signal OUT remains at a high level.

[0100] The seventh stage T7: the input signal IN is at a low level, the first control signal A1 is at a low level, and in the first time period X1, since the first capacitor C1 is quickly charged, the potential of the first node N1 is pulled down to the potential of the first low-level signal V1, the potential of the first low-level signal V1 is less than the potential of the first voltage signal Vgl, the second transistor M2 is turned on, and therefore the potential of the third node N3 is the potential of the first low-level signal V1. The fourth node N4 is at a high level, the second node N2 is at a high level, the eleventh transistor M11 is turned off, and since the potential of the third node N3 is less than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is less than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly approach the saturation state, the tenth transistor M10 is turned on, and the output signal OUT of the shift register is substantially consistent with the first voltage signal Vgl, avoiding the tailing phenomenon of the output signal.

[0101] Fig.25 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.25As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3 and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11 and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, a first transistor M1, a second capacitor C2 and a third transistor M3. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, that is, the second control signal A2 is a potential signal of the first node N1. The source of the third transistor M3 receives the second voltage signal Vgh, the drain is connected to the third node N3, and the gate is connected to the second node N2; in this embodiment, the first clock signal CK1 and the first control signal A1 are the same signal. In the first time period X1, the first control signal A1 is a low level signal, the second control signal A2 controls the first transistor M1 to turn on, and the second node N2 controls the third transistor M3 to turn off. Fig.25 The timing of the circuit structure shown can be seen, for example, in Fig.18 The introduction, compared to Fig.17 as well as Fig.18In the scheme shown, the present invention can use the potential of the second node N2 to control the potential of the third node N3, ensuring that the signal of the third node N3 is stable at a high level. Because each clock signal will undergo multiple jumps, it is possible to cause the potential of the first node N1 and the third node N3 to float during the jump. The embodiment of the present invention sets a third transistor M3. When the second node N2 is at a low level, the third transistor M3 is turned on to control the third node to be stable at a high level. Before the second node N2 becomes a high level, the third transistor M3 is turned off, and the level of the third node N3 does not change. Only when the second node N2 node becomes a high level, the third node N3 becomes a potential lower than the first voltage signal Vgl, thereby reducing the tailing phenomenon.

[0102] Optionally, the first control signal and the first clock signal are pulse signals of different timings, and the first control signal and the second clock signal are pulse signals of different timings; wherein the effective pulses of the first clock signal, the first control signal and the second clock signal are generated in sequence. For example, see Fig. 20 , Fig. 22 as well as Fig.24 shown.

[0103] Optionally, the duration of the effective pulse of the first clock signal is less than or equal to the duration of the effective pulse of the second clock signal, and the duration of the effective pulse of the first control signal is less than or equal to the duration of the effective pulse of the second clock signal. Fig. 20 , Fig. 22 as well as Fig.24 shown.

[0104] Optionally, the time length of the effective pulse of the first control signal is less than or equal to the time length of the effective pulse of the first clock signal. Since the first clock signal needs to participate in the driving process of the first control unit, the second control unit, and the third control unit, and the first control signal only needs to control the fourth control unit, in order to save the time of the effective pulse and save power consumption, the time length of the effective pulse of the first control signal can be set to be less than or equal to the time length of the effective pulse of the first clock signal.

[0105] Optionally, the sum of the time lengths of the effective pulse of the first clock signal and the effective pulse of the first control signal is equal to or greater than the time length of the effective pulse of the second clock signal. The first clock signal and the first control signal jointly control the potential change of the first node and the third node N3, and the second clock signal controls the potential change of the second node N2. In some embodiments of the present invention, the sum of the effective pulses of the first clock signal and the first control signal can be set to be equal to the effective pulse of the second clock signal. In order to fully ensure that the potential of the third node N3 is pulled down in at least the first time period when the first node is at a low potential, the effective pulse time of the first control signal can be appropriately increased to ensure that the output signal of the shift register has no tailing phenomenon.

[0106] Optionally, the effective pulse of the first clock signal and the effective pulse of the first control signal at least partially overlap. The effective pulse of the first clock signal and the effective pulse of the first control signal may partially overlap, and under the premise that the driving period remains unchanged, the effective pulse of the first clock signal and the effective pulse of the first control signal may be appropriately increased to ensure stable control of the potentials of the first node and the third node.

[0107] Optionally, the start time of the effective pulse of the first clock signal is earlier than the start time of the effective pulse of the first control signal; the end time of the effective pulse of the first clock signal is earlier than or the same as the end time of the effective pulse of the first control signal. Since it is necessary to continue to pull down the potential of the first node N1 through the fourth control unit 04 after the first node N1 changes from a high level to a low level, it is necessary for the start time of the effective pulse of the first clock signal to be earlier than the start time of the effective pulse of the first control signal. The embodiment of the present invention sets the end time of the effective pulse of the first clock signal to be earlier than or the same as the end time of the effective pulse of the first control signal, which can ensure that the fourth control unit continues to control the potential of the third node N3 to be pulled down in at least the first time period when the potential of the first node is at a low level. If the end time of the effective pulse of the first clock signal is later than the end time of the effective pulse of the first control signal, it is possible to make the potential of the third node return to the potential before the potential of the first node is pulled down.

[0108] Optionally, according to actual product requirements, it can be set that there is no overlap between the valid pulse of the first control signal and the valid pulse of the first clock signal, for example Fig. 20 , Fig. 22 and Fig.24 .

[0109] Optionally, during the shifting process from the input signal to the output signal, the invalid pulse of the input signal is started earlier than the valid pulse of the first clock signal by a first interval time, and the valid pulse of the first clock signal is started earlier than the valid pulse of the first control signal by a second interval time; wherein the first interval time is equal to the second interval time. For example, see Fig. 20 , the invalid pulse of the input signal IN is at a high level, and the start time of the invalid pulse of the input signal IN is earlier than the start time of the valid pulse (low level) of the first clock signal CK1 by the first interval time t1. The start time of the valid pulse (low level) of the first clock signal CK1 is earlier than the start time of the valid pulse of the first control signal A1 by the second interval time t2. Due to the addition of the control of the first control signal A1, the output signal OUT changes from a high level to a low level only at the start time of the valid pulse of the first control signal A1, and the falling edge of the output signal OUT is delayed by the second interval time t2, which is the difference between the start time of the valid pulse (low level) of the first clock signal CK1 and the start time of the valid pulse of the first control signal A1. Therefore, the rising edge of the input signal IN is earlier than the falling edge of the first clock signal CK1 by the first time interval t1, and the first time interval t1 is equal to the second time interval t2, ensuring that the invalid pulse widths of the input signal IN and the output signal OUT are equal and the waveforms are consistent.

[0110] Optionally, during the first time period, the second clock signal outputs an invalid pulse. Fig. 20 In the embodiment of the present invention, within the first time period X1 before the second clock signal CK2 outputs a valid pulse (low level), the third node N3 is quickly pulled down to a potential lower than the first voltage signal Vgl, thereby eliminating the tailing phenomenon as much as possible.

[0111] Optionally, the time period during which the first node receives the low-level signal also includes a second time period X2, during the first time period X1, the potential of the third node is a first low-level signal, and during the second time period X2, the potential of the third node is a high-level signal. Fig. 20 , Fig. 22 as well as Fig.24 In the second time period X2, when the first clock signal CK1 is at a low level and the first control signal A1 is at a high level, the third node N3 is still a high level signal. In the first time period X1 after the first control signal A1 becomes low level, the third node N3 is pulled down to a potential lower than the first voltage signal Vgl, thereby eliminating the tailing phenomenon.

[0112] Based on the above inventive concept, an embodiment of the present invention further provides a display device. The display device includes the display panel described in any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be repeated here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, which is not limited in the embodiment of the present invention. Exemplarily, Fig.26 Schematic diagram of a display device provided by an embodiment of the present invention. Fig.26 As shown, the display device includes the display panel 100 in the above embodiment.

[0113] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A driving circuit, the driving circuit comprising N stages of shift registers cascaded to each other, N≥2; The shift register comprises: a first control unit that receives an input signal and controls a signal of a first node in response to a first clock signal; a second control unit, the second control unit receiving the first voltage signal and the second voltage signal, and controlling the signal of the second node in response to the signal of the first node, the first clock signal, and the second clock signal; a third control unit, the third control unit receiving the first voltage signal and responding to a signal of a third node, or receiving the second voltage signal and responding to a signal of the second node to generate an output signal, wherein the third node is connected to the first node, the first voltage signal is a low level signal, and the second voltage signal is a high level signal; A fourth control unit, the fourth control unit includes a first capacitor and a first transistor, the first plate of the first capacitor is connected to the third node, the second plate is connected to the drain of the first transistor, the source of the first transistor receives a first control signal, and the gate of the first transistor receives a second control signal; wherein, During at least a first time period when the first node is a low level signal, the second control signal controls the first transistor to be turned on.

2. The display panel according to claim 1, characterized in that: The second control signal is the same signal as the signal received by the first plate of the first capacitor.

3. The display panel according to claim 1, characterized in that: The second control signal is a signal of the first node.

4. The display panel according to claim 1, characterized in that: The first clock signal and the first control signal are the same signal.

5. The display panel according to claim 1, characterized in that: The first control signal and the second control signal are the same signal.

6. The display panel according to claim 1, characterized in that: During the first time period, the first control signal is a low level signal.

7. The display panel according to claim 1, characterized in that: The first control signal and the first clock signal are pulse signals with different timing sequences.

8. The display panel according to claim 1, characterized in that: The duration of the effective pulse of the first control signal is less than or equal to the duration of the effective pulse of the first clock signal.

9. The display panel according to claim 1, characterized in that: The valid pulse of the first clock signal at least partially overlaps with the valid pulse of the first control signal, or, There is no overlap between the valid pulse of the first control signal and the valid pulse of the first clock signal.

10. The display panel according to claim 1, characterized in that: The fourth control unit further includes a second capacitor, a first plate of the second capacitor is connected to the gate of the first transistor, and a second plate receives the second voltage signal.

11. The display panel according to claim 10, characterized in that: The capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.

12. The display panel according to claim 1, characterized in that: The fourth control unit further includes a second transistor, the source of the second transistor is connected to the first node, and the drain is connected to the third node; wherein, During the first time period, the second transistor is turned on.

13. The display panel according to claim 1, characterized in that: The first control unit comprises: a fourth transistor, wherein a source of the fourth transistor receives the input signal, a drain of the fourth transistor is connected to the first node, and a gate of the fourth transistor receives the first clock signal; The second control unit comprises: a fifth transistor, wherein a source of the fifth transistor receives the first clock signal, a drain of the fifth transistor is connected to the fourth node, and a gate of the fifth transistor is connected to the first node; a sixth transistor, wherein a source of the sixth transistor receives the second clock signal, a drain of the sixth transistor is connected to the fifth node, and a gate of the sixth transistor is connected to the fourth node; a seventh transistor, wherein a source of the seventh transistor receives the first voltage signal, a drain of the seventh transistor is connected to the fourth node, and a gate of the seventh transistor receives the first clock signal; an eighth transistor, wherein a source of the eighth transistor receives the second voltage signal, a drain of the eighth transistor is connected to the second node, and a gate of the eighth transistor is connected to the first node; a ninth transistor, wherein a source of the ninth transistor is connected to the fifth node, a drain of the ninth transistor is connected to the second node, and a gate of the ninth transistor receives the second clock signal; a third capacitor, wherein a first electrode plate of the third capacitor is connected to the fourth node, and a second electrode plate of the third capacitor is connected to the fifth node; a fourth capacitor, wherein a first plate of the fourth capacitor receives the second voltage signal, and a second plate of the fourth capacitor is connected to the second node; The third control unit comprises: a tenth transistor, wherein a source of the tenth transistor receives the first voltage signal, a drain of the tenth transistor outputs an output signal, and a gate of the tenth transistor is connected to the third node; An eleventh transistor, wherein a source of the eleventh transistor receives the second voltage signal, a drain outputs an output signal, and a gate is connected to the second node.

14. The display panel according to claim 13, characterized in that: The capacitance value of the first capacitor is smaller than the capacitance value of the third capacitor, or, The capacitance value of the first capacitor is smaller than the capacitance value of the fourth capacitor.

15. A display device, characterized in that: A display panel comprising any one of claims 1-14.

Images