Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a driving circuit, the driving circuit comprises N-stage shift registers which are cascaded with each other, and the shift registers comprise a first control unit, a second control unit, a third control unit and a fourth control unit. The first control unit receives an input signal and controls a signal of a first node in response to a first clock signal; the second control unit receives a first voltage signal and a second voltage signal, controls a signal of a second node in response to a signal of the first node, the first clock signal and a second clock signal; the third control unit receives the first voltage signal and generates an output signal in response to a signal of a third node, or receives the second voltage signal and generates the output signal in response to a signal of the second node; and the fourth control unit is connected to the third node and controls a potential of the third node to be a first low-level signal in at least a first time period when the signal of the first node is a low-level signal, and the potential of the first low-level signal is lower than that of the first voltage signal.

Description

[0001] This application is a divisional application of application No. 202011621871.7, titled "Display panel and display device", filed on December 31, 2020. TECHNICAL FIELD

[0002] The present application relates to the field of display panels, in particular to a display panel and a display device. BACKGROUND

[0003] In the field of display, in order to realize scanning display or other functions, shift register is often used. However, due to the threshold loss of the voltage of the internal control node of the shift register when it works, the corresponding transistor in the shift register cannot be fully turned on, which causes the level of the output end of the shift register to not reach the target voltage, resulting in a tailing phenomenon, which affects the display effect.

[0004] When the output signal of the PMOS transistor in the shift register jumps from high level to low level, the gate potential of the PMOS transistor is Vgl potential, and the source potential of the PMOS transistor is also Vgl potential, that is, the gate and source of the PMOS transistor are both Vgl potential, and the PMOS transistor works in unsaturated state, which will cause the voltage of the drain output to be |Vgl|-|Vth|, wherein Vth is the threshold voltage of the PMOS transistor.

[0005] Since the voltage of the drain output of the PMOS transistor cannot reach the effect of the predetermined output Vgl, the output pulse signal of the current shift register has a tailing phenomenon when the high level jumps to the low level. SUMMARY

[0006] Embodiments of the present application provide a display panel and a display device to solve the problem of tailing of the output signal of the shift register.

[0007] In a first aspect, embodiments of the present application provide a display panel, comprising:

[0008] a driving circuit, the driving circuit comprising N-stage shift registers cascaded with each other, N≥2;

[0009] the shift register comprises:

[0010] a first control unit, the first control unit being configured to receive an input signal and control the signal of the first node in response to a first clock signal;

[0011] a second control unit, the second control unit being configured to receive a first voltage signal and a second voltage signal, and control the signal of the second node in response to the signal of the first node, the first clock signal and a second clock signal;

[0012] A third control unit is configured to receive the first voltage signal and respond to a signal from a third node, or receive the second voltage signal and respond to a signal from a second node, and generate an output signal, wherein the third node is connected to the first node, the first voltage signal is a low-level signal, and the second voltage signal is a high-level signal;

[0013] A fourth control unit, connected to the third node, is configured to control the potential of the third node to a first low-level signal for at least a first time period during which the first node is a low-level signal, wherein the potential of the first low-level signal is lower than the potential of the first voltage signal.

[0014] Secondly, embodiments of the present invention also provide a display device, including the display panel described in the first aspect.

[0015] The display panel provided in this embodiment of the invention includes a driving circuit, which includes N cascaded shift registers, and the shift registers include a first control unit, a second control unit, a third control unit, and a fourth control unit. The third control unit is used to receive a first voltage signal and respond to a signal from a third node, or to receive a second voltage signal and respond to a signal from a second node, generating an output signal. Since the fourth control unit is connected to the third node, it can control the potential of the third node to be a first low-level signal for at least a first time period while the first node is at a low level. The potential of the first low-level signal is lower than the potential of the first voltage signal, i.e., the potential of the third node is lower than the potential of the first voltage signal, so that the transistors in the third control unit quickly approach saturation and output the first voltage signal, avoiding a trailing problem. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a shift register in the prior art;

[0017] Figure 2 for Figure 1 The timing diagram of the shift register is shown.

[0018] Figure 3 This is a schematic diagram of the structure of the shift register of the display panel provided in an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the structure of a shift register for a display panel provided in an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of the structure of a shift register for a display panel provided in an embodiment of the present invention;

[0021] Figure 6 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0022] Figure 7 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0023] Figure 8 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0024] Figure 9 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0025] Figure 10 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0026] Figure 11 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0027] Figure 12 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0028] Figure 13 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0029] Figure 14 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6; Figure 13 A timing diagram of the circuit structure shown in FIG. 6 is shown in FIG. 7;

[0030] Figure 15 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0031] Figure 16 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6; Figure 15 A timing diagram of the circuit structure shown in FIG. 6 is shown in FIG. 7;

[0032] Figure 17 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0033] Figure 18 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6; Figure 17 A timing diagram of the circuit structure shown in FIG. 6 is shown in FIG. 7;

[0034] Figure 19 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0035] Figure 20 A structure diagram of a shift register of a display panel provided by an embodiment of the present application is shown in FIG. 6; Figure 19 A timing diagram of the circuit structure shown in FIG. 6 is shown in FIG. 7;

[0036] Figure 21 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application;

[0037] Figure 22 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application; Figure 21 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application;

[0038] Figure 23 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application;

[0039] Figure 24 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application; Figure 23 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application;

[0040] Figure 25 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application;

[0041] Figure 26 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The present application will be further described below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are intended to serve only as an example of the present application and are not intended to limit the present application. In addition, it should be noted that only the parts related to the present application are shown in the drawings for the convenience of description.

[0043] Figure 1 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application; Figure 2 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application; Figure 1 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application. Figure 1 FIG. 1 shows a structure diagram of a shift register of a display panel according to an embodiment of the present application. Figure 2 When the shift register needs to realize the jump from high level to low level, transistor P1 needs to be turned off and transistor P2 needs to be turned on. At this time, the gate potential of transistor P2 is Vgl potential, and the source potential of transistor P2 is also Vgl potential, that is, the gate and source of transistor P2 are both Vgl potential, and transistor P2 works in unsaturated state, which will cause the voltage output by the drain of transistor P2 to be ∣Vgl∣-∣Vth∣, where Vth is the threshold voltage of transistor P2. Since the voltage output by the drain of transistor P2 cannot reach the effect of the predetermined output Vgl, as shown in Figure 2 the current output pulse signal of the shift register has a tail phenomenon (as shown by the arrow in Figure 2 ).

[0044] In view of this, embodiments of the present invention provide a display panel including a driving circuit, which includes N cascaded shift registers. N is a positive integer greater than or equal to 2. The driving circuit is used to output pulse signals to the display panel line by line. For example, it outputs scan pulse signals to each scan line of the display panel, or outputs light emission control pulse signals to each row of light emission control signal lines of the display panel. Figure 3 This is a schematic diagram of the shift register structure of the display panel provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the shift register of the display panel provided in this embodiment of the invention includes a first control unit 01, a second control unit 02, a third control unit 03, and a fourth control unit 04. The first control unit 01 receives an input signal IN and controls the signal of the first node N1 in response to a first clock signal CK1. The second control unit 02 receives a first voltage signal Vgl and a second voltage signal Vgh, and controls the signal of the second node N2 in response to the signal of the first node N1, the first clock signal CK1, and the second clock signal CK2. The third control unit 03 receives the first voltage signal Vgl and responds to the signal of the third node N3, or receives the second voltage signal Vgh and responds to the signal of the second node N2, generating an output signal OUT. The third node N3 is connected to the first node N1, the first voltage signal Vgl is a low-level signal, and the second voltage signal Vgh is a high-level signal. This embodiment of the invention also includes a fourth control unit 04, which is connected to the third node N3. During at least a first time period when the first node N1 is a low-level signal, the fourth control unit 04 can control the potential of the third node N3 to be a first low-level signal V1, wherein the potential of the first low-level signal V1 is lower than the potential of the first voltage signal Vgl. Therefore, the gate potential of the transistor controlling the generation of the output signal OUT in the third control unit 03 is lower than the potential of the first voltage signal Vgl, and the source potential is the potential of the first voltage signal Vgl. This causes the transistor controlling the generation of the output signal OUT in the third control unit 03 to quickly approach saturation, making the source voltage and drain voltage of the transistor controlling the generation of the output signal OUT in the third control unit 03 approach equal, thus reducing the trailing phenomenon.

[0045] Optionally, based on the above embodiments, the fourth control unit may further include a first capacitor, the first plate of which is connected to the third node, and the second plate of which receives a first control signal; wherein, during the first time period, the first control signal is a low-level signal. See, for example... Figure 4The fourth control unit 04 is provided with a first capacitor C1, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives a first control signal A1. In the first time period, the first node N1 is at a low level, the first control signal A1 is a low level signal, the first capacitor C1 is rapidly charged, so that the potential of the third node N3 rapidly decreases and is lower than the potential of the first voltage signal Vgl.

[0046] Optionally, for example, referring to Figure 5 The fourth control unit 04 can further include a first transistor M1, a source of the first transistor M1 receives the first control signal A1, a drain is connected to the second plate of the first capacitor C1, and a gate receives a second control signal A2; wherein in the first time period, the second control signal A2 controls the first transistor M1 to be turned on, and the first control signal A1 is transmitted to the first capacitor C1, at this time, the first node N1 is at a low potential. Under the control of the first capacitor C1 and the low level of the first control signal A1, the potential of the third node N3 rapidly decreases and is lower than the potential of the first voltage signal Vgl. Since the third node N3 needs to be kept at a high potential when the third control unit 03 receives the second voltage signal Vgh and generates the output signal OUT in response to the signal of the second node N2. That is, the fourth control module 04 does not need to control the potential of the third node N3 to be less than the potential of the first voltage signal Vgl at all times. Therefore, the embodiment of the present application sets the first transistor M1, so that in the first time period, the first transistor M1 is turned on to control the potential of the third node N3 to be less than the potential of the first voltage signal Vgl, and in other time periods, the first transistor M1 can be turned off to avoid interference with the potential of the third node N3 and affect the output signal of the shift register.

[0047] Optionally, the first control signal and the second control signal can be the same signal. For example, as shown in Figure 6 The source and the gate of the first transistor M1 are electrically connected and both receive the first control signal A1 (or the second control signal A2). In this way, the number of signal lines in the display panel can be reduced.

[0048] Optionally, the first clock signal CK1 and the first control signal A1 can be the same signal. As shown in Figure 7 The embodiment of the present application can further reduce the number of signal lines in the display panel. By adjusting the timing of the shift register, the first clock signal CK1 is ensured to be a low level signal in the first time period, so that the fourth control unit can control the potential of the third node to be the first low level signal, that is, lower than the potential of the first voltage signal Vgl.

[0049] Optionally, the second control signal can be the signal of the first node. As shown in Figure 8As shown, the gate of the first transistor M1 is connected to the first node N1, and thus the second control signal A2 is the signal of the first node N1. When the first node N1 is at a low level, the first transistor M1 is turned on, and the first control signal A1 is transmitted to the first capacitor C1, thereby controlling the potential of the third node N3 to be lower than the potential of the first voltage signal Vgl in the first time period.

[0050] Optionally, the fourth control unit in the embodiment of the present application can further include a second capacitor, the first plate of the second capacitor is connected to the gate of the first transistor, and the second plate receives a second voltage signal. For example, as shown in Figure 9 As shown, the fourth control unit 04 includes a second capacitor C2, the first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives a second voltage signal Vgh. When the second control signal A2 is the signal of the first node N1, the embodiment of the present application can stabilize the potential of the first node N1 by the second voltage signal Vgh and the second capacitor C2, thereby avoiding the influence of the floating potential of the first node N1 on the potential of the third node N3.

[0051] Optionally, the capacitance of the first capacitor is smaller than the capacitance of the second capacitor. Since the first capacitor C1 is used to control the pull-down of the third node potential, according to the relationship U=Q / C among the capacitance C, the charge Q, and the voltage U, it can be known that, in the case of the same charge, if the voltage is to be rapidly decreased, a smaller capacitance value is needed, and the smaller the capacitance is, the faster the pull-down speed of the third node potential is, and thus the effect of reducing the tailing phenomenon is more easily improved. Therefore, the first capacitor C1 needs a smaller capacitance value. The second capacitor C2 is mainly used to stabilize the potentials of the first node N1 and the third node N3, and thus the second capacitor C2 needs a larger capacitance value to avoid too much change of the potential of the first node N1 in the process of charging and discharging of the capacitor, thereby improving the stability of the node potential. Therefore, the embodiment of the present application sets the capacitance of the first capacitor to be smaller than the capacitance of the second capacitor.

[0052] Optionally, the fourth control unit can further include a second transistor, the source of the second transistor is connected to the first node, the drain is connected to the third node, and the gate receives the first control signal; wherein in the first time period, the first control signal controls the second transistor to be turned on. For example, as shown in Figure 10As shown in the figure, the fourth control unit 04 comprises a first capacitor C1, a first transistor M1 and a second transistor M2. The source of the first transistor M1 receives a first control signal A1, the drain is connected to a third node N3, and the gate receives a second control signal A2; the first capacitor is located between the drain of the first transistor M1 and the third node N3. In the first time period, the second control signal A2 controls the first transistor M1 to be turned on, and in the first time period, the first control signal A1 is a low-level signal. The source of the second transistor M2 is connected to the first node N1, the drain is connected to the third node N3, and the gate receives the first control signal A1; wherein in the first time period, the first control signal A1 controls the second transistor M2 to be turned on.

[0053] If the potential of the first node N1 is transmitted to the third node N3 before the first control signal A1 has not fallen to a low level, the tailing problem of the shift register cannot be avoided. The embodiment of the present application sets the second transistor M2 between the first node N1 and the third node N3, because the gate of the second transistor M2 receives the first control signal A1, only when the first control signal A1 is low and the first transistor M1 is turned on, the second transistor M2 is also turned on, thereby realizing the pull-down of the potential of the third node N3, and preventing the potential of the first node N1 from being directly transmitted to the third control unit 03 without the pull-down action of the fourth control unit 04, thereby generating the tailing problem of the output signal.

[0054] Optionally, the fourth control unit can further comprise a third transistor, the source of the third transistor receives a second voltage signal, the drain is connected to the third node, and the gate is connected to the second node; wherein in the first time period, the second node controls the third transistor to be turned off. For example, as shown in the figure, Figure 11 As shown in the figure, the fourth control unit 04 comprises a first capacitor C1, a first transistor M1 and a third transistor M3. The source of the first transistor M1 receives a first control signal A1, the drain is connected to a third node N3, and the gate receives a second control signal A2; the first capacitor is located between the drain of the first transistor M1 and the third node N3. In the first time period, the second control signal A2 controls the first transistor M1 to be turned on, and in the first time period, the first control signal A1 is a low-level signal. The source of the third transistor M3 receives a second voltage signal Vgh, the drain is connected to the third node N3, and the gate is connected to the second node N2; wherein in the first time period, the second node N2 controls the third transistor M3 to be turned off.

[0055] Because each clock signal in the shift register will undergo multiple jumps, the potentials of the first node N1 and the third node N3 will be floating during the jumps. The embodiment of the present application sets the third transistor M3 to control the potential of the third node N3 by the potential of the second node N2, and ensures the signal stability of the third node N3 when it is at a high level. For example, if the shift register needs to output a high level (the second voltage signal Vgh), the second node N2 is at a low potential, and the third node N3 needs to maintain a stable high potential. The embodiment of the present application sets the third transistor M3, the gate of which is connected to the second node N2, and the second node N2 is at a low potential, so that the third transistor M3 is turned on to make the third node N3 maintain a high potential of the second voltage signal Vgh, and ensure that the level of the third node N3 does not change until the second node N2 becomes a high level. Only when the second node N2 becomes a high level, the third node N3 becomes a low level signal lower than the first voltage signal Vgl, so as to weaken the tailing phenomenon.

[0056] Optionally, the first control unit can include a fourth transistor, the source of which is connected to the input signal, the drain is connected to the first node, and the gate receives the first clock signal. The second control unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a third capacitor and a fourth capacitor. The source of the fifth transistor receives the first clock signal, the drain is connected to the fourth node, and the gate is connected to the first node. The source of the sixth transistor receives the second clock signal, the drain is connected to the fifth node, and the gate is connected to the fourth node. The source of the seventh transistor receives the first voltage signal, the drain is connected to the fourth node, and the gate receives the first clock signal. The source of the eighth transistor receives the second voltage signal, the drain is connected to the second node, and the gate is connected to the first node. The source of the ninth transistor is connected to the fifth node, the drain is connected to the second node, and the gate receives the second clock signal. The first plate of the third capacitor is connected to the fourth node, and the second plate is connected to the fifth node. The first plate of the fourth capacitor receives the second voltage signal, and the second plate is connected to the second node. The third control unit includes a tenth transistor and an eleventh transistor, and the fourth capacitor. The source of the tenth transistor receives the first voltage signal, the drain outputs the output signal, and the gate is connected to the third node. The source of the eleventh transistor receives the second voltage signal, the drain outputs the output signal, and the gate is connected to the second node.

[0057] For example, refer to Figure 12As shown, the first control unit 01 can include a fourth transistor M4, the source of the fourth transistor M4 receiving the input signal IN, the drain connected to the first node N1, and the gate receiving the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and the fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2.

[0058] Optionally, the capacitance value of the first capacitor C1 is smaller than the capacitance value of the third capacitor C3, or the capacitance value of the first capacitor C1 is smaller than the capacitance value of the fourth capacitor C4. Since the first capacitor C1 is used to control the pull-down of the third node N3 potential, the smaller the capacitance, the faster the pull-down speed of the third node N3 potential, and the easier it is to improve the effect of reducing the tailing phenomenon. Therefore, the first capacitor C1 is set to be smaller than the capacitance value of the third capacitor C3 or the capacitance value of the fourth capacitor C4. The third capacitor C3 is mainly used to stabilize the potential of the fourth node N4, and the fourth capacitor C4 is used to stabilize the potential of the second node N2. Therefore, the capacitance value of the third capacitor C3 and the fourth capacitor C4 is set to be larger than that of the first capacitor C1.

[0059] The specific implementation principles of the present application will be described in detail below through several specific shift register circuit structure examples. Figure 13 Another circuit structure diagram of a shift register provided by an embodiment of the present application is shown in FIG. 4. Figure 13As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 further includes a first transistor M1, the source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. In this embodiment, the first clock signal, the first control signal A1, and the second control signal A2 are the same signal. In the first time period, the first control signal A1 is a low-level signal, and the second control signal A2 controls the first transistor M1 to be turned on. Figure 14 For Figure 13 the timing diagram of the circuit structure shown. Below, reference Figure 13 and Figure 14 will be made to detailed introduction.

[0060] The first stage T1: the input signal IN is high level, the first clock signal CK1 is low level, the fourth transistor M4 is turned on, the first node N1 is high level, and the third node N3 is high level. The seventh transistor M7 is turned on, and the fourth node N4 is low level. The second clock signal CK2 is high level, the second node N2 keeps high level, the eleventh transistor M11 is disconnected, and the output signal OUT keeps low level.

[0061] The second stage T2: the input signal IN is high level, the first clock signal CK1 is high level, the fourth transistor M4 is disconnected, the first node N1 keeps high level, and the third node N3 keeps high level. The fourth node N4 keeps low level, the second clock signal CK2 is low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 becomes low level, the eleventh transistor M11 is turned on, and the output signal OUT becomes high level.

[0062] The third stage T3: the input signal IN is high level, the first clock signal CK1 is low level, the first node N1 is high level, the third node N3 is high level, the seventh transistor M7 is turned on, the fourth node N4 is low level, the second clock signal CK2 is high level, the sixth transistor M6 is turned on, the fifth node N5 is high level, the ninth transistor M9 is disconnected, the second node N2 keeps low level, the eleventh transistor M11 is turned on, and the output signal OUT keeps high level.

[0063] The fourth stage T4: the input signal IN is low level, the first clock signal CK1 is high level, the first node N1 keeps high level, the third node N3 keeps high level, the fourth node N4 keeps low level, the second clock signal CK2 is low level, the second node N2 is low level, and the output signal OUT keeps high level.

[0064] The fifth stage T5: the input signal IN is low level, the first clock signal CK1 is low level, and the first node N1 is low level. In the first time period X1, the first transistor M1 is turned on, the first capacitor C1 is rapidly charged, the potential of the third node N3 rapidly decreases to the first low level signal V1. The fourth node N4 is low level, the second clock signal CK2 is high level, and the second node N2 is high level. Since the first low level signal V1 is lower than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is less than the source potential of the tenth transistor M10, so the tenth transistor M10 can rapidly tend to be in a saturated state, the tenth transistor M10 is turned on, the eleventh transistor M11 is disconnected, the output signal OUT of the shift register is basically consistent with the first voltage signal Vgl, and the tailing phenomenon of the output signal is avoided.

[0065] Figure 15 Another circuit structure schematic diagram of a shift register provided by the embodiment of the present application is as follows:Figure 15 As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 also includes a first transistor M1, the source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. The second control signal A2 in this embodiment is the signal of the first node N1. The first clock signal CK1 and the first control signal A1 are the same signal. In the first time period, the first control signal A1 is a low-level signal, and the second control signal A2 controls the first transistor M1 to be turned on. Figure 16 For Figure 15 The timing diagram of the circuit structure as shown. Below, reference Figure 15 And Figure 16 will be described in detail.

[0066] The first stage T1: the input signal IN is high, the first clock signal CK1 is low, the fourth transistor M4 is turned on, the first node N1 is high, the third node N3 is high, the seventh transistor M7 is turned on, and the fourth node N4 is low. The second clock signal CK2 is high, the second node N2 remains high, the eleventh transistor M11 is disconnected, and the output signal OUT remains low.

[0067] The second stage T2: the input signal IN is high, the first clock signal CK1 is high, the fourth transistor M4 is disconnected, the first node N1 remains high, and the third node N3 remains high. The fourth node N4 remains low, the second clock signal CK2 is low, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 becomes low, the eleventh transistor M11 is turned on, and the output signal OUT becomes high.

[0068] The third stage T3: the input signal IN is high, the first clock signal CK1 is low, the first node N1 is high, the third node N3 is high, the seventh transistor M7 is turned on, the fourth node N4 is low, the second clock signal CK2 is high, the sixth transistor M6 is turned on, the fifth node N5 is high, the ninth transistor M9 is disconnected, the second node N2 remains low, the eleventh transistor M11 is turned on, and the output signal OUT remains high.

[0069] The fourth stage T4: the input signal IN is low, the first clock signal CK1 is high, the first node N1 remains high, the third node N3 remains high, the fourth node N4 remains low, the second clock signal CK2 is low, the second node N2 is low, and the output signal OUT remains high.

[0070] The fifth stage T5: the input signal IN is low, the first clock signal CK1 is low, the first node N1 is low, the gate of the first transistor M1 is connected to the first node N1, and the first transistor M1 is turned on in the first time period X1. The first capacitor C1 is quickly charged, and the potential of the third node N3 rapidly decreases to the first low-level signal V1. The fourth node N4 is low, the second clock signal CK2 is high, and the second node N2 is high. Since the first low-level signal V1 is lower than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is less than the source potential of the tenth transistor M10, and thus the tenth transistor M10 can quickly reach a saturated state. The tenth transistor M10 is turned on, the eleventh transistor M11 is disconnected, the output signal OUT of the shift register is basically consistent with the first voltage signal Vgl, and the tailing phenomenon of the output signal is avoided.

[0071] Figure 17Another schematic diagram of the circuit structure of the shift register provided by the embodiment of the present application is shown in Figure 17 The first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and the fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes the first capacitor C1, the first transistor M1, and the second capacitor C2. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, i.e., the second control signal A2 is the potential signal of the first node N1. In this embodiment, the first clock signal CK1 and the first control signal A1 are the same signal. In the first time period, the first control signal A1 is a low-level signal, and the second control signal A2 controls the first transistor M1 to be turned on. Figure 18 The timing diagram of the circuit structure shown in Figure 17 is shown below. The detailed description is made below with reference to Figure 17 and Figure 18 .

[0072] The first stage T1: the input signal IN is high, the first clock signal CK1 is low, the fourth transistor M4 is turned on, the first node N1 is high, the third node N3 is high, the seventh transistor M7 is turned on, and the fourth node N4 is low. The second clock signal CK2 is high, the second node N2 remains high, the eleventh transistor M11 is turned off, and the output signal OUT remains low.

[0073] The second stage T2: the input signal IN is high, the first clock signal CK1 is high, the fourth transistor M4 is turned off, the first node N1 remains high, and the third node N3 remains high. The fourth node N4 remains low, the second clock signal CK2 is low, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 becomes low, the eleventh transistor M11 is turned on, and the output signal OUT becomes high.

[0074] The third stage T3: the input signal IN is high, the first clock signal CK1 is low, the first node N1 is high, the third node N3 is high, the seventh transistor M7 is turned on, the fourth node N4 is low, the second clock signal CK2 is high, the sixth transistor M6 is turned on, the fifth node N5 is high, the ninth transistor M9 is turned off, the second node N2 remains low, the eleventh transistor M11 is turned on, and the output signal OUT remains high.

[0075] The fourth stage T4: the input signal IN is low, the first clock signal CK1 is high, the first node N1 remains high, the third node N3 remains high, the fourth node N4 remains low, the second clock signal CK2 is low, the second node N2 is low, and the output signal OUT remains high.

[0076] In the fifth stage T5, the input signal IN is low, the first clock signal CK1 is low, the first node N1 is low, in the first time period X1, the gate of the first transistor M1 is connected to the first node N1, so the first transistor M1 is turned on, the first capacitor C1 is rapidly charged, the potential of the third node N3 is rapidly decreased to the first low-level signal V1. The fourth node N4 is low, the second clock signal CK2 is high, the second node N2 is high. Since the first low-level signal V1 is lower than the potential of the first voltage signal Vgl, the potential of the gate of the tenth transistor M10 is less than the potential of the source of the tenth transistor M10, so the tenth transistor M10 can rapidly tend to be in a saturated state, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned off, and the output signal OUT of the shift register is basically consistent with the first voltage signal Vgl, thereby avoiding the tailing phenomenon of the output signal. The fourth control unit 04 in the embodiment of the present application is provided with the second capacitor C2, the potential of the first node N1 can be stabilized by the second voltage signal Vgh and the second capacitor C2, thereby avoiding the influence of the floating of the potential of the first node N1 on the potential of the third node N3, and further avoiding the influence of the potential of the third node N3 on the output signal OUT of the shift register.

[0077] Figure 19 Another circuit structure schematic diagram of the shift register provided by the embodiment of the present application is shown in FIG. 6. Figure 19As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, a first transistor M1, a second capacitor C2, and a second transistor M2. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, that is, the second control signal A2 is the potential signal of the first node N1. The source of the second transistor M2 is connected to the first node N1, the drain is connected to the third node N3, and the gate receives the first control signal A1. In the first time period, the first control signal A1 controls the second transistor M2 to be turned on. In the first time period, the first control signal A1 is a low-level signal, and the second control signal A2 controls the first transistor M1 to be turned on. Figure 20 For Figure 19 The timing diagram of the circuit structure is shown. The following will be described in detail with reference to Figure 19 and Figure 20 .

[0078] The first stage T1: the input signal IN is high level, the first clock signal CK1 is low level, the second clock signal CK2 is high level, the fourth transistor M4 is turned on, the first node N1 is high level, the fourth node N4 is low level, the first control signal A1 is high level, the second transistor M2 is disconnected, the third node N3 keeps low level, the second node N2 is high level, and the output signal OUT is low level.

[0079] The second stage T2: the input signal IN is high level, the first control signal A1 is low level, the second clock signal CK2 is high level, the first node N1 is high level, the second transistor M2 is turned on, the third node N3 is high level, the fourth node N4 is low level, the second node N2 is high level, and the output signal OUT keeps low level.

[0080] The third stage T3: the input signal IN is high level, the second clock signal CK2 is low level, the first node N1 is high level, the third node N3 is high level, the fourth node N4 is low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 becomes low level, the eleventh transistor M11 is turned on, and the output signal OUT is high level.

[0081] The fourth stage T4: the input signal IN is high level, the second clock signal CK2 is high level, the first node N1 is high level, the third node N3 is high level, the fourth node N4 is low level, the second node N2 is low level, and the output signal OUT keeps high level.

[0082] The fifth stage T5: the input signal IN is low level, the first clock signal CK1 is high level, the first control signal A1 is high level, the second clock signal CK2 is low level, the first node N1 is high level, the third node N3 is high level, the fourth node N4 is low level, the second node N2 is low level, and the output signal OUT keeps high level.

[0083] The sixth stage T6: the input signal IN is low level, the first clock signal CK1 is low level, the second clock signal CK2 is high level, the first node N1 is low level, the fifth transistor M5 is turned on, the fourth node N4 is low level, the first control signal A1 is high level, the second transistor M2 is disconnected, the third node N3 is high level. The second node N2 becomes high level due to the eighth transistor M8 being turned on, the tenth transistor M10 and the eleventh transistor M11 are disconnected, and the output signal OUT keeps high level.

[0084] In the seventh stage T7, the input signal IN is at low level, the first control signal A1 is at low level, the first node N1 is at low level, and in the first time period X1, the first capacitor C1 is rapidly charged to pull down the first node N1 to the potential of the first low level signal V1, the potential of the first low level signal V1 is less than the potential of the first voltage signal Vgl, the second transistor M2 is turned on, and thus the third node N3 is at the potential of the first low level signal V1. The fourth node N4 and the second node N2 are both at high level, the eleventh transistor M11 is turned off, the potential of the third node N3 is less than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is less than the source potential of the tenth transistor M10, the tenth transistor M10 can rapidly tend to be in a saturated state, the tenth transistor M10 is turned on, and the output signal OUT of the shift register is basically consistent with the first voltage signal Vgl, thereby avoiding the tailing phenomenon of the output signal.

[0085] Figure 21 Another circuit structure diagram of a shift register provided by an embodiment of the present application is shown in FIG. 6. Figure 21As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 further includes a first transistor M1, the source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. The second control signal A2 in this embodiment is the signal of the first node N1. In the first time period, the first control signal A1 is a low-level signal, and the second control signal A2 controls the first transistor M1 to be turned on. In addition, the fourth control unit 04 further includes a second transistor M2, the source of the second transistor M2 is connected to the first node N1, the drain is connected to the third node N3, and the gate receives the first control signal A1; in the first time period, the first control signal A1 controls the second transistor M2 to be turned on. Figure 22 For Figure 21 the timing diagram of the circuit structure shown. Below, reference Figure 21 and Figure 22 will be made to introduce in detail.

[0086] The first stage T1: the input signal IN is high, the first clock signal CK1 is low, the second clock signal CK2 is high, the fourth transistor M4 is turned on, the first node N1 is high, the first control signal A1 is high, the second transistor M2 is disconnected, the third node N3 keeps low, the seventh transistor M7 is turned on, the fourth node N4 is low. The second node N2 is high, the eleventh transistor M11 is disconnected, the tenth transistor M10 is turned on, and the output signal OUT is low.

[0087] The second stage T2: the input signal IN is high, the first clock signal CK1 is high, the first control signal A1 is low, the second clock signal CK2 is high, the first node N1 is high, the second transistor M2 is turned on, the third node N3 is high; the fourth node N4 is low, the second node N2 is high, and the output signal OUT keeps low.

[0088] The third stage T3: the input signal IN is high, the first clock signal CK1 is high, the second clock signal CK2 is low, the first control signal A1 is high, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 is low, the eleventh transistor M11 is turned on, and the output signal OUT is high.

[0089] The fourth stage T4: the input signal IN is high, the second clock signal CK2 is high, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, and the output signal OUT keeps high.

[0090] The fifth stage T5: the input signal IN is low, the second clock signal CK2 is low, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, and the output signal OUT keeps high.

[0091] The sixth stage T6: the input signal IN is low, the first clock signal CK1 is low, the second clock signal CK2 is high, the first node N1 is low, the fourth node N4 is low, the first control signal A1 is high, the second transistor M2 is disconnected, and the third node N3 is high. The second node N2 becomes high due to the eighth transistor M8 being turned on, the tenth transistor M10 and the eleventh transistor M11 are disconnected, and the output signal OUT keeps high.

[0092] In the seventh stage T7, the input signal IN is at a low level, the first control signal A1 is at a low level, and in the first time period X1, the first capacitor C1 is rapidly charged, the first node N1 is pulled down to the potential of the first low-level signal V1, the potential of the first low-level signal V1 is less than the potential of the first voltage signal Vgl, the second transistor M2 is turned on, and thus the potential of the third node N3 is the potential of the first low-level signal V1. The fourth node N4 is at a high level, the second node N2 is at a high level, the eleventh transistor M11 is turned off, the potential of the third node N3 is less than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is less than the source potential of the tenth transistor M10, the tenth transistor M10 can rapidly tend to be in a saturated state, the tenth transistor M10 is turned on, and the output signal OUT of the shift register is basically consistent with the first voltage signal Vgl, thereby avoiding the tailing phenomenon of the output signal.

[0093] Figure 23 A circuit structure diagram of another shift register provided by the embodiment of the application is shown in FIG. 6. Figure 23As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The fourth control unit 04 further includes a first transistor M1, the source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. In this embodiment, the first control signal A1 and the second control signal A2 are the same signal. In the first time period, the first control signal A1 is a low-level signal, and the second control signal A2 controls the first transistor M1 to be turned on. Figure 24 For Figure 23 The timing diagram of the circuit structure is shown. The following will be described in detail with reference to Figure 23 and Figure 24 .

[0094] The first stage T1: the input signal IN is high, the first clock signal CK1 is low, the second clock signal CK2 is high, the fourth transistor M4 is turned on, the first node N1 is high, the seventh transistor M7 is turned on, the fourth node N4 is low, the first control signal A1 is high, the third node N3 keeps low, the second node N2 is high, the eleventh transistor M11 is disconnected, and the output signal OUT keeps low.

[0095] The second stage T2: the input signal IN is high, the first control signal A1 is low, the second clock signal CK2 is high, the first node N1 is high, the fourth node N4 is low, the second transistor M2 is turned on, the third node N3 is high, the second node N2 is high, and the output signal OUT keeps low.

[0096] The third stage T3: the input signal IN is high, the second clock signal CK2 is low, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, the eleventh transistor M11 is turned on, and the output signal OUT is high.

[0097] The fourth stage T4: the input signal IN is high, the second clock signal CK2 is high, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, and the output signal OUT keeps high.

[0098] The fifth stage T5: the input signal IN is low, the second clock signal CK2 is low, the first node N1 is high, the third node N3 is high, the fourth node N4 is low, the second node N2 is low, and the output signal OUT keeps high.

[0099] The sixth stage T6: the input signal IN is low, the first clock signal CK1 is low, the second clock signal CK2 is high, the first node N1 is low, the fourth node N4 is low, the first control signal A1 is high, the second transistor M2 is disconnected, the third node N3 is high. Because the eighth transistor M8 is turned on, the second node N2 becomes high, the tenth transistor M10 and the eleventh transistor M11 are disconnected, and the output signal OUT keeps high.

[0100] In the seventh stage T7, the input signal IN is at low level, the first control signal A1 is at low level, and in the first time period X1, the first node N1 is pulled down to the potential of the first low level signal V1 due to the rapid charging of the first capacitor C1, the potential of the first low level signal V1 is less than the potential of the first voltage signal Vgl, the second transistor M2 is turned on, and thus the potential of the third node N3 is the potential of the first low level signal V1. The fourth node N4 is at high level, the second node N2 is at high level, the eleventh transistor M11 is turned off, the potential of the third node N3 is less than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is less than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly tend to be in a saturated state, the tenth transistor M10 is turned on, and the output signal OUT of the shift register is basically consistent with the first voltage signal Vgl, thereby avoiding the tailing phenomenon of the output signal.

[0101] Figure 25 Another circuit structure diagram of a shift register provided by the embodiment of the present application is shown in FIG. 6. Figure 25As shown, the first control unit 01 includes a fourth transistor M4, the source of the fourth transistor M4 receives the input signal IN, the drain is connected to the first node N1, and the gate receives the first clock signal CK1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. Among them, the source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The source of the sixth transistor M6 receives the second clock signal CK2, the drain is connected to the fifth node N5, and the gate is connected to the fourth node N4. The source of the seventh transistor M7 receives the first voltage signal Vgl, the drain is connected to the fourth node N4, and the gate receives the first clock signal CK1. The source of the eighth transistor M8 receives the second voltage signal Vgh, the drain is connected to the second node N2, and the gate is connected to the first node N1. The source of the ninth transistor M9 is connected to the fifth node N5, the drain is connected to the second node N2, and the gate receives the second clock signal CK2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The source of the tenth transistor M10 receives the first voltage signal Vgl, the drain outputs the output signal OUT, and the gate is connected to the third node N3. The source of the eleventh transistor M11 receives the second voltage signal Vgh, the drain outputs the output signal OUT, and the gate is connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, a first transistor M1, a second capacitor C2, and a third transistor M3. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal A1. The source of the first transistor M1 receives the first control signal A1, the drain is connected to the second plate of the first capacitor C1, and the gate receives the second control signal A2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, that is, the second control signal A2 is the potential signal of the first node N1. The source of the third transistor M3 receives the second voltage signal Vgh, the drain is connected to the third node N3, and the gate is connected to the second node N2; in this embodiment, the first clock signal CK1 and the first control signal A1 are the same signal. In the first time period X1, the first control signal A1 is a low-level signal, the second control signal A2 controls the first transistor M1 to be turned on, and the second node N2 controls the third transistor M3 to be turned off. Figure 25 The timing of the circuit structure can be seen in the introduction of Figure 18 , compared with Figure 17 and Figure 18In the shown scheme, the embodiment of the present application can utilize the potential of the second node N2 to control the potential of the third node N3, and ensure the signal stability of the third node N3 at high level. Since each clock signal will undergo multiple jumps, it is possible to cause the potential of the first node N1 and the third node N3 to float during the jump. The embodiment of the present application sets the third transistor M3, when the second node N2 is at low level, the third transistor M3 is turned on, and the third node is controlled to be stable at high level. Before the second node N2 becomes high level, the third transistor M3 is turned off, and the level of the third node N3 does not change. Only when the second node N2 becomes high level, the third node N3 becomes a lower potential than the first voltage signal Vgl, thereby reducing the tailing phenomenon.

[0102] Optionally, the first control signal and the first clock signal are pulse signals of different time sequences, and the first control signal and the second clock signal are pulse signals of different time sequences; wherein, the effective pulses of the first clock signal, the first control signal and the second clock signal are sequentially generated. For example, refer to Figure 20 、 Figure 22 and Figure 24 .

[0103] Optionally, the time length of the effective pulse of the first clock signal is less than or equal to the time length of the effective pulse of the second clock signal, and the time length of the effective pulse of the first control signal is less than or equal to the time length of the effective pulse of the second clock signal. For example, refer to Figure 20 、 Figure 22 and Figure 24 .

[0104] Optionally, the time length of the effective pulse of the first control signal is less than or equal to the time length of the effective pulse of the first clock signal. Since the first clock signal needs to participate in the driving process of the first control unit, the second control unit and the third control unit, and the first control signal only needs to control the fourth control unit, therefore, in order to save the time of the effective pulse and save power consumption, the time length of the effective pulse of the first control signal can be set to be less than or equal to the time length of the effective pulse of the first clock signal.

[0105] Optionally, the sum of the time length of the active pulse of the first clock signal and the active pulse of the first control signal is equal to or greater than the time length of the active pulse of the second clock signal. The first clock signal and the first control signal jointly control the potential change of the first node and the third node N3, and the second clock signal controls the potential change of the second node N2. In some embodiments of the present application, the sum of the active pulse of the first clock signal and the active pulse of the first control signal can be equal to the active pulse of the second clock signal. If it is necessary to ensure that the potential of the third node N3 is pulled down for at least a first time period when the first node is at a low potential, the time of the active pulse of the first control signal can be appropriately increased to ensure that there is no tailing phenomenon in the output signal of the shift register.

[0106] Optionally, the active pulse of the first clock signal at least partially overlaps with the active pulse of the first control signal. The active pulse of the first clock signal can partially overlap with the active pulse of the first control signal, and under the premise of keeping the driving period unchanged, the active pulse of the first clock signal and the active pulse of the first control signal can be appropriately increased to ensure the stable control of the potentials of the first node and the third node.

[0107] Optionally, the start time of the active pulse of the first clock signal is earlier than the start time of the active pulse of the first control signal, and the end time of the active pulse of the first clock signal is earlier than or the same as the end time of the active pulse of the first control signal. Because it is necessary to continue to pull down the potential of the first node N1 through the fourth control unit 04 after the first node N1 changes from a high potential to a low potential, the start time of the active pulse of the first clock signal needs to be earlier than the start time of the active pulse of the first control signal. The embodiment of the present application sets that the end time of the active pulse of the first clock signal is earlier than or the same as the end time of the active pulse of the first control signal, which can ensure that the fourth control unit continuously controls the potential of the third node N3 to be pulled down for at least a first time period when the potential of the first node is at a low potential. If the end time of the active pulse of the first clock signal is later than the end time of the active pulse of the first control signal, the potential of the third node may change back to the potential before the potential of the first node is pulled down.

[0108] Optionally, according to the actual product demand, the active pulse of the first control signal can also be set to have no overlap with the active pulse of the first clock signal, for example Figure 20 、 Figure 22 and Figure 24 .

[0109] Optionally, during the shift process of the invalid pulse of the input signal to the output signal, the invalid pulse of the input signal is earlier than the active pulse of the first clock signal by a first interval, and the active pulse of the first clock signal is earlier than the active pulse of the first control signal by a second interval; wherein the first interval is equal to the second interval. For example, refer to Figure 20 The invalid pulse of the input signal IN is high, and the invalid pulse of the input signal IN is earlier than the active pulse (low) of the first clock signal CK1 by a first interval t1. The active pulse (low) of the first clock signal CK1 is earlier than the active pulse of the first control signal A1 by a second interval t2. Due to the control of the first control signal A1, the output signal OUT changes from high to low at the active pulse of the first control signal A1, and the falling edge of the output signal OUT is delayed by the second interval t2, which is the difference between the active pulse of the first clock signal CK1 and the active pulse of the first control signal A1. Therefore, the rising edge of the input signal IN is earlier than the falling edge of the first clock signal CK1 by a first interval t1, and the first interval t1 is equal to the second interval t2, which ensures that the invalid pulse widths of the input signal IN and the output signal OUT are equal and the waveforms are consistent.

[0110] Optionally, the second clock signal outputs an invalid pulse in the first time period. For example, refer to Figure 20 In the first time period X1 before the second clock signal CK2 outputs an active pulse (low), the third node N3 is quickly pulled down to a potential lower than the first voltage signal Vgl, thereby eliminating the tail phenomenon as much as possible.

[0111] Optionally, the time period in which the first node receives a low-level signal also includes a second time period X2. In the first time period X1, the potential of the third node is a first low-level signal, and in the second time period X2, the potential of the third node is a high-level signal. For example, refer to Figure 20 , Figure 22 and Figure 24 In the second time period X2, when the first clock signal CK1 is low and the first control signal A1 is high, the third node N3 is still a high-level signal. In the first time period X1 after the first control signal A1 becomes low, the third node N3 is pulled down to a potential lower than the first voltage signal Vgl, thereby eliminating the tail phenomenon.

[0112] Based on the above inventive concept, the embodiments of the present application further provide a display device. The display device comprises the display panel according to any one of the embodiments of the present application, and therefore the display device provided by the embodiments of the present application has the corresponding beneficial effects of the display panel provided by the embodiments of the present application, which will not be described herein. For example, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, and the like, and the embodiments of the present application are not limited thereto. Figure 26 FIG. 36 is a structural schematic diagram of a display device according to an embodiment of the present application. Figure 26 As shown in FIG. 36, the display device comprises the display panel 100 in the above embodiments.

[0113] It should be noted that the above are only preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the inventive concept, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a driving circuit comprising N-stage shift registers connected in cascade, N≥2; the shift register comprises: a first control unit receiving an input signal and controlling a signal of a first node in response to a first clock signal; a second control unit receiving a first voltage signal and a second voltage signal and controlling a signal of a second node in response to the signal of the first node, the first clock signal and a second clock signal; a third control unit receiving the first voltage signal and generating an output signal in response to a signal of a third node, or receiving the second voltage signal and generating the output signal in response to a signal of the second node, wherein the third node is connected to the first node, the first voltage signal is a low-level signal and the second voltage signal is a high-level signal; a fourth control unit comprising a first capacitor and a first transistor, a first plate of the first capacitor being connected to the third node, a second plate of the first capacitor being connected to a drain of the first transistor, a source of the first transistor receiving a first control signal, a gate of the first transistor receiving a second control signal; wherein the second control signal controls the first transistor to be turned on at least in a first time period when the signal of the first node is a low-level signal.

2. The display panel of claim 1, wherein the second control signal is the same as a signal received by the first plate of the first capacitor.

3. The display panel of claim 1, wherein the second control signal is the signal of the first node.

4. The display panel of claim 1, wherein the first clock signal is the same as the first control signal.

5. The display panel of claim 1, wherein the first control signal is the same as the second control signal.

6. The display panel of claim 1, wherein the first control signal is a low-level signal in the first time period.

7. The display panel of claim 1, wherein the first control signal and the first clock signal are pulse signals with different timings.

8. The display panel of claim 1, wherein a time length of an effective pulse of the first control signal is less than or equal to a time length of an effective pulse of the first clock signal.

9. The display panel of claim 1, wherein the effective pulse of the first control signal at least partially overlaps with the effective pulse of the first clock signal, or the effective pulse of the first control signal does not overlap with the effective pulse of the first clock signal.

10. The display panel of claim 1, wherein the fourth control unit further comprises a second capacitor, a first plate of the second capacitor being connected to the gate of the first transistor, and a second plate of the second capacitor receiving the second voltage signal.

11. The display panel of claim 10, wherein The capacitance of the first capacitor is less than the capacitance of the second capacitor.

12. The display panel of claim 1, wherein, The fourth control unit further comprises a second transistor, a source of the second transistor is connected to the first node, and a drain of the second transistor is connected to the third node. During the first time period, the second transistor is turned on.

13. The display panel of claim 1, wherein, The first control unit comprises: a fourth transistor, a source of the fourth transistor receives the input signal, a drain of the fourth transistor is connected to the first node, and a gate of the fourth transistor receives the first clock signal; The second control unit comprises: a fifth transistor, a source of the fifth transistor receives the first clock signal, a drain of the fifth transistor is connected to a fourth node, and a gate of the fifth transistor is connected to the first node; a sixth transistor, a source of the sixth transistor receives the second clock signal, a drain of the sixth transistor is connected to a fifth node, and a gate of the sixth transistor is connected to the fourth node; a seventh transistor, a source of the seventh transistor receives the first voltage signal, a drain of the seventh transistor is connected to the fourth node, and a gate of the seventh transistor receives the first clock signal; an eighth transistor, a source of the eighth transistor receives the second voltage signal, a drain of the eighth transistor is connected to the second node, and a gate of the eighth transistor is connected to the first node; a ninth transistor, a source of the ninth transistor is connected to the fifth node, a drain of the ninth transistor is connected to the second node, and a gate of the ninth transistor receives the second clock signal; a third capacitor, a first plate of the third capacitor is connected to the fourth node, and a second plate of the third capacitor is connected to the fifth node; a fourth capacitor, a first plate of the fourth capacitor receives the second voltage signal, and a second plate of the fourth capacitor is connected to the second node; The third control unit comprises: a tenth transistor, a source of the tenth transistor receives the first voltage signal, a drain of the tenth transistor outputs an output signal, and a gate of the tenth transistor is connected to the third node; an eleventh transistor, a source of the eleventh transistor receives the second voltage signal, a drain of the eleventh transistor outputs an output signal, and a gate of the eleventh transistor is connected to the second node.

14. The display panel of claim 13, wherein, the capacitance of the first capacitor is less than the capacitance of the third capacitor, or the capacitance of the first capacitor is less than the capacitance of the fourth capacitor.

15. A display device comprising: A display panel as claimed in any one of claims 1 to 14.

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