Power management driver and display device

Abstract

The invention relates to a power management driver and a display device. The power management driver includes: a power source supplying a first voltage to a driving power terminal of a pixel through a power line during a sensing period, and supplying a second voltage to the driving power terminal of the pixel through the power line during a display period; and a controller coupled to the power supply to generate a first enable signal and a second enable signal. The power supply includes: a digital-to-analog converter outputting the first voltage based on input power; the first switch is coupled between the digital-to-analog converter and the power line, and the first switch is turned on in response to the first enable signal; and a second switch coupled between the power line and a voltage source supplied with the second voltage, the second switch being turned on in response to the second enable signal.

Description

[0001] This application is a divisional application of the invention patent application with application date of December 16, 2020, application number 202011489101.1, and invention name “Power management driver and display device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Korean Patent Application No. 10-2019-0179066 filed on December 31, 2019 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure relates to display devices, and more particularly, to display devices with power management drivers. Background Art

[0005] Self-emissive display devices use pixels coupled to a plurality of scan lines and data lines to display images. For such operation, each pixel has a light-emitting element.

[0006] Such a light emitting element is electrically coupled to a first driving power terminal supplying a first driving power VSS and a second driving power terminal supplying a second driving power VDD, and emits light based on a current or a voltage generated between the driving power terminals.

[0007] A power line or conductive pattern for transmitting a power supply voltage in a display device may contact other wires due to unexpected reasons such as cracks, foreign matter, or panel deformation, and cause a short circuit failure. For any short circuit failure in the power line, an overcurrent may occur, and thus there may be a risk of heat or fire. Summary of the invention

[0008] Embodiments of the present disclosure relate to a display device having a power management driver. According to at least one embodiment, the power management driver senses the voltage of the driving power terminal after the voltage of the driving power terminal has been stably supplied during a sensing period, and thereby can detect a short circuit fault ("short circuit") in the power line and protect the circuit. Exemplary embodiments of the present disclosure relate to a display device having such a power management driver. Aspects of the present disclosure are not limited to the foregoing, and may be expanded in various ways without departing from the scope or spirit of the present disclosure.

[0009] An exemplary embodiment of the present disclosure may provide a power management driver. The power management driver may include: a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and to supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control a timing of outputting the first voltage and a timing of outputting the second voltage in response to a sensing control signal during a transition period between the display period and the sensing period; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

[0010] In an exemplary embodiment, the first power supply may include: a voltage determiner configured to determine the first voltage based on input power; a first switch coupled between the voltage determiner and the power line, and the first switch is configured to be turned on in response to a first enable signal; and a second switch coupled between the power line and a voltage source supplied with the second voltage, and the second switch is configured to be turned on in response to a second enable signal.

[0011] In an exemplary embodiment, the controller may include: a first delay component configured to generate the first enable signal by delaying the sensing control signal, and supplying the first enable signal to the first switch during the sensing period; and a second delay component configured to generate the second enable signal by inverting and delaying the sensing control signal, and supplying the second enable signal to the second switch during the display period.

[0012] In an exemplary embodiment, when the sensing period is performed after the display period, during a first transition period between the display period and the sensing period, the first switch may be turned on after the second switch has been turned off.

[0013] In an exemplary embodiment, when the display period is performed after the sensing period, during a second transition period between the sensing period and the display period, the second switch may be turned on after the first switch has been turned off.

[0014] In an exemplary embodiment, the second voltage may be a ground voltage, and the first voltage may be higher than the second voltage.

[0015] In an exemplary embodiment, the short circuit detector may include: a detection value extractor configured to extract at least one of a first detection value and a second detection value based on a positive current or a negative current flowing through the output terminal during the sensing period; and a protector configured to generate a protection signal based on the first detection value and the second detection value.

[0016] In an exemplary embodiment, the controller may limit the output of the protection signal by the short circuit detector during the transition period and a masking period including a preset initial period of the sensing period.

[0017] In an exemplary embodiment, the protector may include: a first comparator configured to compare the first detection value with a first reference value and then generate a first result; a second comparator configured to compare the second detection value with a second reference value and then generate a second result; a logic OR operation component configured to generate the protection signal based on the result of the logic OR operation of the first result and the second result; and a switch configured to control the output of the protection signal in response to a masking signal during the sensing period.

[0018] In an exemplary embodiment, the controller may provide the protector with the masking signal for turning off the switch during a masking period which is a preset initial period of the sensing period after the transition period.

[0019] In an exemplary embodiment, the controller may include: a shutdown controller configured to count the time during which the protection signal is output; and a counting controller configured to provide a reset signal for resetting the count value to the shutdown controller based on a comparison result between a first glitch time for the first detection value and a preset noise ignoring time.

[0020] In an exemplary embodiment, when the count value is greater than a preset shutdown reference time, the shutdown controller may output the protection signal as a shutdown signal.

[0021] In an exemplary embodiment, the count controller may generate the reset signal when the first glitch time is longer than the noise ignore time.

[0022] In an exemplary embodiment, the count controller may generate the reset signal based on a comparison result between a second glitch time for the second detection value and the noise ignore time.

[0023] In an embodiment, when the second glitch time is longer than the noise neglect time, the count controller may generate the reset signal.

[0024] In an exemplary embodiment, the power management driver may further include: a second power supply configured to supply a voltage of a second driving power terminal to the pixel during the sensing period and the display period.

[0025] An exemplary embodiment of the present disclosure may provide a display device. The display device may include: a pixel coupled to a scan line, a control line, a data line, and a sensing line; a scan driver configured to supply a scan signal to the scan line and a control signal to the control line; a data driver configured to supply one of an image data signal and a sensing data signal to the data line; a sensing circuit configured to sense a characteristic of a driving transistor included in the pixel based on a sensing current supplied through the sensing line during a sensing period; and a power management driver configured to provide a first driving power and a second driving power to the pixel. The power management driver may include: a first power supply configured to supply a first voltage of the first driving power to the pixel through a first power line during a sensing period, and to supply a second voltage of the first driving power to the pixel through the first power line during a display period; a second power supply configured to supply a voltage of the second driving power to the pixel through a second power line during the sensing period and the display period; a controller configured to control a timing of outputting the first voltage of the first driving power and a timing of outputting the second voltage of the first driving power in response to a sensing control signal during a transition period between the display period and the sensing period; and a fault detector configured to detect a fault of impedance reduction in the first power line based on a current flowing through an output terminal during the sensing period.

[0026] In an exemplary embodiment, each of the pixels may include: a light emitting element; and a driving transistor configured to control a current flowing from a source of the second driving power into the light emitting element and electrically coupled to the light emitting element. The source of the first driving power may be coupled to an electrode of the light emitting element.

[0027] In an exemplary embodiment, the first power supply may include: a voltage determiner configured to determine the first voltage based on input power; a first switch coupled between the voltage determiner and the first power line and configured to be turned on in response to a first enable signal; and a second switch coupled between the first power line and a voltage source supplied with the second voltage and configured to be turned on in response to a second enable signal.

[0028] In an exemplary embodiment, when the sensing period is performed after the display period, during a first transition period between the display period and the sensing period, after the second switch has been turned off, the first switch can be turned on, and when the display period is performed after the sensing period, during a second transition period between the sensing period and the display period, after the first switch has been turned off, the second switch can be turned on. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic block diagram showing a display device according to an embodiment of the present disclosure.

[0030] Figure 2A is shown to be included in Figure 1 Schematic circuit diagram of an example of a pixel in a display device.

[0031] Figure 2B is shown to be included in Figure 1 Schematic circuit diagram of an example of a pixel in a display device.

[0032] Figure 3 It shows Figure 1 A graphical timing diagram of an example of the operation of a display device.

[0033] Figure 4 It shows Figure 2A or Figure 2B A graphical timing diagram of an example of the operation of a pixel.

[0034] Figure 5 is a schematic hybrid block / circuit diagram illustrating a power management driver according to an embodiment of the present disclosure.

[0035] Figure 6 It shows Figure 5 A schematic hybrid block diagram / circuit diagram of an example of a power management driver.

[0036] Figure 7 It shows Figure 6 A graphical timing diagram of an example of the operation of a power management driver.

[0037] Figure 8 It shows Figure 6 A graphical timing diagram of an example of the operation of a power management driver.

[0038] Fig. 9 is shown to be included in Figure 6 Schematic block diagram of an example of a short circuit fault (“short”) detector and controller in a power management driver.

[0039] Fig.10It shows Fig. 9 A graphical timing diagram of an example of the operation of the short circuit detector and controller.

[0040] Fig.11 is shown to be included in Figure 6 Schematic circuit diagram of an example of a short circuit detector in a power management driver.

[0041] Fig.12 is shown to be included in Figure 6 Schematic block diagram of an example of a controller in a power management driver.

[0042] Fig.13 It shows Fig.12 A mixed graphical timing and conceptual diagram of an example of the operation of a controller. DETAILED DESCRIPTION

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals may be used to indicate the same or similar features, and their repeated description may be omitted.

[0044] Figure 1 A display device according to an exemplary embodiment of the present disclosure is shown.

[0045] Reference Figure 1 , the display device 1000 may include a pixel unit 100 , a scan driver 200 , a data driver 300 , a sensing circuit 400 , a power management driver 500 , and a timing controller 600 .

[0046] The display device 1000 may be a flat display device, a flexible display device, a curved display device, a foldable display device, a bendable display device, or a stretchable display device. In addition, the display device 1000 may be applied to a transparent display device, a head-mounted display device, or a wearable display device. In addition, the display device 1000 may be applied to various electronic devices such as a smart phone, a tablet computer, a smart tablet computer, a television (TV), or a monitor.

[0047] The display device 1000 may be implemented as an organic light-emitting display device. The configuration shown and described is only an example, and the configuration of the display device 1000 is not limited thereto. For example, the display device 1000 may be a self-emitting display device including an inorganic light-emitting element or a liquid crystal display device, etc.

[0048] In an embodiment, the display device 1000 may be driven while dividing a period of the display device 1000 into a display period during which an image is displayed and a sensing period during which a characteristic of a driving transistor included in each pixel PX is sensed. The sensed characteristic may in turn be used to detect a fault, a pixel condition, and / or adaptively adjust a display output characteristic.

[0049] The pixel unit 100 may include pixels PX, which are arranged to be coupled to data lines DL1 to DLm (where m is a natural number), scan lines SL1 to SLn (where n is a natural number), control lines CL1 to CLn, and sensing lines SSL1 to SSLm. The pixels PX may be driven by the first driving power terminal (at Figure 2A and Figure 2B PT1 in FIG. 1 ) receives the voltage of the first driving power VSS and passes through the second driving power terminal (in FIG. 1 ) of the power management driver 500. Figure 2A and Figure 2B (indicated as PT2) receives the voltage of the second driving power VDD.

[0050] Despite Figure 1 , n scan lines SL1 to SLn are shown, but the present disclosure is not limited thereto. For example, one or more control lines, scan lines, emission control lines, or sensing lines may be additionally formed in the pixel unit 100 according to the circuit structure of each pixel PX.

[0051] In an embodiment, the transistor included in each pixel PX may be an N-type oxide thin film transistor (TFT). For example, such an oxide TFT may be a low temperature polycrystalline oxide (LTPO) TFT. However, this is merely exemplary, and the transistor is not limited thereto. For example, the active pattern or semiconductor layer included in each transistor may include an inorganic semiconductor such as amorphous silicon or polycrystalline silicon or an organic semiconductor, etc. At least one of the transistors included in the display device 1000 may be replaced with a P-type transistor.

[0052] The timing controller 600 may generate a data drive control signal DCS, a scan drive control signal SCS, and a power drive control signal PCS in response to an externally supplied synchronization signal. The data drive control signal DCS generated by the timing controller 600 may be supplied to the data driver 300, the scan drive control signal SCS may be supplied to the scan driver 200, and the power drive control signal PCS may be supplied to the power management driver 500.

[0053] In addition, the timing controller 600 may supply the image data DATA in which the externally supplied input image data is reorganized to the data driver 300 .

[0054] The data drive control signal DCS may include a source start signal and a clock signal. The source start signal may control the time point at which the sampling of the data starts. The clock signal may be used to control the sampling operation.

[0055] The scan drive control signal SCS may include a scan start signal, a control start signal and a clock signal. The scan start signal may control the timing of the scan signal. The control start signal may control the timing of the control signal. The clock signal may be used to shift the scan start signal and / or the control start signal.

[0056] The power drive control signal PCS may control the supply of a voltage of a first drive power VSS of a first drive power terminal and a voltage of a second drive power VDD of a second drive power terminal, respectively, wherein the voltage of the first drive power VSS of the first drive power terminal and the voltage of the second drive power VDD of the second drive power terminal include actual signal levels of the voltages. In an embodiment, the power drive control signal PCS may include a sensing control signal SCTL for controlling an actual voltage level of the first drive power VSS at the first drive power terminal.

[0057] The timing controller 600 may also control the operation of the sensing circuit 400. For example, the timing controller 600 may control the timing of supplying a reference voltage to the pixel PX through the sensing lines SSL1 to SSLm and / or the timing of sensing a current generated in the pixel PX through the sensing lines SSL1 to SSLm.

[0058] The scan driver 200 may receive the scan driving control signal SCS from the timing controller 600. The scan driver 200, having received the scan driving control signal SCS, may supply the scan signals to the scan lines SL1 to SLn and may supply the control signals to the control lines CL1 to CLn.

[0059] For example, the scan driver 200 may sequentially supply scan signals to the scan lines SL1 to SLn. When the scan signals are sequentially supplied to the scan lines SL1 to SLn, the pixels PX may be selected based on horizontal lines. For this operation, each scan signal may be set to a gate-on voltage such as a logic high level so that a transistor included in a corresponding pixel PX is turned on.

[0060] Similarly, the scan driver 200 may sequentially supply control signals to the control lines CL1 to CLn. The control signals may be used to sense or extract a driving current flowing through a pixel, which may be based on a current flowing through a corresponding driving transistor. The timing and waveform of supplying the scan signals and the control signals may be set differently according to the display period and the sensing period.

[0061] Despite Figure 1 2 shows a single scan driver 200 as outputting both scan signals and control signals, but the present disclosure is not limited thereto. For example, the scan driver 200 may include a first scan driver supplying scan signals to the pixel unit 100 and a second scan driver supplying control signals to the pixel unit 100.

[0062] The data driver 300 may receive a data driving control signal DCS from the timing controller 600. The data driver 300 may supply a data signal such as a sensing data signal for detecting pixel characteristics to the pixel unit 100 during a sensing period. The data driver 300 may supply a data signal for displaying an image to the pixel unit 100 based on the image data DATA during a display period.

[0063] The sensing circuit 400 may generate a compensation value for compensating a characteristic value of the pixel PX based on a sensing value such as a sensing current provided from the sensing lines SSL1 to SSLm. In detail, the sensing circuit 400 may calculate or sense a degradation amount of a driving transistor and / or a degradation amount of a light emitting element included in each pixel PX using a sensing value such as a sensing current provided from the sensing lines SSL1 to SSLm. For example, the sensing circuit 400 may detect and compensate for a change in the characteristic of the light emitting element that occurs due to a change in the threshold voltage of the driving transistor included in each pixel PX, a change in the mobility of the driving transistor, and a degradation of the driving transistor.

[0064] In an embodiment, the sensing circuit 400 may supply a predetermined reference voltage to the pixel PX through the sensing lines SSL1 to SSLm during the sensing period and receive a current or voltage extracted from the pixel PX. The extracted current or voltage may correspond to a sensing value, and the sensing circuit 400 may detect a change in the characteristics of the driving transistor based on the sensing value. The sensing circuit 400 may calculate a compensation value for compensating the input image data based on the detected characteristic change. The compensation value may be provided to the timing controller 600 or the data driver 300.

[0065] During a display period, the sensing circuit 400 may supply a predetermined reference voltage for displaying an image to the pixel unit 100 through the sensing lines SSL1 to SSLm.

[0066] Despite Figure 16. The sensing circuit 400 is shown as a component separated from the timing controller 600, but at least some of the components of the sensing circuit 400 may be included in the timing controller 600. For example, the sensing circuit 400 and the timing controller 600 may be formed in a single driver integrated circuit (IC). In addition, the data driver 300 may also be included in the timing controller 600. Therefore, at least some of the sensing circuit 400, the data driver 300, and the timing controller 600 may be formed in a single driver IC.

[0067] The power management driver 500 may supply a voltage of the first driving power VSS and a voltage of the second driving power VDD to the pixel unit 100 in response to the power driving control signal PCS. In an embodiment, the voltage at the first driving power terminal (the voltage of the first driving power VSS) may determine a cathode voltage of the light emitting element, and the voltage at the second driving power terminal (the voltage of the second driving power VDD) may determine a drain voltage of the driving transistor.

[0068] In an embodiment, the power management driver 500 may supply a voltage to the first driving power terminal as a first voltage during the sensing period and supply a voltage to the first driving power terminal as a second voltage during the display period. For example, the second voltage V2 may be ground GND (see Figure 6 ) voltage.

[0069] The voltage of the first driving power terminal can be supplied to the pixel PX through the first power line PL1, and the voltage of the second driving power terminal can be supplied to the pixel PX through the second power line PL2. In an embodiment, the first power line PL1 can be arranged on the front surface of the pixel unit 100 in the form of a common electrode. Such a first power line PL1 may have a high probability of short-circuiting or contacting with another line or conductive element due to a crack in the display panel including the pixel unit 100 or a deformation of the display panel including the pixel unit 100, so that, for example, a short circuit or impedance reduction fault is caused. By a short circuit fault ("short circuit") occurring on the first power line PL1, an overcurrent will occur, and therefore, there will be a risk of heating. Although the present disclosure shows the detection of short circuit and / or impedance reduction faults for exemplary purposes, it is not limited thereto. For example, an open circuit and / or impedance increase fault can be similarly detected.

[0070] Figure 2A Shown is included in Figure 1 An example of a pixel in a display device, and Figure 2B Shown is included in Figure 1 Another example of a pixel in a display device.

[0071] exist Figure 2A and Figure 2B In FIG. 1 , for convenience of description, pixels located on the i-th horizontal line and coupled to the j-th data line DLj are shown.

[0072] Reference Figure 2A and Figure 2B , the pixel PXij may include a light emitting element LD, a first pixel transistor T1 such as a driving transistor, a second pixel transistor T2 , a third pixel transistor T3 or T3 ′, and a storage capacitor Cst.

[0073] A first electrode of the light emitting element LD (which may be an anode or a cathode without limitation) is coupled to the second node N2, and a second electrode of the light emitting element LD (which may be the other of the anode and the cathode without limitation) is coupled to a source of a first driving power VSS of a first driving power terminal. The light emitting element LD may generate light having a predetermined brightness according to the amount of current supplied from the first pixel transistor T1 (such as through a driving transistor).

[0074] The first electrode of the first pixel transistor T1 may be coupled to the second driving power terminal PT2, the voltage of the second driving power VDD is supplied to the second driving power terminal PT2, and the second electrode of the first pixel transistor T1 may be coupled to the first electrode of the light emitting element LD. The gate electrode of the first transistor T1 may be coupled to the first node N1. The first pixel transistor T1 controls the amount of current flowing into the light emitting element LD according to the voltage of the first node N1.

[0075] A first electrode of the second pixel transistor T2 may be coupled to the data line DLj, and a second electrode of the second pixel transistor T2 may be coupled to the first node N1. A gate electrode of the second pixel transistor T2 may be coupled to the scan line SLi. When a scan signal is supplied through the scan line SLi, the second pixel transistor T2 may be turned on, and then a data signal from the data line DLj may be transmitted to the first node N1.

[0076] In an embodiment, Figure 2A As shown in , the third pixel transistor T3 may be coupled between the sensing line SSLj and the second electrode (such as the second node N2) of the first pixel transistor T1. The gate electrode of the third pixel transistor T3 may be coupled to the control line CLi. When a control signal is supplied through the control line CLi, the third pixel transistor T3 may be turned on, and then the sensing line SSLj and the second node N2 (such as the second electrode of the first pixel transistor T1) may be electrically coupled to each other.

[0077] In an embodiment, when the third pixel transistor T3 is turned on, the reference voltage may be supplied to the second node N2 through the sensing line SSLj. In an embodiment, when the third pixel transistor T3 is turned on, the current generated in the first pixel transistor T1 may be supplied to a sensing circuit (such as a sensing circuit) through the sensing line SSLj. Figure 1 sensing circuit 400).

[0078] In another embodiment, if Figure 2B As shown in , the third pixel transistor T3' may be coupled between the data line DLj and the second electrode (such as the second node N2) of the first pixel transistor T1. The gate electrode of the third pixel transistor T3' may be coupled to the control line CLi. When a control signal is supplied through the control line CLi, the third pixel transistor T3' may be turned on, and then the data line DLj and the second node N2 (such as the second electrode of the first pixel transistor T1) may be electrically coupled to each other.

[0079] In an embodiment, when the third pixel transistor T3' is turned on, the reference voltage may be supplied to the second node N2 through the data line DLj. In an embodiment, when the third pixel transistor T3' is turned on, the current generated in the first pixel transistor T1 may be supplied to the sensing circuit (e.g., Figure 1 400). In this way, Figure 2B The pixel PXij may receive a data signal through the data line DLj in a time-division manner or transmit the current sensed from the pixel PXij to a sensing circuit (eg, Figure 1 of 400).

[0080] The storage capacitor Cst may be coupled between the first node N1 and the second node N2. The storage capacitor Cst may store a voltage corresponding to a voltage difference between the first node N1 and the second node N2.

[0081] In the embodiment of the present disclosure, the circuit structure of the pixel PXij is not affected by Figure 2A or Figure 2B For example, the light emitting element LD may be interposed between the second driving power terminal PT2 and the first electrode of the first pixel transistor T1. Figure 2A and Figure 2B Pixel transistors T1 to T3 are shown as NMOS transistors in FIG. 1 , but the present disclosure is not limited thereto. For example, at least one of the pixel transistors T1 to T3 may be implemented as a PMOS transistor.

[0082] Figure 3 Shows Figure 1 An example of the operation of the display device, and Figure 4 Shows Figure 2A or Figure 2B Example of pixel operations.

[0083] Reference Figures 1 to 4 , the display device 1000 may be driven such that its period is divided into a display period DP during which an image is displayed and a sensing period SP during which a characteristic of the first pixel transistor T1 included in each pixel PX is sensed.

[0084] In an embodiment, during the sensing period SP, image data may be compensated based on the sensed characteristic information.

[0085] During the display period DP, a predetermined reference voltage as a constant voltage may be supplied to the sensing lines SSL1 to SSLm.

[0086] The scan driver 200 may sequentially supply scan signals to the scan lines SL1 to SLn during the display period DP. In addition, the scan driver 200 may sequentially supply control signals to the control lines CL1 to CLn during the display period DP.

[0087] For the i-th horizontal line, the scan signal and the control signal may be supplied substantially at the same time. Therefore, the second pixel transistor T2 and the third pixel transistor T3 may be turned on or off at the same time.

[0088] When the second pixel transistor T2 is turned on, a data signal DS corresponding to the image data may be supplied from the corresponding data line DLj to the first node N1. When the third pixel transistor T3 is turned on, a reference voltage may be supplied to the second node N2. Therefore, the storage capacitor Cst may store a voltage corresponding to the voltage difference between the data signal DS and the reference voltage.

[0089] Here, since the reference voltage is set to a constant voltage, the voltage stored in the storage capacitor Cst may be stably determined by the data signal DS.

[0090] When supply of the scan signal and the control signal to the i-th scan line SLi and the i-th control line CLi is stopped, the second pixel transistor T2 and the third pixel transistor T3 may be turned off.

[0091] Thereafter, the first pixel transistor T1 may control the amount of current (driving current) supplied to the light emitting element LD according to the voltage stored in the storage capacitor Cst. Therefore, the light emitting element LD may emit light having brightness corresponding to the driving current of the first pixel transistor T1.

[0092] The power management driver 500 may output a voltage of the first driving power VSS to the first driving power terminal PT1. In an embodiment, during the display period DP, the power management driver 500 may output a second voltage V2 of the first driving power VSS to the first driving power terminal PT1. During the display period DP, the first driving power terminal PT1 may be output in the form of a constant voltage. The second voltage V2 may have a voltage level that is sufficiently different from the first voltage V1 to be applied for image display. For example, the second voltage V2 may be a ground voltage.

[0093] In an embodiment, the scan driver 200 may sequentially supply scan signals to the scan lines SL1, SL2 to SLn during the sensing period SP. Also, the scan driver 200 may sequentially supply control signals to the control lines CL1, CL2 to CLn during the display period DP.

[0094] In an embodiment, the length of the control signal supplied during the sensing period SP may be longer than the length of the control signal supplied during the display period DP. In addition, during the sensing period SP, a portion of the control signal supplied to the i-th control line CLi may overlap with the scan signal supplied to the i-th scan line SLi. For example, the control signal supplied to the i-th control line CLi starts to be supplied at the same time as the scan signal supplied to the i-th scan line SLi, and the control signal supplied to the i-th control line CLi may be supplied for a longer time than the time of the scan signal.

[0095] When the scan signal and the control signal are supplied at the same time, the second pixel transistor T2 and the third pixel transistor T3 are turned on. When the second pixel transistor T2 is turned on, a sensing data signal or a voltage SGV for sensing may be supplied from the corresponding data line DLj to the first node N1. Simultaneously with the supply of the sensing data signal, a reference voltage may be supplied to the second node N2 by the turn-on operation of the third pixel transistor T3. Therefore, the storage capacitor Cst may store a voltage corresponding to a voltage difference between the sensing data signal SGV and the reference voltage.

[0096] Thereafter, when the supply of the scanning signal is stopped, the second pixel transistor T2 may be turned off. When the second pixel transistor T2 is turned off, the first node N1 may float. Therefore, the voltage of the second node N2 may increase, and thus, a sensing current may be generated by the first pixel transistor T1. The sensing current may be supplied to a sensing circuit (e.g., Figure 1 of 400).

[0097] In an embodiment, during the sensing period SP, the power management driver 500 may output a first voltage V1 of the first driving power VSS to the first driving power terminal PT1 in order to calculate the characteristic. For example, the first voltage V1 may be higher than a reference voltage (e.g., a voltage supplied to the second node N2 through the sensing line SSLj). In addition, the first voltage V1 may be set to a voltage higher than the second voltage V2.

[0098] In other words, the first voltage V1 may be set to a voltage higher than the voltage of the second node N2 so that the light emitting element LD does not emit light. Therefore, during the sensing period SP, the sensing current may flow through the sensing circuit 400 along the sensing line SSLj without flowing through the light emitting element LD.

[0099] In an embodiment, a transition period TP may be inserted between the display period DP and the sensing period SP. During the transition period TP, the power management driver 500 may be controlled so that the timing of outputting the first voltage V1 of the first driving power terminal PT1 does not overlap with the timing of outputting the second voltage V2.

[0100] Figure 4 The timing diagram indicates that the current supplied to the display period DP, the transition period TP and the sensing period SP Figure 2A or Figure 2B The signal of the pixel PXij is shown in the above reference Figure 3 The described operation schemes are substantially the same as the operation schemes. Therefore, repeated description thereof may be omitted.

[0101] Figure 5 A power management driver according to an exemplary embodiment of the present disclosure is shown.

[0102] Reference Figure 1 and Figure 5 , the power management driver 500 may include a first power source 520 , a second power source 540 , a controller 560 , and a short circuit detector 580 .

[0103] In an embodiment, the power management driver 500 may be mounted on the display device 1000 in the form of a driver IC. However, this is merely exemplary, and at least some of the components of the power management driver 500 may be directly formed on the display panel or may be included in the timing controller 600.

[0104] The first power source 520 may supply the voltage of the first driving power terminal PT1 to the first power line PL1. In an embodiment, the first power line PL1 may be coupled to a cathode electrode of the light emitting element LD included in the pixel PXij.

[0105] The first power supply 520 can supply the first voltage V1 of the first driving power terminal PT1 to the pixel PXij through the first power line PL1 in response to the first enable signal EN1 during the sensing period. In addition, the first power supply 520 can supply the second voltage V2 of the first driving power terminal PT1 to the pixel PXij through the first power line PL1 in response to the second enable signal EN2 during the display period.

[0106] In an embodiment, the first power supply 520 may convert the input power VIN supplied from an external power source (eg, a battery, etc.) into a first voltage V1 or a second voltage V2 of the first driving power terminal PT1. For example, the first power supply 520 may have a structure of a boost converter or an inverting buck-boost converter.

[0107] In an embodiment, the first power supply 520 may sequentially control the output of the first voltage V1 and the output of the second voltage V2 in response to the first enable signal EN1 and the second enable signal EN2. Figure 6 This operation is described in more detail.

[0108] The second power supply 540 can supply the voltage of the second driving power terminal PT2 (the voltage of the second driving power VDD) to the pixel PXij through the second power line PL2 in response to the third enable signal EN3. In an embodiment, the second power line PL2 can be coupled to the drain electrode of the first pixel transistor T1 (or driving transistor) of the pixel PXij.

[0109] The second driving power terminal PT2 may have a high potential direct current (DC) voltage. For example, the voltage of the second driving power terminal PT2 may be higher than the first voltage V1 and the second voltage V2. However, this is only exemplary, and the voltage of the second driving power terminal PT2 may be higher than the second voltage V2, but may be lower than or equal to the first voltage V1.

[0110] The second power source 540 may convert input power VIN supplied from an external power source (eg, a battery, etc.) into a voltage of the second driving power terminal PT2. For example, the second power source 540 may have a structure of a boost converter.

[0111] In an embodiment, the second driving power terminal PT2 may supply a voltage having a constant magnitude to the second power line PL2 regardless of the sensing period, the transition period, and the display period. However, this is merely exemplary, and the voltage level of the second driving power terminal PT2 may be changed if necessary.

[0112] The controller 560 may control the timing of outputting the first voltage V1 and the second voltage V2 respectively in response to the sensing control signal SCTL during the transition period. In an embodiment, the controller 560 may generate the first enable signal EN1 by delaying the sensing control signal SCTL, and may generate the second enable signal EN2 by inverting and delaying the sensing control signal SCTL.

[0113] In addition, the controller 560 may control the detection operation and / or protection operation of the short circuit detector 580. For example, the controller 560 may limit the output of a protection signal (or shutdown signal) based on short circuit detection during a masking period present in an initial stage of the sensing period.

[0114] According to an embodiment, the controller 560 may analyze a glitch (or noise) in the detection value detected by the short circuit detector 580, and then may determine whether to stop the driving of the power management driver 500. For example, when the time during which the noise in the detection value is detected is longer than a predetermined reference time (e.g., a noise ignoring time), the controller 560 may control the power management driver 500 so that the power management driver 500 is not shut down. In addition, when the time during which the noise is detected is shorter than or equal to the reference time, the power management driver 500 may be controlled so that such noise is ignored when controlling the power to be shut down.

[0115] The short circuit detector 580 can detect a short circuit in the second power line PL2 based on the current flowing through the output terminal (e.g., the second power line PL2) during the sensing period. Because the current (e.g., the sensing current) generated in the first pixel transistor T1 of the pixel PXij flows into the sensing line SSLj through the third pixel transistor T3 during the sensing period, a current path to the normal first power line PL1 is not formed, or alternatively, a very small amount of current flows through the first power line PL1.

[0116] However, when the first power line PL1 contacts or shorts with other lines, a current path may be formed through the short-circuit point. For example, a line for transmitting a scan signal of a logic high level (e.g., about 25V) or the like may be shorted to the first power line PL1. In this case, since the logic high level is higher than the output voltage of the first power source 520, a negative current sinking from the first power line PL1 to the first power source 520 may be detected.

[0117] In contrast, a line for transmitting a scan signal of a logic low level (e.g., about -10V) or the like may be shorted to the first power line PL1. In this case, since the logic low level is lower than the output voltage of the first power source 520, a positive current flowing from the output terminal of the first power source 520 to the first power line PL1 can be detected.

[0118] The short circuit detector 580 may extract such negative and positive currents, and may then output a protection signal for protecting the power management driver 500 and the display device 1000 based on a comparison result between the extracted value and the reference value. Based on the protection signal, driving of the power management driver 500 and / or the display device 1000 may be stopped or shut down.

[0119] Figure 6 Shows Figure 5 Example of a power management driver.

[0120] For ease of description, Figure 6 An embodiment is shown in which some components of the first power supply 520 and the controller 560 are implemented.

[0121] Reference Figure 5 and Figure 6 , the power management driver 500 may include a first power source 520 , a second power source 540 , a controller 560 , and a short circuit detector 580 .

[0122] The first power supply 520 may include a voltage determiner 525, a first switch SW1, and a second switch SW2. The first power supply 520 may supply a first voltage V1 to the first power line PL1 during a sensing period, and may supply a second voltage V2 to the first power line PL1 during a display period.

[0123] The voltage determiner 525 may determine the first voltage V1 based on the input power VIN. In an embodiment, the voltage determiner 525 may include a digital-to-analog converter (DAC) 522 and a voltage output circuit 524. However, this is merely exemplary, and the voltage determiner 525 may also include an additional boost converter component for generating a voltage of the first drive power terminal (i.e., a voltage of the first drive power VSS).

[0124] The DAC 522 may output a first voltage V1 having a voltage level corresponding to the driving condition based on the voltage of the input power VIN. For example, the first voltage V1 as an analog output may be determined based on an 8-bit digital input value.

[0125] The voltage output circuit 524 may temporarily store the first voltage V1 and then output the first voltage V1 to the output terminal OT. Figure 6 The buffer structure operated by the DC driving power VCC and outputting the input voltage and the structure in which the first switch SW1 is coupled are shown, but the present disclosure is not limited thereto. For example, the voltage output circuit 524 can also be implemented as a three-state or tri-state buffer, which also includes an enable terminal for turning on or off the connection between its input terminal and output terminal.

[0126] The first switch SW1 may be coupled between the voltage determiner 525 (e.g., the voltage output circuit 524) and the first power line PL1. The first switch SW1 may be turned on in response to the first enable signal EN1. When the first switch SW1 is turned on, the first voltage V1 may be supplied to the first power line PL1 through the predetermined node PN1. In an embodiment, the first switch SW1 may be implemented using various structures such as a bipolar junction transistor (BJT) and a field effect transistor (FET) (e.g., a metal oxide semiconductor field effect transistor (MOSFET)).

[0127] The second switch SW2 may be coupled between the first power line PL1 and a voltage source supplied with a second voltage V2. In an embodiment, the voltage source may be ground GND, and the second voltage V2 may be a voltage of ground GND. However, this structure is merely exemplary, and the magnitude of the second voltage V2 is not limited thereto. For example, as the second voltage V2, any voltage capable of ensuring stable driving of the pixel circuit PC and the light emitting element LD of the pixel PXij during the display period is sufficient. The second voltage V2 may be a predetermined negative voltage. Here, the pixel circuit PC may represent a voltage that is substantially the same as the voltage V2. Figure 2A or Figure 2B The transistors T1 , T2 , and T3 and the storage capacitor Cst in addition to the light emitting element LD in the configuration of the pixel PXij correspond to the configuration.

[0128] The second switch SW2 may be turned on in response to the second enable signal EN2 When the second switch SW2 is turned on, the first power line PL1 may be electrically coupled to the ground GND, and the voltage of the first driving power terminal may be set to the voltage of the ground GND.

[0129] In an embodiment, the second switch SW2 may include a first sub-transistor SST1 and a second sub-transistor SST2. The first sub-transistor SST1 and the second sub-transistor SST2 may be coupled in parallel between the node PN1 and the ground GND. The gate electrode of the first sub-transistor SST1 and the gate electrode of the second sub-transistor SST2 may commonly receive the second enable signal EN2.

[0130] In an embodiment, the controller 560 may include a first delay component 562 and a second delay component 564 .

[0131] The first delay component 562 may generate the first enable signal EN1 by delaying the sensing control signal SCTL. The sensing control signal SCTL may have an activation level (or a gate-on level) during the sensing period, and may have an inactivation level (or a gate-off level) during the display period. The first delay component 562 may control a time point at which the first enable signal EN1 is transitioned during the transition period.

[0132] The second delay component 564 may generate the second enable signal EN2 by inverting and delaying the sensing control signal SCTL. In an embodiment, the second delay component 564 may include an inverter that inverts the sensing control signal SCTL. The second delay component 564 may control the time point at which the second enable signal EN2 transitions during the transition period.

[0133] When the first switch SW1 and the second switch SW2 are turned on at the same time, the output terminal OT is electrically coupled to the ground GND. Therefore, the output of the voltage determiner 525 is provided to the ground GND through the node PN1, and thus an overcurrent may occur.

[0134] The on time and on timing of the first switch SW1 and the second switch SW2 can be controlled by driving the first delay component 562 and the second delay component 564. Therefore, the driving error in which the first switch SW1 and the second switch SW2 are turned on at the same time and the overcurrent (and heat generation) attributable to the driving error can be prevented.

[0135] Each of the first delay component 562 and the second delay component 564 may include components such as various types of known signal deformation circuits (or delay circuits) and shift registers.

[0136] Figure 7 Shows Figure 6 An example of the operation of a power management driver.

[0137] Reference Figure 1 , Figure 6 and Figure 7 , the first delay component 562 and the second delay component 564 can output the first enable signal EN1 and the second enable signal EN2, respectively, by controlling the sensing control signal SCTL.

[0138] The driving of the display device 1000 may include a display period DP, a sensing period SP, and a first transition period TP1 inserted between the display period DP and the sensing period SP.

[0139] In an embodiment, Figure 7 The driving scheme of the display device 1000 may be applied to a display-off or power-off operation of the display device 1000. For example, after the display operation has been terminated, sensing of the pixel PX may be performed. After the display period DP, the first transition period TP1 may be activated. For example, the first transition period TP1 may be a preparation period for sensing the pixel PX during the sensing period SP. The length of the first transition period TP1 may be set to about 60 μs. However, this is merely exemplary, and the length of the first transition period TP1 may be set according to the resolution, the size of the display device 1000, or the driving frequency, etc.

[0140] The sensing control signal SCTL may have a gate-on level during the sensing period SP and a gate-off level during the display period DP. Hereinafter, description will be made on the premise that a logic high level is the gate-on level.

[0141] During the display period DP, the first enable signal EN1 may have a gate-off level, and the second enable signal EN2 may have a gate-on level. During the display period DP, the first switch SW1 may be turned off, and the second switch SW2 may be turned on. Therefore, the source of the first driving power terminal may be coupled to the ground GND and may have a second voltage V2.

[0142] During the first transition period TP1 , the scan signal and the control signal are not supplied. In an embodiment, during the first transition period TP1 , after the second switch SW2 has been turned off, the first switch SW1 may be turned on.

[0143] The second enable signal EN2 may be changed from a gate-on level to a gate-off level at a first time point t1 of the first transition period TP1. Therefore, the second switch SW2 may remain turned on during a first period P1 of the first transition period TP1 and may be turned off at the first time point t1. For example, the length of the first period P1 may be set to 1 μs.

[0144] The second delay component 564 may delay the inverted signal of the sensing control signal SCTL to the first time point t1, and may output the delayed signal as the second enable signal EN2. Since the voltage of the first driving power terminal is maintained at the second voltage V2 during the first period P1, the display of the image may be stably performed during the display period DP.

[0145] The second enable signal EN2 may have a gate-off level in response to the sensing control signal SCTL during the sensing period SP.

[0146] Next, at the second time point t2, the first enable signal EN1 may be changed from the gate-off level to the gate-on level. The first switch SW1 may be turned on at the second time point t2. When the first switch SW1 is turned on, the voltage of the first driving power terminal may be output as the first voltage V1.

[0147] The first delay component 562 may delay the sensing control signal SCTL to a second time point t2 and may output the delayed signal as the first enable signal EN1. The first enable signal EN1 may have a gate-on level in response to the sensing control signal SCTL during the sensing period SP.

[0148] During the second period P2 between the first time point t1 and the second time point t2, both the first switch SW1 and the second switch SW2 may be turned off. The length of the second period P2 may be set to about 10 μs to 60 μs. Here, because the time during which the first switch SW1 and the second switch SW2 are turned off is very short, the first power line PL1 may be maintained at the second voltage V2.

[0149] That is, since the time point when the second switch SW2 is turned off is clearly separated from the time point when the first switch SW1 is turned on, heat generation and unnecessary power consumption that may occur when the output value from the output terminal OT is supplied to the ground GND can be prevented or minimized.

[0150] During the sensing period SP, the scan signal and the control signal may be supplied to the pixel PX again. In an embodiment, after the second time point t2, the sensing period SP may start. Therefore, during the third period P3, the voltage of the first driving power terminal may rise to the first voltage V1. Therefore, during the sensing period SP, the first voltage V1 of the first driving power terminal may be stably supplied.

[0151] However, this is merely exemplary, and the second time point t2 may be the same as the start point of the sensing period SP.

[0152] Figure 8 Shows Figure 6 An example of the operation of a power management driver.

[0153] Reference Figure 1 , Figure 6 , Figure 7 and Figure 8 , the first delay component 562 and the second delay component 564 can output the first enable signal EN1 and the second enable signal EN2, respectively, by controlling the sensing control signal SCTL.

[0154] In an embodiment, Figure 8 The driving scheme may also be applied to the display-on or power-on operation of the display device 1000. For example, before the display operation starts, sensing of the pixel PX may be performed. After the sensing period SP, the second transition period TP2 may be activated. For example, the second transition period TP2 may be a preparation period for displaying an image during the display period DP. The length of the second transition period TP2 may be set to about 60 μs. However, this is merely exemplary, and the length of the second transition period TP2 may be set according to the resolution, the size of the display device 1000, or the driving frequency, etc.

[0155] During the second transition period TP2 , the scan signal and the control signal are not supplied. In an embodiment, during the second transition period TP2 , after the first switch SW1 has been turned off, the second switch SW2 may be turned on.

[0156] The first enable signal EN1 may transition from a gate-on level to a gate-off level at a third time point t3 of the second transition period TP2. Therefore, the first switch SW1 may remain turned on during a fourth period P4 of the second transition period TP2, and may be turned off at a third time point t3.

[0157] In an embodiment, the length of the fourth period P4 may correspond to the sum of the length of the first period P1 and the length of the second period P2. The length of the fourth period P4 may correspond to the time when the first enable signal EN1 is delayed from the sensing control signal SCTL. The length of the fourth period P4 may be set to about 10 μs to 60 μs. However, this structure is only exemplary, and the length of the fourth period P4 is not limited thereto.

[0158] The first delay component 562 may delay the sensing control signal SCTL to a third time point t3 and may output the delayed signal as the first enable signal EN1. Since the voltage of the first driving power terminal is maintained at the first voltage V1 during the fourth period P4, the sensing operation may be stably performed during the sensing period SP.

[0159] Thereafter, at a fourth time point t4, the second enable signal EN2 may be changed from a gate-off level to a gate-on level. The second switch SW2 may be turned on at the fourth time point t4. When the second switch SW2 is turned on, the voltage of the first driving power terminal may be output as a second voltage V2.

[0160] The second delay component 564 may delay the inversion signal of the sensing control signal SCTL to a fourth time point t4 and may output the delayed signal as the second enable signal EN2 .

[0161] During the fifth period P5 between the third time point t3 and the fourth time point t4, both the first switch SW1 and the second switch SW2 may be turned off. The length of the fifth period P5 may be set to about 10 μs to 60 μs. Here, because the time when the first switch SW1 and the second switch SW2 are turned off is very short, the first power line PL1 may be maintained at the first voltage V1.

[0162] In an embodiment, after the fourth time point t4, the display period DP may start. Therefore, during the sixth period P6, the voltage of the first driving power terminal may drop to the second voltage V2.

[0163] That is, since the time point when the first switch SW1 is turned off and the time point when the second switch SW2 is turned on are clearly separated by the first and second transition periods TP1 and TP2, heat generation and unnecessary power consumption that may occur when the output of the output terminal OT is supplied to the ground GND can be prevented or minimized.

[0164] Fig. 9 Shown is included in Figure 6 Examples of short circuit detectors and controllers in power management drives, and Fig.10 Shows Fig. 9 An example of the operation of the short circuit detector and controller.

[0165] Reference Figure 6 , Fig. 9 and Fig.10 , the short circuit detector 580 may include a detection value extractor 582 and a protector 584 .

[0166] The detection value extractor 582 may extract a first detection value POSV based on a positive current flowing through the output terminal OT during the sensing period SP, and may extract a second detection value NEGV based on a negative current flowing through the output terminal OT. The first detection value POSV and the second detection value NEGV may be extracted as voltage values ​​or current values.

[0167] In an embodiment, the detection value extractor 582 may extract the first detection value POSV and the second detection value NEGV based on a positive current and / or a negative current flowing into the amplifier type voltage output circuit 524 .

[0168] During the display period DP, the first switch SW1 is turned off, and therefore, current detection and extraction by the detection value extractor 582 are not performed.

[0169] The protector 584 may be supplied with a first detection value POSV and a second detection value NEGV. The protector 584 may generate a protection signal PTS based on the first detection value POSV and the second detection value NEGV. In an embodiment, the protector 584 may compare the first detection value POSV with a first reference value REF1, and may compare the second detection value NEGV with a second reference value REF2.

[0170] When the first detection value POSV or the second detection value NEGV is greater than a predetermined reference, the protector 584 may determine that a short circuit has occurred in the first power line PL1 and may output a protection signal PTS. The protection signal PTS may be used to determine whether to drive the power management driver 500 and / or the display device (e.g., Figure 1 of 1000).

[0171] In the initial stage of the sensing period SP, due to the change in the voltage level of the first driving power terminal and the change in the driving of the pixel, the first detection value POSV and the second detection value NEGV may be in an unstable state. For example, in the initial stage of the sensing period SP, the first detection value POSV and the second detection value NEGV may contain unnecessary noise. Therefore, there is a possibility of erroneously determining that a short circuit has occurred due to noise.

[0172] In an embodiment, in order to prevent such a driving error, the controller 560 may limit the output of the protection signal PTS during the masking period MSP. For example, the controller may supply the masking signal MSS to the short circuit detector 580 during the first transition period TP1 and the masking period MSP. Fig.10 In the present invention, the mask signal MSS may be set to a gate-off level such as a logic low level in order to inactivate the operation of a predetermined component.

[0173] The masking period MSP may be a preset initial period of the sensing period SP. For example, the masking period MSP may be a period during which the current / voltage detected by the detection value extractor 582 and / or the protection signal PTS output by the protector 584 are suppressed or masked. The length of the masking period MSP may be set to about 1 ms to 5 ms.

[0174] The detection value extractor 582 does not extract the first detection value POSV and the second detection value NEGV in response to the mask signal MSS. Alternatively, the protector 584 may block the output of the protection signal PTS in response to the mask signal MSS.

[0175] As described above, the masking period MSP may be inserted into the initial stage of the sensing period SP, thereby improving the reliability of short circuit detection and the protective driving by the short circuit detector 580 may be improved.

[0176] Fig.11 Shown is included in Figure 6 Example of a short circuit detector in a power management driver.

[0177] Reference Figure 6 , Fig. 9 , Fig.10 and Fig.11 , the short circuit detector 580 may include a detection value extractor 582 and a protector 584 .

[0178] In an embodiment, the detection value extractor 582 may be configured in or coupled to the amplifier type voltage output circuit 524. The voltage output circuit 524 may include a comparator 5241, a first transistor M1, and a second transistor M2.

[0179] The comparator 5241 may compare the internal driving voltage V0 with the first voltage V1 output from the comparator 5241 and may output a voltage corresponding to a result of the comparison.

[0180] The first transistor M1 may be coupled between the source of the first DC power VCC1 and the output terminal OT. The second transistor M2 may be coupled between the output terminal OT and ground. The gate electrode of the first transistor M1 and the gate electrode of the second transistor M2 may be coupled to the output terminal of the comparator 5241. The first transistor M1 may be a PMOS transistor, and the second transistor M2 may be an NMOS transistor.

[0181] According to a result of comparison between the internal driving voltage V0 and the first voltage V1 by the comparator 5241 , one of the first transistor M1 and the second transistor M2 is turned on, and thus, the first voltage V1 having a constant voltage level may be output through the output terminal OT.

[0182] The detection value extractor 582 may include third to sixth transistors M3 to M6 and first and second resistors R1 and R2 .

[0183] The detection value extractor 582 may extract the first detection value POSV using a third transistor M3 coupled between the source of the first DC power VCC1 and the ground. A gate electrode of the third transistor M3 may receive the output voltage of the comparator 5241. In an embodiment, the third transistor M3 may be a PMOS transistor.

[0184] The first resistor R1 may be coupled between the third transistor M3 and ground.

[0185] When the third transistor M3 is turned on, a positive current flows into the ground through the third transistor M3 and the first resistor R1 , and the voltage of the first sensing node SN1 may be extracted as the first detection value POSV.

[0186] In an embodiment, the size of the third transistor M3 may be smaller than that of the first transistor M1. For example, the channel length of the third transistor M3 may be shorter than that of the first transistor M1. Therefore, the positive current may be converted into a value corresponding to the ratio of the channel length and the value may be extracted.

[0187] The detection value extractor 582 may extract the second detection value NEGV using the fourth to sixth transistors M4 to M6 .

[0188] The fourth transistor M4 may be coupled between the source of the second DC power VCC2 and the sixth transistor M6, and the fifth transistor M5 may be coupled between the source of the second DC power VCC2 and the second resistor R2. The gate electrode of the fourth transistor M4 and the gate electrode of the fifth transistor M5 may be coupled to each other, and the gate electrode and the drain electrode of the fourth transistor M4 may be coupled to each other. That is, the fourth transistor M4 and the fifth transistor M5 may be coupled in a current mirror structure. In an embodiment, the fourth transistor M4 and the fifth transistor M5 may be PMOS transistors.

[0189] The sixth transistor M6 may be coupled between the fourth transistor M4 and the ground, and may include a gate electrode coupled to the output terminal of the comparator 5241. The sixth transistor M6 may be an NMOS transistor.

[0190] When the second transistor M2 and the sixth transistor M6 are turned on, a negative current or a current obtained by reducing the negative current at a predetermined rate can flow through the second sensing node SN2 by driving the current mirror composed of the fourth transistor M4 and the fifth transistor M5. Therefore, the voltage of the second sensing node SN2 can be extracted as the second detection value NEGV.

[0191] In an embodiment, the size of the fourth transistor M4 and the size of the fifth transistor M5 may be smaller than the size of the second transistor M2. For example, the channel length of the fourth transistor M4 and the channel length of the fifth transistor M5 may be shorter than the channel length of the second transistor M2. In addition, the channel length of the fourth transistor M4 and the channel length of the fifth transistor M5 may be the same as or different from each other. Therefore, the size of the negative current can be controlled according to the ratio of the channel lengths.

[0192] Meanwhile, the voltage level of the first DC power VCC1 and the voltage level of the second DC power VCC2 may be the same as or different from each other.

[0193] When a short circuit occurs in the first power line PL1 , the absolute value of the first detection value POSV and / or the absolute value of the second detection value NEGV may increase due to the occurrence of an overcurrent.

[0194] The protector 584 may include a first comparator 5841 , a second comparator 5842 , a logical OR operation component 5843 , and a switch 5844 .

[0195] The first comparator 5841 may compare the first detection value POSV with the first reference value REF1, and may output a first result CR1. When the first detection value POSV is greater than the first reference value REF1, it may be determined that a short circuit has occurred between the first power line PL1 and a line for transmitting a voltage higher than the first voltage V1. Here, the first result CR1 may have a first level (e.g., a logic high level). When the first detection value POSV is less than or equal to the first reference value REF1, the first result CR1 may have a second level (e.g., a logic low level).

[0196] The second comparator 5842 may compare the second detection value NEGV with the second reference value REF2, and may output a second result CR2. When the magnitude (or absolute value) of the second detection value NEGV is greater than the second reference value REF2, it may be determined that a short circuit has occurred between the first power line PL1 and a line for transmitting a voltage lower than the first voltage V1. Here, the second result CR2 may have a first level (e.g., a logic high level). When the absolute value of the second detection value NEGV is less than or equal to the second reference value REF2, the second result CR2 may have a second level (e.g., a logic low level).

[0197] The logical OR operation component 5843 may generate a protection signal PTS based on the result of the logical OR operation of the first result CR1 and the second result CR2. In an embodiment, when at least one of the first result CR1 and the second result CR2 has a first level, the logical OR operation component 5843 may output the protection signal PTS (or a protection signal having a logic high level). In contrast, when both the first result CR1 and the second result CR2 have a second level, the logical OR operation component 5843 does not output the protection signal PTS (optionally, outputs the protection signal PTS having a logic low level).

[0198] In an embodiment, the switch 5844 may control the output of the protection signal PTS in response to the mask signal MSS during the sensing period SP. That is, the switch 5844 may be turned off by the output of the mask signal MSS (or the output of the mask signal MSS having a gate-off level). Therefore, during the mask period MSP, the output of the protection signal PTS may be blocked.

[0199] Fig.12 Shown is included in Figure 6 An example of a controller in a power management drive, and Fig.13 Shows Fig.12 An example of an action for a controller.

[0200] Reference Figure 1 , Figure 6 , Fig.12 and Fig.13 , the controller 560 may include a counting controller 566 and a shutdown controller 568 .

[0201] The shutdown controller 568 may count the time during which the protection signal PTS is output. For example, the shutdown controller 568 may include a counter that counts the period during which the gate-on level of the protection signal PTS is output.

[0202] When the count value is greater than the preset shutdown reference time REFT, the shutdown controller 568 may output the protection signal PTS as the shutdown signal SDS. For example, counting may be performed at intervals of 1 ms, and the shutdown reference time REFT may be set to about 5 ms. Therefore, when the protection signal PTS having the gate-on level is output for a time of 5 ms, the shutdown signal SDS may be output, and driving for protecting the power management driver 500 or the display device 1000 from the influence of overcurrent may be performed. According to an embodiment, the shutdown signal SDS may shut down the operation of the power management driver 500 or the display device 1000.

[0203] The count controller 566 may generate a reset signal RST for resetting the count value based on a first glitch time, which is a time during which a glitch in the first detection value POSV is detected. The reset signal RST may be provided to the shutdown controller 568 .

[0204] In addition, the count controller 566 may generate a reset signal RST based on a second glitch time which is a time during which a glitch in the second detection value NEGV is detected.

[0205] The first glitch time may correspond to a time during which noise in the first detection value POSV is output. Fig.13 As shown in , the first glitch time may be defined as a period GT1 or GT2 during which the first detection value POSV drops below the first reference value REF1. Similarly, the second glitch time during which the noise in the second detection value NEGV is output may be defined as a period during which the second detection value NEGV drops below the second reference value REF2.

[0206] During short circuit detection, the sensitivity and accuracy of short circuit detection may be degraded due to noise including glitches, etc. The count controller 566 may control the output of the reset signal RST based on the length of time during which the noise occurs. That is, the count controller 566 may determine whether the respective states of the first detection value POSV and the second detection value NEGV are in an overcurrent state or in a temporary state attributable to noise, etc.

[0207] In an embodiment, when the first glitch time is greater than the preset noise ignoring time NIT (for example, this relationship is Fig.13 When the noise ignoring time NIT is 0.5 ms, the count controller 566 may generate a reset signal RST. For example, the noise ignoring time NIT may be set to about 0.5 ms. The shutdown controller 568 may reset the count value in response to the reset signal RST.

[0208] In an embodiment, when the first glitch time is less than or equal to the noise ignoring time NIT (for example, this relationship is Fig.13 When the first glitch time is less than or equal to the noise ignoring time NIT, the corresponding glitch or noise can be ignored. Therefore, the shutdown controller 568 can maintain the counting operation. When the count value corresponds to the shutdown reference time REFT (for example, this is Fig.13 When t6 is indicated in the figure, a shutdown signal SDS may be output.

[0209] Similarly, the count controller 566 may determine whether to output the reset signal RST according to a comparison result between the second glitch time and the noise ignoring time NIT.

[0210] In this way, the controller 560 can identify glitches and noise in the first detection value POSV and the second detection value NEGV detected during the sensing period, and can perform a protection function related to short circuit detection (overcurrent detection), thereby improving the reliability of short circuit detection.

[0211] As described above, the power management driver 500 and the display device 1000 having the power management driver 500 according to the embodiment of the present disclosure can clearly separate the turn-off time point of the first switch SW1 from the turn-on time point of the second switch SW2 through the transition period between the display period and the sensing period. Therefore, it is possible to prevent or minimize heat generation and unnecessary power consumption that may occur when the first driving power having the first voltage V1 is supplied to the ground GND during the sensing period.

[0212] In addition, protection functions related to short circuit detection and / or overcurrent detection can be performed in a manner such that a masking period is inserted into the initial stage of a sensing period, and glitches and noise in the detection values ​​POSV and NEGV detected during the sensing period are identified or removed, thereby improving the sensitivity and reliability of the functions of detecting a short circuit in the first power line PL1 and protecting the first power line PL1.

[0213] The embodiments of the present disclosure are not limited to the foregoing, and can be expanded in various ways without departing from the spirit and scope of the present disclosure. For example, detectable faults are not limited to short circuit faults, but can include other faults based on detectable impedance changes, such as, for example, short circuit faults, reduced but non-zero impedance faults, increased but non-infinite impedance faults, and open circuit faults. In addition, the transition period can be after the display period and before the next sensing period and / or after the sensing period and before the next display period, but is not limited.

[0214] Although exemplary embodiments of the present disclosure have been described, it will be appreciated by those skilled in the relevant art that the present disclosure may be modified and changed in various forms without departing from the scope or spirit of the disclosure as set forth in the appended claims and their equivalents.

Claims

1. A power management driver, wherein: The power management driver comprises: a power supply that supplies a first voltage to a driving power terminal of a pixel through a power line during a sensing period, and that supplies a second voltage to the driving power terminal of the pixel through the power line during a display period; and a controller coupled to the power supply to generate a first enable signal and a second enable signal, Wherein, the power supply comprises: a digital-to-analog converter that outputs the first voltage based on input power; A first switch coupled between the digital-to-analog converter and the power line, the first switch being turned on in response to the first enable signal; and The second switch is coupled between the power line and a voltage source supplied with the second voltage, and the second switch is turned on in response to the second enable signal.

2. The power management driver of claim 1, wherein: Prior to the sensing period, the first enable signal enables the first transition after the second enable signal disables the second transition.

3. The power management driver according to claim 2, wherein: The sensing period is after the display period, and The first transition and the second transition occur in a transition period between the display period and the sensing period.

4. The power management driver of claim 1, wherein: Prior to the display period, after the first enable signal disables the second transition, the second enable signal enables the first transition.

5. The power management driver of claim 4, wherein: The display period is after the sensing period, and The first transition and the second transition occur in a transition period between the sensing period and the display period.

6. The power management driver of claim 1, wherein: The controller is configured to generate the first enable signal and the second enable signal in response to a sensing control signal that causes transitions to be enabled prior to the sensing period.

7. The power management driver of claim 1, wherein: The power management driver further comprises: a first delay component that generates the first enable signal by delaying a sensing control signal, and the first delay component supplies the first enable signal to the first switch during the sensing period; and A second delay component generates the second enable signal by inverting and delaying the sensing control signal, and the second delay component supplies the second enable signal to the second switch during the display period.

8. The power management driver of claim 7, wherein: When the sensing period is performed after the display period, during a first transition period between the display period and the sensing period, the first enable signal is transitioned from the gate-off level to the gate-on level after the second enable signal has been transitioned from the gate-on level to the gate-off level.

9. The power management driver of claim 8, wherein: When the display period is performed after the sensing period, during a second transition period between the sensing period and the display period, after the first enable signal has been changed from the gate-on level to the gate-off level, the second enable signal is changed from the gate-off level to the gate-on level.

10. The power management driver of claim 1, wherein: The power management driver further comprises: A fault detector includes a detection value extractor and is configured to detect a current flowing through the power line during the sensing period to detect a fault in the power line.

11. The power management driver of claim 10, wherein: The fault detector is coupled to the power line through the first switch.

12. The power management driver of claim 10, wherein: The detection value extractor is configured to extract at least one of a first detection value and a second detection value based on a positive current or a negative current flowing through the power line during the sensing period, and Wherein, the fault detector further comprises: A protector is connected to the detection value extractor to generate a protection signal based on the first detection value and the second detection value.

13. The power management driver of claim 1, wherein: The second voltage is a ground voltage, and the first voltage is higher than the second voltage.

14. The power management driver of claim 1, wherein: The power management driver further comprises: Another power source supplies a voltage of a second driving power to the pixel during the sensing period and the display period.

15. A display device, wherein: The display device comprises: a pixel coupled to the data line and the sensing line; a data driver that supplies an image data signal to the data line during a display period, and that supplies a sensing data signal to the data line during a sensing period; a sensing circuit that senses a characteristic of a driving transistor included in the pixel based on a sensing current flowing through the sensing line during the sensing period; and a power management driver connected to a driving power terminal of the pixel, Wherein, the power management driver comprises: a power supply that supplies a first voltage to the driving power terminal of the pixel through a power line during the sensing period, and that supplies a second voltage to the driving power terminal of the pixel through the power line during the display period; and a controller coupled to the power supply to generate a first enable signal and a second enable signal, Wherein, the power supply comprises: a digital-to-analog converter that outputs the first voltage based on input power; A first switch coupled between the digital-to-analog converter and the power line, the first switch being turned on in response to the first enable signal; and The second switch is coupled between the power line and a voltage source supplied with the second voltage, and the second switch is turned on in response to the second enable signal.

16. The display device according to claim 15, wherein: Prior to the sensing period, the first enable signal enables the first transition after the second enable signal disables the second transition.

17. The display device according to claim 16, wherein: The sensing period is after the display period, and The first transition and the second transition occur in a transition period between the display period and the sensing period.

18. The display device according to claim 15, wherein: Prior to the display period, after the first enable signal disables the second transition, the second enable signal enables the first transition.

19. The display device according to claim 18, wherein: The display period is after the sensing period, and The first transition and the second transition occur in a transition period between the sensing period and the display period.

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