Display device

Abstract

One aspect of the present disclosure provides a display device including a substrate having a plurality of pixel regions; a plurality of pixels disposed in the plurality of pixel regions, and each including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a reserved sub-pixel; first light emitting elements disposed in the first sub-pixel and the reserved sub-pixel, respectively; second light emitting elements disposed in the second sub-pixel and the reserved sub-pixel, respectively; and a third light emitting element disposed in the third sub-pixel and the reserved sub-pixel, respectively, in which the first light emitting element, the second light emitting element, and the third light emitting element are disposed on different layers in the reserved sub-pixel.

Description

Technical Field

[0001] The present disclosure relates to display devices, and more particularly, for example but not limited to, to display devices using light emitting diodes (LEDs). Background Art

[0002] As display devices used for monitors of computers, televisions, mobile phones, and the like, there are organic light emitting displays (OLEDs) configured to emit light autonomously and liquid crystal displays (LCDs) requiring a separate light source.

[0003] The application range of the display device is various, ranging from computer monitors and televisions to personal mobile devices, and research is being conducted on display devices having a wide display area and having reduced volume and weight.

[0004] In addition, recently, a display device including a light emitting diode (LED) that can be made of an inorganic material has attracted attention as a next-generation display device. Because LEDs are made of inorganic materials rather than organic materials, LEDs are more reliable and have a longer life than liquid crystal display devices or organic light emitting display devices. In addition, LEDs can be turned on or off quickly, have excellent luminous efficiency, high impact resistance, and high stability, and display high-brightness images.

[0005] The description provided in this Background section should not be assumed to be prior art merely because it is mentioned in or related to the Background section.The Background section may include information that describes one or more aspects of the subject technology. Summary of the invention

[0006] An aspect of the present disclosure is to provide a transparent display device having improved transmittance.

[0007] Another aspect of the present disclosure is to provide a display device including a reserved sub-pixel for repairing a defective light emitting element.

[0008] Yet another aspect of the present disclosure is to repair multiple sub-pixels by using a single reserved sub-pixel.

[0009] Yet another aspect of the present disclosure is to provide a display device, wherein a plurality of light emitting elements disposed in a reserved sub-pixel are vertically stacked to reduce an area of ​​the reserved sub-pixel.

[0010] Yet another aspect of the present disclosure is to provide a display device in which an area of ​​a reserved sub-pixel is reduced to maximize or increase an area of ​​a transmission region.

[0011] Yet another aspect of the present disclosure is to provide a display device in which a high-density driving current is provided to a light-emitting element to improve the light-emitting efficiency of the light-emitting element.

[0012] Yet another aspect of the present disclosure is to provide a display device capable of displaying high-resolution images.

[0013] Aspects of the present disclosure are not limited to the above-mentioned aspects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0014] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a display device includes a substrate having a plurality of pixel regions; a plurality of pixels, the plurality of pixels being arranged in the plurality of pixel regions and each including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a reserved sub-pixel; a first light-emitting element, which is arranged in the first sub-pixel and the reserved sub-pixel, respectively; a second light-emitting element, which is arranged in the second sub-pixel and the reserved sub-pixel, respectively; and a third light-emitting element, which is arranged in the third sub-pixel and the reserved sub-pixel, respectively, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element are arranged on different layers in the reserved sub-pixel. Therefore, the plurality of light-emitting elements arranged in the reserved sub-pixel are vertically stacked, which can reduce the area of ​​the reserved sub-pixel.

[0015] Additional details of illustrative embodiments are included in the detailed description and accompanying drawings.

[0016] According to the present disclosure, a transparent display device with improved transmittance can be realized.

[0017] According to the present disclosure, among the components of the display device, opaque components may be disposed to overlap with each other, thereby ensuring a maximum area or an increased area of ​​a transmission region of the display device.

[0018] According to the present disclosure, a plurality of sub-pixels may be repaired by using reserved sub-pixels.

[0019] According to the present disclosure, a plurality of sub-pixels may be repaired by using one reserved sub-pixel.

[0020] According to the present disclosure, a plurality of light emitting elements disposed in a reserved sub-pixel are vertically stacked, which can reduce the area of ​​the reserved sub-pixel.

[0021] According to the present disclosure, the area of ​​the transmission region may be maximized or increased by reducing the area of ​​the reserved sub-pixel.

[0022] According to the present disclosure, the light emission efficiency of the light emitting element can be improved by supplying a high-density driving current to the light emitting element.

[0023] According to the present disclosure, a high-resolution display device can be realized.

[0024] The effects according to the present disclosure are not limited to the contents of the above examples, and more various effects are included in the present disclosure.

[0025] It is to be understood that both the foregoing description and the following description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which may be included to provide a further understanding of the disclosure and may be incorporated in and constitute a part of this disclosure, illustrate embodiments of the disclosure and together with the description serve to explain various principles of the disclosure.

[0027] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 2B is a perspective view of a spliced ​​display device according to an example embodiment of the present disclosure;

[0031] Figure 3A is a schematic enlarged top plan view of a display area of ​​a display device according to an example embodiment of the present disclosure;

[0032] Figure 3B is a schematic configuration diagram of a pixel of a display device according to an example embodiment of the present disclosure;

[0033] Figure 4 is an enlarged top plan view of a display area of ​​a display device according to an example embodiment of the present disclosure;

[0034] Figures 5 to 7 is a cross-sectional view of a plurality of sub-pixels of a display device according to an example embodiment of the present disclosure;

[0035] Figure 8 is a cross-sectional view of a reserved sub-pixel of a display device according to an example embodiment of the present disclosure; and

[0036] Fig. 9 and Fig.10 is a cross-sectional view of a welding region of a display device according to an example embodiment of the present disclosure.

[0037] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures.The size, length, and thickness of layers, regions, and elements and their illustrations may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, when a detailed description of a well-known function or configuration associated with this document is determined to be unnecessary to obscure the gist of the inventive concept, its detailed description will be omitted or briefly provided. The described progression of processing steps and / or operations is an example; however, the order of steps and / or operations is not limited to the order set forth herein, and may be changed as known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals designate similar elements throughout the text. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification, and therefore may be different from the names used in the actual product.

[0039] By referring to the following and attached Figure 1 The advantages and features of the present disclosure and the methods for achieving the advantages and features will become clear from the exemplary embodiments described in detail. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0040] The shapes, sizes, areas, proportions, angles, quantities, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Similar reference numerals generally refer to similar elements throughout the present disclosure. In addition, in the following description of the present disclosure, a detailed explanation of known related technologies may be omitted or briefly provided to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," "comprising," and "consisting of" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only." Unless otherwise expressly stated, any reference to the singular may include the plural.

[0041] Even if not expressly stated, the components are interpreted as including ordinary margins of error.

[0042] When describing a positional relationship, for example, when using "on", "above", "below", "over", "under", "down", "adjacent", "close to", or "adjacent", "beside", "next to", etc. to describe the positional relationship between two components, one or more other components may be arranged between the two components, unless more restrictive terms such as "immediately", "directly" or "closely" are used. For example, when a structure is described as being located "on", "above", "below", "above", "below", "below", "adjacent to" another structure, "close to" another structure, or "adjacent to" another structure, "beside", "next to" another structure, this description should be interpreted as including the situation where the structures are in contact with each other and the situation where a third structure is arranged or inserted therebetween. In addition, the terms "left", "right", "top", "bottom", "downward", "upward", "up", "down", etc. refer to an arbitrary reference system.

[0043] When an element or layer is disposed “on” another element or layer, the other layer or element may be directly on or between the other element or layer.

[0044] Although the terms "first", "second", "A", "B", "(a)", "(b)", etc. are used to describe various components, these components are not subject to these terms. These terms are only used to distinguish one component from another. Therefore, in the technical concept of the present disclosure, the first component mentioned below may be the second component. In addition, when an element or layer is described as being "connected", "coupled" or "adhered" to another element or layer, the element or layer may not only be directly connected or adhered to the other element or layer, but may also be indirectly connected or adhered to the other element or layer with one or more intermediate elements or layers "arranged" between the elements or layers, unless otherwise specified.

[0045] Like reference numerals generally refer to like elements throughout this disclosure.

[0046] The size and thickness of each component shown in the drawings are exemplified for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0047] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of a first element, a second element, and a third element" covers the combination of all three listed elements, the combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0048] The features of various embodiments of the present disclosure may be adhered to or combined with each other in part or in whole, and may be connected and operated in various technical ways, and the embodiments may be implemented independently or in association with each other.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "component" or "unit" may apply, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as will be understood by one of ordinary skill in the art.

[0050] The transistor used in the display device according to the exemplary embodiment of the present disclosure can be implemented as any one of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor can be implemented as an oxide semiconductor transistor having an oxide semiconductor as an active layer, or a low temperature polysilicon (LTPS) transistor having LTPS as an active layer. The transistor may include at least a gate electrode, a source electrode, and a drain electrode. The transistor may be implemented as a thin film transistor (TFT) on a display panel. The carriers in the transistor flow from the source electrode to the drain electrode. In the case of an n-channel transistor (NMOS), since the carriers are electrons, the source voltage may be lower than the drain voltage, so that the electrons can flow from the source electrode to the drain electrode. In an n-channel transistor (NMOS), the current can flow from the drain electrode to the source electrode, and the source electrode may be an output terminal. In the case of a p-channel transistor (PMOS), since the carriers are holes, the source voltage may be higher than the drain voltage, so that the holes can flow from the source electrode to the drain electrode. Since holes flow from the source electrode to the drain electrode in a p-channel transistor (PMOS), current can flow from the source electrode to the drain electrode, and the drain electrode can be an output terminal. Therefore, it should be noted that since the source and drain can change according to the applied voltage, the source and drain of the transistor are not fixed. In the present disclosure, the description is made by assuming that the transistor is an n-channel transistor (NMOS), but the present disclosure is not limited to this, but a p-channel transistor can be used, and therefore the circuit configuration can also be changed.

[0051] The gating signal of the transistor used as a switching element can swing between a gate-on voltage and a gate-off voltage. The gate-on voltage can be set to a voltage higher than the threshold voltage Vth of the transistor, and the gate-off voltage can be set to a voltage lower than the threshold voltage Vth of the transistor. The transistor is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage. In the case of an n-channel transistor (NMOS), the gate-on voltage can be a gate high voltage (VGH), and the gate-off voltage can be a gate low voltage (VGL). In the case of a p-channel transistor (PMOS), the gate-on voltage can be a gate low voltage (VGL), and the gate-off voltage can be a gate high voltage (VGH).

[0052] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a schematic configuration diagram of a display device according to an embodiment of the present disclosure. For ease of description, Figure 1 Only the display panel PN, the gate driving part GD, the data driving part DD, and the timing controller TC are illustrated among various constituent elements of the display device 100 .

[0054] Reference Figure 1 The display device 100 includes: a display panel PN, the display panel PN includes a plurality of sub-pixels SP; a data driving part DD and a gate driving part GD, the data driving part DD and the gate driving part GD are configured to provide various types of signals to the display panel PN; and a timing controller TC, the timing controller TC is configured to control the gate driving part GD and the data driving part DD.

[0055] The gate driving part GD supplies a plurality of scan signals to the plurality of scan lines SL in response to a plurality of gate control signals supplied from the timing controller TC. Figure 1 It is illustrated that a single gate driver GD is disposed to be spaced apart from one side of the display panel PN. However, the number and arrangement of the gate driver GD are not limited thereto. For example, the gate driver GD may be disposed on one or both sides of the display panel PN in a gate-in-panel (GIP) manner, or may be disposed in a display area of ​​the display panel PN in a gate-in-display-area (GIA) manner, and the present disclosure is not limited thereto.

[0056] The data driving part DD supplies data voltages to the plurality of data lines DL in response to a plurality of data control signals and image data supplied from the timing controller TC. The data driving part DD may convert the image data into data voltages by using reference gamma voltages and supply the converted data voltages to the plurality of data lines DL.

[0057] The timing controller TC aligns image data input from the outside and provides the image data to the data driving part DD. The timing controller TC can generate a gate control signal and a data control signal by using a synchronization signal (e.g., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal input from the outside). In addition, the timing controller TC can control the gate driving part GD and the data driving part DD by providing the generated gate control signal and data control signal to the gate driving part GD and the data driving part DD, respectively.

[0058] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL may cross each other, and a plurality of sub-pixels SP may be formed at intersections between the scan lines SL and the data lines DL.

[0059] A display area AA and a non-display area NA may be defined on the display panel PN.

[0060] The display area AA is an area of ​​the display device 100 that displays an image. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels PX, and a pixel circuit configured to operate the plurality of sub-pixels SP. The plurality of sub-pixels SP are the smallest units constituting the display area AA. n sub-pixels SP may constitute a single pixel PX. Thin film transistors and the like for operating the plurality of light-emitting elements 120 may be respectively arranged in the plurality of sub-pixels SP. The plurality of light-emitting elements 120 may be differently defined according to the type of the display panel PN. For example, in the case where the display panel PN is an inorganic light-emitting display panel PN, the light-emitting element 120 may be a light-emitting diode (LED) or a micro light-emitting diode (micro LED).

[0061] A plurality of signal lines for transmitting various types of signals to a plurality of sub-pixels SP are provided in the display area AA. For example, the plurality of signal lines may include a plurality of data lines DL for providing data voltages to the plurality of sub-pixels SP and a plurality of scan lines SL for providing scan signals to the plurality of sub-pixels SP. The plurality of scan lines SL may extend in one direction in the display area AA and be connected to the plurality of sub-pixels SP. The plurality of data lines DL may extend in a direction different from a direction in which the scan lines extend in the display area AA and be connected to the plurality of sub-pixels SP. In addition, a low potential power line VSS, a high potential power line VDD, etc. may also be provided in the display area AA. However, the present disclosure is not limited thereto.

[0062] The non-display area NA may be defined as an area where an image is not displayed, for example, an area adjacent to and extending from the display area AA. The non-display area NA may include link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include driver ICs such as a gate driver IC and a data driver IC.

[0063] In addition, the non-display area NA may be located on the rear surface of the display panel PN (eg, a surface where the sub-pixels SP do not exist). Alternatively, the non-display area NA may be excluded. However, the present disclosure is not limited to the configurations shown in the drawings.

[0064] In addition, the driving parts such as the gate driving part GD, the data driving part DD and the timing controller TC can be connected to the display panel PN in various ways. For example, the gate driving part GD can be installed in the non-display area NA by a gate in panel (GIP) method, or installed between the plurality of sub-pixels SP in the display area AA by a gate in display area (GIA) method.

[0065] For example, the data driving part DD and the timing controller TC may be formed on separate flexible films and printed circuit boards, and the display panel PN, the data driving part DD, and the timing controller TC may be electrically connected by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0066] As another example, in the case where the gate driver GD is installed in the display area AA by the GIA method and the side line SRL connects the signal line on the front surface of the display panel PN to the pad electrode on the rear surface of the display panel PN (the pad electrode is formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN), the non-display area NA on the front surface of the display panel PN can be reduced. Therefore, in the case where the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN by the above method, a zero frame in which there is substantially no frame can be achieved. Referring to Figure 2A and Figure 2B Describes a more detailed description.

[0067] Figure 2A is a partial cross-sectional view of a display device according to an embodiment of the present disclosure. Figure 2B is a stereoscopic view of a spliced ​​display device according to an embodiment of the present disclosure.

[0068] A plurality of pad electrodes for transmitting various types of signals to a plurality of sub-pixels SP are disposed in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 configured to transmit signals to a plurality of sub-pixels SP is disposed in the non-display area NA on the front surface of the display panel PN. A second pad electrode PAD electrically connected to a driving component such as a flexible film and a printed circuit board is disposed in the non-display area NA on the rear surface of the display panel PN.

[0069] In this case, although not shown in the drawings, various types of signal lines (eg, scan lines SL, data lines DL, etc.) connected to the plurality of sub-pixels SP may extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0070] In addition, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal received from a driving component on the rear surface of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, the driving component is disposed on the rear surface of the display panel PN, and a signal transmission route is defined between the front surface and the rear surface of the display panel PN, which may minimize or reduce the area of ​​the non-display area NA on the front surface of the display panel PN.

[0071] In addition, refer to Figure 2B , a spliced ​​display device TD having a large screen can be realized by connecting or combining a plurality of display devices 100. In this case, Figure 2A As shown, when the spliced ​​display device TD is implemented using the display device 100 with a minimized frame, the seam area between the display devices 100 where no image is displayed can be minimized or reduced, thereby improving the display quality.

[0072] For example, one pixel PX may include a plurality of sub-pixels SP. An interval D1 between an outermost peripheral pixel PX of one display device 100 and an outermost peripheral pixel PX of another display device 100 adjacent to the one display device 100 may be implemented to be equal to an interval D1 between pixels PX in one display device 100. Therefore, as a constant interval of pixels PX is implemented between display devices 100 and display devices 100, a seam area may be minimized or reduced.

[0073] However, if Figure 2A and Figure 2B As shown, the display device 100 according to the embodiment of the present disclosure may be a general display device in which a frame exists. However, the present disclosure is not limited thereto.

[0074] In the following, reference will be made to FIG. 3A to FIG. 10 The display panel PN of the display device 100 according to the embodiment of the present disclosure is described in more detail.

[0075] Figure 3A is a schematic enlarged top plan view of a display area of ​​a display device according to an embodiment of the present disclosure. Figure 3B is a schematic configuration diagram of a pixel of a display device according to an embodiment of the present disclosure. Figure 4 is an enlarged top plan view of a display area of ​​a display device according to an embodiment of the present disclosure. Figures 5 to 7 is a cross-sectional view of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. Figure 8 is a cross-sectional view of a reserved sub-pixel of a display device according to an embodiment of the present disclosure. Fig. 9 and Fig.10 is a cross-sectional view of a welding area of ​​a display device according to an embodiment of the present disclosure. Specifically, Figures 5 to 7 is a cross-sectional view of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Fig. 9 and Fig.10 are cross-sectional views of the welding area WA before and after the welding process.

[0076] Reference Figure 3A and Figure 3B , the display area AA has a pixel area UPA, a pixel PX is formed in the pixel area UPA, and a transmission area TA is configured to surround the pixel area UPA. The display area AA includes a plurality of pixel areas UPA and a plurality of transmission areas TA. However, the present disclosure is not limited thereto, and a plurality of transmission areas TA may be omitted from the display device of the present application.

[0077] A pixel circuit including a driving element and a light emitting element 120 operated by the pixel circuit are formed in the pixel PX in the display area AA, so that a plurality of pixel areas UPA forming the pixel PX may be substantially opaque areas, and a plurality of transmission areas TA not forming the pixel PX may be substantially transparent areas. In this case, the pixel area UPA defined as having the pixel PX is an area in which the light emitted from the light emitting element 120 is displayed. Therefore, the pixel area UPA may be defined as a light emitting area. In addition, the pixel area UPA defined as having the pixel PX is an area in which a pixel circuit including a driving element is formed. Therefore, the pixel area UPA may also be defined as a circuit area.

[0078] The pixel area UPA is an area in which the driving element and the light emitting element 120 are arranged to display an image. A plurality of pixel areas UPA may be arranged to be spaced apart from each other with the transmission area TA interposed therebetween. For example, a plurality of pixel areas UPA may be arranged in a plurality of rows and columns.

[0079] A pixel PX including a plurality of sub-pixels SP and a plurality of reserved sub-pixels SPA is disposed in each of a plurality of pixel areas UPA. The plurality of sub-pixels SP may each include a light emitting element 120 and a pixel circuit and emit light independently. For example, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit light beams of different colors. For example, the first sub-pixel SP1 may be a red sub-pixel SP, the second sub-pixel SP2 may be a green sub-pixel SP, and the third sub-pixel SP3 may be a blue sub-pixel SP. However, the present disclosure is not limited thereto. For example, sub-pixels of different colors within a pixel PX may have different arrangements.

[0080] The reserved sub-pixel SPA is a sub-pixel SP configured to be used when any one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 among the plurality of sub-pixels SP is defective. For example, the reserved sub-pixel SPA can be used to repair the defective sub-pixel SP. The reserved sub-pixel SPA may include a plurality of light-emitting elements 120 and be used as any one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. When a defective sub-pixel SP occurs, one of the plurality of light-emitting elements 120 of the reserved sub-pixel SPA may be electrically connected to the driving transistor DT of the defective sub-pixel SP and operate.

[0081] For example, refer to Figure 3B , the red light emitting element 120R can be set in the first sub-pixel SP1, the green light emitting element 120G can be set in the second sub-pixel SP2, the blue light emitting element 120B can be set in the third sub-pixel SP3, and all the red light emitting elements 120R, the green light emitting element 120G and the blue light emitting element 120B can be set in the reserved sub-pixel SPA. In addition, in the event that a defect occurs on the red light emitting element 120R of the first sub-pixel SP1 among the multiple sub-pixels SP, the red light emitting element 120R of the reserved sub-pixel SPA and the driving transistor DT of the first sub-pixel SP1 can be electrically connected to operate the red light emitting element 120R of the reserved sub-pixel SPA to emit light. In this case, in order to reduce the area occupied by the reserved sub-pixel SPA, the red light emitting element 120R, the green light emitting element 120G and the blue light emitting element 120B can be vertically stacked in the reserved sub-pixel SPA. The following will refer to Figures 4 to 8 Describe it in more detail.

[0082] Hereinafter, the following assumption will be described: one pixel PX includes one first sub-pixel SP1, one second sub-pixel SP2, one third sub-pixel SP3 and one reserved sub-pixel SPA, for example, includes one red sub-pixel SP, one green sub-pixel SP, one blue sub-pixel SP and one reserved sub-pixel SPA. However, the configuration of the pixel PX is not limited thereto.

[0083] The pixel area UPA may overlap with a line (e.g., data line DL, reference line RL, low potential power line VSS, and high potential power line VDD) extending in the column direction among the plurality of lines. The pixel area UPA may be formed in an area where a plurality of opaque lines are provided, so that the area of ​​the transmission area TA may be ensured in the entire display area AA. Specifically, due to the configuration of setting the pixel circuit, the light emitting element 120, etc. in the plurality of sub-pixels SP, the pixel area UPA may be an area having a low transmittance and being substantially opaque. Therefore, the plurality of sub-pixels SP in the pixel area UPA may be arranged to overlap with the opaque lines (e.g., data line DL, reference line RL, low potential power line VSS, and high potential power line VDD) extending in the row direction. Therefore, the plurality of sub-pixels SP in the pixel area UPA are arranged to overlap with the plurality of lines, so that the area of ​​the opaque area may be reduced in the entire display area AA, ensuring the maximization or increase of the area of ​​the transmission area TA.

[0084] The transmission area TA may be an area of ​​the display area AA excluding an area in which a plurality of lines and a plurality of pixel areas UPA are disposed. The transmission area TA has a high transmittance. The transmission area TA transmits light so that a background located on the rear surface of the display device 100 is visible from the front surface of the display device 100. A plurality of transmission areas TA may be disposed to be spaced apart from each other, and a plurality of lines and a plurality of pixel areas UPA are interposed therebetween. A plurality of transmission areas TA may be disposed to surround a plurality of pixel areas UPA. Therefore, the display device 100 according to an embodiment of the present disclosure may be implemented as a transparent display device 100 including a plurality of transmission areas TA.

[0085] Reference Figures 3A to 5, each of the plurality of sub-pixels SP includes a pixel circuit and one or more light-emitting elements 120. The pixel circuit may include a plurality of transistors such as T1, T2, and DT and a storage capacitor Cst, and provide a driving current to the light-emitting element 120. For example, the pixel circuit may include a first transistor T1, a second transistor T2, a driving transistor DT, and a storage capacitor Cst. In addition, a plurality of sub-pixels SP disposed in one pixel area UPA may be connected to a scan line SL, a plurality of data lines DL, a reference line RL, a high potential power line VDD, and a low potential power line VSS, and be provided with various types of signals. However, the present disclosure is not limited thereto, and the pixel circuit may include more or fewer elements than shown. Figure 4 The example shown shows a 3T1C structure in which three transistors and one capacitor are provided, but the embodiments of the present disclosure are not limited thereto. For example, 3T2C, 4T1C, 5T1C, 3T2C, T52C, 4T2C, 6T2C, 7T1C, 7T2C, 8T2C structures, etc. are also possible. And more or fewer transistors and capacitors may be included.

[0086] First, the substrate 110 is a component for supporting various constituent elements included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. In addition, the substrate 110 may include plastic such as a polymer and may be made of a material having flexibility.

[0087] The light blocking layer LS is disposed on each of the plurality of sub-pixels SP on the substrate 110. The light blocking layer LS blocks light entering the driving active layer DACT of the driving transistor DT from the lower side of the substrate 110, which will be described below. The light blocking layer LS may block light entering the driving active layer DACT of the driving transistor DT, thereby minimizing or reducing leakage current.

[0088] The buffer layer 111 is disposed on the substrate 110 and the light blocking layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 can be configured as a single layer or a multilayer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto. However, the buffer layer 111 can be excluded according to the type of substrate 110 or the type of transistor. However, the present disclosure is not limited thereto.

[0089] The driving transistor DT, the first transistor T1 , and the second transistor T2 are disposed in each of the plurality of sub-pixels SP on the buffer layer 111 .

[0090] The driving transistor DT, the first transistor T1, and the second transistor T2 of each of the plurality of sub-pixels SP may be a P-type thin film transistor or an N-type thin film transistor. For example, in a P-type thin film transistor, positive holes move from the source electrode to the drain electrode, so that current can flow from the source electrode to the drain electrode. In an N-type thin film transistor, electrons move from the source electrode to the drain electrode, so that current can flow from the drain electrode to the source electrode. The following description is made by taking the driving transistor DT, the first transistor T1, and the second transistor T2 as a P-type thin film transistor in which current flows from the source electrode to the drain electrode as an example. However, the present disclosure is not limited thereto.

[0091] Next, a driving transistor DT is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The driving transistor DT is a transistor for controlling a driving current provided to the light emitting element 120. In one pixel area UPA, the driving transistors DT of the plurality of sub-pixels SP may be disposed in a line along a column direction. The plurality of driving transistors DT of the plurality of sub-pixels SP may be disposed in a line while overlapping an area where the reference line RL and the data line DL are disposed.

[0092] The driving transistor DT includes a driving active layer DACT, a driving gate electrode DGE, a driving source electrode DSE, and a driving drain electrode DDE.

[0093] The driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon or polycrystalline silicon. However, the present disclosure is not limited thereto. The oxide semiconductor may be made of a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and their oxides. Specifically, the oxide semiconductor may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO), but is not limited thereto.

[0094] The gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer for insulating the driving active layer DACT and the driving gate electrode DGE from each other. The gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0095] The driving gate electrode DGE is disposed on the gate insulating layer 112. The driving gate electrode DGE may be configured as a single layer or multiple layers made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto. For example, although the driving transistor DT is Figure 5 Although shown as a top gate type in FIG. 1 , the driving transistor DT may also be implemented as a bottom gate type or a double gate type in other examples.

[0096] The first interlayer insulating layer 113a is disposed on the driving gate electrode DGE. A contact hole is formed in the first interlayer insulating layer 113a, and the driving source electrode DSE is connected to the driving active layer DACT through the contact hole. The first interlayer insulating layer 113a is an insulating layer for protecting components disposed under the first interlayer insulating layer 113a. The first interlayer insulating layer 113a may be configured as a single layer or a multilayer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0097] The driving source electrode DSE is disposed on the first interlayer insulating layer 113a. The driving source electrode DSE is electrically connected to the driving active layer DACT through a contact hole formed in the first interlayer insulating layer 113a. In addition, the driving source electrode DSE may be electrically connected to the second transistor T2. The driving source electrode DSE may be configured as a single layer or multiple layers made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0098] A second interlayer insulating layer 113b is disposed on the driving source electrode DSE. The second interlayer insulating layer 113b is an insulating layer for protecting components disposed under the second interlayer insulating layer 113b. The second interlayer insulating layer 113b may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0099] The first passivation layer 114a is disposed on the second interlayer insulating layer 113b. The first passivation layer 114a is an insulating layer for protecting components disposed below the first passivation layer 114a. The first passivation layer 114a may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0100] The driving drain electrode DDE is disposed on the first passivation layer 114a. The driving drain electrode DDE is electrically connected to the driving active layer DACT through a contact hole formed in the first passivation layer 114a, the first interlayer insulating layer 113a, and the second interlayer insulating layer 113b. In addition, the driving drain electrode DDE may be electrically connected to the low potential power supply line VSS through a contact hole formed in the first passivation layer 114a. The driving drain electrode DDE may be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0101] Next, a first transistor T1 is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The first transistor T1 may be a transistor configured to transmit a data voltage Vdata to a gate electrode of the driving transistor DT. The first transistor T1 may be referred to as a switching transistor. In this case, in one pixel area UPA, a plurality of first transistors T1 in a plurality of sub-pixels SP may be disposed to overlap the scan line SL and a protrusion of the scan line SL and to be disposed in a line in the row direction.

[0102] Specifically, the scan line SL may extend in a row direction on the gate insulating layer 112 and be disposed to pass through the plurality of pixel areas UPA. In this case, the scan line SL may include a protrusion protruding toward the plurality of sub-pixels SP in a column direction in a region overlapping the plurality of pixel areas UPA.

[0103] The first transistors T1 of the plurality of subpixels SP may be arranged in a line in a region where the scan line SL is provided. The first transistors T1 of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be arranged in a line in a row direction in a region where the scan line SL is provided.

[0104] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0105] The first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present disclosure is not limited thereto.

[0106] The first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 may be electrically connected to the scan line SL. For example, the first gate electrode GE1 may be integrated with the scan line SL. The first gate electrode GE1 may be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0107] The first drain electrode DE1 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The first drain electrode DE1 is electrically connected to the first active layer ACT1 through a contact hole formed in the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the first drain electrode DE1 may be electrically connected to the second gate electrode GE2 of the second transistor T2 through the contact hole of the first interlayer insulating layer 113a. The first drain electrode DE1 may be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0108] The first source electrode SE1 is disposed on the first passivation layer 114a. The first source electrode SE1 is electrically connected to the first active layer ACT1 through the first passivation layer 114a, the second interlayer insulating layer 113b, and the contact hole of the first interlayer insulating layer 113a. In addition, the first source electrode SE1 may be electrically connected to the data line DL. For example, the first source electrode SE1 may be integrated with the data line DL. The first source electrode SE1 may be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0109] Next, a second transistor T2 is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The second transistor T2 may be a transistor configured to compensate for the threshold voltage of the driving transistor DT. The second transistor T2 may be referred to as a sensing transistor. The second transistors T2 of the plurality of sub-pixels SP may be disposed in a line along a protrusion of the scan line SL protruding in the column direction. For example, the second transistors T2 of the plurality of sub-pixels SP may be disposed to correspond to the protrusion of the scan line SL protruding in the column direction. Therefore, the plurality of second transistors T2 disposed in one pixel area UPA may be disposed in a line along the column direction.

[0110] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0111] The second active layer ACT2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present disclosure is not limited thereto.

[0112] In this case, the second active layers ACT2 of a plurality of adjacent sub-pixels SP may be connected to each other. For example, the second active layers ACT2 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may extend in the column direction and be connected to each other, and the second active layer ACT2 may be connected to the second drain electrode DE2 disposed in the first sub-pixel SP1. For example, the connection portion of the channel region of the second active layer ACT2 for connecting the reference line RL and the plurality of sub-pixels SP is made of a transparent material of the second active layer ACT2, rather than an opaque conductive material, so that the transmittance may be increased at the outermost edge of the pixel area UPA. In addition, the connection portion of the channel region of the second active layer ACT2 for connecting the reference line RL and the plurality of sub-pixels SP is made of the material of the second active layer ACT2, so that the contact hole may be eliminated and the structure of the pixel area UPA may be simplified.

[0113] The second gate electrode GE2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate electrode GE2 may be electrically connected to the scan line SL. For example, the second gate electrode GE2 may be integrated with a protrusion of the scan line SL and electrically connected to the protrusion of the scan line SL. The second gate electrode GE2 may be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof). However, the present disclosure is not limited thereto.

[0114] The second source electrode SE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the second active layer ACT2 through the contact holes of the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the second source electrode SE2 may be integrated with the driving source electrode DSE and electrically connected to the driving source electrode DSE. The second source electrode SE2 may be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0115] The second drain electrode DE2 is disposed between the first passivation layer 114a and the second passivation layer 114b. The second drain electrode DE2 is electrically connected to the second active layer ACT2 through a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. The second drain electrode DE2 may be integrated with the reference line RL and electrically connected to the reference line RL. The second drain electrode DE2 may be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0116] Next, a storage capacitor Cst is disposed on the gate insulating layer 112. The storage capacitor Cst may store a potential difference between the driving gate electrode DGE and the driving source electrode DSE of the driving transistor DT when the light emitting element 120 emits light, so that a constant driving current may be provided to the light emitting element 120. The storage capacitor Cst may include a first capacitor electrode C1 electrically connected to the driving gate electrode DGE and a second capacitor electrode C2 electrically connected to the driving source electrode DSE. The storage capacitor Cst may maintain a constant voltage of the driving gate electrode DGE and the driving source electrode DSE.

[0117] Specifically, the first capacitor electrode C1 is disposed on the gate insulating layer 112. The first capacitor electrode C1 may be integrated with the driving gate electrode DGE. The second capacitor electrode C2 is disposed on the first interlayer insulating layer 113a. The first capacitor electrode C1 and the second capacitor electrode C2 may be disposed to overlap each other, and the first interlayer insulating layer 113a is interposed therebetween. In this case, the second capacitor electrode C2 may be integrated with the driving source electrode DSE. The first capacitor electrode C1 and the second capacitor electrode C2 may each be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof). However, the present disclosure is not limited thereto.

[0118] Next, an auxiliary electrode AE ​​is disposed on the first passivation layer 114a. The auxiliary electrode AE ​​is an electrode for electrically connecting the driving source electrode DSE and the first reflective electrode RE1. The driving source electrode DSE and the first reflective electrode RE1 may be electrically connected to each other through the auxiliary electrode AE. The auxiliary electrode AE ​​may be configured as a single layer or a multilayer made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof). However, the present disclosure is not limited thereto. It should be noted that the driving source electrode DSE may be directly connected to the first reflective electrode RE1, and thus the auxiliary electrode AE ​​may be omitted.

[0119] The low potential power line VSS is disposed on the second interlayer insulating layer 113b. The low potential power line VSS may be disposed in the column direction and overlap with a plurality of pixel areas UPA. The low potential power line VSS may be electrically connected to the drive drain electrode DDE. The low potential power line VSS may be configured as a single layer or multiple layers made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof). However, the present disclosure is not limited thereto.

[0120] In addition, the low potential power line VSS may overlap with a region where a plurality of data lines DL are disposed. The low potential power line VSS may have a relatively large width so that one low potential power line VSS and a plurality of data lines DL may overlap with each other. The low potential power line VSS may cover the storage capacitors Cst and the driving transistors DT of a plurality of sub-pixels SP. Since only the low potential power line VSS is disposed between the second interlayer insulating layer 113b and the first passivation layer 114a, the low potential power line VSS may be easily formed in a region other than a region where the contact hole is disposed.

[0121] The opening portion may be formed in the low potential power line VSS and overlap with the contact hole. For example, the opening portion may be formed in the low potential power line VSS and overlap with the contact hole through which the first source electrode SE1 and the first active layer ACT1 are connected and the contact hole through which the drive drain electrode DDE and the drive active layer DACT are connected. The first source electrode SE1 and the drive drain electrode DDE are disposed on the low potential power line VSS, and the first active layer ACT1 and the drive active layer DACT are disposed below the low potential power line VSS. Therefore, the opening portion is formed in the low potential power line VSS so that the components connected to the upper and lower parts of the low potential power line VSS can be easily connected.

[0122] The low potential power line VSS may be provided between the storage capacitor Cst, the driving transistor DT and the plurality of data lines DL, and may be used as a barrier film for suppressing voltage fluctuations of the driving transistor DT caused by the data lines DL. The low potential power line VSS to which a predetermined constant voltage is applied may be provided between the storage capacitor Cst, the driving transistor DT and the data lines DL, and may prohibit the data lines DL, the storage capacitor Cst and the driving transistor DT from being connected. The low potential power line VSS may be provided to at least cover the driving gate electrode DGE of the driving transistor DT, and to protect the driving gate electrode DGE, so that the voltage of the driving gate electrode DGE does not fluctuate due to the data lines DL.

[0123] Next, a reference line RL is disposed on the first passivation layer 114a. The reference line RL may be disposed in a column direction and overlap a plurality of pixel areas UPA. The reference line RL may be disposed adjacent to a protrusion of the scan line SL and electrically connected to a plurality of second transistors T2 disposed on the protrusion of the scan line SL. The reference line RL may be configured as a single layer or multiple layers made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0124] A plurality of data lines DL are disposed on the first passivation layer 114a. The plurality of data lines DL may extend in a column direction and overlap with the plurality of pixel areas UPA. The plurality of data lines DL may include data lines DL connected to the first transistors T1 of the plurality of first sub-pixels SP1, data lines DL connected to the first transistors T1 of the plurality of second sub-pixels SP2, and data lines DL connected to the first transistors T1 of the plurality of third sub-pixels SP3.

[0125] Next, a second passivation layer 114b is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the reference line RL, and the data line DL. The second passivation layer 114b may be an insulating layer for protecting components disposed below the second passivation layer 114b. The second passivation layer 114b may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0126] The first planarization layer 115a is disposed on the second passivation layer 114b. The first planarization layer 115a may planarize the upper portion of the substrate 110 on which a plurality of transistors and the storage capacitor Cst are disposed. For example, the first planarization layer 115a may be configured as a single layer or multiple layers and made of a photoresist or acrylic-based organic material. However, the present disclosure is not limited thereto.

[0127] In addition, although not shown in the drawings, an additional passivation layer may be further disposed on the first planarization layer 115a. For example, a passivation layer configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx) may be disposed on the first planarization layer 115a and protect components disposed below the passivation layer.

[0128] Next, a plurality of first reflective electrodes RE1 are disposed on the first planarization layer 115a. The plurality of first reflective electrodes RE1 may be disposed in the plurality of sub-pixels SP, respectively, and electrically connect the driving transistor DT and the light emitting element 120. In addition, the plurality of first reflective electrodes RE1 may reflect light emitted from the light emitting element 120 to the outside of the display device 100. The plurality of first reflective electrodes RE1 may be disposed adjacent to the driving source electrode DSE in the plurality of sub-pixels SP. The first reflective electrode RE1 may be connected to the auxiliary electrode AE ​​through a contact hole formed in the first planarization layer 115a and the second passivation layer 114b. The first reflective electrode RE1 may be electrically connected to the driving source electrode DSE and the second source electrode SE2 through the auxiliary electrode AE. The plurality of first reflective electrodes RE1 may be made of an opaque conductive material having high reflection efficiency (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof). However, the present disclosure is not limited thereto.

[0129] In this case, a contact hole through which the first reflective electrode RE1 and the auxiliary electrode AE ​​or the driving source electrode DSE are connected may be provided in an area where the first connection electrode CE1 is not provided. The contact hole through which the first reflective electrode RE1 and the auxiliary electrode AE ​​or the driving source electrode DSE are connected and the contact hole through which the first connection electrode CE1 and the first reflective electrode RE1 are connected may be provided in different areas or may be spaced apart from each other. In order to suppress a bright spot defect in which the light emitting element 120 continues to emit light in the event of a defect in the light emitting element 120, a driving current route between the defective light emitting element 120 and the pixel circuit may be blocked by damaging a portion in which the first reflective electrode RE1 and the first connection electrode CE1 are connected. In this case, even if a portion in which the first reflective electrode RE1 and the first connection electrode CE1 are connected is damaged, a portion in which the first reflective electrode RE1 and the auxiliary electrode AE ​​are connected may remain in a connected state without being damaged. Thereafter, during a repair process, the first reflective electrode RE1 may electrically connect the repair line WRL and the driving transistor DT. A more detailed description of the repair process will be described below.

[0130] Next, a second reflective electrode RE2 or a high potential power line VDD is disposed on the first planarization layer 115a. The second reflective electrode RE2 and the high potential power line VDD may be integrated and configured to provide a high potential power supply voltage to the light emitting element 120 and reflect the light emitted from the light emitting element 120 to the outside of the display device 100. The second reflective electrodes RE2 of a plurality of sub-pixels SP may be connected to each other and integrated. The second reflective electrode RE2 and the high potential power line VDD may extend in a column direction and be disposed to overlap with the light emitting element 120. The second reflective electrode RE2 and the high potential power line VDD may be disposed to overlap with a plurality of data lines DL, a reference line RL, and a low potential power line VSS. The second reflective electrode RE2 and the high potential power line VDD may be made of an opaque conductive material having a high reflection efficiency (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof). However, the present disclosure is not limited thereto.

[0131] The third passivation layer 114c is disposed on the plurality of first reflective electrodes RE1 and the second reflective electrode RE2. The third passivation layer 114c may be an insulating layer for protecting components disposed under the third passivation layer 114c. The third passivation layer 114c may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0132] The first bonding layer AD1 is disposed on the third passivation layer 114c. The first bonding layer AD1 may be formed on the front surface of the substrate 110 and fix the light emitting element 120 disposed on the first bonding layer AD1. The first bonding layer AD1 may be made of a photocurable bonding material that can be cured by light. For example, the first bonding layer AD1 may be made of any one of an adhesive polymer, an epoxy resist, a UV resin, a polyimide-based material, an acrylate-based material, a urethane-based material, and polydimethylsiloxane (PDMS). However, the present disclosure is not limited thereto.

[0133] A plurality of light emitting elements 120 are disposed on the first bonding layer AD1 and are disposed in each of the plurality of sub-pixels SP. The light emitting element 120 may be an element configured to emit light by current, and include a red light emitting element 120R configured to emit red light, a green light emitting element 120G configured to emit green light, and a blue light emitting element 120B configured to emit blue light. The combination of the light emitting elements 120 may realize various colors including white. For example, the light emitting element 120 may be a light emitting diode (LED) or a micro LED. However, the present disclosure is not limited thereto.

[0134] The red light emitting element 120R may be disposed in the first sub-pixel SP1, the green light emitting element 120G may be disposed in the second sub-pixel SP2, and the blue light emitting element 120B may be disposed in the third sub-pixel SP3. A plurality of light emitting elements 120 disposed in one pixel area UPA may be disposed in a line along a column direction. In addition, the plurality of light emitting elements 120 may be disposed in a plurality of sub-pixels SP, respectively, and disposed to overlap with the second reflective electrode RE2.

[0135] In addition, the red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B may be arranged on different layers. For example, the red light emitting element 120R may be arranged on the first bonding layer AD1, the green light emitting element 120G may be arranged on the second bonding layer AD2 formed on the red light emitting element 120R, and the blue light emitting element 120B may be arranged on the third bonding layer AD3 formed on the green light emitting element 120G. In order to reduce the area of ​​the reserved sub-pixel SPA, the red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B may be vertically stacked in the reserved sub-pixel SPA. In this process, the light emitting elements 120 of the plurality of sub-pixels SP may be transferred to different layers.

[0136] First, please refer to Figure 5 and Figure 8 The red light emitting element 120R is disposed on the first bonding layer AD1 and is disposed in each of the first sub-pixel SP1 and the reserved sub-pixel SPA. The red light emitting element 120R includes a first semiconductor layer 121, a red light emitting layer 122R, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126.

[0137] The first semiconductor layer 121 is disposed on the first bonding layer AD1, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may each be a layer formed by doping a specific material with n-type or p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP) or gallium arsenide (GaAs) with n-type or p-type impurities. In addition, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc. The n-type impurity may be silicon (Si), germanium, tin (Sn), etc. However, the present disclosure is not limited thereto.

[0138] The red light emitting layer 122R is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The red light emitting layer 122R may emit light by receiving positive holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The red light emitting layer 122R may be configured as a single layer or a multi-quantum well (MQW) structure. For example, the red light emitting layer 122R may be made of gallium arsenide (GaAs), gallium arsenide nitride (GaAsP), indium gallium nitride (InGaN), gallium nitride (GaN), etc. However, the present disclosure is not limited thereto.

[0139] The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode electrically connecting the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on an upper surface (e.g., a top surface) of the first semiconductor layer 121 exposed from the red light emitting layer 122R and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof). However, the present disclosure is not limited thereto.

[0140] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on an upper surface (e.g., a top surface) of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting a high potential power line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof). However, the present disclosure is not limited thereto.

[0141] Next, an encapsulation film 126 is provided to surround the first semiconductor layer 121, the red light emitting layer 122R, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 may be made of an insulating material and protect the first semiconductor layer 121, the red light emitting layer 122R, and the second semiconductor layer 123. In addition, a contact hole exposing the first electrode 124 and the second electrode 125 may be formed in the encapsulation film 126 so that the first connection electrode CE1 and the first electrode 124 may be electrically connected and the second connection electrode CE2 and the second electrode 125 may be electrically connected.

[0142] In addition, a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation film 126. The light emitting element 120 manufactured on the wafer may be separated from the wafer and transferred to the display panel PN. However, a portion of the encapsulation film 126 may be torn during the process of separating the light emitting element 120 from the wafer. For example, during the process of separating the light emitting element 120 from the wafer, a portion of the encapsulation film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light emitting element 120 may be torn, so that a portion of the lower side surface of the first semiconductor layer 121 may be exposed to the outside. Although the lower portion of the light emitting element 120 is exposed from the encapsulation film 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after forming the second planarization layer 115b covering the side surface of the first semiconductor layer 121, thereby reducing short circuit defects.

[0143] Next, the second planarization layer 115b is disposed on the first bonding layer AD1 and the red light emitting element 120R. The second planarization layer 115b may be disposed to cover the red light emitting element 120R of the first sub-pixel SP1 and the reserved sub-pixel SPA. For example, the second planarization layer 115b may be configured as a single layer or multiple layers and made of a photoresist or an acrylic-based organic material. However, the present disclosure is not limited thereto.

[0144] The second planarization layer 115b may be provided to cover the red light emitting element 120R, and to fix and protect the red light emitting element 120R. The second planarization layer 115b may cover the torn portion of the encapsulation film 126 that protects the side surface of the first semiconductor layer 121 of the red light emitting element 120R. Therefore, the second planarization layer 115b covers the lower portion of the first semiconductor layer 121, and the encapsulation film 126 is torn from the lower portion of the first semiconductor layer 121, thereby suppressing contact defects and short circuit defects of the connection electrode and the first semiconductor layer 121.

[0145] In addition, a contact hole exposing the first electrode 124 and the second electrode 125 of the red light emitting element 120R may be formed in the second planarization layer 115b. The first electrode 124 and the second electrode 125 of the red light emitting element 120R may be exposed from the second planarization layer 115b. However, the second planarization layer 115b is partially disposed in the region between the first electrode 124 and the second electrode 125, thereby reducing short circuit defects.

[0146] A first connection electrode CE1 connected to the first electrode 124 of the light emitting element 120 and a second connection electrode CE2 connected to the second electrode 125 of the light emitting element 120 are provided in each of the plurality of sub-pixels SP and the reserved sub-pixel SPA. The first connection electrode CE1 provided in each sub-pixel SP may electrically connect the driving transistor DT and the first electrode 124 of the light emitting element 120. The first connection electrode CE1 provided in the reserved sub-pixel SPA may electrically connect the repair line WRL and the first electrode 124 of the light emitting element 120. The second connection electrode CE2 provided in each of the plurality of sub-pixels SP and the reserved sub-pixel SPA may electrically connect the high potential power line VDD and the second electrode 125 of the light emitting element 120. The first connection electrode CE1 and the second connection electrode CE2 may be made of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present disclosure is not limited thereto.

[0147] In this case, the plurality of light emitting elements 120 are respectively disposed on different layers, so that the first connection electrode CE1 and the second connection electrode CE2 may also be configured as a plurality of electrodes disposed on different layers. For example, the first connection electrode CE1 includes a 1-1 connection electrode CE1a connected to the first electrode 124 of the red light emitting element 120R, a 1-2 connection electrode CE1b connected to the first electrode 124 of the green light emitting element 120G, and a 1-3 connection electrode CE1c connected to the first electrode 124 of the blue light emitting element 120B. The second connection electrode CE2 may include a 2-1 connection electrode CE2a connected to the second electrode 125 of the red light emitting element 120R, a 2-2 connection electrode CE2b connected to the second electrode 125 of the green light emitting element 120G, and a 2-3 connection electrode CE2c connected to the second electrode 125 of the blue light emitting element 120B.

[0148] First, the 1-1 connection electrode CE1a and the 2-1 connection electrode CE2a are disposed on the second planarization layer 115b and are disposed in the first sub-pixel SP1 and the reserved sub-pixel SPA. The 1-1 connection electrode CE1a may be electrically connected to the first electrode 124 of the red light emitting element 120R through a contact hole formed in the second planarization layer 115b. The 2-1 connection electrode CE2a may be electrically connected to the second electrode 125 of the red light emitting element 120R through a contact hole formed in the second planarization layer 115b.

[0149] The 1-1 connection electrode CE1a disposed in the first subpixel SP1 may be electrically connected to the first reflective electrode RE1 through a contact hole formed in the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the first subpixel SP1, the first electrode 124 of the red light emitting element 120R and the first reflective electrode RE1, the auxiliary electrode AE, and the driving source electrode DSE may be electrically connected to each other through the first connection electrode CE1a.

[0150] The 1-1st connection electrode CE1a disposed in the reserved sub-pixel SPA may be connected to the first repair line WRL1 among the plurality of repair lines WRL. The 1-1st connection electrode CE1a and the first repair line WRL1 may be disposed on the same layer, made of the same material, and integrated with each other. Therefore, in the reserved sub-pixel SPA, the first repair line WRL1 and the first electrode 124 of the red light emitting element 120R may be electrically connected through the 1-1st connection electrode CE1a.

[0151] The repair line WRL is a line that electrically connects the light emitting element 120 of the reserved sub-pixel SPA to the driving transistor DT of another sub-pixel SP when a defect occurs. A more detailed description thereof will be described below.

[0152] The 2-1st connection electrode CE2a provided in the first sub-pixel SP1 may be electrically connected to the second reflective electrode RE2 or the high potential power line VDD through a contact hole formed in the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the first sub-pixel SP1, the high potential power line VDD and the second electrode 125 of the red light emitting element 120R may be electrically connected to each other through the 2-1st connection electrode CE2a.

[0153] The 2-1 connection electrode CE2a provided in the reserved sub-pixel SPA may be electrically connected to the second reflective electrode RE2 or the high potential power line VDD through a contact hole formed in the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the reserved sub-pixel SPA, the high potential power line VDD and the second electrode 125 of the red light emitting element 120R may be electrically connected to each other through the 2-1 connection electrode CE2a. In this case, without performing a repair process, the first electrode 124 of the red light emitting element 120R may be in a floating state without being connected to the driving transistor DT. Therefore, even if the second electrode 125 of the red light emitting element 120R of the reserved sub-pixel SPA is electrically connected to the high potential power line VDD, it is possible to suppress the abnormal light emission of the red light emitting element 120R of the reserved sub-pixel SPA.

[0154] The second bonding layer AD2 is disposed on the second planarization layer 115b, the 1-1 connection electrode CE1a, and the 2-1 connection electrode CE2a. The second bonding layer AD2 may be formed on the front surface of the substrate 110 and fix the green light emitting element 120G disposed on the second bonding layer AD2. The second bonding layer AD2 may be made of a photocurable bonding material that can be cured by light. For example, the second bonding layer AD2 may be made of any one of an adhesive polymer, an epoxy resist, a UV resin, a polyimide-based material, an acrylate-based material, a urethane-based material, and polydimethylsiloxane (PDMS). However, the present disclosure is not limited thereto.

[0155] The green light emitting element 120G is disposed on the second bonding layer AD2 and is disposed in each of the second sub-pixel SP2 and the reserved sub-pixel SPA. In this case, the green light emitting element 120G disposed in the reserved sub-pixel SPA may overlap with a region where the red light emitting element 120R is disposed in the reserved sub-pixel SPA. For example, the green light emitting element 120G and the red light emitting element 120R may be disposed to overlap each other in the reserved sub-pixel SPA.

[0156] The green light emitting element 120G includes a first semiconductor layer 121, a green light emitting layer 122G, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126. The green light emitting element 120G has substantially the same structure as the red light emitting element 120R, except that the green light emitting element 120G includes the green light emitting layer 122G. For example, the first semiconductor layer 121, the green light emitting layer 122G, and the second semiconductor layer 123 of the green light emitting element 120G are sequentially disposed on the second bonding layer AD2, and the first electrode 124 and the second electrode 125 may be disposed above the first semiconductor layer 121 and the second semiconductor layer 123, respectively. In addition, the encapsulation film 126 may be formed to surround the first semiconductor layer 121, the green light emitting layer 122G, the second semiconductor layer 123, the first electrode 124, and the second electrode 125 of the green light emitting element 120G.

[0157] Next, a third planarization layer 115c is disposed on the second bonding layer AD2 and the green light emitting element 120G. The third planarization layer 115c may be disposed to cover the green light emitting element 120G of the second sub-pixel SP2 and the reserved sub-pixel SPA. For example, the third planarization layer 115c may be configured as a single layer or multiple layers and may be made of a photoresist or acrylic-based organic material. However, the present disclosure is not limited thereto.

[0158] The 1-2nd connection electrode CE1b and the 2-2nd connection electrode CE2b are disposed on the third planarization layer 115c and are disposed in the second sub-pixel SP2 and the reserved sub-pixel SPA. The 1-2nd connection electrode CE1b may be electrically connected to the first electrode 124 of the green light emitting element 120G through a contact hole formed in the third planarization layer 115c. The 2-2nd connection electrode CE2b may be electrically connected to the second electrode 125 of the green light emitting element 120G through a contact hole formed in the third planarization layer 115c.

[0159] The 1-2nd connection electrode CE1b disposed in the second sub-pixel SP2 may be electrically connected to the first reflective electrode RE1 through a contact hole formed in the third planarization layer 115c, the second bonding layer AD2, the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the second sub-pixel SP2, the first electrode 124 of the green light emitting element 120G and the first reflective electrode RE1, the auxiliary electrode AE, and the driving source electrode DSE may be electrically connected to each other through the 1-2nd connection electrode CE1b.

[0160] The 1-2nd connection electrode CE1b disposed in the reserved sub-pixel SPA may be connected to the second repair line WRL2 among the plurality of repair lines WRL. The 1-2nd connection electrode CE1b and the second repair line WRL2 may be disposed on the same layer, made of the same material, and integrated with each other. Therefore, in the reserved sub-pixel SPA, the second repair line WRL2 and the first electrode 124 of the green light emitting element 120G may be electrically connected through the 1-2nd connection electrode CE1b.

[0161] The 2-2nd connection electrode CE2b provided in the second sub-pixel SP2 may be electrically connected to the second reflective electrode RE2 or the high potential power line VDD through a contact hole formed in the third planarization layer 115c, the second bonding layer AD2, the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the second sub-pixel SP2, the high potential power line VDD and the second electrode 125 of the green light emitting element 120G may be electrically connected to each other through the 2-2nd connection electrode CE2b.

[0162] The 2-2nd connection electrode CE2b disposed in the reserved sub-pixel SPA may also be electrically connected to the second reflective electrode RE2 or the high potential power line VDD through a contact hole formed in the third planarization layer 115c, the second bonding layer AD2, the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the reserved sub-pixel SPA, the high potential power line VDD and the second electrode 125 of the green light emitting element 120G may be electrically connected to each other through the 2-2nd connection electrode CE2b.

[0163] Next, the third bonding layer AD3 is disposed on the third planarization layer 115c, the 1-2 connection electrode CE1b, and the 2-2 connection electrode CE2b. The third bonding layer AD3 may be formed on the front surface of the substrate 110 and fix the blue light emitting element 120B disposed on the third bonding layer AD3. The third bonding layer AD3 may be made of a photocurable bonding material that can be cured by light. For example, the third bonding layer AD3 may be made of any one of an adhesive polymer, an epoxy resist, a UV resin, a polyimide-based material, an acrylate-based material, a urethane-based material, and polydimethylsiloxane (PDMS). However, the present disclosure is not limited thereto.

[0164] The blue light emitting element 120B is disposed on the third bonding layer AD3 and is disposed in each of the third sub-pixel SP3 and the reserved sub-pixel SPA. The blue light emitting element 120B of the reserved sub-pixel SPA may overlap with the green light emitting element 120G and the red light emitting element 120R. The red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B disposed in the reserved sub-pixel SPA may at least partially overlap with each other.

[0165] The blue light emitting element 120B includes a first semiconductor layer 121, a blue light emitting layer 122B, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126. The blue light emitting element 120B has substantially the same structure as the red light emitting element 120R and the green light emitting element 120G, except that the blue light emitting element 120B includes the blue light emitting layer 122B. For example, the first semiconductor layer 121, the blue light emitting layer 122B, and the second semiconductor layer 123 of the blue light emitting element 120B may be sequentially disposed on the third bonding layer AD3, and the first electrode 124 and the second electrode 125 may be disposed above the first semiconductor layer 121 and the second semiconductor layer 123, respectively. In addition, the encapsulation film 126 may be formed to surround the first semiconductor layer 121, the blue light emitting layer 122B, the second semiconductor layer 123, the first electrode 124, and the second electrode 125 of the blue light emitting element 120B.

[0166] Next, a fourth planarization layer 115d is disposed on the third bonding layer AD3 and the blue light emitting element 120B. The fourth planarization layer 115d may be disposed to cover the blue light emitting element 120B of the third sub-pixel SP3 and the reserved sub-pixel SPA. For example, the fourth planarization layer 115d may be configured as a single layer or multiple layers and may be made of a photoresist or acrylic-based organic material. However, the present disclosure is not limited thereto.

[0167] The 1-3rd connection electrode CE1c and the 2-3rd connection electrode CE2c are disposed on the fourth planarization layer 115d and disposed in the third sub-pixel SP3 and the reserved sub-pixel SPA. The 1-3rd connection electrode CE1c may be electrically connected to the first electrode 124 of the blue light emitting element 120B through a contact hole formed in the fourth planarization layer 115d. The 2-3rd connection electrode CE2c may be electrically connected to the second electrode 125 of the blue light emitting element 120B through a contact hole formed in the fourth planarization layer 115d.

[0168] The 1-3rd connection electrode CE1c disposed in the third sub-pixel SP3 may be electrically connected to the first reflective electrode RE1 through a contact hole formed in the fourth planarization layer 115d, the third bonding layer AD3, the third planarization layer 115c, the second bonding layer AD2, the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the third sub-pixel SP3, the first electrode 124 of the blue light emitting element 120B and the first reflective electrode RE1, the auxiliary electrode AE, and the driving source electrode DSE may be electrically connected to each other through the 1-3rd connection electrode CE1c.

[0169] The 1-3rd connection electrode CE1c disposed in the reserved sub-pixel SPA may be connected to the third repair line WRL3 among the plurality of repair lines WRL. The 1-3rd connection electrode CE1c and the third repair line WRL3 may be disposed on the same layer, made of the same material, and integrated with each other. Therefore, in the reserved sub-pixel SPA, the third repair line WRL3 and the first electrode 124 of the blue light emitting element 120B may be electrically connected through the 1-3rd connection electrode CE1c.

[0170] The 2nd-3rd connection electrode CE2c disposed in the third sub-pixel SP3 may be electrically connected to the second reflective electrode RE2 or the high potential power line VDD through a contact hole formed in the fourth planarization layer 115d, the third bonding layer AD3, the third planarization layer 115c, the second bonding layer AD2, the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the third sub-pixel SP3, the high potential power line VDD of the blue light emitting element 120B and the second electrode 125 may be electrically connected to each other through the 2nd-3rd connection electrode CE2c.

[0171] The 2nd-3rd connection electrode CE2c disposed in the reserved sub-pixel SPA may also be electrically connected to the second reflective electrode RE2 or the high potential power line VDD through a contact hole formed in the fourth planarization layer 115d, the third bonding layer AD3, the third planarization layer 115c, the second bonding layer AD2, the second planarization layer 115b, the first bonding layer AD1, and the third passivation layer 114c. Therefore, in the reserved sub-pixel SPA, the high potential power line VDD and the second electrode 125 of the blue light emitting element 120B may be electrically connected to each other through the 2nd-3rd connection electrode CE2c.

[0172] In this case, refer to Figure 8 , the 2-3rd connection electrode CE2c, the 2-2nd connection electrode CE2b, and the 2-1st connection electrode CE2a of the reserved sub-pixel SPA may be connected to the high potential power line VDD through the same contact hole. Therefore, the 2-3rd connection electrode CE2c may be adjacent to the 2-2nd connection electrode CE2b, and the 2-2nd connection electrode CE2b may be adjacent to the 2-1st connection electrode CE2a. Therefore, in the reserved sub-pixel SPA, the 2-3rd connection electrode CE2c, the 2-2nd connection electrode CE2b, the 2-1st connection electrode CE2a, the second electrode 125 of the red light emitting element 120R, the second electrode 125 of the green light emitting element 120G, and the second electrode 125 of the blue light emitting element 120B may be electrically connected to each other.

[0173] Next, in the pixel area UPA, a bank BB is provided on the fourth planarization layer 115d, the 1st-3rd connection electrode CE1c, and the 2nd-3rd connection electrode CE2c. The bank BB may be provided to be spaced apart from the region where the plurality of light emitting elements 120 are provided at a predetermined interval. The bank BB may be provided between the plurality of sub-pixels SP and on the boundary between the first sub-pixel SP1 and the reserved sub-pixel SPA, and the bank BB may cover a portion of the first connection electrode CE1 and a portion of the second connection electrode CE2. The bank BB may be provided to be spaced apart from the transmission area TA. The bank BB may be made of an opaque material (e.g., black particles or a black resin) to reduce color mixing between the plurality of sub-pixels SP and the reserved sub-pixel SPA. However, the present disclosure is not limited thereto.

[0174] In addition, although not shown in the figure, a protective layer may be provided on the bank BB. The protective layer is a layer for protecting components provided below the protective layer. For example, the protective layer may be configured as a single layer or multiple layers made of benzocyclobutene, a light-transmitting epoxy resin, a photoresist, an acrylic organic material, or an inorganic material (e.g., silicon oxide (SiOx) or silicon nitride (SiNx)). However, the present disclosure is not limited thereto.

[0175] Next, a plurality of repair lines WRL are provided between the reserved sub-pixel SPA and the plurality of sub-pixels SP. The plurality of repair lines WRL are lines for repairing defective sub-pixels SP by electrically connecting the light-emitting elements 120 of the reserved sub-pixels SPA to the driving transistors DT of the defective sub-pixels SP when a defect occurs on the light-emitting elements 120 of some sub-pixels SP. When a defect occurs in the light-emitting element 120 of any of the plurality of sub-pixels SP, the repair line WRL may be used to connect the light-emitting element 120 of the reserved sub-pixel SPA to the pixel circuit of the defective sub-pixel SP to operate the light-emitting element 120 of the reserved sub-pixel SPA instead of the defective light-emitting element 120.

[0176] The plurality of repair lines WRL may be disposed on the peripheral portion of the pixel area UPA and adjacent to the transmission area TA. Therefore, the plurality of repair lines WRL may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), thereby minimizing or reducing a decrease in transmittance.

[0177] The plurality of repair lines WRL include a first repair line WRL1, a second repair line WRL2, and a third repair line WRL3. The first repair line WRL1, the second repair line WRL2, and the third repair line WRL3 may at least partially overlap each other. The first repair line WRL1, the second repair line WRL2, and the third repair line WRL3 may be disposed on different layers.

[0178] First, the first repair line WRL1 is disposed on the second planarization layer 115b and between the reserved sub-pixel SPA and the first sub-pixel SP1. The first repair line WRL1 is a line for electrically connecting the red light emitting element 120R of the reserved sub-pixel SPA to the pixel circuit of the first sub-pixel SP1 when a defect occurs on the red light emitting element 120R of the first sub-pixel SP1. One end of the first repair line WRL1 may be connected to the 1-1 connection electrode CE1a of the reserved sub-pixel SPA, and the other end of the first repair line WRL1 may overlap the first reflective electrode RE1 of the first sub-pixel SP1. The other end of the first repair line WRL1 may be disposed to overlap the first reflective electrode RE1 of the first sub-pixel SP1 and to be spaced apart from the 1-1 connection electrode CE1a of the first sub-pixel SP1. When a defect occurs in the red light emitting element 120R of the first sub-pixel SP1, a welding process of irradiating the other end of the first repair line WRL1 with a laser beam may be performed to electrically connect the first repair line WRL1 and the first reflective electrode RE1. Therefore, after the welding process, the red light emitting element 120R of the reserved sub-pixel SPA may be operated by electrically connecting the red light emitting element 120R of the reserved sub-pixel SPA to the driving transistor DT of the first sub-pixel SP1 through the first repair line WRL1.

[0179] The second repair line WRL2 is disposed on the third planarization layer 115c and between the reserved sub-pixel SPA and the second sub-pixel SP2. The second repair line WRL2 is a line for electrically connecting the green light emitting element 120G of the reserved sub-pixel SPA to the pixel circuit of the second sub-pixel SP2 when a defect occurs on the green light emitting element 120G of the second sub-pixel SP2. One end of the second repair line WRL2 may be connected to the 1-2 connection electrode CE1b of the reserved sub-pixel SPA, and the other end of the second repair line WRL2 may overlap with the first reflection electrode RE1 of the second sub-pixel SP2. The other end of the second repair line WRL2 may be disposed to overlap with the first reflection electrode RE1 of the second sub-pixel SP2 and to be spaced apart from the 1-2 connection electrode CE1b of the second sub-pixel SP2. When a defect occurs on the green light emitting element 120G of the second sub-pixel SP2, a welding process of irradiating the other end of the second repair line WRL2 with a laser beam may be performed to electrically connect the second repair line WRL2 and the first reflection electrode RE1. Therefore, after the welding process, the green light emitting element 120G of the reserved sub-pixel SPA may be operated by electrically connecting the green light emitting element 120G of the reserved sub-pixel SPA to the driving transistor DT of the second sub-pixel SP2 through the second repair line WRL2.

[0180] The third repair line WRL3 is disposed on the fourth planarization layer 115d and between the reserved sub-pixel SPA and the third sub-pixel SP3. The third repair line WRL3 is a line for electrically connecting the blue light emitting element 120B of the reserved sub-pixel SPA to the pixel circuit of the third sub-pixel SP3 when a defect occurs on the blue light emitting element 120B of the third sub-pixel SP3. One end of the third repair line WRL3 may be connected to the 1st-3rd connection electrode CE1c of the reserved sub-pixel SPA, and the other end of the third repair line WRL3 may overlap with the first reflective electrode RE1 of the third sub-pixel SP3. The other end of the third repair line WRL3 may be disposed to overlap with the first reflective electrode RE1 of the third sub-pixel SP3 and to be spaced apart from the 1st-3rd connection electrode CE1c of the third sub-pixel SP3. When a defect occurs in the blue light emitting element 120B of the third sub-pixel SP3, a welding process using a laser beam to irradiate the other end of the third repair line WRL3 may be performed to electrically connect the third repair line WRL3 and the first reflective electrode RE1. Therefore, after the welding process, the blue light emitting element 120B of the reserved sub-pixel SPA may be operated by electrically connecting the blue light emitting element 120B of the reserved sub-pixel SPA to the driving transistor DT of the third sub-pixel SP3 through the third repair line WRL3.

[0181] The first repair line WRL1, the second repair line WRL2, and the third repair line WRL3 may at least partially overlap each other. Because the first repair line WRL1, the second repair line WRL2, and the third repair line WRL3 are disposed on different layers, the first repair line WRL1, the second repair line WRL2, and the third repair line WRL3 do not interfere with each other even if the first repair line WRL1, the second repair line WRL2, and the third repair line WRL3 are disposed in the same area. For example, a portion of the first repair line WRL1 and a portion of the second repair line WRL2 may overlap each other, and a portion of the second repair line WRL2 may overlap with the third repair line WRL3.

[0182] However, among the plurality of repair lines WRL, only one repair line WRL may be disposed in the welding area WA of each of the plurality of sub-pixels SP. For example, the other end of the first repair line WRL1 may be disposed only in the welding area WA of the first sub-pixel SP1. If the first repair line WRL1 and the second repair line WRL2 are disposed together in the welding area WA of the first sub-pixel SP1, the first repair line WRL1, the second repair line WRL2, and the first reflective electrode RE1 are connected together during the welding process, which may cause a defect in that the green light emitting element 120G is connected to the driving transistor DT of the first sub-pixel SP1. Therefore, only one repair line WRL may be disposed in the welding area WA.

[0183] In addition, a region where the first reflective electrode RE1 overlaps each of the plurality of repair lines WRL may also be defined as a welding region WA irradiated with a laser beam during a repair process.

[0184] In addition, the first connection electrode CE1 of each of the plurality of sub-pixels SP is not disposed in the welding area WA. If the first connection electrode CE1 is disposed even in the welding area WA, the repair line WRL and the first connection electrode CE1 are connected to each other, and the light emitting element 120 of the reserved sub-pixel SPA or the sub-pixel SP may operate abnormally. Therefore, the 1-1 connection electrode CE1a of the first sub-pixel SP1, the 1-2 connection electrode CE1b of the second sub-pixel SP2, and the 1-3 connection electrode CE1c of the third sub-pixel SP3 may be disposed to be spaced apart from the welding area WA.

[0185] Next, refer to Figure 4 , Fig. 9 and Fig.10 When a defect occurs on the light emitting element 120 of any one of the multiple sub-pixels SP, a repair process can be performed by separating the pixel circuit and the defective light emitting element 120 and connecting the light emitting element 120 of the reserved sub-pixel SPA to the pixel circuit of the sub-pixel SP in which the defective light emitting element 120 is provided.

[0186] First, the defective light emitting element 120 and the pixel circuit may be separated. If the pixel circuit is not electrically separated from the defective light emitting element 120, a bright spot defect in which the defective light emitting element 120 operates abnormally may occur. For example, the defective light emitting element 120 continues to emit light regardless of the image, which may cause a problem of recognizing a bright spot. Therefore, the pixel circuit and the defective light emitting element 120 may be separated so that a driving current is not provided from the pixel circuit to the defective light emitting element 120.

[0187] By destroying the connection between the defective light emitting element 120 and the driving source electrode DSE of the driving transistor DT, the driving current transmission route between the defective light emitting element 120 and the pixel circuit can be eliminated. The light emitting element 120 and the driving transistor DT of each of the plurality of sub-pixels SP can be electrically connected to each other through the auxiliary electrode AE, the first reflective electrode RE1 and the first connection electrode CE1. In addition, any of the connection portions between the auxiliary electrode AE, the first reflective electrode RE1 and the first connection electrode CE1 can be destroyed by irradiation with a laser beam. For example, the first connection electrode CE1 and the first reflective electrode RE1 can be electrically separated by irradiating a region with a contact hole through which the first connection electrode CE1 and the first reflective electrode RE1 are connected with a laser beam. Therefore, the path for providing the driving current between the defective light emitting element 120 and the driving transistor DT can be blocked, which can suppress the bright spot defect of the defective light emitting element 120 continuously emitting light. However, another part of the connection portion between the driving transistor DT and the defective light emitting element 120 can be irradiated with a laser beam, and the present disclosure is not limited thereto. It should be noted that although Figures 4 to 8 The specific arrangement and layer structure of the display device are shown, but this is provided only by way of example, and the present disclosure is not limited thereto. For example, the layer structure of the display device can be changed in various ways, and one or more of the interlayer insulating layer or the planarization layer can be omitted when necessary.

[0188] Next, refer to Fig. 9 and Fig.10, by irradiating the other end of the repair line WRL connected to the light emitting element 120 of the same type as the light emitting element 120 of the defective sub-pixel SP with a laser beam, the repair line WRL can be electrically connected to the first reflective electrode RE1 of the sub-pixel SP in which the defective light emitting element 120 is disposed. For example, the repair line WRL and the first reflective electrode RE1 can be electrically connected by irradiating the welding area WA of the other end of the repair line WRL with a laser beam. A welding process of electrically connecting the repair line WRL and the first reflective electrode RE1 can be performed to electrically connect one of the light emitting elements 120 of the reserved sub-pixel SPA to the pixel circuit of the sub-pixel SP, for example, the driving transistor DT. Therefore, instead of the defective light emitting element 120, the light emitting element 120 of the reserved sub-pixel SPA can be operated by connecting the light emitting element 120 of the reserved sub-pixel SPA to the pixel circuit of another sub-pixel SP, so that an image can be displayed normally.

[0189] For example, when the red light emitting element 120R of the first sub-pixel SP1 is defective, the contact portion between the 1-1 connection electrode CE1a of the first sub-pixel SP1 and the first reflective electrode RE1 may be destroyed, which may suppress the bright spot defect of the defective red light emitting element 120R. Fig. 9 and Fig.10 , the first repair line WRL1 and the first reflective electrode RE1 of the first sub-pixel SP1 can be electrically connected by irradiating the welding area WA (where the first repair line WRL1 and the first reflective electrode RE1 of the first sub-pixel SP1 overlap each other) with a laser beam. Therefore, the red light emitting element 120R of the reserved sub-pixel SPA can be electrically connected between the high potential power line VDD and the driving transistor DT of the first sub-pixel SP1, and a driving current is provided. Therefore, instead of the defective red light emitting element 120R of the first sub-pixel SP1, the red light emitting element 120R of the reserved sub-pixel SPA can display an image, and the reserved sub-pixel SPA can be used as the first sub-pixel SP1.

[0190] For example, in the case where the green light emitting element 120G of the second sub-pixel SP2 is defective, the contact portion between the 1-2 connection electrode CE1b of the second sub-pixel SP2 and the first reflective electrode RE1 can be destroyed, which can suppress the bright spot defect of the defective green light emitting element 120G. In addition, the second repair line WRL2 and the first reflective electrode RE1 of the second sub-pixel SP2 can be electrically connected by irradiating the welding area WA with a laser beam (where the second repair line WRL2 and the first reflective electrode RE1 of the second sub-pixel SP2 overlap each other). Therefore, the green light emitting element 120G of the reserved sub-pixel SPA can be electrically connected between the high potential power line VDD and the driving transistor DT of the second sub-pixel SP2, and a driving current is provided. Therefore, instead of the defective green light emitting element 120G of the second sub-pixel SP2, the green light emitting element 120G of the reserved sub-pixel SPA can display an image, and the reserved sub-pixel SPA can be used as the second sub-pixel SP2.

[0191] Finally, in the case where the blue light emitting element 120B of the third sub-pixel SP3 is defective, the contact portion between the 1-3 connection electrode CE1c of the third sub-pixel SP3 and the first reflective electrode RE1 can be destroyed, which can suppress the bright spot defect of the defective blue light emitting element 120B. In addition, the third repair line WRL3 and the first reflective electrode RE1 of the third sub-pixel SP3 can be electrically connected by irradiating the welding area WA (where the third repair line WRL3 and the first reflective electrode RE1 of the third sub-pixel SP3 overlap each other) with a laser beam. Therefore, the blue light emitting element 120B of the reserved sub-pixel SPA can be electrically connected between the high potential power supply line VDD and the driving transistor DT of the third sub-pixel SP3, and a driving current is provided. Therefore, instead of the defective blue light emitting element 120B of the third sub-pixel SP3, the blue light emitting element 120B of the reserved sub-pixel SPA can display an image, and the reserved sub-pixel SPA can be used as the third sub-pixel SP3.

[0192] In this case, the red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B set in the reserved sub-pixel SPA, and the repair line WRL connected to the red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B can be set on different layers and separated from each other. Therefore, even if two or more sub-pixels SP among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are defective, one reserved sub-pixel SPA can be used to repair the two or more sub-pixels SP. For example, when the first sub-pixel SP1 and the second sub-pixel SP2 are defective, the red light emitting element 120R and the green light emitting element 120G of the reserved sub-pixel SPA can be electrically connected to the driving transistors DT of the first sub-pixel SP1 and the second sub-pixel SP2, so that the reserved sub-pixel SPA can be used as both the first sub-pixel SP1 or the second sub-pixel SP2.

[0193] In addition, in the reserved sub-pixel SPA, the plurality of light-emitting elements 120 may be arranged to at least partially overlap each other. However, the light-emitting element 120 located on the upper side of the plurality of light-emitting elements 120 may be configured to be substantially transparent, which may minimize or reduce the extent to which the light-emitting element 120 obstructs the propagation of light emitted from other light-emitting elements 120.

[0194] For example, in the case where the red light emitting element 120R disposed at the lowermost side among the plurality of light emitting elements 120 emits light, the first electrode 124 and the second electrode 125 of the green light emitting element 120G and the blue light emitting element 120B disposed above the red light emitting element 120R may be made of a transparent conductive material so that the light emitted from the red light emitting element 120R can be normally transmitted. For example, in the reserved sub-pixel SPA, the green light emitting element 120G and the blue light emitting element 120B disposed on the red light emitting element 120R may include a transparent first electrode 124 and a transparent second electrode 125 so that the light emitted from the red light emitting element 120R can be transmitted to the outside of the display device 100. Similarly, in the case where the green light emitting element 120G of the reserved sub-pixel SPA emits light, the blue light emitting element 120B on the green light emitting element 120G may include a transparent first electrode 124 and a transparent second electrode 125 so that the light emitted from the green light emitting element 120G can be easily transmitted to the outside of the display device 100.

[0195] In addition, at least any one of the first electrode 124 and the second electrode 125 of the red light emitting element 120R disposed at the lowermost side among the plurality of light emitting elements 120 of the reserved sub-pixel SPA may be made of an opaque conductive material. However, because the red light emitting element 120R having an opaque electrode is disposed below the green light emitting element 120G and the blue light emitting element 120B in the reserved sub-pixel SPA, the red light emitting element 120R may not hinder the propagation of light emitted from the green light emitting element 120G and the blue light emitting element 120B. However, the present disclosure is not limited thereto, and the first electrode 124 and the second electrode 125 of the red light emitting element 120R may also be formed of a transparent conductive material.

[0196] Therefore, based on the display device 100 according to the embodiment of the present disclosure, when the light emitting element 120 disposed in one of the plurality of sub-pixels SP is defective, the reserved sub-pixel SPA can eliminate the defect. All of the red light emitting elements 120R, the green light emitting elements 120G, and the blue light emitting elements 120B are disposed in the reserved sub-pixel SPA. In addition, in the case where any of the light emitting elements 120 disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 is defective, the light emitting element 120 of the reserved sub-pixel SPA can be electrically connected to the pixel circuit of the sub-pixel SP including the defective light emitting element 120, so that the light emitting element 120 of the reserved sub-pixel SPA can replace the defective light emitting element 120 for operation. For example, in the case where the red light emitting element 120R of the first sub-pixel SP1 is defective, the red light emitting element 120R of the reserved sub-pixel SPA and the driving transistor DT of the first sub-pixel SP1 can be electrically connected, so that the red light emitting element 120R of the reserved sub-pixel SPA can operate.

[0197] In this case, the light emitting element 120 of the reserved sub-pixel SPA and the pixel circuits of the plurality of sub-pixels SP may be selectively connected by using a plurality of repair lines WRL. For example, one end of each of the plurality of repair lines WRL may be electrically connected to the first electrode 124 of each of the plurality of light emitting elements 120 of the reserved sub-pixel SPA, and the other end of each of the plurality of repair lines WRL may overlap with the first reflective electrode RE1 of each of the plurality of sub-pixels SP. At the initial time, the other end of the repair line WRL and the first reflective electrode RE1 may be in an insulating state with an insulating layer interposed therebetween. In addition, in the case where a sub-pixel SP including a defective light emitting element 120 is detected, the insulating layer may be opened by irradiating a welding area WA (where the first reflective electrode RE1 and the other end of the repair line WRL overlap) with a laser beam, so that the first reflective electrode RE1 and the repair line WRL may be electrically connected. Therefore, the light emitting element 120 of the reserved sub-pixel SPA may be electrically connected to the driving transistor DT of the sub-pixel SP including the defective light emitting element 120 through the repair line WRL and the first reflective electrode RE1.

[0198] In addition, in the related art, a plurality of light-emitting elements are connected to one pixel circuit to prepare for a defect of a sub-pixel, and even if one light-emitting element is defective, the sub-pixel is operated by using the remaining light-emitting elements. However, since a plurality of light-emitting elements are connected in parallel to one pixel circuit, the density of the driving current to be supplied to the light-emitting element is reduced, and the luminous efficiency of the light-emitting element is deteriorated.

[0199] Therefore, based on the display device 100 according to the embodiment of the present disclosure, only one light emitting element 120 is connected to one pixel circuit, which can improve the density of the driving current to be provided to the light emitting element 120. For example, the driving transistor DT of the pixel circuit of the first sub-pixel SP1 can be connected to only one red light emitting element 120R and provide a high-density driving current. In addition, even if a defect occurs on the light emitting element 120 set in each sub-pixel SP, the light emitting element 120 set in the reserved sub-pixel SPA can also be used to repair the light emitting element 120, which can minimize or reduce the degradation of the display quality of the display device 100.

[0200] In addition, based on the display device 100 according to the embodiment of the present disclosure, a plurality of light-emitting elements 120 formed in the reserved sub-pixel SPA may be stacked in the vertical direction, which may reduce the area occupied by the reserved sub-pixel SPA. For example, in the reserved sub-pixel SPA, the red light-emitting element 120R may be disposed on the first bonding layer AD1, the green light-emitting element 120G may be disposed above the red light-emitting element 120R, the blue light-emitting element 120B may be disposed above the green light-emitting element 120G, and the red light-emitting element 120R, the green light-emitting element 120G, and the blue light-emitting element 120B may at least partially overlap each other. In this case, an area for disposing the red light-emitting element 120R, an area for disposing the green light-emitting element 120G, and an area for disposing the blue light-emitting element 120B may be formed on different planes. If the red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B are disposed on the same layer, the area of ​​the reserved sub-pixel SPA can be increased to ensure an area for disposing the red light emitting element 120R, an area for disposing the green light emitting element 120G, and an area for disposing the blue light emitting element 120B. Therefore, in the display device 100 according to an embodiment of the present disclosure, the red light emitting element 120R, the green light emitting element 120G, and the blue light emitting element 120B can be stacked in the reserved sub-pixel SPA, which can reduce the area occupied by the reserved sub-pixel SPA and increase the area of ​​the transmission area TA of the display device 100 to the extent that the area of ​​the reserved sub-pixel SPA is reduced.

[0201] In addition, one pixel PX does not include a plurality of additional sub-pixels SP for repairing a plurality of sub-pixels SP, but one pixel PX includes only one reserved sub-pixel SPA, which can reduce the area of ​​the pixel area UPA. Therefore, more pixel areas UPA can be formed while maintaining the same level of transmittance as the related art, which can realize a high-resolution display device 100.

[0202] In the display device 100 according to an embodiment of the present disclosure, the electrode of the light-emitting element 120 disposed on the upper side among the plurality of light-emitting elements 120 vertically stacked in the reserved sub-pixel SPA may be made of a transparent conductive material so as not to inhibit the propagation of light emitted from the light-emitting element 120 located on the lower side. In order to reduce the area of ​​the reserved sub-pixel SPA, the red light-emitting element 120R, the green light-emitting element 120G, and the blue light-emitting element 120B may be disposed while being vertically stacked and overlapping each other. In this case, when the electrodes of the green light-emitting element 120G and the blue light-emitting element 120B disposed on the red light-emitting element 120R are made of an opaque conductive material, the propagation efficiency of the light emitted from the red light-emitting element 120R disposed on the lower side may be degraded or reduced. Therefore, the electrodes of the green light-emitting element 120G and the blue light-emitting element 120B located on the red light-emitting element 120R may be made of a transparent conductive material, which may improve the light propagation efficiency of the reserved sub-pixel SPA.

[0203] Exemplary embodiments of the present disclosure may also be described as follows:

[0204] According to one aspect of the present disclosure, a display device includes: a substrate having a plurality of pixel areas; a plurality of pixels, the plurality of pixels are arranged in the plurality of pixel areas and each includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a reserved sub-pixel; a first light-emitting element, the first light-emitting element is respectively arranged in the first sub-pixel and the reserved sub-pixel; a second light-emitting element, the second light-emitting element is respectively arranged in the second sub-pixel and the reserved sub-pixel; and a third light-emitting element, the third light-emitting element is respectively arranged in the third sub-pixel and the reserved sub-pixel, and the first light-emitting element, the second light-emitting element and the third light-emitting element are arranged on different layers in the reserved sub-pixel.

[0205] The plurality of pixel regions may be spaced apart from one another, and the transmissive region may be disposed between the plurality of pixel regions.

[0206] The first light emitting element may emit red light, the second light emitting element may emit green light, and the third light emitting element may emit blue light.

[0207] In the reserved sub-pixel, the first light emitting element, the second light emitting element, and the third light emitting element may at least partially overlap with each other.

[0208] The first light-emitting element of the first sub-pixel can be set on the same layer as the first light-emitting element of the reserved sub-pixel, the second light-emitting element of the second sub-pixel can be set on the same layer as the second light-emitting element of the reserved sub-pixel, and the third light-emitting element of the third sub-pixel can be set on the same layer as the third light-emitting element of the reserved sub-pixel.

[0209] The display device may also include a plurality of repair lines connected to the reserved sub-pixel, wherein the plurality of repair lines may include: a first repair line, one end of which is connected to the first electrode of the first light-emitting element of the reserved sub-pixel; a second repair line, one end of which is connected to the first electrode of the second light-emitting element of the reserved sub-pixel; and a third repair line, one end of which is connected to the first electrode of the third light-emitting element of the reserved sub-pixel, and wherein the first repair line, the second repair line and the third repair line may be arranged on different layers.

[0210] The first repair line, the second repair line, and the third repair line may at least partially overlap one another.

[0211] The display device may further include: a driving transistor, which is respectively arranged in the first sub-pixel, the second sub-pixel and the third sub-pixel; a first reflective electrode, which is respectively arranged in the first sub-pixel, the second sub-pixel and the third sub-pixel, is arranged on the driving transistor, and is each configured to electrically connect the driving transistor to the first electrode of the corresponding light-emitting element among the first light-emitting element, the second light-emitting element and the third light-emitting element; and a second reflective electrode, which is respectively arranged in the first sub-pixel, the second sub-pixel and the third sub-pixel, is arranged on the driving transistor, and is electrically connected to the second electrode of each of the first light-emitting element, the second light-emitting element and the third light-emitting element.

[0212] The display device may also include a data line and a low potential power line, which are connected to and overlap with multiple pixel areas, wherein the low potential power line can be arranged between the data line and the driving transistor and can at least cover the driving gate electrode of the driving transistor.

[0213] The display device may further include: a first planarization layer, the first planarization layer is arranged between the driving transistor and the first reflective electrode and between the driving transistor and the second reflective electrode; a first bonding layer, the first bonding layer is arranged on the first reflective electrode and the second reflective electrode, and the first light-emitting element is attached to the upper surface of the first bonding layer; a second planarization layer, the second planarization layer is arranged on the first light-emitting element and the first bonding layer; a second bonding layer, the second bonding layer is arranged on the second planarization layer, and the second light-emitting element is attached to the upper surface of the second bonding layer; a third planarization layer, the third planarization layer is arranged on the second light-emitting element and the second bonding layer; a third bonding layer, the third bonding layer is arranged on the third planarization layer, and the third light-emitting element is attached to the upper surface of the third bonding layer; and a fourth planarization layer, the fourth planarization layer is arranged on the third light-emitting element and the third bonding layer.

[0214] The first repair line may be disposed between the second planarization layer and the second bonding layer, the second repair line may be disposed between the third planarization layer and the third bonding layer, and the third repair line may be disposed on the fourth planarization layer.

[0215] The display device may also include: a 1-1 connecting electrode, the 1-1 connecting electrode is arranged in the first sub-pixel and the reserved sub-pixel, each 1-1 connecting electrode is arranged between the second planarization layer and the second bonding layer, and each 1-1 connecting electrode is electrically connected to the first electrode of the first light-emitting element; a 1-2 connecting electrode, the 1-2 connecting electrode is arranged in the second sub-pixel and the reserved sub-pixel, each 1-2 connecting electrode is arranged between the third planarization layer and the third bonding layer, and each 1-2 connecting electrode is electrically connected to the first electrode of the second light-emitting element; and a 1-3 connecting electrode, the 1-3 connecting electrode is arranged in the third sub-pixel and the reserved sub-pixel, each 1-3 connecting electrode is arranged on the fourth planarization layer, and each 1-3 connecting electrode is electrically connected to the first electrode of the third light-emitting element, wherein the 1-1 connecting electrode and the first repair line arranged in the first sub-pixel can be arranged to be spaced apart from each other, the 1-2 connecting electrode and the second repair line arranged in the second sub-pixel can be arranged to be spaced apart from each other, and the 1-3 connecting electrode and the third repair line arranged in the third sub-pixel can be arranged to be spaced apart from each other.

[0216] The 1-1 connection electrode set in the first sub-pixel can be set to be separated from the first area, the 1-2 connection electrode set in the second sub-pixel can be set to be separated from the second area, and the 1-3 connection electrode set in the third sub-pixel can be set to be separated from the third area. In the first area, the first repair line can overlap with the first reflective electrode of the first sub-pixel, in the second area, the second repair line can overlap with the first reflective electrode of the second sub-pixel, and in the third area, the third repair line can overlap with the first reflective electrode of the third sub-pixel.

[0217] A contact region where the driving transistor contacts the first reflective electrode may be different from another contact region where the first reflective electrode contacts the 1-1 connection electrode, the 1-2 connection electrode, or the 1-3 connection electrode.

[0218] The 1-1th connection electrode in the first sub-pixel may be electrically connected to the first reflective electrode through a contact hole formed in the second planarization layer and the first bonding layer.

[0219] The 1-2 connecting electrode in the second sub-pixel can be electrically connected to the first reflective electrode through a contact hole formed in the third planarization layer, the second bonding layer, the second planarization layer, and the first bonding layer, and the 1-3 connecting electrode in the third sub-pixel can be electrically connected to the first reflective electrode through a contact hole formed in the fourth planarization layer, the third bonding layer, the third planarization layer, the second bonding layer, the second planarization layer, and the first bonding layer.

[0220] The display device may further include: a 2-1st connecting electrode, the 2-1 connecting electrode is arranged in the first sub-pixel and the reserved sub-pixel, each 2-1 connecting electrode is arranged between the second planarization layer and the second bonding layer, and each 2-1 connecting electrode is electrically connected to the second reflective electrode and the second electrode of the first light-emitting element; a 2-2 connecting electrode, the 2-2 connecting electrode is arranged in the second sub-pixel and the reserved sub-pixel, each 2-2 connecting electrode is arranged between the third planarization layer and the third bonding layer, and each 2-2 connecting electrode is electrically connected to the second reflective electrode and the second electrode of the second light-emitting element; and a 2-3 connecting electrode, the 2-3 connecting electrode is arranged in the third sub-pixel and the reserved sub-pixel, each 2-3 connecting electrode is arranged on the fourth planarization layer, and each 2-3 connecting electrode is electrically connected to the second reflective electrode and the second electrode of the third light-emitting element.

[0221] The first contact hole, the second contact hole, and the third contact hole may overlap with each other, the 2-1 connection electrode and the second reflective electrode may contact each other through the first contact hole, the 2-2 connection electrode and the second reflective electrode may contact each other through the second contact hole, the 2-3 connection electrode and the second reflective electrode may contact each other through the third contact hole, and the 2-1 connection electrode, the 2-2 connection electrode, and the 2-3 connection electrode may be adjacent to each other.

[0222] The first electrode and the second electrode of the third light emitting element may be made of a transparent conductive material, and the first electrode and the second electrode of the second light emitting element may be made of a transparent conductive material.

[0223] The first electrode and the second electrode of the first light emitting element may be at least partially made of an opaque conductive material.

[0224] The other end of the first repair line may overlap the first reflective electrode of the first subpixel, the other end of the second repair line may overlap the first reflective electrode of the second subpixel, and the other end of the third repair line may overlap the first reflective electrode of the third subpixel.

[0225] In some of the plurality of pixels, the other end of each of the plurality of repair lines and the first reflective electrode may be disposed to be spaced apart from each other with an insulating layer interposed therebetween.

[0226] In some of the remaining pixels among the plurality of pixels, the insulating layer may be opened, and the other end of one of the first repair line, the second repair line, and the third repair line and the first reflective electrode may be connected to each other.

[0227] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

[0228] CROSS-REFERENCE TO RELATED APPLICATIONS

[0229] This application claims the benefit of and priority to Korean Patent Application No. 10-2023-0136745 filed in Korea on October 13, 2023, the entire disclosure of which is incorporated herein by reference for all purposes.

Claims

1. A display device, comprising: A substrate having a plurality of pixel regions; A plurality of pixels, the plurality of pixels are arranged in the plurality of pixel regions and each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a reserved sub-pixel; A first light-emitting element, wherein the first light-emitting element is respectively arranged in the first sub-pixel and the reserved sub-pixel; a second light emitting element, wherein the second light emitting element is respectively disposed in the second sub-pixel and the reserved sub-pixel; a third light-emitting element, wherein the third light-emitting element is respectively arranged in the third sub-pixel and the reserved sub-pixel, The first light-emitting element, the second light-emitting element and the third light-emitting element are arranged on different layers in the reserved sub-pixel.

2. The display device according to claim 1, wherein: The plurality of pixel regions are spaced apart from each other, and the transmissive region is disposed between the plurality of pixel regions.

3. The display device according to claim 1, wherein: The first light emitting element emits red light, the second light emitting element emits green light, and the third light emitting element emits blue light.

4. The display device according to claim 1, wherein: In the reserved sub-pixel, the first light emitting element, the second light emitting element, and the third light emitting element at least partially overlap with each other.

5. The display device according to claim 1, wherein: The first light-emitting element of the first sub-pixel is arranged on the same layer as the first light-emitting element of the reserved sub-pixel, the second light-emitting element of the second sub-pixel is arranged on the same layer as the second light-emitting element of the reserved sub-pixel, and the third light-emitting element of the third sub-pixel is arranged on the same layer as the third light-emitting element of the reserved sub-pixel.

6. The display device according to claim 1, further comprising a plurality of repair lines connected to the reserved sub-pixels, in, The plurality of repair lines include: a first repair line, one end of which is connected to the first electrode of the first light-emitting element of the reserved sub-pixel; a second repair line, one end of which is connected to the first electrode of the second light emitting element of the reserved sub-pixel; and a third repair line, one end of which is connected to the first electrode of the third light emitting element of the reserved sub-pixel, and Wherein, the first repair line, the second repair line and the third repair line are arranged on different layers.

7. The display device according to claim 6, wherein: The first repair line, the second repair line, and the third repair line at least partially overlap one another.

8. The display device according to claim 6, further comprising: driving transistors, wherein the driving transistors are respectively arranged in the first sub-pixel, the second sub-pixel and the third sub-pixel; first reflective electrodes, which are respectively disposed in the first sub-pixel, the second sub-pixel, and the third sub-pixel, are disposed on the driving transistor, and are each configured to electrically connect the driving transistor to the first electrode of a corresponding light-emitting element among the first light-emitting element, the second light-emitting element, and the third light-emitting element; as well as A second reflective electrode is disposed in the first sub-pixel, the second sub-pixel and the third sub-pixel, respectively, is disposed on the driving transistor, and is electrically connected to a second electrode of each of the first light-emitting element, the second light-emitting element and the third light-emitting element.

9. The display device according to claim 8, further comprising a data line and a low potential power line, the data line and the low potential power line being connected to and overlapping the plurality of pixel regions, in, The low potential power supply line is provided between the data line and the driving transistor and covers at least a driving gate electrode of the driving transistor.

10. The display device according to claim 8, further comprising: a first planarization layer, the first planarization layer being disposed between the driving transistor and the first reflective electrode and between the driving transistor and the second reflective electrode; a first bonding layer, the first bonding layer being disposed on the first reflective electrode and the second reflective electrode, and the first light emitting element being attached to an upper surface of the first bonding layer; a second planarization layer, the second planarization layer being disposed on the first light emitting element and the first bonding layer; a second bonding layer, the second bonding layer being disposed on the second planarization layer and having the second light emitting element attached to an upper surface of the second bonding layer; a third planarization layer, the third planarization layer being disposed on the second light emitting element and the second bonding layer; a third bonding layer, the third bonding layer being disposed on the third planarization layer and having the third light emitting element attached to an upper surface of the third bonding layer; as well as A fourth planarization layer is provided on the third light emitting element and the third bonding layer.

11. The display device according to claim 10, wherein: The first repair line is disposed between the second planarization layer and the second bonding layer, the second repair line is disposed between the third planarization layer and the third bonding layer, and the third repair line is disposed on the fourth planarization layer.

12. The display device according to claim 11, further comprising: a 1-1 connecting electrode, the 1-1 connecting electrode being disposed in the first sub-pixel and the reserved sub-pixel, each 1-1 connecting electrode being disposed between the second planarization layer and the second bonding layer, and each 1-1 connecting electrode being electrically connected to the first electrode of the first light-emitting element; a 1-2 connecting electrode, wherein the 1-2 connecting electrode is disposed in the second sub-pixel and the reserved sub-pixel, each 1-2 connecting electrode is disposed between the third planarization layer and the third bonding layer, and each 1-2 connecting electrode is electrically connected to the first electrode of the second light-emitting element; as well as a 1st-3rd connecting electrode, wherein the 1st-3rd connecting electrode is disposed in the third sub-pixel and the reserved sub-pixel, each 1st-3rd connecting electrode is disposed on the fourth planarization layer, and each 1st-3rd connecting electrode is electrically connected to the first electrode of the third light-emitting element, Among them, the 1-1 connecting electrode and the first repair line set in the first sub-pixel are set to be spaced apart from each other, the 1-2 connecting electrode and the second repair line set in the second sub-pixel are set to be spaced apart from each other, and the 1-3 connecting electrode and the third repair line set in the third sub-pixel are set to be spaced apart from each other.

13. The display device according to claim 12, wherein: The 1-1 connecting electrode set in the first sub-pixel is set to be separated from the first area, the 1-2 connecting electrode set in the second sub-pixel is set to be separated from the second area, and the 1-3 connecting electrode set in the third sub-pixel is set to be separated from the third area, in the first area, the first repair line overlaps with the first reflective electrode of the first sub-pixel, in the second area, the second repair line overlaps with the first reflective electrode of the second sub-pixel, and in the third area, the third repair line overlaps with the first reflective electrode of the third sub-pixel.

14. The display device according to claim 12, wherein: A contact region where the driving transistor contacts the first reflective electrode is different from another contact region where the first reflective electrode contacts the 1-1 connection electrode, the 1-2 connection electrode, or the 1-3 connection electrode.

15. The display device according to claim 12, wherein: The 1-1 connection electrode in the first sub-pixel is electrically connected to the first reflective electrode through a contact hole formed in the second planarization layer and the first bonding layer, The 1-2 connection electrode in the second sub-pixel is electrically connected to the first reflective electrode through a contact hole formed in the third planarization layer, the second bonding layer, the second planarization layer, and the first bonding layer, and The 1-3rd connecting electrode in the third subpixel is electrically connected to the first reflective electrode through a contact hole formed in the fourth planarization layer, the third bonding layer, the third planarization layer, the second bonding layer, the second planarization layer, and the first bonding layer.

16. The display device according to claim 11, further comprising: 2-1 connecting electrodes, the 2-1 connecting electrodes being arranged in the first sub-pixel and the reserved sub-pixel, each 2-1 connecting electrode being arranged between the second planarization layer and the second bonding layer, and each 2-1 connecting electrode being electrically connected to the second reflective electrode and the second electrode of the first light-emitting element; 2-2 connecting electrodes, the 2-2 connecting electrodes being arranged in the second sub-pixel and the reserved sub-pixel, each 2-2 connecting electrode being arranged between the third planarization layer and the third bonding layer, and each 2-2 connecting electrode being electrically connected to the second reflective electrode and the second electrode of the second light-emitting element; as well as The 2nd-3rd connecting electrode is arranged in the third sub-pixel and the reserved sub-pixel, each 2nd-3rd connecting electrode is arranged on the fourth planarization layer, and each 2nd-3rd connecting electrode is electrically connected to the second reflective electrode and the second electrode of the third light-emitting element.

17. The display device according to claim 16, wherein: The first contact hole, the second contact hole, and the third contact hole overlap each other, the 2-1 connection electrode and the second reflective electrode contact each other through the first contact hole, the 2-2 connection electrode and the second reflective electrode contact each other through the second contact hole, the 2-3 connection electrode and the second reflective electrode contact each other through the third contact hole, and The 2-1st connecting electrode, the 2-2nd connecting electrode, and the 2-3rd connecting electrode are adjacent to each other.

18. The display device according to claim 10, wherein: The first electrode and the second electrode of the third light emitting element are made of a transparent conductive material, and the first electrode and the second electrode of the second light emitting element are made of a transparent conductive material.

19. The display device according to claim 18, wherein: The first electrode and the second electrode of the first light emitting element are at least partially made of an opaque conductive material.

20. The display device according to claim 8, wherein: The other end of the first repair line overlaps the first reflective electrode of the first subpixel, the other end of the second repair line overlaps the first reflective electrode of the second subpixel, and the other end of the third repair line overlaps the first reflective electrode of the third subpixel.

21. The display device according to claim 20, wherein: In some of the plurality of pixels, the other end of each of the plurality of repair lines and the first reflective electrode are disposed to be spaced apart from each other, and an insulating layer is interposed between the other end of each of the plurality of repair lines and the first reflective electrode.

22. The display device according to claim 21, wherein: In some of the remaining pixels among the plurality of pixels, the insulating layer is opened, and the other end of one of the first repair line, the second repair line, and the third repair line and the first reflective electrode are connected to each other.

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