GMSK quadrature modulator

Abstract

The invention belongs to the technical field of communication and signal processing, and particularly relates to a GMSK quadrature modulator which comprises a quadrature modulation baseband generator composed of a bidirectional counter, a four-curve data table, an in-phase component processor and a quadrature component processor, and a binary code element sequence and a system clock are input into the quadrature modulation baseband generator. A system clock carries out frequency division to generate a code element frequency multiplication clock to drive the bidirectional counter to carry out oscillation reciprocating counting, the in-phase component processor and the orthogonal component processor carry out processing to generate curve selection types and curve symbols, output of the bidirectional counter is used as a curve look-up table address, and a pre-stored four-curve data table looks up to generate an orthogonal modulation baseband signal. The signal is input into a digital up-conversion (DUC) circuit to generate a GMSK modulation signal. Compared with the prior art, the method saves more resources, is high in precision and small in stray, and is very suitable for design and implementation of an embedded system or a programmable device.

Description

Technical Field

[0001] The invention belongs to the technical field of communication and signal processing, and in particular relates to a GMSK quadrature modulator. Background Art

[0002] In order to make the spectrum compact and reduce interference to adjacent channels, digital frequency modulation generally uses continuous phase frequency modulation (CPM). General smooth frequency modulation (GTFM) using Gaussian premodulation technology is the most widely used and has better effects. GMSK modulation is a typical representative. GMSK generally uses Figure 1 The orthogonal balanced digital FM modulator shown.

[0003] The traditional steps to generate GMSK modulated signals are: first generate a Gaussian filter rectangular pulse response, then perform output integration and phase accumulation after bipolar code element weighted superposition, then use a lookup table (LUT) to output the corresponding phase of the sine and cosine waveforms, and then use DDS technology to achieve orthogonal up-conversion, and output to the RF power amplifier through a high-speed DAC.

[0004] The signal processing method of directly mapping the associated code element combination to the orthogonal modulation baseband signal can omit signal processing steps such as Gaussian filtering and phase integration, greatly simplify the GMSK modulator, and avoid the truncation error that may be caused by Gaussian filtering and phase integration.

[0005] When the correlation length L = 3, there are only 8 combinations of three adjacent correlation symbols, so 8 Gaussian filter signals can be mapped. After integration, the 8 Gaussian filter signals correspond to 8 phase integration paths with an initial phase of zero, such as Figure 2 According to the characteristics of phase continuity, a set of 8 phase integration paths in the first quadrant can be obtained, as shown in Figure 3 This set of phase integration paths is recorded as The digital superscript 1 represents the first quadrant, and the digital subscript j corresponds to the binary value of the associated code element combination.

[0006] right Figure 3 The eight phase integration paths shown are used to calculate the cosine and sine respectively, and the corresponding in-phase component signals are obtained. and quadrature component signals like Figure 4 , Figure 5 shown.

[0007] contrast Figure 4 , Figure 5 It can be found that four of the curves can generate all the in-phase component signals and orthogonal component signals in the first quadrant. These four curves are as follows Figure 6As shown. Further analysis based on the quadrant characteristics of trigonometric functions can prove that the orthogonal modulation baseband signals I(t) and Q(t) in any quadrant can be expressed by and One of them is obtained directly or indirectly, and the indirect form includes sign reversal, order reversal, or reversal in both sign and order.

[0008] Therefore, a quadrature modulator based on LUT (lookup table) technology can be used to implement GMSK modulation, such as Figure 7 As shown. The LUT lookup table is established according to the N times sampling values ​​of the above four basic curves. The lookup table controller needs to complete the following signal processing:

[0009] (1) According to the phase path, calculate the quadrant in which the current symbol integrated phase is located;

[0010] (2) According to the associated code element combination and the quadrant where the integrated phase is located, respectively calculate and determine which of the four basic curves the current in-phase modulation component and the orthogonal modulation component should adopt;

[0011] (3) respectively calculating and determining the order direction of the curves corresponding to the current in-phase modulation component and the orthogonal modulation component, calculating and generating the lookup table address of the LUT lookup table, and looking up the table to generate the amplitudes of the in-phase modulation component and the orthogonal modulation component;

[0012] (4) Calculate and determine the sign bits of the current in-phase modulation component and the orthogonal modulation component respectively, and output the in-phase modulation component and the orthogonal modulation component.

[0013] Although the GMSK quadrature modulator based on LUT (lookup table) technology has omitted signal processing steps such as Gaussian filtering and phase integration, its lookup table controller needs to perform relevant processing based on the full mapping relationship of the four basic curves in any quadrant transformation, and its implementation process is still slightly complicated. Some literatures have also proposed a method for separating the steady-state phase and the transient phase. Although the logic of the lookup table controller is simplified, at least four curves are required for mapping the in-phase component and the orthogonal component, which doubles the memory resources, which is not worth the loss. Summary of the invention

[0014] In view of this, the present invention provides a GMSK quadrature modulator, aiming to optimize and improve the prior art.

[0015] The technical solution of the present invention is:

[0016] A GMSK quadrature modulator consists of a quadrature modulation baseband generator and an up-conversion (DUC) circuit. Its principle block diagram is shown in the figure. Figure 8As shown. The modulator uses a digital architecture of signal processor plus high-speed DAC. The RF power amplifier, power supply and other parts are the same as the conventional design and are omitted here. The hardware to implement the signal processor can be FPGA, DSP or single-chip microcomputer, etc. Figure 8 The quadrature modulation baseband generator in the up-conversion circuit and the DDS, multiplier and adder and other functional modules can be implemented in the signal processor. Up-conversion can also be achieved by using a DAC chip with an internal NCO, and the signal processor only needs to generate the quadrature modulation baseband. If the carrier frequency is high, the signal processor can be used to first generate the quadrature modulation baseband model, then mix it with the intermediate frequency carrier, and then use the DAC chip with an internal NCO to achieve up-conversion. The core of these architectures is the quadrature modulation baseband generator. The quadrature modulation baseband generator is implemented in the signal processor of the digital modulator. Its main input is the modulated code element sequence (or data stream) from the front end of the digital modulator, and the output is connected to the up-conversion (or mixing) module.

[0017] Preferably, the orthogonal modulation baseband generator is composed of a bidirectional counter, a four-curve data table, an in-phase component processor and an orthogonal component processor. The symbol period is T b The binary code element sequence to be modulated and the system clock are input into the orthogonal modulation baseband generator, and the system clock is divided to generate the code element multiplied clock (multiplied period T b / N) pulse; the orthogonal modulation baseband generator collects and stores the associated 3 code elements of this code element period, completes a signal processing in each multiplied clock period, and outputs the orthogonal modulation baseband signal point by point and

[0018] The associated 3-code is denoted as a -1 , a0, a +1 , which represent the binary symbols of the previous symbol period, the current symbol period and the next symbol period currently saved by the orthogonal modulation baseband generator. a -1 , a0, a +1 Can participate in Boolean operations as bits.

[0019] During initialization, the previous cycle symbol of the first symbol is the same as the first symbol; when the modulator stops, the default next cycle symbol is 0.

[0020] Preferably, the bidirectional counter counts the frequency-multiplied clock pulses in a controllable direction, and changes the counting direction according to the odd-even order of the code element sequence to be modulated, with odd-numbered code elements counted down from N-1 to 0, and even-numbered code elements counted up from 1 to N.

[0021] During initialization, the initial value of the bidirectional counter is N, and the first code element is an odd number.

[0022] Preferably, the four-curve data table contains four types of curve data, which are selected from a group of orthogonal modulated baseband signals with a phase path located in the first quadrant, and are obtained by sampling and digital quantization at a sampling rate N.

[0023] The four curves are:

[0024]

[0025]

[0026] in:

[0027] n∈[0,N]

[0028] is a set of phase integration paths corresponding to different associated codeword combinations, where the digital superscript 1 represents the first quadrant, and the digital subscript j corresponds to the binary value of the associated codeword combination.

[0029] Theoretically, the four curves are b When any value greater than 0 is selected, the following requirements can be met:

[0030] S0(0)=S2(0)=sin(0)

[0031] S1(0) = S3(0) = sin(δ)

[0032] S0(N)=S3(N)=cos(0)

[0033] S1(N)=S2(N)=cos(δ)

[0034] Among them, δ is the phase change value caused by inter-code interference, which is related to BT b The correlation reflects the influence of the Gaussian filter on the modulation phase and the continuity relationship of the phase path.

[0035] Through sampling and digital quantization, each curve contains N+1 points of data, using fixed-point numbers and stored in the data memory at the first address interval (N+1).

[0036] If 16-bit fixed-point quantization is used, in order to meet the requirement of independent resolution between the four quantized values ​​corresponding to sin(0) (i.e. 0x0000), sin(δ), cos(0) (i.e. 0x7FFF), and cos(δ), BT b Any value between 0.01 and 30 can be selected, which is sufficient to meet the practical needs of GMSK modulation.

[0037] The four curve types are numbered 0, 1, 2, and 3, respectively, and are represented by two-bit binary codes, with the high bit being c1 and the low bit being c0. c1 and c0 can be used as bits for Boolean operations.

[0038] Preferably, the in-phase component processor is composed of a curve type selector and a processing unit, the input is the associated 3-code element, the multiplied frequency clock pulse and the bidirectional counter, and the output is the in-phase component signal The curve type selector generates the curve type number of the in-phase component of the current symbol period. The processing unit generates the table lookup address, the in-phase component symbol and the end table lookup data record. During initialization, the initial value of the in-phase component symbol is positive, and the initial value of the end table lookup data record is the cos(0) quantized value.

[0039] Preferably, the orthogonal component processor is composed of a curve type selector and a processing unit, the input is the associated 3 code element, the multiplied clock pulse and the bidirectional counter, and the output is the orthogonal component signal The curve type selector generates the orthogonal component curve type number of this symbol period. The processing unit generates the table lookup address, orthogonal component symbol and the end table lookup data record. During initialization, the initial value of the orthogonal component symbol is equal to the first symbol value, and the initial value of the end table lookup data record is the sin(0) quantized value.

[0040] Preferably, the in-phase component processor and the quadrature component processor each include a curve type selector, and each operates independently. During the high level period of the frequency multiplier clock pulse, the curve type selector selects the curve type according to the following logic:

[0041] (1) When the three associated code elements are the same, the curve type is selected as S0(n);

[0042] (2) When the codeword is the same as the previous and next codewords, but the codeword is different from the previous and next codewords, the curve type is S1(n);

[0043] (3) When the previous and next symbols of the current symbol are different, and the table data record at the end of the previous symbol period recorded by the processing unit is not equal to the cos(0) or sin(δ) quantized value, the curve type is selected as S2(n);

[0044] (4) When the preceding and following codewords of the current codeword are different, and the table data record at the end of the preceding codeword period recorded by the processing unit is equal to the cos(0) or sin(δ) quantized value, the curve type is selected as S3(n).

[0045] The bit position f indicates whether the table lookup data record at the end of the previous symbol period recorded by the processing unit is equal to the cos(0) or sin(δ) quantized value, f=1, indicating true, and f=0, indicating false.

[0046] The curve type selection can generate the curve type number through the following logical operation:

[0047]

[0048] Preferably, the in-phase component processor and the quadrature component processor each include a processing unit, and each operates independently. The processing unit performs the following processing:

[0049] (1) During the high level period of the frequency-multiplied clock pulse, the table data record at the end of the previous symbol period is queried. If it is equal to the quantized value of sin(0) (i.e., 0), the symbol of the current symbol period is the inverse of the symbol of the previous symbol period; otherwise, the symbol of the current symbol period is equal to the symbol of the previous symbol period; according to whether the table data record at the end of the previous symbol period is equal to the quantized value of cos(0) or sin(δ), which is true, the bit f is assigned a value.

[0050] (2) During the high level period of the frequency multiplication clock pulse, the curve type number generated by the curve type selector is multiplied by (N+1) to generate the lookup table head address of the four-curve data table;

[0051] (3) During the low level period of the frequency multiplier clock pulse, the in-phase component processor processing unit adds the table lookup first address to the bidirectional counter output to generate the in-phase component table lookup address; the quadrature component processor processing unit adds N to the table lookup first address and subtracts the bidirectional counter output to generate the quadrature component table lookup address;

[0052] (4) Obtain the table lookup data in the four-curve data table according to the table lookup address, and record the table lookup data when the bidirectional counter is equal to 0 or N as the last table lookup data record for the next query;

[0053] (5) Add sign bit to table lookup data and output;

[0054] (6) Repeat (1) to (5).

[0055] The beneficial effects of the present invention are: simple implementation, resource saving, high reliability, and convenient implementation using a small-scale signal processor or processing unit. High sampling rate is supported. The higher the sampling rate, the more ideal the modulator characteristics are, and subsequent low-pass filters may not be used to eliminate spurious signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 GMSK Quadrature Modulator Principle

[0058] Figure 2 The initial phase of the symbol combination mapping is the zero phase path (BT b =0.3)

[0059] Figure 3 The first quadrant phase path (BT b =0.3)

[0060] Figure 4 The first quadrant in-phase component signal I(t)(BT b =0.3)

[0061] Figure 5 The first quadrature component signal Q(t)(BT b =0.3)

[0062] Figure 6 Four basic curves (BT b =0.3)

[0063] Figure 7 Principle block diagram of GMSK quadrature modulator based on LUT technology

[0064] Figure 8 Principle block diagram of the GMSK quadrature modulator of the present invention DETAILED DESCRIPTION

[0066] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0067] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0068] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0069] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0070] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0071] The present invention is used to realize a GMSK quadrature modulator. Before introducing a specific implementation scheme, the characteristics of the GMSK quadrature modulator need to be introduced first.

[0072] When the correlation length L = 3, three adjacent correlation symbol combinations can be mapped to directly obtain the orthogonal modulation baseband signal, which allows us to use LUT technology to simplify and optimize the design of GMSK orthogonal modulator. This mapping relationship is shown in Table 1.

[0073] Table 1 Mapping table of associated symbol combinations and orthogonal modulation baseband signals

[0074]

[0075] in, express A signal that is reversed in order on the time axis.

[0076] According to this mapping table, the orthogonal modulation baseband signals I(t) and W(t) in any quadrant can be obtained by and One of them can be obtained directly or indirectly, and the indirect form includes sign reversal, order reversal, or reversal in both sign and order. Using this mapping table, the GMSK orthogonal modulator can be implemented using the LUT technology.

[0077] Take the code sequence 0010111100 as an example to illustrate how to use Figure 7 The GMSK modulator shown generates a quadrature modulated baseband signal.

[0078] Assume that the initial phase is 0, and the first symbol is the same as the first symbol. Then, according to the symbol combination and its corresponding phase change, the start and end phases of the current symbol can be obtained by phase accumulation, and the quadrant of the current symbol phase path can be determined. Then, according to the above table, the type of the corresponding orthogonal modulation baseband signal can be found. Using the above method, it can be concluded that when BT b When =0.5 and N=10, in the orthogonal modulation baseband signal waveform of the codeword sequence 0010111100, the mapping relationship between the codeword sequence, the baseband signal and the four curves is shown in Table 2.

[0079] Table 2 Signal processing results of table lookup controller for code element sequence 0010111100

[0080]

[0081] In one embodiment of the present invention, a GMSK quadrature modulator is provided, comprising a quadrature modulation baseband generator and a digital up-conversion circuit;

[0082] The orthogonal modulation baseband generator is responsible for converting the modulated code element sequence into orthogonal in-phase component and quadrature component signals, which are then input into the digital up-conversion circuit to complete carrier modulation and generate GMSK modulated signals;

[0083] The binary symbol sequence and the system clock are input to the orthogonal modulation baseband generator; the system clock is divided to generate a symbol frequency multiplication clock pulse to drive the bidirectional counter to oscillate and count back and forth according to the odd and even order of the symbol sequence to be modulated;

[0084] The in-phase component processor and the orthogonal component processor process and generate the current curve selection type and the current curve symbol according to the associated codeword combination in the sampled binary codeword sequence and the curve continuity relationship reflected by the previous processing result.

[0085] The output of the bidirectional counter is used as the table lookup address of the current curve, and the orthogonal in-phase component and quadrature component signals are output point by point by looking up the pre-stored four-curve data table;

[0086] The orthogonal in-phase component and quadrature component signals are input to a digital up-conversion circuit, and the up-conversion circuit generates a GMSK modulated signal.

[0087] In one embodiment, the quadrature modulation baseband generator is composed of a bidirectional counter, a four-curve data table, an in-phase component processor and an orthogonal component processor;

[0088] The symbol period is Tb After the binary modulation symbol sequence and the system clock are input into the orthogonal modulation baseband generator, the system clock is divided to generate a frequency multiplication period of T b / N code element frequency-multiplied clock pulse; the orthogonal modulation baseband generator completes a signal processing in each frequency-multiplied clock cycle and outputs the orthogonal in-phase component signal point by point and quadrature component signals

[0089] In one embodiment, the bidirectional counter counts the frequency-multiplied clock pulses in a controllable direction, and changes the counting direction according to the odd-even order of the code element sequence to be modulated; the odd-numbered code elements of the code element sequence to be modulated are counted down from N-1 to 0; and the even-numbered code elements of the code element sequence to be modulated are counted up from 1 to N.

[0090] In one embodiment, the four-curve data table includes four curves, each curve includes N+1 point data, the four curves are respectively recorded as S0(n), S1(n), S2(n) and S3(n), and the four curves are stored in a data memory with a first address interval of N+1 using fixed-point numbers; the curve type numbers of the four curves are 0, 1, 2 and 3 respectively;

[0091] The four curves are selected from a set of quadrature modulated baseband signals whose phase paths are located in the first quadrant, sampled at a sampling rate N and digitally quantized; the data of the selected four curves meet the following requirements:

[0092] S0(0)=S2(0)=sin(0)

[0093] S1(0) = S3(0) = sin(δ)

[0094] S0(N)=S3(N)=cos(0)

[0095] S1(N)=S2(N)=cos(δ)

[0096] Among them, δ is the phase change value caused by inter-code interference, which is related to BT b Correlation is used to reflect the effect of the Gaussian filter on the modulation phase.

[0097] In one embodiment, the in-phase component processor is composed of a curve type selector and a processing unit, the input of which is the adjacent previous symbol, current symbol and next symbol, as well as the output of the frequency-multiplied clock pulse and the bidirectional counter, and the output is the in-phase component signal

[0098] The curve type selector generates the curve type number of the in-phase component of the current symbol period;

[0099] The processing unit generates a table lookup address, an in-phase component symbol and a table lookup data record at the end.

[0100] In one embodiment, the orthogonal component processor is composed of a curve type selector and a processing unit, the input is the adjacent previous code element, current code element and next code element, as well as the output of the frequency-multiplied clock pulse and the bidirectional counter, and the output is the orthogonal component signal

[0101] The curve type selector of the orthogonal component processor generates the orthogonal component curve type number of the current code element period;

[0102] The processing unit generates table lookup addresses, orthogonal component symbols and end table lookup data records.

[0103] In one embodiment, the curve type selector is provided in both the in-phase component processor and the orthogonal component processor, and each operates independently;

[0104] During the high level period of the frequency multiplier clock pulse, the curve type selector selects the curve type according to the following logic:

[0105] When the adjacent previous codeword, current codeword and next codeword are the same, the curve type is S0(n), and the curve type number is 0;

[0106] When the current codeword is the same as the next codeword, but the current codeword is different from the previous codeword and the next codeword, the curve type is S1(n), and the curve type number is 1;

[0107] When the current symbol is different from the next symbol, and the table data record at the end of the previous symbol period recorded by the processing unit is not equal to the cos(0) or sin(δ) quantized value, the curve type is selected as S2(n), and the curve type number is 2;

[0108] When the current symbol is different from the subsequent symbol and the table data record at the end of the previous symbol period recorded by the processing unit is equal to the cos(0) or sin(δ) quantized value, the curve type is selected as S3(n) and the curve type number is 3.

[0109] In one embodiment, the processing unit is provided in both the in-phase component processor and the orthogonal component processor, and each of them operates independently, and the processing unit completes the following processing:

[0110] During the high level of the frequency multiplication clock pulse, if the table data record at the end of the previous symbol period is equal to the sin(0) quantized value, the symbol of this symbol period is the inverse of the symbol of the previous symbol period, otherwise, the symbol of this symbol period is equal to the symbol of the previous symbol period;

[0111] During the high level period of the frequency multiplication clock pulse, the curve type number generated by the curve type selector is multiplied by (N+1) to generate the lookup table head address of the four-curve data table;

[0112] During the low level period of the frequency multiplier clock pulse, the in-phase component processor processing unit adds the table lookup first address to the bidirectional counter output to generate the in-phase component table lookup address; the quadrature component processor processing unit adds N to the table lookup first address and subtracts the bidirectional counter output to generate the quadrature component table lookup address;

[0113] Obtain the table lookup data in the four-curve data table according to the table lookup address, and record the table lookup data when the bidirectional counter is equal to 0 or N, as the end table lookup data record for the next query;

[0114] Add sign bit to the table lookup data output.

[0115] The following describes a specific implementation scheme of the present invention using the code element sequence 0010111100 as an example.

[0116] The GMSK quadrature modulator of the embodiment of the present invention is composed of a quadrature modulation baseband generator and an up-conversion (DUC) circuit. Figure 8 As shown in the figure. The modulator adopts the hardware architecture of signal processor plus high-speed DAC. The RF power amplifier, power supply and other parts are the same as the conventional design and are omitted here. The hardware to implement the signal processor can be FPGA, DSP or single-chip microcomputer, etc. Figure 8 The quadrature modulation baseband generator in the up-conversion circuit and the DDS, multiplier and adder and other functional modules can be implemented in the signal processor. A DAC chip with an internal NCO can also be used to achieve up-conversion, and the signal processor only needs to generate the quadrature modulation baseband. If the carrier frequency is high, the signal processor can be used to first generate the quadrature modulation baseband signal, then mix it with the intermediate frequency carrier, and then use the DAC chip with an internal NCO to achieve up-conversion. The core of these architectures is the quadrature modulation baseband generator.

[0117] The orthogonal modulation baseband generator consists of a bidirectional counter, a four-curve data table, an in-phase component processor and an orthogonal component processor. The symbol period is T b The binary code sequence to be modulated is a k The system clock clk is input into the orthogonal modulation baseband generator, and the system clock is divided to generate a symbol multiplied clock (multiplied period T b / N) pulse; at the rising edge of the frequency-multiplied clock pulse, the orthogonal modulation baseband generator collects and stores the associated 3 code elements of this code element period.

[0118] The associated 3-code is denoted as a -1 , a0, a +1 , which represent the binary symbols of the previous symbol period, the current symbol period and the next symbol period currently saved by the orthogonal modulation baseband generator. a -1 , a0, a +1 Can participate in Boolean operations as bits.

[0119] The bidirectional counter counts the frequency-multiplied clock pulses in a controllable direction, and changes the counting direction according to the odd-even order of the code element sequence to be modulated. The odd-numbered code elements are counted down from N-1 to 0, and the even-numbered code elements are counted up from 1 to N.

[0120] Get BT b =0.5, N=10, the original data of the four curves are sampled from and The corresponding binary curve type numbers are 00B, 01B, 10B, and 11B. The original data of the four curves are digitally quantized using hexadecimal fixed-point decimals and stored in the data memory, as shown in Table 3.

[0121] Table 3 Four curve data table when N=10

[0122]

[0123] During initialization, the first symbol is the same as the first symbol in the previous cycle; the initial value of the bidirectional counter is N (i.e. 10), and the first symbol is an odd number; the initial value of the in-phase component channel symbol is positive (i.e. 0), and the initial value of the lookup table data record at the end is the cos(0) quantized value (i.e. 0x7FFF); the initial value of the quadrature component channel symbol is equal to the first symbol value (i.e. 0), and the initial value of the lookup table data record at the end is the sin(0) quantized value (i.e. 0x0000). When the modulator stops, the default next cycle symbol is 0.

[0124] The in-phase component processor consists of a curve type selector and a processing unit. The curve type number and curve symbol are generated by the table lookup data record processing of the associated 3 code elements and the end of the previous code element period, and then the table lookup address is calculated by multiplying the curve type number by (N+1) plus the bidirectional counter value. The signal processing process of the in-phase component processor can be reflected in Table 4.

[0125] Table 4 Signal processing process of the in-phase component processor of the code element sequence 0010111100

[0126]

[0127]

[0128] Similarly, the quadrature component processor is composed of a curve type selector and a processing unit. The curve type number and curve symbol are generated by the table lookup data record processing of the associated 3 code elements and the end of the previous code element period, and then the table lookup address is calculated by multiplying the curve type number by (N+1) plus N and subtracting the bidirectional counter value. The signal processing process of the quadrature component processor can be reflected in Table 5.

[0129] Table 5 Signal processing process of the orthogonal component processor of the code element sequence 0010111100

[0130]

[0131] By looking up the table addresses obtained by the in-phase component processor and the orthogonal component processor respectively and adding signs, the orthogonal modulated baseband signals I(t) and Q(t) can be obtained, which are consistent with the results in the above Table 2, and it can be verified that this embodiment is effective.

[0132] I(t) and Q(t) are input into DUC to generate GMSK modulated signal. DUC can be (but not limited to) high-speed DAC chip with internal NCO such as DAC5686 or DAC3482 from TI.

[0133] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A GMSK quadrature modulator, characterized in that: Including orthogonal modulation baseband generator and digital up-conversion circuit; The orthogonal modulation baseband generator is responsible for converting the modulated code element sequence into orthogonal in-phase component and quadrature component signals, which are then input into the digital up-conversion circuit to complete carrier modulation and generate GMSK modulated signals; The binary symbol sequence and the system clock are input to the quadrature modulation baseband generator; The system clock frequency is divided to generate a symbol frequency multiplication clock pulse to drive the bidirectional counter to oscillate and count back and forth according to the odd and even sequence of the symbol sequence to be modulated; The in-phase component processor and the orthogonal component processor process and generate the current curve selection type and the current curve symbol according to the associated codeword combination in the sampled binary codeword sequence and the curve continuity relationship reflected by the previous processing result. The output of the bidirectional counter is used as the table lookup address of the current curve, and the orthogonal in-phase component and quadrature component signals are output point by point by looking up the pre-stored four-curve data table; The orthogonal in-phase component and quadrature component signals are input to a digital up-conversion circuit, and the up-conversion circuit generates a GMSK modulated signal.

2. The GMSK quadrature modulator according to claim 1, characterized in that: The quadrature modulation baseband generator is composed of a bidirectional counter, a four-curve data table, an in-phase component processor and an orthogonal component processor; The symbol period is T b After the binary modulation symbol sequence and the system clock are input into the orthogonal modulation baseband generator, the system clock is divided to generate a frequency multiplication period of T b / N symbol frequency-multiplied clock pulse; The orthogonal modulation baseband generator completes signal processing once in each frequency-multiplied clock cycle and outputs orthogonal in-phase component signals point by point. and quadrature component signals 3. The GMSK quadrature modulator according to claim 2, characterized in that: The bidirectional counter counts the frequency-multiplied clock pulses in a controllable direction and changes the counting direction according to the odd-even order of the code element sequence to be modulated; the odd-numbered code elements of the code element sequence to be modulated are counted down from N-1 to 0; the even-numbered code elements of the code element sequence to be modulated are counted up from 1 to N.

4. The GMSK quadrature modulator according to claim 2, characterized in that: The four-curve data table includes four curves, each curve includes N+1 point data, the four curves are respectively recorded as S0(n), S1(n), S2(n) and S3(n), and the four curves are stored in a data memory with a first address interval of N+1 using fixed-point numbers; the curve type numbers of the four curves are 0, 1, 2 and 3 respectively; The four curves are selected from a set of quadrature modulated baseband signals whose phase paths are located in the first quadrant, sampled at a sampling rate N and digitally quantized; the data of the selected four curves meet the following requirements: S0(0)=S2(0)=sin(0) S1(0) = S3(0) = sin(δ) S0(N)=S3(N)=cos(0) S1(N)=S2(N)=cos(δ) Among them, δ is the phase change value caused by inter-code interference, which is related to BT b Correlation is used to reflect the effect of the Gaussian filter on the modulation phase.

5. The GMSK quadrature modulator according to claim 2, characterized in that: The in-phase component processor is composed of a curve type selector and a processing unit. The input is the adjacent previous code element, current code element and next code element as well as the output of the frequency-multiplied clock pulse and the bidirectional counter. The output is the in-phase component signal The curve type selector generates the curve type number of the in-phase component of the current symbol period; The processing unit generates a table lookup address, an in-phase component symbol and a table lookup data record at the end.

6. The GMSK quadrature modulator according to claim 2, characterized in that: The orthogonal component processor is composed of a curve type selector and a processing unit. The input is the adjacent previous code element, current code element and next code element, as well as the output of the frequency-multiplied clock pulse and the bidirectional counter. The output is the orthogonal component signal The curve type selector of the orthogonal component processor generates the orthogonal component curve type number of the current code element period; The processing unit generates table lookup addresses, orthogonal component symbols and end table lookup data records.

7. The GMSK quadrature modulator according to claim 5 or 6, characterized in that: The curve type selector is provided in each of the in-phase component processor and the orthogonal component processor, and each operates independently; During the high level period of the frequency multiplier clock pulse, the curve type selector selects the curve type according to the following logic: When the adjacent previous codeword, current codeword and next codeword are the same, the curve type is S0(n), and the curve type number is 0; When the current codeword is the same as the next codeword, but the current codeword is different from the previous codeword and the next codeword, the curve type is S1(n), and the curve type number is 1; When the current symbol is different from the next symbol, and the table data record at the end of the previous symbol period recorded by the processing unit is not equal to the cos(0) or sin(δ) quantized value, the curve type is selected as S2(n), and the curve type number is 2; When the current symbol is different from the subsequent symbol and the table data record at the end of the previous symbol period recorded by the processing unit is equal to the cos(0) or sin(δ) quantized value, the curve type is selected as S3(n) and the curve type number is 3.

8. The GMSK quadrature modulator according to claim 5 or 6, characterized in that: The processing unit is provided in each of the in-phase component processor and the orthogonal component processor, and each operates independently. The processing unit completes the following processing: During the high level of the frequency multiplication clock pulse, if the table data record at the end of the previous symbol period is equal to the sin(0) quantized value, the symbol of this symbol period is the inverse of the symbol of the previous symbol period, otherwise, the symbol of this symbol period is equal to the symbol of the previous symbol period; During the high level period of the frequency multiplication clock pulse, the curve type number generated by the curve type selector is multiplied by (N+1) to generate the lookup table head address of the four-curve data table; During the low level period of the frequency multiplier clock pulse, the in-phase component processor processing unit adds the table lookup first address to the bidirectional counter output to generate the in-phase component table lookup address; the quadrature component processor processing unit adds N to the table lookup first address and subtracts the bidirectional counter output to generate the quadrature component table lookup address; Obtain the table lookup data in the four-curve data table according to the table lookup address, and record the table lookup data when the bidirectional counter is equal to 0 or N, as the end table lookup data record for the next query; Add sign bit to the table lookup data output.

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