Memory device having hexagonal memory cells with integrated digital lines

Abstract

Embodiments of the invention relate to a memory device having hexagonal memory cells with integrated digital lines. Various applications may include a memory device having an array of memory cells arranged as hexagonal cells, where each of the memory cells has a gate-all-around (GAA) transistor coupled to a capacitor. An access line may be coupled to gates of a first plurality of GAA transistors of the memory cell. A digital line may be coupled to a second plurality of GAA transistors of the memory cell, wherein the digital line is wound on sidewalls of an active region of each GAA transistor in the second group. Additional apparatus and methods are disclosed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to integrated circuits, and more particularly, to memory devices and the formation thereof. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits (ICs) in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM)), or three-dimensional (3D) XPoint TM Memory, etc. The properties of memory devices and other electronic devices may be improved by enhancing the design and fabrication of components of electronic devices, such as, but not limited to, memory devices in ICs of electronic devices. Summary of the invention

[0003] According to one embodiment of the present application, a memory device is provided. The memory device includes: a memory cell array, wherein each of the memory cells has a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; an access line coupled to the gates of a first plurality of GAA transistors of the memory cell; and a digit line coupled to a second plurality of GAA transistors of the memory cell, the digit line winding around the sidewalls of the active region of each GAA transistor in the second group.

[0004] According to another embodiment of the present application, a method of forming a memory device is provided. The method includes: forming a memory cell array, which includes forming the memory cells of the array as hexagonal cells and forming each of the memory cells as a gate-all-around (GAA) transistor having a capacitor coupled to it; forming a set of access lines, wherein the access lines in the set of access lines are coupled to gates of a first set of multiple GAA transistors of the memory cells; and forming a set of digit lines, wherein the digit lines in the set of digit lines are wrapped around the sidewalls of the active area of ​​each GAA transistor in a second set of multiple GAA transistors of the memory cells.

[0005] According to another embodiment of the present application, a method for forming a memory device is provided, the method comprising: preparing an array wafer having an array of gate-all-around (GAA) transistors connected to access lines and digit lines, wherein the digit lines are wound around the sidewalls of the active regions of the GAA transistors; preparing a control circuit system wafer; and coupling the array wafer and the control circuit system wafer together. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed in this document by way of example and not limitation.

[0007] Figure 1 A top view of a representation of an open digit line architecture illustrating the case of a shared access line for an array of one or more memory cells, wherein each memory cell includes a gate-all-around transistor coupled to a capacitor, according to various embodiments.

[0008] Figure 2 A structure with an arrangement of memory cells according to various embodiments is illustrated, wherein each memory cell has an access transistor and a capacitor, wherein the access transistor is a gate-all-around transistor with an active area integrated with a digit line.

[0009] Figures 3 to 37 Description of various embodiments and methods for forming a Figure 2 The structure of the memory cells and the arrangement of the memory cells are features associated with an example process flow of a memory device.

[0010] Fig.38 Description of various embodiments Fig.34 An example architecture in which a structure or similar structure may be located.

[0011] Fig.39 is a flow chart of features of an example method of forming a memory device in accordance with various embodiments.

[0012] Fig.40 is a flow chart of features of an example method of forming a memory device in accordance with various embodiments.

[0013] Fig.41 is a schematic diagram of an electrical arrangement of components of an example dynamic random access memory device that may include an architecture having hexagonal memory cells with all-around gate transistors in accordance with various embodiments. DETAILED DESCRIPTION

[0014] The following detailed description refers to the accompanying drawings, which show various embodiments that can be implemented in an illustrative manner. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical and electrical changes may be made to these embodiments. The term "horizontal" as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal as defined above, and may be in a direction from or to the horizontal. Various features may have a vertical component in the direction of their structure. Various embodiments do not have to be mutually exclusive, because some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the detailed description below should not be understood as limiting.

[0015] In various embodiments, a memory device may be structured with an array of memory cells arranged as hexagonal cells, each of which has a gate-all-around (GAA) transistor coupled to a capacitor. A hexagonal memory cell is a memory cell that is surrounded by six other memory cells such that the other memory cells are at the vertices of a hexagonal structure formed by connecting the centers of adjacent memory cells of the other memory cells. A GAA transistor is a transistor structured with a gate of a transistor coupled to a channel structure of the transistor on all sides of the channel structure. A GAA transistor may be structured as a thin film transistor (TFT). A GAA transistor may be structured with a pillar arrangement containing an active region (source and drain) and a channel structure, with a gate structured around the channel structure. The pillar structure of a GAA transistor may be structured as a semiconductor nanowire. A nanowire is a nanostructure having a nanometer-scale diameter.

[0016] GAA nanowire transistors as access devices for capacitors in DRAM memory cells can provide enhanced I ON capability and transistor threshold voltage (V T ) can be adjusted flexibly. ON is the on-state current of the transistor, where the current I OFF is the off-state current of the transistor. The ratio I ON / I OFF It is an excellent indicator of high performance and low leakage power of the transistor. High performance and larger I ON associated with low leakage power and smaller I OFF Associated.

[0017] A memory device having one or more arrays of hexagonal memory cells of GAA transistors can be implemented in several different architectures together with control logic and sensing circuitry. The control logic and sensing circuitry can be located in a peripheral area adjacent to the array of hexagonal memory cells on a chip, which is an IC chip. Another compatible architecture includes control logic and sensing circuitry located under one or more memory arrays in a circuit under array (CuA) architecture. The control logic and sensing circuitry can be arranged to sense the programming data state of the memory cells of one or more memory arrays of the memory device, and can enhance the reduction of die size or increase the space utilization in a die or die combination. CuA generally refers to the circuitry in a memory die under the memory array of a memory die. CoA can also be referred to as CMOS under array by means of control logic and sensing circuitry manufactured under the memory array using semiconductor processing that can include CMOS (complementary metal oxide semiconductor) processing technology.

[0018] Another compatible architecture may include control logic and sensing circuitry located above a memory array in a circuit on array (CoA) architecture. The control logic and sensing circuitry may be arranged to sense the programming data state of a memory cell of one or more memory arrays of a memory device, and may enhance the reduction of die size or increase space utilization in a die or die combination. CoA generally refers to a circuitry in a memory die located above one or more memory arrays of a memory die. CoA may also be referred to as CMOS on array by using a control logic and sensing circuitry manufactured on one or more memory arrays using semiconductor processing that may include CMOS. CuA architecture and CoA architecture may be implemented with a wafer-to-wafer architecture, wherein control logic and sensing circuitry are formed on one wafer, and one or more memory arrays are formed on another wafer, wherein the two wafers are combined. Wafer-to-wafer interconnect architecture may include a wafer-on-wafer architecture. Wafer-to-wafer bonding of back-to-back wafers with a CoA architecture may move capacitor modules for data storage in DRAM to the bottom of a stack of wafers. This arrangement may reduce interconnect congestion between stacked wafers.

[0019] The memory device may include a set of access lines (WLs), wherein each WL in the set of WLs may be coupled to the gates of a first set of multiple GAA transistors of a memory cell of a memory array. With the aid of the double-sided WLs of the GAA transistors of the memory cell, control of the WL impedance-capacitance (RC) of the directly adjacent WLs may be obtained. Each WL may be formed together with a corresponding gate of a GAA transistor formed in a replacement gate process, which may provide enhanced gate control. The memory device may include a set of digital lines (BLs), wherein each BL in the set of BLs may be coupled to a second set of multiple GAA transistors of the memory cell. Each BL may be wound around the sidewalls of the active area of ​​each GAA transistor in the second group. The BL may be a damascene digital. In a damascene process, a dielectric is first formed on the structure and patterned, followed by metal formation that fills the patterned dielectric. Metal formation may be achieved by a process suitable for the metal being formed, such as appropriate metal deposition. The damascene digital may provide enhanced digital impedance. The BL may be placed in the memory device at an angle of 90° relative to the WL, wherein the BL is vertically separated from the WL.

[0020] The memory device may have 4F 2 Memory array configuration. Using nF 2 The memory cell size is measured by the formula, where 'n' is a constant derived from the cell design, and 'F' is the feature size of the process technology. For the same feature size, as the cell size becomes smaller, the memory capacity increases. 2 In the memory cell, the WL pitch and the BL pitch are equal to 2F.

[0021] Figure 1 A representation 100 of an open BL architecture is shown for the case of a shared WL for one or more memory cell arrays, where each memory cell includes a GAA transistor coupled to a capacitor. For ease of presentation, Figure 1 One of similar multiple features in the and subsequent figures may be labeled, rather than all similar features. The BL is located at a different physical level of the memory device than the WL. In an open BL architecture, the BL is divided into multiple segments, and differential sense amplifiers (SAs) are placed between the BL segments, where the BL is routed in pairs from adjacent pads to the SAs. A pad (which may also be referred to as a tile) is a structure of a sub-array (the sub-array may be one of multiple arrays of memory cells of a larger storage array of a memory device), such as Figure 2 Instance structure 200 and Fig.34 Example structure 3400. The open BL architecture may also be referred to as an open SA architecture.

[0022] The open BL architecture of representation 100 may include SAs 139-0, 139-1, and 139-2 in different portions of the memory device structure. BLs D1, D2, D3, and D4 are in region 197, which includes multiple WLs, where each WL is shared by multiple memory cells. For example, region 197 may include WLs 130-1 and 130-2, which are separated from each other by a dielectric region, where WL 130-1 may be coupled to multiple memory cells 121-1, and WL 130-2 may be coupled to multiple memory cells 121-2. WL 130-1 may be integrated with the gate of the GAA transistor of each memory cell 121-1, and WL 130-2 may be integrated with the gate of the GAA transistor of each memory cell 121-2. BLs D1*, D2*, D3*, and D4* are in region 198, which includes multiple WLs, where each WL is shared by multiple memory cells. For example, region 198 may include two WLs 130-3 and 130-4 separated from each other by a dielectric region, wherein WL 130-3 may be coupled to a plurality of memory cells 121-3, and WL 130-4 may be coupled to a plurality of memory cells 121-4. WL 130-3 may be integrated with the gate of a GAA transistor of each memory cell 121-3, and WL 130-4 may be integrated with the gate of a GAA transistor of each memory cell 121-4.

[0023] BLs D1, D2, D3, and D4 may be located between SA 139-0 (which may be referred to as an even SA) and SA 139-1 (which may be referred to as an odd SA). BLs D1*, D2*, D3*, and D4* may be located between odd SA 139-1 and SA 139-2 (which may be referred to as an even SA). Regions 197 and 198 may be formed as individual pads. BLs D1 and D1*, BLs D2 and D2*, BLs D3 and D3*, and BLs D4 and D4* may be arranged in pairs with respect to SA 139-1, with BLs D1, D2, D3, and D4 in region 197 adjacent to SA 139-1, and BLs D1*, D2*, D3*, and D4* in region 198 adjacent to SA 139-1. Regions 197 and 198 may be formed in individual subtractive processes. A subtractive process includes removing material from a block of solid starting material. Figure 2 and 34 The GAA transistors and capacitors of the associated structure may be implemented as multiple pads in an open BL architecture.

[0024] Figure 2A structure 200 is illustrated having an arrangement of memory cells, wherein each memory cell has an access transistor and a capacitor, wherein the access transistor is a GAA transistor having an active region integrated with a BL. The memory cells are arranged on a wafer, which may be referred to as an array wafer 201, due to the structuring of the memory cells at a level above the wafer 201. A bonding dielectric 222 is positioned on the array wafer 201, wherein the bonding dielectric is structured to bond to the array wafer 201 during formation of the memory cells. Within the bonding dielectric 222 is a hard mask 213, which is a residue of the construction structure 200. A hard mask is a material that can be used as an etch mask in an etching process, wherein the material is different from a polymer or other relatively soft material, such as a relatively soft resist material. A hard mask is typically a high density material used in an etching process to protect certain areas of the structure being processed from etching chemicals used in the etching process. A dielectric 218 is located on the bonding dielectric 222 and on the hard mask 213. BL 235 is positioned in dielectric 218, on bonding dielectric 222, and between the lines of hard mask 213 at a level above hard mask 213, which provides a pattern for BL 235 during fabrication.

[0025] The semiconductor pillars 207 extend approximately from a level at the top of the hard mask 213. The semiconductor pillars 207 may be implemented as nanowires. Each semiconductor pillar 207 includes a channel between two source / drain regions. For each semiconductor pillar 207, a gate dielectric 223 is positioned around the channel provided by the semiconductor pillar 207. A gate 227 is positioned around each gate dielectric 223, thereby coupling the gate 227 to the semiconductor pillar 207 and coupling the semiconductor pillar to a WL 230 that contacts the gate 227. The gates 227 and WL 230 may be structured in a format that integrates the WL 230 with multiple gates 227, such as in FIG. Figure 2 . The two source / drain regions of each semiconductor pillar 207 are active areas. Each active area may include a contact junction. For each semiconductor pillar 207, the channel is coupled to the capacitor through an active area 208 having a cell contact junction, and is coupled to a BL 235 through an active area 206 having a digital contact junction (a digital contact may be referred to as a bit contact or bitcon). The center of the BL 235 may be structured to align with the center of the active area 206. Each BL 235 may wrap around the sidewalls of the active area 206, which provides a BL integrated with a memory cell. The active area 206 and the BL 235 may be structured in a format that allows the BL 235 to be integrated with the active area 206, as shown in FIG. Figure 2 The bit contact junction region can be configured as a shield to reduce the capacitance between the BLs.

[0026] A dielectric 217 is above the gate 227 and WL 230, with a dielectric 269 on the dielectric 217. The dielectrics 217 and 269 originate from the processing structure 200 and provide electrical isolation to the conductive components in the structure 200. Above the dielectric 269 is a set of capacitors 229. Each capacitor 229 includes a capacitor dielectric 259 between two electrodes 257 and 258. The electrode 258 may be referred to as a bottom electrode coupled to the active region 208 of the semiconductor pillar 207, while the electrode 257 is a top electrode that may be coupled to a reference node. The capacitor dielectric may be, but is not limited to, a high-k dielectric. A high-k dielectric is a dielectric having a dielectric constant greater than that of silicon dioxide. The structure 200 may include a dielectric region 298 or a connection wafer on the set of capacitors 229.

[0027] Figures 3 to 37 Description and formation Figure 2 The memory cell arrangement of structure 200 is associated with features of an example process flow of an embodiment of a memory device. 2 The memory cells may be arranged in a certain architecture. For the procedures discussed herein, the choice of process materials may depend on the materials selected to form the various components of the memory device and the contacts to the components. The process materials may be selected to allow removal of one or more materials while retaining one or more other materials. In addition, deposition techniques may be used that are typical for the materials being formed, the dimensions of the materials being formed, and the architecture in which the materials are being formed.

[0028] Figure 3 The structure 300 is shown after a block of material has been formed on a substrate 311. The block may be a semiconductor material. For example, the block may be formed with a silicon germanium (SiGe) layer 307 on a substrate 311, where the substrate 311 may be a silicon substrate. The SiGe may be 15% SiGe that may be formed by an appropriate deposition process. Materials other than SiGe may be used. The thickness of the SiGe from the substrate 311 may be, but is not limited to, a range between about ten to twenty nanometers. The formation of the block of material may include forming an epitaxial Si layer 304 on the SiGe. Materials other than epitaxial Si may be used. The thickness of the epitaxial Si on the SiGe may be, but is not limited to, a range between about 150 nm and 300 nm. After the epitaxial Si is formed, a hard mask 313 may then be formed on the epitaxial Si.

[0029] Figure 4 Display in processing Figure 34. The structure 400 is a structure 400 after the structure 300 of FIG. 4. The channel of the GAA transistor has been patterned and formed into a pillar 407 from layer 304 while removing a portion of layer 304, leaving layer 307 or a portion of layer 307. Alternatively, a portion of layer 304 of structure 300 may remain in the base of pillar 407 along with layer 307 from the process of forming pillar 407. In the case where layer 304 of structure 300 is epitaxial Si, pillar 407 is a pillar of epitaxial Si. Photolithography may be used in the patterning and formation of pillar 407 using deep ultraviolet radiation (DUV) or extreme ultraviolet radiation (EUV). Pillar 407 may be formed to have, but is not limited to, a channel diameter in the range of about 6 nm to 20 nm. A channel having a diameter in the range of about 20 nm to 50 nm may be formed for a GAA access device.

[0030] Figure 5 exhibit Figure 4 500 is a top view of the structure 400. The representation 500 illustrates that the pillars 407 are arranged in a unit where the nearest neighbors form a hexagon 533. The unit repeating unit of the pillars 407 is a 4F 2 Parallelogram of architecture. 4F 2 The hexagonal unit of the architecture can be formed into 2 The square units of the architecture are smaller units.

[0031] Figure 6 Display in processing Figure 4 Structure 600 is a structure subsequent to structure 400. Dielectric 618 has been formed on layer 307, filling the spaces between pillars 407. Dielectric 618 and pillars 407 have been subjected to a chemical mechanical polishing (CMP) process, leaving the top surfaces of pillars 407 exposed in dielectric 618. Dielectric 618 may be formed by a deposition process suitable for a material for dielectric 618. Dielectric 618 may be an oxide, such as, but not limited to, silicon oxide.

[0032] Figure 7 Display in processing Figure 6 600. A hard mask 713 has been formed on the top surface of the structure 600, and an underlayer 728 for forming the BL has been formed and patterned on the hard mask 713. The underlayer is a carbon-based hard mask placed under the photoresist. The pattern formed provides a pattern for forming a damascene structure of the BL. The hard mask 713 and the underlayer 728 can be formed by a deposition process of materials suitable for this part of the process flow.

[0033] Figure 8 Display in processing Figure 7800 after structure 700. Hard mask 713 has been patterned and portions of dielectric 618 have been removed using lower layer 728, and lower layer 728 is removed. Removing portions of dielectric 618 exposes the sidewalls of pillar 407. The exposed sidewalls of pillar 407 are processed as active areas of a GAA transistor to be formed, wherein the exposed sidewalls are implanted to form junctions of a bit contact of a capacitor to be formed in the process flow, for forming a GAA transistor having a Figure 2 The memory device of the arrangement of memory cells of the structure 200. After the implant process, the structure may be subjected to an implant cleaning process.

[0034] Fig. 9 exhibit Figure 8 900 is a representation of a top view of structure 800. The top view shows the pattern of hard mask 713 with spaces between the material lines of hard mask 713. The spaces are also the spaces between pillars 407 under the lines of hard mask 713, where each material line of hard mask 713 partially covers a plurality of pillars 407.

[0035] Fig.10 Shown in Figure 8 1000 after possible further processing of structure 800. One of the cross-sectional views of structure 1000 illustrates pillars 407 extending down through dielectric 618 to layer 307. The lines of material may be further shaped, such as further narrowed, to form dielectric 1013, or the material and shape of the lines of hard mask 713 may be maintained.

[0036] Fig.11 exhibit Fig.10 100 is a representation 1100 of a top view of structure 1000. The top view shows dielectric 1013 with spaces between lines of dielectric 1013. The spaces are also spaces between pillars 407 under the lines of dielectric 1013, where each line of material of dielectric 1013 partially covers a plurality of pillars 407.

[0037] Fig.12 Display in processing Fig.10 The structure 1000 is followed by the structure 1200. Fig.12 1000, metal 1235 has been formed on dielectric 1013 and in the spaces between material lines of dielectric 1013 on the exposed surface of structure 1000. In the manufacture of the current process flow, metal 1235 for BL is formed. Other conductive materials can be used for metal 1235, which has properties similar to conductive metals. Metal 1235 can be formed at relevant locations by a deposition process suitable for metals formed on the exposed surface of structure 1000. Metal 1235 can be formed at intervals ranging from about 7nm to 12nm.

[0038] Fig.13 exhibit Fig.12 1300 is a representation of a top view of structure 1200. In this view, metal 1235 formed on the top surface of dielectric 1013 is not shown to illustrate the metal 1235 formed in the spaces between the lines of dielectric 1013 and around pillars 407. The two active areas of pillars 407 are on the left and right sides of each of the lines of dielectric 1013.

[0039] Fig.14 Display in processing Fig.12 Structure 1400 is a structure after structure 1200. Metal 1235 has been etched through to form isolation trenches. Fig.15 exhibit Fig.14 Representation 1500 of a top view of structure 1400. The lines of metal 1235 are on both sides under the lines of dielectric 1013. Fig.15 Isolation provided by post metal punch is shown with metal 1235 on both sides of the isolation trench. Minimum metal to metal spacing may be, for example but not limited to, about 5 nm. As shown, metal 1235 wraps around pillar 407.

[0040] Fig.16 Display in processing Fig.14 The structure 1600 after the structure 1400 of FIG. A bonding dielectric 1622 is formed on the exposed surface of the structure 1400. The bonding dielectric 1622 covers the dielectric 1013 and the metal 1235. The bonding dielectric 1622 has been polished, subjected to a CMP process, and cleaned. The formation of the bonding dielectric 1622 can be performed using a deposition process suitable for the material selected for the bonding dielectric 1622. The material for the bonding dielectric 1622 can be, but is not limited to, tetraethoxysilane (TEOS), silicon nitride carbon (SiCN), a material for a high aspect ratio process (HARP) or a combination of similar materials.

[0041] Fig.17 Display in processing Fig.16 Structure 1700 after structure 1600. Bonding dielectric 1622 has been bonded to carrier wafer 1701, and the bonded structure is flipped over so that substrate 311 is on top of structure 1700. Carrier wafer 1701 can be an inexpensive wafer or a glass carrier with an oxide deposition surface. Bonding can be performed by fusion bonding.

[0042] Fig.18 Display in processing Fig.17 Structure 1800 after structure 1700. Structure 1700 has been subjected to a CMP process which exposes the tops of pillars 407 for the channels of the GAA transistors formed in the process flow. These tops of pillars 407 will provide the cell contacts to the junctions of the capacitors. Substrate 311 and layer 307 have been removed.

[0043] Fig.19 Display in processing Fig.18 1800. Portions of dielectric 618 have been selectively removed to selected levels of dielectric 618, exposing pillar 407. Since dielectric 618 is an oxide, and pillar 407 is silicon, the oxide of dielectric 618 is selectively recessed to the Si surface. In order to recess dielectric 618 to a specified level, a selective wet etch may be used. The selective wet etch may be a time controlled etch.

[0044] Fig. 20 Display in processing Fig.19 407. A structure 2000 is formed after structure 1900. A dielectric material 2023 has been formed on the exposed surface of structure 1900. Dielectric material 2023 covers the exposed portion of pillar 407 and will provide a gate dielectric for a GAA transistor formed around pillar 407. Dielectric material 2023 may be, but is not limited to, a gate oxide material. Dielectric material 2023 may be formed by a deposition process suitable for the selected material of dielectric material 2023. Alternatively, dielectric material 2023 may be formed by in-situ steam generation (ISSG), wherein the ISSG process includes generating steam proximate to the wafer surface, thereby providing wet oxidation.

[0045] Fig.21 Display in processing Fig. 20 The structure 2100 after the structure 2000 is exposed. A liner 2113 has been formed on the exposed structure 2000. The formation of the liner 2113 may be performed using a deposition process suitable for the material of the liner 2113. The liner 2113 may be, but is not limited to, a nitride liner. In the process flow, the liner 2113 is formed as a sacrificial liner.

[0046] Fig. 22 Display in processing Fig.21 2100. A dielectric 2218 has been formed over the exposed surface of the structure 2100, filling the space between the pads 2113, and subjected to a CMP process. The dielectric 2218 may be, but is not limited to, an oxide. The structure resulting from the CMP process has been selectively etched back, exposing the pillars 407. Since the dielectric 2218 is an oxide and the pillars 407 are silicon, the selective etch back may be a dry etch back that is selective to silicon, exposing portions of the pillars 407 designed for junctions to be fabricated to the cell contacts of the capacitor.

[0047] Fig.23 exhibit Fig. 22 Representation 2300 of a top view of structure 2200 . Fig.23An array of cells is shown being formed. Each cell shown comprises a central pillar 407 providing a channel surrounded by a dielectric material 2023 provided as a gate material, wherein the dielectric material 2023 is surrounded by a liner 2113.

[0048] Fig.24 Display in processing Fig.23 Structure 2400 after structure 2200. A photolithography process has been performed for preparing WL. A carbon-based hard mask 2428 has been applied to the surface of structure 2200 and has been selectively removed to the top surface of dielectric 2218. Dry etching can be used to form Fig.24 The pattern of the carbon-based hard mask 2428 is shown in FIG.

[0049] Fig.25 exhibit Fig.24 Representation 2500 of a top view of structure 2400 . Fig.25 The pattern of a carbon-based hard mask 2428 is shown relative to a cell having a central pillar 407 surrounded by a dielectric material 2023, which is surrounded by a liner 2113.

[0050] Fig.26 Display in processing Fig.24 The structure 2400 is followed by the structure 2600. The carbon-based hard mask 2428 has been stripped. Fig. 27 exhibit Fig.26 Representation 2700 of a top view of structure 2600 . Fig. 27 Again the cell array being formed is illustrated. Each cell shown comprises a central pillar 407 surrounded by dielectric material 2023 which is surrounded by a liner 2113.

[0051] Fig.28 Display in processing Fig.26 Structure 2800 after structure 2600. The liner 2113, which was a sacrificial liner, has been removed. The liner 2113 may be removed using a wet etch. Since the liner 2113 is a nitride liner and the pillar 407 is silicon, the nitride may be removed using a wet etch that is selective to oxide. For example, thermal phosphide may be used in the wet etch.

[0052] Fig.29 exhibit Fig.28 Representation 2900 of a top view of structure 2800 . Fig.29 Illustrate an array of cells being formed. Each cell shown comprises a central pillar 407 surrounded by dielectric material 2023. The pad 2113 is no longer part of the cell.

[0053] Fig.30 Display in processing Fig.28Structure 3000 is formed after structure 2800. Conductive material 3027 is formed for the gate, and conductive material 3030 is formed for the WL. Conductive material 3027 and conductive material 3030 may be formed by a suitable deposition technique, which may be chemical vapor deposition (CVD) or atomic layer deposition (ALD). Conductive material 3027 may be formed as a metal deposited to form the gate of the GAA transistor, and conductive material 3030 may be formed as a metal deposited to form the WL. Fig.30 As shown, the conductive material 3030 formed has been recessed, as shown in FIG. Fig.30 As shown in .

[0054] Fig.31 exhibit Fig.30 3100 is a representation of a top view of structure 3000 of FIG. Conductive material 3030 for a WL surrounds conductive material 3027 for a gate of a GAA transistor coupled to conductive material 3030, thereby providing a group of memory cells coupled to the WL. Conductive material 3027 for a gate of a GAA transistor may be referred to as gate 3027. The center of conductive material 3030 for one access line may be structured midway between two adjacent GAA transistors 3121 as access devices for two memory cells, each of which may store one bit.

[0055] Fig.32 Display in processing Fig.30 Structure 3200 after structure 3000. Dielectric 3217 has been formed as a partial fill followed by wet recessing. Dielectric 3217 may be, but is not limited to, oxygen. The junction of the cell contact of pillar 407 has been implanted for coupling to the capacitor. The implant may be an n+ implant.

[0056] Fig.33 Display in processing Fig.32 3200. An etch stop 3369 has been formed. The etch stop 3369 may be formed by a deposition procedure suitable for the material used for the etch stop 3369. The etch stop 3369 may be a nitride etch stop. A set of capacitors has been formed on the etch stop 3369. In forming the capacitor, a bottom electrode 3358 coupled to the pillar 407 has been formed. A top electrode 3357 has been formed, separated from the bottom electrode 3358 by a capacitor dielectric 3359. The capacitor dielectric 3359 may be formed as, but not limited to, a high-k dielectric. The capacitor process may be implemented using the same mask set as used to pattern the active area of ​​the GAA transistor. The capacitor modules may be aligned on the junction of the cell contact-active area-channel arrangement provided by the pillar 407.

[0057] Fig.34 Display in processing Fig.333300. A capping layer 3498 has been formed on top of the set of capacitors. Structure 3400 provides an array structure that is ready to be processed with control and sensing circuitry of a memory device, such as a DRAM device. Capping layer 3498 may be a wafer for mounting structure 3400 for coupling to control and sensing circuitry.

[0058] Figures 35 to 37 exhibit Fig.34 Detail of structure 3400. Structure 3400 has been flipped over, and Fig.34 The capacitor on top is now located Figures 35 to 37 To provide a more detailed view of structure 3400, Fig.35 Various dielectric layers formed in the fabrication of structure 3400 are not shown in structure 3500 of FIG. Metal 1235 of BL surrounds a junction cell contact of an active area 3306 of a GAA transistor having a channel formed by pillar 407. A gate 3027 of the GAA transistor separated by dielectric material 2023 is formed around pillar 407, where gate 3027 contacts WL. Pillar 407 includes a junction contact contact of an active area 3308 of a GAA transistor that contacts an electrode 3358 of a capacitor of a memory cell of structure 3300.

[0059] Fig.37 Representation 3700 shows a top view of the metal 1235 of the structure 3500 with respect to the BL. The metal 1235 of the structure 3400 and the structure 3500 may be referred to as BL 1235. The BL 1235 are separated from each other, wherein each BL 1235 contacts a plurality of memory cells by contacting a plurality of pillars 407. Fig.37 A representation 3700 of a top view of structure 3500 is shown with respect to WL 3030. WL 3030 contacts a plurality of memory cells by contacting the gate 3027 of the GAA transistor of each memory cell, where a memory cell in the plurality of memory cells is on each side of WL 3030. WL 3030 contacts the gate 3027 of the GAA transistor arranged as an access device for capacitor 3329 of structure 3400.

[0060] Figures 3 to 37The process flow provides several enhancements to memory devices such as DRAM devices. In this process flow or a similar process flow, the BL can be formed before forming the WL. The WL can be formed as a replacement gate for the GAA transistor, which can provide enhanced gate control. The capacitor formation of this process flow allows the use of redistribution layers (RDLs) to be omitted. Typical DRAMs use RDL interconnects to rotate the cell contacts into a hexagonal form for capacitor landing. The capacitor is preferably in a hexagonal form because the capacitor has the maximum surface area (and therefore storage capacity) when hexagonal. With a hexagonal active area, there is no need to pattern the hexagonal RDL module. Avoiding the use of several RDLs can reduce the manufacturing cost of the memory device.

[0061] Various deposition techniques for components in the process flows discussed herein may be used, which are typical for the materials being formed, the size of the materials being formed, and the architecture in which the materials are being formed in the manufacture of the memory device. The materials and structures may be formed by suitable processes, such as but not limited to deposition processes, wherein the deposition processes may include but are not limited to physical vapor deposition (PVD), CVD, ALD, or other deposition processes. Other processes may be used. Selective etching may be used to remove selected areas in the processing discussed with respect to the process flow. Selective etching is a process in which one or more materials are removed from a structure, while one or more other materials remain in the structure without or almost without being removed. Selective etching may depend on the material to be etched, the material not to be etched, the etchant used, and the method used for etching. Etching types may include wet etching and dry etching, wherein each of these two basic methods includes several different etching procedures. In addition, conventional masking techniques that provide protection areas in processing may be used to remove selected areas in components forming memory devices.

[0062] Fig.38 illustrate Fig.343400 or similar structures may be located therein. The architecture 3800 is structured as a wafer-to-wafer interconnect architecture, which includes a control wafer 3802 having a bonding area 3812-2 attached to an array wafer 3801 having a bonding area 3812-1. The combination of the control wafer 3802 attached to the array wafer 3801 can be mounted on a carrier wafer 3803 or other suitable platform. The control wafer 3802 can be attached to the array wafer 3801 by bonding the bonding area 3812-1 with the bonding area 3812-2. The bonding process can be performed by fusion bonding. The array wafer 3801 may include one or more of the structure 3400 or similar structures having one or more memory cell arrays. The control wafer 3802 may include control and sensing circuit systems for operating the memory cell arrays of one or more structures 3400 of the array wafer 3801 in a CoA architecture. Alternatively, the vertical order of the control wafer 3802 attached to the array wafer 3801 on the carrier wafer 3803 may be reversed, thereby configuring the architecture 3800 as a CuA architecture.

[0063] Fig.39 39 is a flow chart of features of an embodiment of an example method 3900 of forming a memory device. At 3910, a memory cell array is formed. The memory cells are formed as hexagonal cells, and each of the memory cells is formed as a gate all around (GAA) transistor having a coupling to a capacitor. The capacitor may be formed in a hexagonal arrangement.

[0064] At 3920, a group of WLs is formed. A WL in the group of WLs is coupled to the gates of a first plurality of GAA transistors of a memory cell. Other WLs in the group and other WLs may also be coupled to the gates of other plurality of GAA transistors of other groups.

[0065] At 3930, a group of BLs are formed. The BLs in the group of BLs wrap around the sidewalls of the active area of ​​each GAA transistor in the second group of multiple GAA transistors of the memory cell. Other BLs in the group and other BLs may also wrap around the sidewalls of the active area of ​​each GAA transistor in other groups of multiple GAA transistors of the memory cell. The group of WLs may be positioned at an angle of 90° relative to the group of BLs. The BLs may be formed before forming the WLs.

[0066] Variations of method 3900 or methods similar to method 3900 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of the system including the memory device for which such methods are implemented. Such methods may include forming control logic and sensing circuitry above the array. The control logic and sensing circuitry may be formed above the array in a wafer in a wafer-to-wafer interconnect architecture and combined with the array wafer in which the array is formed. The wafer-to-wafer interconnect architecture may include a wafer-on-wafer architecture.

[0067] A variation of method 3900 or a method similar to method 3900 may include forming a vertical nanowire extending above a substrate, wherein the vertical nanowire has a channel structure with a gate of a GAA transistor formed therearound. The vertical nanowire may include epitaxial silicon on silicon germanium above a silicon substrate.

[0068] A variation of method 3900 or a method similar to method 3900 may include performing a first number of manufacturing processes. Vertical semiconductor pillars may be formed for a GAA transistor, wherein the vertical semiconductor pillars extend above a substrate. A dielectric may be formed between the vertical semiconductor pillars. A damascene structure on the dielectric may be patterned. The patterned damascene structure may be used to expose sidewalls of the vertical semiconductor pillars in the dielectric, and may be doped. Metal may be formed for a BL in the set of BLs, wherein the metal wraps around the doped sidewalls.

[0069] A variation of method 3900 or a method similar to method 3900 may include performing a second number of manufacturing processes. A vertical semiconductor pillar may be formed extending above the substrate. An active region may be formed in the vertical semiconductor pillar. Metal for the BL in the group may be formed around the sidewalls of the active region. A gate of the GAA transistor may be formed surrounding the vertical semiconductor pillar, wherein the gate is formed above a level at which the metal is formed. A capacitor coupled to the vertical semiconductor pillar may be formed after forming the GAA transistor. A variation may include forming a GAA transistor having a gate oxide between a gate of the GAA transistor and a channel of the GAA transistor by depositing a gate oxide on the vertical semiconductor pillar or forming the gate oxide on the vertical semiconductor pillar by in-situ generation of vapor.

[0070] Fig.40 4 is a flow chart of features of an embodiment of an example method of forming a memory device. At 4010, an array wafer is prepared as an array of GAA transistors connected to WL and BL, where the BL wraps around the sidewalls of the active area of ​​the GAA transistor. At 4020, a control circuit system wafer is prepared. The preparation of the control circuit system wafer may include forming SA or SWD for the memory array.

[0071] At 4030, the array wafer and the control circuit system wafer are coupled together. The coupling of the array wafer and the control circuit system wafer can be achieved by bonding the array wafer and the control circuit system wafer together. Contacts that connect one or more memory arrays on the array wafer to circuits on the control circuit system wafer can be patterned. For example, the patterned contacts can include, but are not limited to, one or more SAs on the control circuit system wafer to BLs on the array wafer, or SWDs on the control circuit system wafer to WLs on the array wafer. The control circuit system can be coupled above the array wafer.

[0072] Variations of method 4000 or methods similar to method 4000 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of the system including the memory device for which such methods are implemented. Such methods may include forming the GAA transistors as thin film transistors. Variations may include coupling the array wafer with the control circuit system wafer by bonding the control circuit system wafer over the array wafer. Variations may include forming the BL using a damascene process. Variations may include forming the array of GAA transistors as 4F 2 A variant may include forming an array of GAA transistors as a 4F 2 Hexagonal memory cells in the open BL architecture.

[0073] A variation of method 4000 or a method similar to method 4000 may include performing a second number of manufacturing processes for preparing an array wafer. A semiconductor pillar may be formed over a substrate. A BL may be formed around a doped portion of the semiconductor pillar, wherein the doped portion of the semiconductor pillar provides an active region of a GAA transistor. A bonding layer may be formed over the BL and attached to a carrier wafer. The carrier wafer with the bonding layer may be flipped after attaching the bonding layer. Formation of the GAA transistor may be completed after flipping the carrier wafer, and the GAA transistor may be coupled to a capacitor.

[0074] In various embodiments, a memory device may include an array of memory cells, wherein each of the memory cells has a GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. The capacitor may be arranged in a hexagonal shape. The WL is coupled to the gate of a first group of multiple GAA transistors of the memory cell. Other WLs in the first group and other WLs may also be coupled to the gates of other groups of other multiple GAA transistors. The BL is coupled to a second group of multiple GAA transistors of the memory cell, wherein the BL wraps around the sidewalls of the active area of ​​each GAA transistor in the second group. Other BLs in the second group and other BLs may also wrap around the sidewalls of the active area of ​​each GAA transistor in other groups of multiple GAA transistors of the memory cell.

[0075] As taught herein, variations of such memory devices and features thereof may include several different embodiments and features, which may be combined depending on the application of such memory devices, the format of such memory devices, and / or the architecture in which such memory devices are implemented. Variations of such memory devices may include memory devices having control logic and sensing circuitry above the array. The control logic and sensing circuitry, as well as the memory cell array, may be arranged in a wafer-to-wafer interconnect architecture.

[0076] Variations of this memory device and its features may include a 4F 2 A memory cell array of a cell configuration. A variant may include a channel structure and active region of a GAA transistor of a memory cell structured with vertical nanowires. The vertical nanowires may include epitaxial silicon on silicon germanium.

[0077] Fig.41 4100, which may include a physical architecture having an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a GAA transistor coupled to a capacitor. The memory cells may be coupled to BLs, wherein each of the BLs wraps around the sidewalls of the active area of ​​the GAA transistor of each memory cell to which the BL is coupled. Each WL may be structured to contact the gate of the GAA transistor of the memory cell to which a given WL is coupled. Figures 1 to 40 DRAM device 4100 may include an array of memory cells 4125 arranged in rows 4154-1, 4154-2, 4154-3, and 4154-4 and columns 4156-1, 4156-2, 4156-3, and 4156-4 (for ease of representation, in Fig.41 4154-1, 4154-2, 4154-3, and 4154-4 and four columns 4156-1, 4156-2, 4156-3, and 4156-4 of four memory cells are illustrated, a DRAM device like DRAM device 4100 may have significantly more memory cells 4125 per row or column (e.g., tens, hundreds, or thousands of memory cells).

[0078] In this example, each memory cell 4125 may include a single transistor 4121 and a single capacitor 4129, which is typically referred to as a 1T1C (one transistor-one capacitor cell). One plate of the capacitor 4129, which may be referred to as a "node plate," is connected to the drain terminal of the transistor 4121, while the other plate of the capacitor 4129 is connected to ground 4124 or other reference node. Each capacitor 4129 within the array of 1T1C memory cells 4125 is typically used to store one bit of data, and the corresponding transistor 4121 serves as an access device to write to or read from the storage capacitor 4129. Each transistor 4121 may be implemented by a GAA nanowire transistor, as described with respect to Figures 1 to 40 Discussed.

[0079] The transistor gate terminals within each of the rows 4154-1, 4154-2, 4154-3, and 4154-4 are part of a respective WL 4130-1, 4130-2, 4130-3, and 4130-4, and the transistor source terminals within each of the columns 4156-1, 4156-2, 4156-3, and 4156-4 are electrically connected to a respective BL 4135-1, 4135-2, 4135-3, and 4135-4. The row decoder 4132 may selectively drive the individual WLs 4130-1, 4130-2, 4130-3, and 4130-4 in response to a row address signal 4131 input to the row decoder 4132. Driving a given WL at a high voltage turns on the access transistor within the respective row, thereby connecting the storage capacitor within the row to the respective BL so that charge may be transferred between the BL and the storage capacitor for a read or write operation. Both read and write operations may be performed via the SA circuitry 4140, which may transfer bit values ​​between the memory cells 4125 of a selected row of rows 4154-1, 4154-2, 4154-3, and 4154-4 and an input / output buffer 4146 (for write / read operations) or an external input / output data bus 4148.

[0080] A column decoder 4142 responsive to a column address signal 4141 may select which of the memory cells 4125 within the selected row is read or written to. Alternatively, for a read operation, the storage capacitors 4129 within the selected row may be read and latched simultaneously, and the column decoder 4142 may then select a latch bit connected to the output data bus 4148. Since the readout of the storage capacitor destroys the stored information, a read operation is accompanied by a simultaneous rewrite of the capacitor charge. In addition, between read / write operations, the capacitor charge is repeatedly refreshed to prevent data loss. The details of the read / rewrite, write, and refresh operations are well known to those of ordinary skill in the art.

[0081] DRAM device 4100 may be implemented as an IC within a package that includes pins for receiving supply voltages (eg, for providing source and gate voltages for transistor 4121) and signals (including data, address, and control signals). Fig.41 DRAM device 4100 is depicted in simplified form to illustrate basic structural components, omitting many details of memory cells 4125 and associated WLs 4130-1, 4130-2, 4130-3, and 4130-4 and BLs 4135-1, 4135-2, 4135-3, and 4135-4, and peripheral circuitry. For example, in addition to row decoder 4132, column decoder 4142, SA circuitry 4140, and buffer 4146, DRAM device 4100 may include additional peripheral circuitry (e.g., a memory control unit that controls memory operations based on control signals (e.g., provided by an external processor), additional input / output circuitry, or other features associated with a memory device. The details of such peripheral circuitry are generally well known to those of ordinary skill in the art and are not further discussed herein. In a CoA architecture using a wafer-to-wafer interconnect architecture, the peripheral circuitry may be located above the array of memory cells 4125. Alternatively, in a CuA architecture, the peripheral circuitry may be located below the array of memory cells 4125. Alternatively, the peripheral circuitry may be located in a region of the IC of the memory device adjacent to the array region having the array of memory cells 4125.

[0082] In a two-dimensional (2D) DRAM array, the rows 4154-1, 4154-2, 4154-3, and 4154-4 and columns 4156-1, 4156-2, 4156-3, and 4156-4 of memory cells 4125 are arranged along a single horizontal plane (i.e., a plane parallel to the layers) of the semiconductor substrate, for example, in a rectangular lattice having WLs 4130-1, 4130-2, 4130-3, and 4130-4 and BLs 4135-1, 4135-2, 4135-3, and 4135-4. In a 3D DRAM array, the memory cells 4125 may be arranged in a 3D lattice, with one set of memory cells and associated WLs and BLs at a level above another set of memory cells and associated WLs and BLs.

[0083] The example DRAM device 4100 and the like may be implemented in various electronic devices. Figures 1 to 40Electronic devices, such as mobile electronic devices (e.g., smart phones, tablet computers, or other similar communication-related devices), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety systems, comfort systems, or other similar systems), and Internet-connected appliances or devices (e.g., Internet of Things (IoT) devices or other network-related devices)) have storage requirements that vary depending on, among other things, the type of electronic device, the usage environment, performance expectations, or other criteria.

[0084] Such electronic devices may be broken down into several major components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile RAM memory devices, such as dynamic DRAM, mobile or low-power double data rate synchronous DRAM (DDR SDRAM), or other similar memory devices); and a storage device (e.g., a non-volatile memory (NVM) device, such as flash memory, ROM, solid-state drive (SSD), multimedia card (MMC), other memory card structures or assemblies, or other similar storage devices). In some examples, the electronic device may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, or other similar interfacing structures), a graphics processing unit (GPU), a power management circuit, a baseband processor, one or more transceiver circuits, or other similar devices. As used herein, a "processor device" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a processor group or a multi-core device.

[0085] The following examples are example embodiments of devices and methods according to the teachings herein.

[0086] An example memory device 1 may include: a memory cell array, wherein each of the memory cells has a GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; a WL coupled to gates of a first set of multiple GAA transistors of the memory cell; and a BL coupled to a second set of multiple GAA transistors of the memory cell, the BL wrapping around a sidewall of an active area of ​​each GAA transistor in the second set.

[0087] Example memory device 2 may include the features of example memory device 1, and may include control logic and sensing circuitry over the array.

[0088] Example memory device 3 may include features of example memory device 2 and any of the preceding example memory devices, and may include the control logic and sensing circuitry and the memory cell array arranged in a wafer-to-wafer interconnect architecture.

[0089] Example memory device 4 may include features of any of the aforementioned example memory devices, and may include a 4F 2 The memory cell array of the cell configuration.

[0090] The example memory device 5 may include features of any of the aforementioned example memory devices, and may include the channel structure and active regions of the GAA transistors of the memory cells structured with vertical nanowires.

[0091] Example memory device 6 may include features of example memory device 5 and any of the preceding example memory devices, and may include the vertical nanowires to include epitaxial silicon.

[0092] In example memory device 7, any of the memory devices in example memory devices 1-6 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0093] In example memory device 8, any of the memory devices in example memory devices 1-7 may be modified to include any structure present in another of example memory devices 1-7.

[0094] In example memory device 9, any apparatus associated with a memory device in example memory devices 1-8 may further include a machine-readable storage device configured to store instructions as a physical state, where the instructions may be used to perform one or more operations of the apparatus.

[0095] In example memory device 10, any of the memory devices in example memory devices 1-9 may be formed according to any of the following example methods 1-13 of forming a memory device or example methods 1-9 of forming a memory device.

[0096] An example method 1 of forming a memory device may include forming an array of memory cells, including forming the memory cells of the array as hexagonal cells and forming each of the memory cells as a gate all around (GAA) transistor having a coupling to a capacitor; forming a set of WLs, wherein the WLs in the set of WLs are coupled to gates of a first set of a plurality of GAA transistors of the memory cells; and forming a set of BLs, wherein the BLs in the set of BLs wrap around sidewalls of an active area of ​​each GAA transistor in a second set of a plurality of GAA transistors of the memory cells.

[0097] Example method 2 of forming a memory device may include features of example method 1 of forming a memory device, and may include forming control logic and sensing circuitry over the array.

[0098] Example method 3 of forming a memory device may include features of example method 2 of forming a memory device and any of the foregoing example methods of forming a memory device, and may include forming the control logic and sensing circuitry above the array to include forming the control logic and sensing circuitry in a wafer, and combining the wafer with an array wafer in which the array is formed into a wafer-to-wafer interconnect architecture.

[0099] Example method 4 of forming a memory device may include features of any of the preceding example methods of forming a memory device, and may include forming a vertical nanowire extending over a substrate, wherein the vertical nanowire has a channel structure around which a gate of the GAA transistor is formed.

[0100] Example method 5 of forming a memory device may include features of example method 4 of forming a memory device and any of the preceding example methods of forming a memory device, and may include forming the vertical nanowires to include forming epitaxial silicon over a silicon substrate.

[0101] Example method 6 of forming a memory device may include features of any of the aforementioned example methods of forming a memory device, and may include forming vertical semiconductor pillars for the GAA transistor, the vertical semiconductor pillars extending above a substrate; forming a dielectric between the vertical semiconductor pillars; patterning a damascene structure on the dielectric; exposing sidewalls of the vertical semiconductor pillars in the dielectric using the patterned damascene structure; doping the sidewalls; and forming a metal around the doped sidewalls for the BL in the group.

[0102] Example method 7 of forming a memory device may include features of any of the aforementioned example methods of forming a memory device, and may include forming a vertical semiconductor pillar extending above a substrate; forming a first active region in the vertical semiconductor pillar; for the BL in the group, forming a metal around the sidewalls of the first active region; forming a gate of the GAA transistor surrounding the vertical semiconductor pillar, the gate being formed above a level in which the metal is formed; and forming the capacitor coupled to the vertical semiconductor pillar after forming the GAA transistor.

[0103] An example method 8 of forming a memory device may include features of any of the aforementioned example methods of forming a memory device, and may include forming the GAA transistor having a gate oxide between a gate of the GAA transistor and a channel of the GAA transistor by depositing the gate oxide on a vertical semiconductor pillar or by forming the gate oxide by in-situ generating vapor on the vertical semiconductor pillar.

[0104] In example method 9 of forming a memory device, any of example methods 1-8 of forming a memory device may be performed in forming an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0105] In example method 10 of forming a memory device, any of example methods 1-9 of forming a memory device may be modified to include the operations set forth in any other of example methods 1-9 of forming a memory device.

[0106] In example method 11 of forming a memory device, any of example methods 1-10 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0107] Example method 12 of forming a memory device may include features of any of the foregoing example methods 1-11 of forming a memory device, and may include forming features associated with any of the features of example memory devices 1-10.

[0108] An example method 13 of forming a memory device may include preparing an array wafer having an array of gate-all-around (GAA) transistors connected to WLs and BLs, wherein the BLs wrap around sidewalls of active areas of the GAA transistors; preparing a control circuitry wafer; and coupling the array wafer and the control circuitry wafer together.

[0109] Example method 14 of forming a memory device may include features of example method 13 of forming a memory device, and may include forming the GAA transistor as a thin film transistor.

[0110] An example method 15 for forming a memory device may include features of any of the aforementioned example methods 13 to 14 for forming a memory device, and may include preparing the array wafer to include: forming a semiconductor pillar over a substrate; forming a BL surrounding a doped portion of the semiconductor pillar, the doped portion of the semiconductor pillar providing an active area of ​​the GAA transistor; forming a bonding layer over the BL; attaching the bonding layer to a carrier wafer; after attaching the bonding layer, flipping the carrier wafer with the bonding layer; after flipping the carrier wafer, completing formation of the GAA transistor; and coupling the GAA transistor to a capacitor.

[0111] Example method 16 of forming a memory device may include features of any of the foregoing example methods 13-15 of forming a memory device, and may include coupling the array wafer and the control circuitry wafer together to include bonding the control circuitry wafer over the array wafer.

[0112] Example method 17 of forming a memory device may include features of any of the preceding example methods 13-16 of forming a memory device, and may include using a damascene process to form the BL.

[0113] Example method 18 of forming a memory device may include features of any of the foregoing example methods 13-17 of forming a memory device, and may include forming the array of GAA transistors as a 4F 2 Hexagonal memory cells in the architecture.

[0114] In example method 19 of forming a memory device, any of example methods 13-18 of forming a memory device may be performed in forming an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0115] In example method 20 of forming a memory device, any of example methods 13-19 of forming a memory device may be modified to include the operations set forth in any other of example methods 13-19 of forming a memory device.

[0116] In example method 21 of forming a memory device, any of example methods 13-20 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0117] Example method 22 of forming a memory device may include features of any of the foregoing example methods 13-21 of forming a memory device, and may include forming features associated with any of the features of example memory devices 1-10.

[0118] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause the machine to perform operations may include instructions to perform functions associated with any feature of the example memory devices 1-10 or to perform methods associated with any feature of the example methods 1-22 of forming a memory device.

[0119] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments utilize permutations and / or combinations of the embodiments described herein. It should be understood that the above description is intended to be illustrative and not limiting, and that the phraseology or terminology employed herein is for descriptive purposes.

Claims

1. A memory device, comprising: a memory cell array wherein each of the memory cells has a gate-all-around GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; an access line coupled to gates of a first plurality of GAA transistors of the memory cell; and A digit line is coupled to a second plurality of GAA transistors of the memory cell, the digit line wrapping around a sidewall of an active region of each GAA transistor in the second plurality.

2. The memory device of claim 1, wherein the memory device includes control logic and sensing circuitry above the array.

3. The memory device of claim 2, wherein the control logic and sensing circuitry and the memory cell array are arranged in a wafer-to-wafer interconnect architecture.

4. The memory device of claim 1, wherein the memory cell array has a 4F 2 Unit configuration.

5. The memory device of claim 1, wherein a channel structure and an active area of ​​the GAA transistor of a memory cell are structured with vertical nanowires.

6. The memory device of claim 5, wherein the vertical nanowires comprise epitaxial silicon.

7. A method of forming a memory device, the method comprising: forming an array of memory cells including forming the memory cells of the array as hexagonal cells and forming each of the memory cells as a gate-all-around (GAA) transistor having a capacitor coupled to the array; forming a set of access lines, wherein access lines in the set of access lines are coupled to gates of a first plurality of GAA transistors of the memory cell; and A set of digit lines is formed, wherein the digit lines in the set of digit lines wrap around a sidewall of an active region of each GAA transistor in a second plurality of GAA transistors of the memory cell.

8. The method of claim 7, wherein the method includes forming control logic and sensing circuitry over the array.

9. The method of claim 8 wherein forming the control logic and sensing circuitry over the array includes forming the control logic and sensing circuitry in a wafer and combining the wafer with an array wafer in which the array is formed into a wafer-to-wafer interconnect architecture.

10. The method of claim 7, wherein the method comprises forming a vertical nanowire extending above a substrate, wherein the vertical nanowire has a channel structure around which a gate of the GAA transistor is formed.

11. The method of claim 10, wherein forming the vertical nanowires comprises forming epitaxial silicon on silicon germanium over a silicon substrate.

12. The method of claim 7, wherein the method comprises: forming a vertical semiconductor pillar for the GAA transistor, the vertical semiconductor pillar extending above the substrate; forming a dielectric between the vertical semiconductor pillars; patterning a damascene structure on the dielectric; exposing sidewalls of the vertical semiconductor pillars in the dielectric using a patterned damascene structure; doping the sidewalls; and For the digit lines in the set, metal is formed wrapping around the doped sidewalls.

13. The method of claim 7, wherein the method comprises: forming a vertical semiconductor pillar extending above the substrate; forming a first active region in the vertical semiconductor pillar; For the digit lines in the group, forming a metal wrap around the sidewalls of the first active region; forming a gate of the GAA transistor surrounding the vertical semiconductor pillar, the gate being formed above a level where the metal is formed; and The capacitor coupled to the vertical semiconductor pillar is formed after forming the GAA transistor.

14. The method of claim 7, wherein the method comprises forming the GAA transistor having a gate oxide between a gate of the GAA transistor and a channel of the GAA transistor by depositing the gate oxide on a vertical semiconductor pillar or by forming the gate oxide by in-situ generation of vapor on the vertical semiconductor pillar.

15. A method of forming a memory device, the method comprising: preparing an array wafer having an array of gate-all-around GAA transistors connected to access lines and digit lines, wherein the digit lines wrap around the sidewalls of the active areas of the GAA transistors; Preparation of control circuit system chip; and The array chip and the control circuit system chip are coupled together.

16. The method of claim 15, wherein the method comprises forming the GAA transistor as a thin film transistor.

17. The method according to claim 15, wherein preparing the array wafer comprises: forming a semiconductor pillar above the substrate; forming a digit line surrounding a doped portion of the semiconductor pillar, the doped portion of the semiconductor pillar providing an active region of the GAA transistor; forming a bonding layer over the digit line; attaching the bonding layer to a carrier wafer; After attaching the bonding layer, flipping the carrier wafer with the bonding layer; After flipping the carrier wafer, completing the formation of the GAA transistor; and The GAA transistor is coupled to a capacitor.

18. The method of claim 15, wherein coupling the array wafer and the control circuitry wafer together comprises bonding the control circuitry wafer over the array wafer.

19. The method of claim 15, wherein the method includes forming the digit line using a damascene process.

20. The method of claim 15, wherein the method comprises forming the array of GAA transistors into a 4F 2 Hexagonal memory cells in the architecture.

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