Micro light emitting diode and display device thereof

Abstract

The application discloses a micro light emitting diode and a display device thereof, having a semiconductor layer sequence, the semiconductor layer sequence includes a back side and a front side, and sequentially includes a first type semiconductor layer, a second type semiconductor layer, and an active layer between the first type semiconductor layer and the second type semiconductor layer from the front side; the back side of the semiconductor layer sequence has an exposed part, the exposed part penetrates through the second type semiconductor layer and the active layer, and exposes the first type semiconductor layer; the back side of the semiconductor layer sequence includes a first mesa in the exposed part, a second mesa on the second type semiconductor layer, and a mesa sidewall between the first mesa and the second mesa; the back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected with the first type semiconductor layer and a second metal electrode electrically connected with the second type semiconductor layer; and the semiconductor layer sequence is further provided with a passivation layer covering the semiconductor layer sequence and / or the sidewall, the passivation layer has a first opening on the first mesa for arranging the first metal electrode, the first opening includes a first angle close to the mesa sidewall and a second angle away from the mesa sidewall, and the second angle is smaller than the first angle, so that the continuity of the first metal electrode is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing, specifically relating to micro light-emitting diodes and display devices. Background Technology

[0002] Micro-LEDs (mLEDs) are currently a hot research topic as a next-generation display light source. They boast advantages such as low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, low energy consumption, and long lifespan. Furthermore, their power consumption is approximately 10% of that of LCDs and 50% of that of OLEDs. Compared to OLEDs, which are also self-emissive, mLEDs offer several times the brightness and can achieve high pixel density. These significant advantages make mLEDs a promising candidate to replace current OLEDs and LCDs as the light source for next-generation displays. However, mLEDs cannot yet be mass-produced due to numerous technical challenges that need to be overcome, one of the most important being improving the yield of micron-sized LED chips. Summary of the Invention

[0003] To improve the yield of micron-sized chips, this invention provides a micro-light-emitting diode (LED) with a semiconductor layer sequence, including a back side and a front side. Starting from the front side, the semiconductor layer sequence includes a first type semiconductor layer and a second type semiconductor layer, with an active layer located between them. The back side of the semiconductor layer sequence has an exposed portion that penetrates the second type semiconductor layer and the active layer, exposing at least the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between them. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer. It also includes a passivation layer covering the semiconductor layer sequence and / or the sidewall. The passivation layer is partially disposed on the first mesa and has a first opening for disposing of the first metal electrode. The first opening has a first angle α1 near the mesa sidewall and a second angle α2 away from the mesa sidewall relative to the horizontal plane, with the second angle α2 being smaller than the first angle α1.

[0004] This invention also provides a micro light-emitting diode having a semiconductor layer sequence, the semiconductor layer sequence including a back side and a front side, the front side sequentially including a first type semiconductor layer and a second type semiconductor layer, with an active layer located between the two, the back side of the semiconductor layer sequence having an exposed portion that penetrates the second type semiconductor layer and the active layer, at least exposing the first type semiconductor layer, the back side of the semiconductor layer sequence including a first mesa within the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between the two, the exposed portion being a non-closed step, the exposed portion being composed of N side surfaces, N The value is an integer not less than 2, wherein at least one side is a mesa sidewall, at least one side is exposed, a first metal electrode electrically connected to a first type of semiconductor layer and a second metal electrode electrically connected to a second type of semiconductor layer are disposed on the back side of the semiconductor layer sequence, and a passivation layer is also provided covering the semiconductor layer sequence and / or the sidewall, the passivation layer is partially disposed on the first mesa, the passivation layer has a first opening for disposing of the first metal electrode, the first opening includes a first angle α1 near the mesa sidewall and a second angle α2 near the exposed side relative to the horizontal plane, the second angle α2 being less than the first angle α1.

[0005] The present invention also provides a display device, including a plurality of micro light-emitting diodes and a substrate. The micro light-emitting diodes are disposed on the substrate and have a semiconductor layer sequence. The semiconductor layer sequence includes a back side and a front side. Starting from the front side, it sequentially includes a first type semiconductor layer and a second type semiconductor layer. An active layer is located between the two. The back side of the semiconductor layer sequence has an exposed portion that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between the two. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer. It also includes a passivation layer covering the semiconductor layer sequence and / or the sidewall. The passivation layer on the first mesa has a first opening for disposing of the first metal electrode. The first opening has a first angle α1 near the mesa sidewall and a second angle α2 away from the mesa sidewall relative to the horizontal plane. The second angle α2 is smaller than the first angle α1.

[0006] This invention improves both product performance and yield by differentiating the openings in the passivation layer.

[0007] Other beneficial effects of the present invention will be described step by step through the embodiments and accompanying drawings. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, some of the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 and Figure 2 These are a cross-sectional view and a top view of a micro LED chip in the prior art, respectively.

[0010] Figure 3 and Figure 4 These are a cross-sectional view and a top view of the first embodiment of the present invention, respectively.

[0011] Figure 5 This is a top view schematic diagram of the second embodiment of the present invention;

[0012] Figure 6 This is a top view schematic diagram of the third embodiment of the present invention;

[0013] Figure 7 This is a cross-sectional schematic diagram of the fourth embodiment of the present invention;

[0014] Figure 8 This is a cross-sectional schematic diagram of the fifth embodiment of the present invention;

[0015] Figure 9 This is a cross-sectional schematic diagram of the sixth embodiment of the present invention;

[0016] Figure 10 This is a cross-sectional schematic diagram of the seventh embodiment of the present invention.

[0017] The diagram is labeled as follows: 110, Semiconductor layer sequence; 111, First type semiconductor layer; 112, Second type semiconductor layer; 113, Active layer; 210, First metal electrode; 211, 221, First layer; 212, 222, Second layer; 220, Second metal electrode; 300, Passivation layer; 400, Transparent conductive layer; 500, Substrate; CR, Crack; G1, Exposed portion; K1, First opening; K2, Second opening; K11, First electrode hole; K12, Second electrode hole; M1, First mesa; M2, Second mesa; S1, Sidewall; α1, First angle; α2, Second angle; α3, Third angle; α4, Fourth angle; d1, Distance; h, Height; L1, L2, Length; C1, Micro LED; P1: Epoxy resin. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] In some embodiments, a micro-light-emitting diode is provided, having a semiconductor layer sequence including a back side and a front side. Starting from the front side, it sequentially includes a first type semiconductor layer and a second type semiconductor layer, with an active layer located between them. The back side of the semiconductor layer sequence has an exposed portion that penetrates the second type semiconductor layer and the active layer, exposing at least the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between them. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer. It also includes a passivation layer covering the semiconductor layer sequence and / or the sidewall. The passivation layer is partially disposed on the first mesa and has a first opening for disposing of the first metal electrode. The first opening has a first angle α1 near the mesa sidewall and a second angle α2 away from the mesa sidewall relative to the horizontal plane. The second angle α2 is smaller than the first angle α1. Here, the opening of the passivation layer refers to the portion formed by etching away part of the passivation layer. The exposed portion is, for example, a groove or a step.

[0020] In some embodiments, the first angle α1 is 1.05 to 5 times the second angle α2. The angle here mainly refers to the angle between the side of the passivation layer and the horizontal plane. When the correlation multiple is less than 1.05 times, the yield improvement of the first metal electrode is limited. When the passivation layer is a multilayer distributed Bragg reflector (DBR), the correlation multiple exceeds 5 times, and the reflection effect will decrease significantly.

[0021] In some embodiments, the second angle α2 is 15° to 75°. When the second angle α2 is less than 15°, the passivation layer will be too thin, reducing the process yield. If the passivation layer is DBR, it may reduce the reflection efficiency.

[0022] In some embodiments, the length of the first metal electrode and / or the second metal electrode is from 5 μm to 30 μm. When the length is less than 5 μm, especially when the length of the first metal electrode is less than 5 μm, the stability and symmetry of the bond are significantly affected by the exposed portion.

[0023] In some embodiments, the distance between the first opening and the sidewall of the table is 0.5 μm to 5 μm. The closer the first opening is to the sidewall of the table, the more difficult it is to control the first angle in the manufacturing process.

[0024] In some embodiments, the height of the first platform from the second platform in the vertical direction is 0.2 μm to 2 μm. The greater the drop, the more difficult it is to control the first angle in the process.

[0025] In some embodiments, the exposed portion is a non-closed step; three of the four sides of the exposed portion are platform sidewalls, and the other side is exposed to retain more light-emitting area.

[0026] In some embodiments, the exposed portion is a non-closed step; the exposed portion consists of N sides, where N is an integer not less than 2, wherein at least one side is a countertop sidewall, and at least one side is exposed.

[0027] In some embodiments, the first metal electrode extends from the exposed portion to the second mesa, and the height h from the first mesa to the upper surface of the passivation layer on the second mesa is 0.5 μm to 3 μm, which is the vertical height.

[0028] In some embodiments, the projected area of ​​the back surface of the first metal electrode and / or the second metal electrode is 25 μm. 2 Up to 200μm 2 The smaller the projected area, especially the smaller the projected area of ​​the first metal electrode, the more difficult the bonding becomes.

[0029] In some embodiments, a passivation layer covers at least from a first mesa to a second mesa, the passivation layer having a second opening on the second mesa, a first metal electrode being electrically connected to a first type semiconductor layer through the first opening, and a second metal electrode being electrically connected to a second type semiconductor layer through the second opening. Here, the opening of the passivation layer refers to the portion of the passivation layer formed by etching away part of the passivation layer, and a transparent conductive layer is disposed between the second metal electrode and the second type semiconductor layer.

[0030] In some embodiments, the second opening includes a third angle α3 relative to the horizontal plane, which is the tilt angle formed by the passivation layer of the second opening sidewall and the horizontal plane, wherein the third angle α3 is less than the first angle α1, and α3 is (1±30%)*α2.

[0031] In some embodiments, α3 is (1±20%)*α2, and the angle of α2 is designed to be close to that of α3, so as to reduce the angle of α2 as much as possible and achieve a better yield of metal electrode fabrication.

[0032] In some embodiments, the passivation layer is partially disposed between the second metal electrode and the second type semiconductor layer, and the second metal electrode extends from the second opening to the upper surface of the back side of the passivation layer. Alternatively, the second metal electrode is not disposed between the passivation layer and the second type semiconductor layer, i.e., the passivation layer is directly disposed on the second type semiconductor layer, and the second type semiconductor layer, the passivation layer, and the second metal electrode are stacked sequentially. Or, the second metal electrode is not disposed between the passivation layer and the transparent conductive layer, i.e., the passivation layer is directly disposed on the transparent conductive layer, and the second type semiconductor layer, the transparent conductive layer, the passivation layer, and the second metal electrode are stacked sequentially.

[0033] In some embodiments, the thickness of the passivation layer is from 0.1 μm to 3 μm. The thicker the passivation layer, the more difficult it is to fabricate the second opening and the second metal electrode.

[0034] In some embodiments, the first metal electrode is an N-type electrode and the second metal electrode is a P-type electrode.

[0035] In some embodiments, the exposed portion is triangular, rectangular, trapezoidal, semi-elliptical, or semi-elliptical, including cases where individual acute or obtuse angles are chamfered.

[0036] In some embodiments, such as when the passivation layer is designed as a DBR, the angle between the mesa sidewall and the horizontal plane is a fourth angle α4, where α4 is 30° to 70°, or when the passivation layer is a single-layer or double-layer dielectric layer, α4 is 70° to 90°.

[0037] In some embodiments, a display device is provided, including a plurality of microlight-emitting diodes and a substrate. The microlight-emitting diodes are disposed on the substrate and have a semiconductor layer sequence, the semiconductor layer sequence including a back side and a front side, and sequentially including a first type semiconductor layer and a second type semiconductor layer starting from the front side, with an active layer located between the two. The back side of the semiconductor layer sequence has an exposed portion that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between the two. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer. It also includes a passivation layer covering the semiconductor layer sequence and / or the sidewall. The passivation layer is characterized in that the passivation layer has a first opening on the first mesa for disposing of the first metal electrode. The first opening includes a first angle close to the mesa sidewall and a second angle away from the mesa sidewall relative to the horizontal plane, the second angle being smaller than the first angle.

[0038] In some embodiments, the chromium content of the first metal electrode is greater than that of the second metal electrode, and the length of the second metal electrode is 2 μm to 30 μm. Metal migration depends on high temperature and high humidity conditions. Under the catalysis of water vapor, chromium-containing ions migrate. The second metal electrode has a high electric field, and the chromium in the second metal electrode is more likely to migrate than the chromium in the first metal electrode. As the size of the second metal electrode continues to shrink, the metal coating decreases, and chromium leakage is likely to occur. Reducing the chromium content of the second metal electrode helps to reduce the risk of chromium leakage.

[0039] In some embodiments, the first metal electrode is in contact with the first type of semiconductor layer via chromium, while the second metal electrode does not contain chromium, i.e., it is not connected to the second type of semiconductor layer via chromium, or it is not connected to the transparent conductive layer via chromium.

[0040] In some embodiments, the length of the second metal electrode is 5 μm to 30 μm. Increasing the minimum length of the second metal electrode compensates for the loss of adhesion due to the reduced chromium content and reduces the risk of the second metal electrode detaching.

[0041] In some embodiments, the first metal electrode is completely disposed within the exposed portion, which is a non-closed step; three of the four sides of the exposed portion are exposed, and the other side is a platform sidewall, or two of the four sides of the exposed portion are exposed, and the other two sides are platform sidewalls.

[0042] In some embodiments, the projected area of ​​the back surface of the first metal electrode and / or the second metal electrode is 25 μm. 2 Up to 100μm 2 The projected area of ​​the first back surface of the second metal electrode is 30 μm. 2 Up to 100μm 2 To maximize the area of ​​the first layer of the second metal electrode, the adhesion of the electrode should be increased.

[0043] In some embodiments, the distance between the first metal electrode and the second metal electrode is 4 μm to 10 μm.

[0044] In some embodiments, the maximum aperture of the first opening is 2 μm to 20 μm, and the maximum aperture of the second opening is 2 μm to 20 μm. Here, the aperture refers to the diameter at the bottom of the opening, ensuring that the second metal electrode and the second type of semiconductor layer have sufficient connection force to compensate for the loss of adhesion due to the reduction or elimination of chromium content.

[0045] In some embodiments, a passivation layer is disposed between a second metal electrode and a second type of semiconductor layer, with the second metal electrode extending from a second opening to the upper surface of the back side of the passivation layer. The thickness of the passivation layer is 0.1 μm to 3 μm.

[0046] In some embodiments, the back surface of the first metal electrode corresponding to the first opening has a first electrode hole, and the back surface of the second metal electrode corresponding to the second opening has a second electrode hole. The opening area of ​​the first electrode hole is smaller than the opening area of ​​the second electrode hole. Increasing the opening area of ​​the second electrode hole limits the effective contact area since the first metal electrode extends from the exposed portion to the second platform. This embodiment increases the contact area between the second metal electrode and the second type of semiconductor layer or transparent conductive layer on its front side, while also increasing the bonding area when the first metal electrode is bonded to the outside, reducing the risk of bond detachment.

[0047] In some embodiments, the opening area of ​​the first electrode hole accounts for 10% to 40% of the back surface area of ​​the first metal electrode, and the opening area of ​​the second electrode hole accounts for 15% to 50% of the back surface area of ​​the second metal electrode, thereby increasing the bonding area when the first metal electrode is bonded to the outside and reducing the risk of bond detachment.

[0048] In some embodiments, the first metal electrode and the second metal electrode have n metal layers, where n is an integer greater than or equal to 2. The first layer of the first metal electrode, near the first mesa, contains chromium and is used to connect to the first type of semiconductor layer. The first layer of the second metal electrode, near the second mesa, does not contain chromium and is in contact with a transparent conductive layer, which is electrically connected to the second type of semiconductor layer.

[0049] In some embodiments, the length of the first layer of the second metal electrode is greater than 2 μm to 25 μm. The first layer of the second metal electrode serves as a contact layer with the second type semiconductor layer or transparent conductive layer. The material includes, for example, nickel, aluminum, titanium, platinum, gold, or an alloy of any combination thereof. The adhesion of the first layer to the second type semiconductor layer and transparent conductive layer is lower than that of chromium. Therefore, increasing the length is beneficial to improving the overall adhesion of the second metal electrode.

[0050] In some embodiments, the first layer of the second metal electrode includes titanium, which has high adhesion and is not easily migrated under an electric field. That is, the second type semiconductor layer, the transparent conductive layer, and the first layer of the second metal electrode are stacked in sequence.

[0051] In some embodiments, the micro-LED is sealed with epoxy resin. The micro-LED has a semiconductor layer sequence, including a back side and a front side. Starting from the front side, it sequentially includes a first type semiconductor layer and a second type semiconductor layer, with an active layer located between them. The back side of the semiconductor layer sequence has an exposed portion that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between them. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer. The chromium content of the first metal electrode is greater than that of the second metal electrode, and the length of the second metal electrode is 2 μm to 30 μm. Because epoxy resin has high stress, chromium leakage from the second metal electrode is likely to occur. Therefore, reducing or eliminating the chromium content of the first electrode is beneficial for improving product yield.

[0052] In some embodiments, the first metal electrode is in contact with a first type of semiconductor layer via chromium, and the second metal electrode does not contain chromium.

[0053] See Figure 1 and Figure 2 In the prior art, silicone is usually used as the encapsulation material. Silicone has the technical effect of low stress. The micro light-emitting diode includes: a semiconductor layer sequence 110, which has a first type semiconductor layer 111 and a first type semiconductor layer 112, with an active layer 113 located between them. A first metal electrode 210 is electrically connected to the first type semiconductor layer 111, and a second metal electrode 220 is electrically connected to the first type semiconductor layer 112.

[0054] On the one hand, the passivation layer 300 has a first opening K1 on the first mesa M1. The first metal electrode 210 is connected to the passivation layer 300 from the first mesa M1. Due to the close proximity to the sidewall of the exposed part G1 and the limited aperture of the first opening K1, the angle between the first opening K1 and the horizontal plane is too large, which increases the difficulty of manufacturing the first metal electrode 210 and makes it easy for cracks CR to appear.

[0055] On the one hand, in order to replace existing technologies, when the client uses epoxy resin as the encapsulation material, the stress of the encapsulation adhesive increases, making it easier for the chromium in the first layer 221 of the second metal electrode 220 to leak. On the other hand, since the size of the micro LED chip is at the micrometer level and significantly smaller than that of the traditional LED chip, the size of the second metal electrode 220 also needs to be continuously reduced. The first layer 221 of the second metal electrode 220 usually serves as a contact layer to provide adhesive force, and the second layer or above of the second metal electrode 220 serves as a protective layer to cover the first layer 221 of the second metal electrode 220 and prevent the material of the first layer 221 of the second metal electrode 220 from leaking. As the size of the second metal electrode 220 continues to shrink, the covering effect of the second layer 222 of the second metal electrode 220 decreases, making it easier for the material of the first layer 221 of the second metal electrode 220 to leak.

[0056] See Figure 3 and Figure 4 In a first embodiment of the present invention, a micro-light-emitting diode (LED) is provided. The LED is rectangular, with a short side length of 10 μm to 30 μm and a long side length of 15 μm to 40 μm. For example, the LED has a size of 10 μm * 25 μm. It has a semiconductor layer sequence 110, which includes a back side and a front side. Starting from the front side, it sequentially includes a first type semiconductor layer 111, a second type semiconductor layer 112, and an active layer 113 located between them. The first type semiconductor layer 111 of the LED is at least partially removed from the front side, for example, through substrate stripping and epitaxial thinning processes. To improve the light extraction efficiency of the flip chip, the light-emitting surface (N-GaN surface) needs to be roughened or patterned. After the COW process is completed, the chip is bonded and laser-lifted. Laser-lifting utilizes a high-photon-energy laser to decompose gallium nitride at the chip-sapphire interface, thereby achieving separation of the chip from the substrate. The parameters of the laser source (spot size, power, scanning path) in the laser lift-off process have a significant impact on the chip lift-off effect.

[0057] In this embodiment, the first type of semiconductor layer 111 is further fabricated with periodic or non-periodic roughening patterns from the front side, with the front side serving as the light-emitting surface to improve light extraction efficiency. The semiconductor layer sequence 110 is gallium nitride-based.

[0058] The back side of the semiconductor layer sequence 110 has an exposed portion G1, which serves as a Mesa trench, providing a window for fabricating electrodes. The exposed portion G1 penetrates the second type semiconductor layer 112 and the active layer 113, exposing at least the first type semiconductor layer 111, or removing a portion of the first type semiconductor layer 111. The back side of the semiconductor layer sequence 110 includes a first mesa M1 within the exposed portion G1, a second mesa M2 on the second type semiconductor layer 112, and a mesa sidewall S1 located between the two. The back side of the semiconductor layer sequence 110 is provided with a first metal electrode 210 electrically connected to the first type semiconductor layer 111 and a second metal electrode 220 electrically connected to the second type semiconductor layer 112, and also includes a covering... A passivation layer 300 is disposed on the top and / or sidewalls of the semiconductor layer sequence 110. The passivation layer 300 is partially disposed on the first mesa M1. The passivation layer M1 has a first opening K1 for disposing of a first metal electrode 210. The first metal electrode 210 extends across the sidewall of the first opening K1 to the passivation layer 300, and further extends from the passivation layer 300 to the top of the second mesa M2. The first opening K1 includes a first angle α1 near the mesa sidewall S1 and a second angle α2 away from the mesa sidewall S1 relative to the horizontal plane. The second angle α2 is smaller than the first angle α1. Here, the opening of the passivation layer 300 refers to the portion of the passivation layer 300 formed by etching away part of the passivation layer 300. The exposed portion G1 is, for example, a groove or step with an exposed side.

[0059] In some embodiments of this example, the length L1 of the first metal electrode 210 and the length L2 of the second metal electrode 220 are 5 μm to 30 μm.

[0060] In some embodiments of this example, the projected area of ​​the back surface of the first metal electrode 210 and / or the second metal electrode 220 is 25 μm. 2 Up to 100μm 2 .

[0061] In some embodiments of this example, the exposed portion G1 is a non-closed step; three of the four sides of the exposed portion are mesa sidewalls, each consisting of a central arcuate surface and two side surfaces on either side of the arcuate surface. The two side surfaces can be either planar or arcuate. The remaining side is exposed to retain more light-emitting area. In this embodiment, the exposed portion G1 is semi-elliptical or quasi-elliptical to maximize the area of ​​the active layer 113. The opening direction of the semi-elliptical or quasi-elliptical shape is parallel to the long side of the chip rectangle. In this embodiment, the symmetrical central axis of the exposed portion G1 is parallel to the symmetrical central axis of the long side of the chip rectangle to improve the symmetry of the bonding surface of the first metal electrode 210 and enhance the reliability of bonding with external circuitry.

[0062] In some embodiments of this example, the height of the first mesa M1 from the second mesa M2 in the vertical direction is 0.2 μm to 2 μm. The first metal electrode 210 covers the second mesa M2 from the exposed portion G1. The height h from the first mesa M1 to the upper surface of the passivation layer 300 on the second mesa M2 is 0.5 μm to 3 μm. For clarity, the height h from the first mesa M1 to the upper surface of the passivation layer 300 on the second mesa M2 is the vertical height.

[0063] In some embodiments of this example, the passivation layer 300 is partially disposed between the second metal electrode 220 and the second type semiconductor layer 112. The second metal electrode 220 extends from the second opening K2 to the upper surface of the back side of the passivation layer 300. Alternatively, the second metal electrode 220 may not be disposed between the passivation layer 300 and the second type semiconductor layer 112, i.e., the passivation layer 300 is directly disposed on the second type semiconductor layer 112. The second type semiconductor layer 112, the passivation layer 300, and the second metal electrode 220 are stacked sequentially. Or, the second metal electrode 220 may not be disposed between the passivation layer 300 and the transparent conductive layer 400, i.e., the passivation layer 300 is directly disposed on the transparent conductive layer 400. The second type semiconductor layer 112, the transparent conductive layer 400, the passivation layer 300, and the second metal electrode 220 are stacked sequentially.

[0064] In some embodiments of this example, when viewed in the vertical projection direction, the first platform M1 and the second platform M2 are combined to form a rectangle. The single-side dimension of the second platform M2 is 5μm to 35μm. Experiments have shown that a rectangle with a small size helps to increase the current density of the product, thereby improving the brightness of the product.

[0065] In this embodiment, the second mesa M2 is located on the side of the first type semiconductor layer 112 away from the active layer 113. A passivation layer 300 is disposed on the second mesa M2, covering at least from the second mesa M2 to the first mesa M1. The passivation layer 300 has a first opening K1 on the first mesa M1 and a second opening K2 on the second mesa M2. The first metal electrode 210 is electrically connected to the first type semiconductor layer 111 through the first opening K1, and the second metal electrode 220 is electrically connected to the first type semiconductor layer 112 through the second opening K2. The maximum aperture of the second opening K2 is 2μm to 20μm. A transparent conductive layer 400 is disposed between the second metal electrode 220 and the first type semiconductor layer 112.

[0066] The passivation layer 300 is made of materials including silicon dioxide, silicon nitride, aluminum oxide, or titanium oxide, and can be a single layer, double layer, or multiple layers. The passivation layer 300 primarily serves as an electrical insulator. In some cases, a DBR structure can be used to increase light reflection. The passivation layer 300 is disposed between the second metal electrode 220 and the first type semiconductor layer 112. The second metal electrode 220 extends from the second opening K2 to the upper surface of the back side of the passivation layer 300. The thickness of the passivation layer 300 is 0.1 μm to 3 μm. For example, when the thickness of the passivation layer 300 is 0.5 μm to 3 μm, the angle control of the first opening K1 becomes significantly more difficult. In this embodiment, the second metal electrode 220 is not disposed between the passivation layer 300 and the first type semiconductor layer 112, or the second metal electrode 220 is not disposed between the passivation layer 300 and the transparent conductive layer 400.

[0067] In this embodiment, the distance d1 between the first opening K1 and the mesa sidewall S1 is 0.5μm to 5μm. This distance refers to the minimum distance between the bottom of the first opening K1 and the bottom of the mesa sidewall S1. The closer the distance, the more difficult it is to fabricate the first opening K1 in the passivation layer 300. Since the second angle α2 is far away from the mesa sidewall S1, it is not restricted by the mesa sidewall S1, and the process difficulty of adjusting the angle is low. By reducing the second angle α2 on the side away from the mesa sidewall S1, the abnormal probability of the first metal electrode 210 is reduced. The first angle α1 is 1.05 times to 5 times the second angle α2. This angle mainly refers to the angle between the side of the passivation layer 300 and the horizontal plane. When the relevant multiple is less than 1.05 times, the yield improvement of the first metal electrode 210 is limited. The first angle α1 is 60° to 90°, and the second angle α2 is 15° to 75°.

[0068] The second angle α2 is designed to be as close as possible to the size of the first angle α1 to improve process consistency. The second opening K2 is relative to the horizontal plane and includes a third angle α3, which is the tilt angle formed by the passivation layer of the sidewall of the second opening K2 and the horizontal plane. The third angle α3 is smaller than the first angle α1, and α3 is (1±30%)*α2. Furthermore, α3 is (1±20%)*α2.

[0069] See Figure 5In a second embodiment of the present invention, a micro-light-emitting diode is provided. The main difference from the first embodiment is that the exposed side of the exposed portion G1 is rotated from the side closer to the short side of the chip to the side closer to the long side of the chip. In this embodiment, the first opening K1 is offset from the central axis of the long side direction and is closer to the long side of the exposed side relative to the central axis of the long side direction. Correspondingly, to ensure the reliability of bonding, the second opening K2 is offset from the central axis of the long side direction and is farther away from the long side of the exposed side relative to the central axis of the long side direction. The first opening K1 and the second opening K2 are symmetrically arranged with respect to the central axis of the short side direction of the chip rectangle.

[0070] See Figure 6 In the third embodiment of the present invention, a micro light-emitting diode is provided. The main difference from the first embodiment is that the exposed portion G1 is a non-closed step; the exposed portion G1 is composed of N side surfaces, where N is an integer not less than 2, wherein at least one side surface is a platform sidewall, and at least one side surface is exposed. Taking this embodiment as an example, the exposed portion G1 is composed of 4 side surfaces, two of which are platform sidewalls. In this embodiment, the exposed portion G1 is rectangular or a rectangular-like structure with chamfers.

[0071] In some embodiments of this example, the exposed portion G1 may also be designed as a triangle, rectangle, or trapezoid.

[0072] See Figure 7 In the fourth embodiment of the present invention, a micro light-emitting diode is provided. The main difference from the first embodiment is that in the first embodiment, when the passivation layer 300 can be a single layer or a double layer dielectric layer, α4 is 70° to 90°. However, in this embodiment, when the passivation layer 300 is designed as a DBR, in order to improve the reflection efficiency and the DBR coating quality, the angle between the platform sidewall S1 and the horizontal plane is set to the fourth angle α4. The slope is relatively gentle, and α4 is 30° to 70°. If α4 is less than 30°, it will also lead to the loss of light-emitting area. If α4 is greater than 70°, the DBR reflection effect will decrease.

[0073] See Figure 8In a fifth embodiment of the present invention, a first metal electrode 210 electrically connected to a first type semiconductor layer 111 and a second metal electrode 220 electrically connected to a first type semiconductor layer 112 are disposed on the back side of the semiconductor layer sequence 110. The first metal electrode 210 has a higher chromium content than the second metal electrode 220. The first metal electrode 210 and the second metal electrode 220 are used for bonding to an external power source, and the length of the second metal electrode 220 is 2 μm to 30 μm. In this embodiment, the first type semiconductor layer 111 is an N-type semiconductor layer, the first type semiconductor layer 112 is a P-type semiconductor layer, the first metal electrode 210 is an N-type electrode, and the second metal electrode 220 is a P-type electrode. The difference from Embodiment 1 is that the second metal electrode 220 is not plated with chromium metal in the process; for example, the chromium content of the second metal electrode 220 is zero. The spacing between the first metal electrode 210 and the second metal electrode 220 is 4 μm to 10 μm.

[0074] In this embodiment, the first metal electrode 210 extends from within the exposed portion G1 to the second mesa M2 on the first type semiconductor layer 112. Two of the four sides of the exposed portion G1 are exposed, and the other two sides are the sidewalls S1 of the exposed portion G1. The height of the sidewalls S1 of the exposed portion G1 is 0.5 μm to 2 μm.

[0075] In some embodiments of this example, the first metal electrode 210 is completely disposed within the exposed portion G1, which is a non-closed step; three of the four sides of the exposed portion G1 are exposed, and the remaining side is the sidewall S1 of the exposed portion G1. The second mesa M2 is located on the side of the first type semiconductor layer 112 away from the active layer 113. A passivation layer 300 is disposed on the second mesa M2, covering at least from the first mesa M1 to the second mesa M2. The passivation layer 300 has a first opening K1 on the first mesa M1 and a second opening K2 on the second mesa M2. The first metal electrode 210 is electrically connected to the first type semiconductor layer 111 through the first opening K1, and the second metal electrode 220 is electrically connected to the first type semiconductor layer 112 through the second opening K2. The maximum aperture of the second opening K2 is 2μm to 20μm. A transparent conductive layer 400 is disposed between the second metal electrode 220 and the first type semiconductor layer 112.

[0076] In this embodiment, the back surface of the first metal electrode 210 corresponding to the first opening K1 has a first electrode hole K11, and the back surface of the second metal electrode 220 corresponding to the second opening K2 has a second electrode hole K12. The opening area of ​​the first electrode hole K11 is smaller than the opening area of ​​the second electrode hole K12. The opening area of ​​the first electrode hole K11 accounts for 10% to 40% of the area of ​​the back surface of the first metal electrode 210, and the opening area of ​​the second electrode hole K12 accounts for 15% to 50% of the area of ​​the back surface of the second metal electrode 220. It should be noted that, due to the different shapes of the exposed portions G1, the first electrode hole K11 is caused by both the first opening K2 and the exposed portion G1, and may not have a completely closed boundary. Sufficient bonding area is required, and this does not affect the implementation of this embodiment.

[0077] See Figure 9 In the sixth embodiment of the present invention, the difference from embodiment five is that the first metal electrode 210 and the second metal electrode 220 have n metal layers, where n is an integer greater than or equal to 2. The first layer 211 of the first metal electrode 210, near the first mesa M1, contains chromium and is used to connect to the first type semiconductor layer 111. The first layer 221 of the second metal electrode 220, near the second mesa M2, does not contain chromium and is in contact with a transparent conductive layer 400. The transparent conductive layer 400 is electrically connected to the first type semiconductor layer 112. In this embodiment, the first type semiconductor layer 111 is an N-type semiconductor layer, the first type semiconductor layer 112 is a P-type semiconductor layer, the first metal electrode 210 is an N-type electrode, and the second metal electrode 220 is a P-type electrode.

[0078] The length L21 of the first layer 221 of the second metal electrode 220 is greater than 2 μm to 25 μm. The first layer 221 of the second metal electrode 220 serves as a contact layer with the first type semiconductor layer 112 or the transparent conductive layer 400. The material includes, for example, nickel, aluminum, titanium, platinum, gold, or an alloy of any combination thereof. Its adhesion to the first type semiconductor layer 112 and the transparent conductive layer 400 is lower than that of chromium; therefore, increasing the length is beneficial to improving the overall adhesion of the second metal electrode 220. In this embodiment, titanium is preferably used for the first layer 221 of the second metal electrode 220. The transparent conductive layer 400 is, for example, ITO. In this embodiment, the length of the first layer 221 of the second metal electrode 220 refers to its longest dimension.

[0079] In some embodiments of this example, the projected area of ​​the back surface of the first layer 221 of the second metal electrode 220 is 30 μm. 2 Up to 100μm 2 The area of ​​the first layer 221 of the second metal electrode 220 should be increased as much as possible to enhance electrode adhesion.

[0080] See Figure 10 In a seventh embodiment of the present invention, a display device is provided, which uses a micro-light-emitting diode (LED) as described in Embodiment 5 or Embodiment 6 for sealing. The LED C1 is sealed with epoxy resin P1 and bonded to a substrate 500. The device has a semiconductor layer sequence 110, which includes a back side and a front side. Starting from the front side, the semiconductor layer sequence 110 sequentially includes a first-type semiconductor layer 111 and a first-type semiconductor layer 112, with an active layer 113 located between them. The back side of the semiconductor layer sequence 110 has an exposed portion G1 that penetrates the first-type semiconductor layer 112. An active layer 113 exposes a first type semiconductor layer 111. The back side of the semiconductor layer sequence 110 includes a first mesa M1 within the exposed portion G1, a second mesa M2 on the first type semiconductor layer 112, and a sidewall S1 of the exposed portion G1 located between them. A first metal electrode 210 electrically connected to the first type semiconductor layer 111 and a second metal electrode 220 electrically connected to the first type semiconductor layer 112 are disposed on the back side of the semiconductor layer sequence 110. The chromium content of the first metal electrode 210 is greater than that of the second metal electrode 220, and the length of the second metal electrode 220 is 2 μm to 30 μm. Because the epoxy resin P1 has high stress, chromium leakage in the second metal electrode 220 is likely to occur. Therefore, reducing or eliminating the chromium content of the first electrode is beneficial to improving product yield and effectively improving the overall performance and yield of the display device.

[0081] In the eighth embodiment of the present invention, a display device is provided, which differs from the sixth embodiment in that it uses the micro light-emitting diode chip of the second embodiment. The first metal electrode 210 is in contact with the first type semiconductor layer 111 through the first layer 211 chromium of the first metal electrode, and the first layer 221 of the second metal electrode 220 does not contain chromium. This improves the overall performance and yield of the display device.

[0082] In the ninth embodiment of the present invention, the difference from the seventh embodiment is that a display device is provided, which adopts the micro light-emitting diode chip of the first to fourth embodiments.

[0083] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A micro light-emitting diode (LED) having a semiconductor layer sequence, the semiconductor layer sequence including a back side and a front side, the front side sequentially including a first type semiconductor layer and a second type semiconductor layer, an active layer located between the two, the back side of the semiconductor layer sequence having an exposed portion penetrating the second type semiconductor layer and the active layer, at least exposing the first type semiconductor layer, the back side of the semiconductor layer sequence including a first mesa within the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between the two, the back side of the semiconductor layer sequence being provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer, and further including a passivation layer covering the top and / or sidewall of the semiconductor layer sequence, characterized in that, A passivation layer is partially disposed on the first mesa. The passivation layer has a first opening for disposing of a first metal electrode. The first opening has a first angle α1 relative to the horizontal plane, which is close to the sidewall of the mesa and a second angle α2 away from the sidewall of the mesa. The second angle α2 is smaller than the first angle α1. 1， The first angle α1 is 1.05 to 5 times the second angle α2.

2. A micro light-emitting diode according to claim 1, characterized in that: The first angle α1 is 60° to 90°, and the second angle α2 is 15° to 75°.

3. A micro light-emitting diode according to claim 1, characterized in that: The length of the first metal electrode and / or the second metal electrode is 5 μm to 30 μm.

4. A micro light-emitting diode according to claim 1, characterized in that: The distance between the first opening and the sidewall of the platform is 0.5 μm to 5 μm.

5. A micro light-emitting diode according to claim 1, characterized in that: In the vertical direction, the height of the first platform from the second platform is 0.2 μm to 2 μm.

6. A micro light-emitting diode according to claim 1, characterized in that: The exposed portion is a non-closed step; the exposed portion consists of N sides, where N is an integer not less than 2, at least one side is a sidewall of the platform, and at least one side is exposed.

7. A micro light-emitting diode according to claim 1, characterized in that: The exposed portion can be triangular, rectangular, trapezoidal, semi-elliptical, or semi-elliptical.

8. A micro light-emitting diode according to claim 1, characterized in that: The exposed portion is a non-closed step; three of the four sides of the exposed portion are platform sidewalls, and the other side is exposed.

9. A micro light-emitting diode according to claim 1, characterized in that: The first metal electrode extends from the exposed portion to the second mesa, and the height h of the upper surface of the passivation layer from the first mesa to the second mesa is 0.5 μm to 3 μm.

10. A micro light-emitting diode according to claim 1, characterized in that: The projected area of ​​the back surface of the first metal electrode and / or the second metal electrode is 25 μm. 2 Up to 200μm 2 .

11. A micro light-emitting diode according to claim 1, characterized in that: The passivation layer covers at least from the first mesa to the second mesa. The passivation layer has a second opening on the second mesa. The first metal electrode is electrically connected to the first type semiconductor layer through the first opening. The second metal electrode is electrically connected to the second type semiconductor layer through the second opening. A transparent conductive layer is disposed between the second metal electrode and the second type semiconductor layer.

12. A micro light-emitting diode according to claim 11, characterized in that: The second opening relative to the horizontal plane includes a third angle α3, which is less than the first angle α1, where α3 is (1±30%)*α2.

13. A micro light-emitting diode according to claim 11, characterized in that: The maximum aperture of the first opening is 2μm to 20μm, and the maximum aperture of the second opening is 2μm to 20μm.

14. A micro light-emitting diode according to claim 11, characterized in that: The passivation layer is partially disposed between the second metal electrode and the second type semiconductor layer. The second metal electrode extends from the second opening to the upper surface of the back side of the passivation layer. Alternatively, the second metal electrode may not be disposed between the passivation layer and the second type semiconductor layer, or the second metal electrode may not be disposed between the passivation layer and the transparent conductive layer.

15. A micro light-emitting diode according to claim 1, characterized in that: The thickness of the passivation layer is 0.1 μm to 3 μm.

16. A micro light-emitting diode according to claim 1, characterized in that: The passivation layer is a multi-layered distributed Bragg reflector.

17. A micro light-emitting diode according to claim 1, characterized in that: The first metal electrode is an N-type electrode, and the second metal electrode is a P-type electrode.

18. A micro light-emitting diode according to claim 1, characterized in that: The angle between the side wall of the tabletop and the horizontal plane is the fourth angle α4, where α4 is 30° to 70° or 70° to 90°.

19. A display device comprising a plurality of microlight-emitting diodes (LEDs) and a substrate, wherein the LEDs are disposed on the substrate and have a semiconductor layer sequence, the semiconductor layer sequence comprising a back side and a front side, wherein, starting from the front side, a first type semiconductor layer and a second type semiconductor layer are sequentially included, an active layer is located between the two, the back side of the semiconductor layer sequence has an exposed portion penetrating the second type semiconductor layer and the active layer, exposing the first type semiconductor layer, the back side of the semiconductor layer sequence including a first mesa within the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between the two, the back side of the semiconductor layer sequence being provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer, and further comprising a passivation layer covering the semiconductor layer sequence and / or the sidewall, characterized in that, The passivation layer on the first platform has a first opening for setting a first metal electrode. The first opening has a first angle α1 near the sidewall of the platform and a second angle α2 away from the sidewall of the platform relative to the horizontal plane. The second angle α2 is smaller than the first angle α1. The first angle α1 is 1.05 to 5 times the second angle α2.

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