Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a light emitting element layer disposed on a substrate, the light emitting element layer including a plurality of light emitting elements, and an encapsulation layer including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the organic encapsulation layer, the second inorganic encapsulation layer includes a first inorganic layer, a second inorganic layer, and a third inorganic layer disposed on the organic encapsulation layer, a thickness of the second inorganic layer is greater than a thickness of the third inorganic layer, a thickness of the third inorganic layer is greater than a thickness of the first inorganic layer, and a refractive index of the second inorganic layer is about 1.9 or greater.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0139116 filed in the Korean Intellectual Property Office on October 18, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among these flat panel display devices, the light emitting display device includes a light emitting element that enables each pixel of the display panel to emit light by itself. Therefore, the light emitting display device can display an image without a backlight that provides light to the display panel.

[0005] The display device may further include pixels that emit light, scan lines, data lines, and power lines for driving the pixels, a scan driver that outputs scan signals to the scan lines, and a display driver that outputs data voltages to the data lines. Summary of the invention

[0006] Aspects of the present disclosure provide a display device including a thin encapsulation layer and a method of manufacturing the display device.

[0007] However, aspects of the present disclosure may not be limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0008] According to an embodiment of the present disclosure, a display device may include a light-emitting element layer and an encapsulation layer, the light-emitting element layer is arranged on a substrate and includes a plurality of light-emitting elements, the encapsulation layer includes a first inorganic encapsulation layer arranged on the light-emitting element layer, an organic encapsulation layer arranged on the first inorganic encapsulation layer, and a second inorganic encapsulation layer arranged on the organic encapsulation layer, wherein the second inorganic encapsulation layer may include a first inorganic layer arranged on the organic encapsulation layer, a second inorganic layer arranged on the first inorganic layer, and a third inorganic layer arranged on the second inorganic layer, the thickness of the second inorganic layer may be greater than the thickness of the third inorganic layer, the thickness of the third inorganic layer may be greater than the thickness of the first inorganic layer, and the refractive index of the second inorganic layer may be about 1.9 or greater.

[0009] The refractive index difference between the first inorganic layer and the second inorganic layer may be less than or equal to about 0.2, the refractive index difference between the second inorganic layer and the third inorganic layer may be less than or equal to about 0.2, and the refractive index difference between the third inorganic layer and the first inorganic layer may be less than or equal to about 0.2.

[0010] Each of the first inorganic layer, the second inorganic layer, and the third inorganic layer may include silicon nitride (SiN x ).

[0011] The film density of the first inorganic layer may be greater than the film density of the second inorganic layer, and the film density of the third inorganic layer may be greater than the film density of the second inorganic layer.

[0012] The thickness of the second inorganic layer may be greater than the sum of the thickness of the first inorganic layer and the thickness of the third inorganic layer.

[0013] The sum of the thickness of the first inorganic layer, the thickness of the second inorganic layer, and the thickness of the third inorganic layer may be about 210 nm or less.

[0014] The first inorganic layer may have a thickness in a range of about 0.1 nm to about 1.5 nm, the second inorganic layer may have a thickness in a range of about 50 nm to about 150 nm, and the third inorganic layer may have a thickness in a range of about 50 nm to about 100 nm.

[0015] The water vapor transmission rate (WVTR) of the second inorganic encapsulation layer may be about 9*10 -4 g / m 2 daily or less.

[0016] The refractive index of each of the first inorganic layer, the second inorganic layer, and the third inorganic layer may be in the range of about 1.90 to about 2.10.

[0017] The refractive index of the first inorganic layer, the refractive index of the second inorganic layer, and the refractive index of the third inorganic layer may be the same.

[0018] The display device may also include a circuit layer, which is arranged between the substrate and the light-emitting element layer, and includes a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer sequentially arranged on the substrate.

[0019] According to an embodiment of the present disclosure, a display device may include a light-emitting element layer and an encapsulation layer, the light-emitting element layer is arranged on a substrate and includes a plurality of light-emitting elements, the encapsulation layer includes a first inorganic encapsulation layer arranged on the light-emitting element layer, an organic encapsulation layer arranged on the first inorganic encapsulation layer, and a second inorganic encapsulation layer arranged on the organic encapsulation layer, wherein the second inorganic encapsulation layer includes a first inorganic layer arranged on the organic encapsulation layer, a second inorganic layer arranged on the first inorganic layer, and a third inorganic layer arranged on the second inorganic layer, the film density of the first inorganic layer may be greater than the film density of the second inorganic layer, and the refractive index of the first inorganic layer may be equal to or less than the refractive index of the second inorganic layer.

[0020] The thickness of the first inorganic layer may be in the range of about 0.1 nm to about 1.5 nm.

[0021] The refractive index difference between the first inorganic layer and the second inorganic layer may be less than or equal to about 0.2, the refractive index difference between the second inorganic layer and the third inorganic layer may be less than or equal to about 0.2, and the refractive index difference between the third inorganic layer and the first inorganic layer may be less than or equal to about 0.2.

[0022] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: forming a light-emitting element layer on a substrate, the light-emitting layer may include a plurality of light-emitting elements; forming a first inorganic encapsulation layer on the light-emitting element layer; forming an organic encapsulation layer on the first inorganic encapsulation layer; and forming a second inorganic encapsulation layer on the organic encapsulation layer, wherein forming the second inorganic encapsulation layer may include forming the first inorganic layer on the organic encapsulation layer at a first deposition rate, forming the second inorganic layer on the first inorganic layer at a second deposition rate, and forming the third inorganic layer on the second inorganic layer at a third deposition rate, and the second deposition rate may be greater than the first deposition rate and the third deposition rate.

[0023] The second deposition rate may be about 30 nm / minute or more, and the first deposition rate and the third deposition rate may be about 30 nm / minute or less.

[0024] Forming the first inorganic layer, forming the second inorganic layer, and forming the third inorganic layer may be performed in the same chamber.

[0025] The same precursor may be used to form the first inorganic layer, to form the second inorganic layer, and to form the third inorganic layer.

[0026] The precursor may include at least one of cyclosilazane, trisilylamine, bis(diethylamino)silane, bis(tert-butylamino)silane, tris(dimethylamino)silane, tris(isopropylamino)silane, tetrakis(dimethylamino)silane, tri(isopropyl)cyclotrisilazane and tetramethyldisilazane.

[0027] The forming of the first inorganic layer may be performed by a plasma enhanced atomic layer deposition (PEALD) process or a plasma enhanced chemical vapor deposition (PECVD) process, and the forming of the second inorganic layer and the forming of the third inorganic layer may be performed by a PECVD process.

[0028] The display device according to the embodiment may have an inorganic encapsulation layer which may be thin but may have excellent encapsulation characteristics.

[0029] Effects according to the embodiments may not be limited to the above-exemplified contents, and further various effects may be included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a perspective view of a display device according to an embodiment;

[0032] Figure 2 yes Figure 1 A plan view of a display device;

[0033] Figure 3 is along Figure 2 A schematic cross-sectional view taken along line AA';

[0034] Figure 4 is a schematic cross-sectional view of a sub-pixel of a display device according to an embodiment;

[0035] Figure 5 is a schematic diagram of an encapsulation layer of a display device according to an embodiment;

[0036] Figure 6 yes Figure 5 an enlarged view of part B;

[0037] Figure 7 is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0038] Figure 8 It is shown in detail that Figure 7 A flow chart of a process for a second inorganic encapsulation layer in;

[0039] Figures 9 to 14 are views sequentially showing a process of manufacturing a display device according to an embodiment;

[0040] Fig.15 is a perspective view of a head mounted display device according to an embodiment;

[0041] Fig.16 yes Fig.15An exploded perspective view of an example of a head mounted display device; and

[0042] Fig.17 is a perspective view of a head mounted display device according to an embodiment. DETAILED DESCRIPTION

[0043] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the device or method disclosed herein. However, it is obvious that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor do they have to limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0044] Unless otherwise specified, the embodiments shown should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0045] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiment can be implemented in different ways, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals and / or reference symbols represent the same elements.

[0046] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical and / or fluid connection with or without an intervening element. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of a rectangular coordinate system (such as an x-axis, a y-axis and a z-axis), and may be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0047] For the purpose of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or a combination of A and B. In addition, "at least one of A, B, and C" and "at least one selected from the group consisting of A, B, and C" may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0049] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall") or the like may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the term "below" is capable of including both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0050] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the terms "comprises", "comprising", "includes" and / or "including" are used in this specification, the existence of the stated features, wholes, steps, operations, elements, parts and / or clusters thereof is specified, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or clusters thereof is not excluded. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as terms of approximation rather than terms of degree, and are thus used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0051] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular illustrated regions, but rather include deviations in shape resulting from, for example, manufacturing. In this manner, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus are not necessarily intended to be limiting.

[0052] As is customary in the art, some embodiments are described in terms of functional blocks, units and / or modules and are shown in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections and the like that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits). Moreover, without departing from the scope of the inventive concept, each block, unit and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules.

[0053] Unless otherwise defined or implied herein, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0054] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0055] Figure 1 is a perspective view of a display device 10 according to an embodiment.

[0056] Reference Figure 1 The display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs) and in various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices.

[0057] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro or nano light-emitting display device using a micro or nano light-emitting diode. An embodiment in which the display device 10 is an organic light-emitting display device will be described below, but the type of the display device 10 may not be limited thereto.

[0058] In an embodiment, the display device 10 may be formed to be substantially flat. For example, the display device 10 may be formed to be substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a thickness (or height) in the third direction DR3. In an embodiment, the display device 10 may include a bent portion in at least a portion (such as an edge region). The display device 10 may be formed to be flexible so that it can be bent, folded, or curled.

[0059] In an embodiment, the first direction DR1 may be a longitudinal direction, a column direction, or a vertical direction of an image display surface of the display device 10, and the second direction DR2 may be a direction intersecting the first direction DR1, for example, a transverse direction, a row direction, or a horizontal direction. The third direction DR3 may be a thickness direction or a height direction of the display device 10.

[0060] The display device 10 may include a display panel 100 , a driver 200 , and a circuit board 300 .

[0061] The display panel 100 may include a main area MA including a display area DA at which an image is displayed, and a sub area SBA positioned on one side of the main area MA.

[0062] The main area MA may include a display area DA and a non-display area NA around the display area DA. The display area DA may be located in the center of the main area MA and may occupy most of the main area MA. The non-display area NA may be located at an edge of the main area MA and may contact the sub-area SBA.

[0063] The display area DA may be an area where pixels may be arranged and an image may be displayed through the pixels. In an embodiment, a sensing pattern (e.g., a touch electrode) for detecting a touch input or the like may also be provided in the display area DA, and the display area DA may include a sensing area where a touch input may be detected through the sensing pattern.

[0064] In an embodiment, the display area DA may be shaped like a substantially rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2. Each corner where the long sides and short sides of the display area DA intersect may be rounded or right angled. The shape of the display area DA may vary according to embodiments. For example, the display area DA may also have a polygonal shape, a circular shape, or an elliptical shape other than a quadrilateral shape.

[0065] The non-display area NA may be positioned directly around the display area DA. The non-display area NA may surround the display area DA. An embedded circuit may be disposed in the non-display area NA. For example, an embedded circuit (such as a scan driving circuit) may be disposed in the non-display area NA on one side (e.g., the left side or the right side) or both sides of the display area DA.

[0066] The sub-region SBA may be positioned on one side of the main region MA. For example, the sub-region SBA may be a region protruding from one side of the main region MA in the first direction DR1. For example, the sub-region SBA may protrude from the lower end of the main region MA in the first direction DR1. In an embodiment, the sub-region SBA may be narrower than the main region MA. For example, the sub-region SBA may be narrower than the main region MA in the second direction DR2.

[0067] Lines and pads may be provided in the sub-area SBA. For example, lines and pads electrically connected to pixels and / or embedded circuits positioned in the main area MA and the driver 200 and / or circuit board 300 positioned in the sub-area SBA may be provided in the sub-area SBA. In the description of the embodiments, the term "connection" may mean electrical connection and / or physical connection.

[0068] In an implementation, the driver 200 (eg, a display driving circuit) may be mounted in the sub-area SBA. The circuit board 300 may be disposed on a portion of the sub-area SBA.

[0069] The driver 200 may include a data driving circuit for driving pixels. In an embodiment, the driver 200 may be formed as an integrated circuit (IC) and disposed in the sub-area SBA. In an embodiment, the driver 200 may be disposed on the circuit board 300 in the sub-area SBA, or may be disposed on another circuit board electrically connected to the display panel 100 through the circuit board 300.

[0070] The circuit board 300 may be disposed on a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad positioned in a portion (e.g., a lower edge) of the sub-area SBA, and may supply or transmit a power supply voltage and a driving signal for driving the display panel 100 to the display panel 100. For example, the circuit board 300 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be, but is not limited to, a flexible printed circuit board (FPCB), a printed circuit board, or a flexible film such as a chip on film (COF).

[0071] Figure 2 yes Figure 1 FIG. 1 is a plan view of a display device 10 . Figure 3 is along Figure 2 Schematic cross-sectional view taken along line AA'.

[0072] Figure 1 shows a state in which the display device 10 is unfolded without being bent, and Figure 2 and Figure 3 A state in which the display device 10 is bent in the sub-area SBA is shown. Figure 1 shows a state in which the sub-area SBA is expanded to be placed side by side with the main area MA, and Figure 2 and Figure 3 A state in which a part of the sub-area SBA is bent is shown.

[0073] Reference Figure 2 and Figure 3 , the display panel 100 may include a substrate 110 including a main area MA and a sub-area SBA, and a circuit layer 120, a light emitting element layer 130, an encapsulation layer 140, and a color filter layer 150 sequentially disposed on the substrate 110. The circuit layer 120 may be positioned on the substrate 110 in the main area MA and the sub-area SBA. The light emitting element layer 130, the encapsulation layer 140, and the color filter layer 150 may be positioned on a portion of the substrate 110 and the circuit layer 120. For example, the light emitting element layer 130, the encapsulation layer 140, and the color filter layer 150 may be positioned in the main area MA.

[0074] In an embodiment, the display device 10 may further include additional elements disposed on the display panel 100. For example, the display device 10 may further include at least one of a sensor layer (e.g., a touch sensor layer), a polarizing layer, and a protective layer (e.g., a window) disposed on the encapsulation layer 140. Each of the sensor layer, the polarizing layer, and / or the protective layer may be integrally manufactured with the display panel 100, or may be manufactured separately from the display panel 100 and then attached to the display panel 100 by an adhesive layer or the like.

[0075] The main area MA may include a display area DA and a non-display area NA. The non-display area NA may be positioned around the display area DA. For example, the non-display area NA may be an edge area of ​​the main area MA positioned outside the display area DA.

[0076] The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide or other insulating materials. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled. As another example, the substrate 110 may include an insulating material such as glass.

[0077] The circuit layer 120 may include pixel circuits and lines. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors and capacitors) constituting the pixel circuit of each pixel and lines electrically connected to the pixels. In an embodiment, the circuit layer 120 may also include circuit elements constituting embedded circuits (such as scan drive circuits) and lines electrically connected to the embedded circuits.

[0078] The light emitting element layer 130 may include a light emitting element disposed in an emission region of a pixel. For example, each of a plurality of pixels may include at least one light emitting element and a pixel circuit electrically connected to the light emitting element. Each of a plurality of pixels may be positioned in a pixel region including an emission region where a light emitting element may be disposed and a pixel circuit region where a pixel circuit may be disposed. The emission region and the pixel circuit region of each pixel may overlap each other, but the present disclosure may not be limited thereto.

[0079] In the description of the embodiment, the circuit layer 120 and the light emitting element layer 130 may be described as being separated from each other. However, the embodiment may not be limited thereto. For example, the circuit layer 120 and the light emitting element layer 130 may also be integrated.

[0080] The encapsulation layer 140 may cover the light emitting element layer 130 and extend to the non-display area NA to contact the circuit layer 120. In an embodiment, the encapsulation layer 140 may have a multi-layer structure including at least two inorganic encapsulation layers overlapping each other and at least one organic encapsulation layer disposed between the inorganic encapsulation layers.

[0081] In an embodiment, the display panel 100 may be bent in the bending area BA. The bending area BA may be a portion of the sub area SBA and may be spaced apart from the main area MA.

[0082] The substrate 110 and the circuit layer 120 may be bent in the bending area BA corresponding to a portion of the sub-area SBA. Therefore, a bezel area perceived by a user as the non-display area NA can be reduced or minimized.

[0083] Figure 4 is a schematic cross-sectional view of a sub-pixel of the display device 10 according to the embodiment. Figure 4 1 is a schematic cross-sectional view of a portion of a region corresponding to a sub-pixel in the display area DA.

[0084] Reference Figure 4 , the display panel 100 may include a substrate 110 and a circuit layer 120, a light emitting element layer 130, an encapsulation layer 140, and a color filter layer 150 disposed on the substrate 110. The circuit layer 120, the light emitting element layer 130, the encapsulation layer 140, and the color filter layer 150 may be sequentially disposed or stacked on the substrate 110 in the third direction DR3.

[0085] The substrate 110 may be made of a flexible material that can be bent, folded, or rolled. The substrate 110 may be made of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide.

[0086] The circuit layer 120 may include a pixel circuit PXC and lines. For example, the circuit layer 120 may include circuit elements (e.g., a pixel transistor T and a capacitor Cst) constituting the pixel circuit PXC of each sub-pixel and lines (e.g., various power lines and signal lines including a power line, a scan line, an emission control line, and a data line) electrically connected to the sub-pixel.

[0087] Figure 4 The first thin film transistor TFT1 (also referred to as "first pixel transistor"), the second thin film transistor TFT2 (also referred to as "second pixel transistor"), and the capacitor Cst included in the pixel circuit PXC of each sub-pixel are shown among the elements that can be provided in the circuit layer 120. The first thin film transistor TFT1 may represent a first type transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among the pixel transistors T constituting each pixel circuit PXC. Figure 4 , a transistor electrically connected to the light emitting element EL through at least one connection electrode (e.g., the first connection electrode CNE1 and the second connection electrode CNE2) among the first type transistors may be shown as an example of the first thin film transistor TFT1. The second thin film transistor TFT2 may represent a second type transistor (e.g., an N-type transistor) including a second semiconductor material (e.g., an oxide semiconductor) among the pixel transistors T.

[0088] The cross-section of the subpixel may vary according to the type and / or structure of each subpixel and the display panel 100 including the subpixel. For example, the positions and formation order of the first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may vary according to the embodiment.

[0089] The circuit layer 120 may include a semiconductor layer, a conductive layer for forming circuit elements and lines, and an insulating layer disposed between the conductive layer and the semiconductor layer and / or around the conductive layer and the semiconductor layer. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polysilicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating layer), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 124 (e.g., a second gate insulating layer), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating layer), a third conductive layer CDL3 (e.g., a third gate conductive layer), a fifth insulating layer 127 (e.g., a second interlayer insulating layer), a fourth conductive layer CDL4 (e.g., a first source-drain conductive layer), and a sixth insulating layer 128 (e.g., a first via layer or a first planarization layer) sequentially disposed on the substrate 110 in the third direction DR3. In an embodiment, the circuit layer 120 may further include a fifth conductive layer CDL5 (e.g., a second source-drain conductive layer) and a seventh insulating layer 129 (e.g., a second via layer or a second planarization layer) sequentially disposed on the sixth insulating layer 128. In an embodiment, the circuit layer 120 may further include a bottom conductive layer BCDL disposed between the substrate 110 and the first semiconductor layer SCL1, a barrier layer 121 disposed between the substrate 110 and the bottom conductive layer BCDL, and a buffer layer 122 disposed between the bottom conductive layer BCDL and the first semiconductor layer SCL1.

[0090] The barrier layer 121 may be disposed on the substrate 110. The barrier layer 121 may protect the elements disposed in the circuit layer 120 and the light emitting element layer 130 from moisture introduced through the substrate 110 which may be easily permeated by moisture. The barrier layer 121 may include at least one inorganic layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, other inorganic insulating materials, or a combination thereof). The material of the barrier layer 121 may vary according to the embodiment.

[0091] The bottom conductive layer BCDL may be disposed on the barrier layer 121. The bottom conductive layer BCDL may include a bottom metal layer BML overlapping an active layer (eg, a first active layer ACT1 and / or a second active layer ACT2) of at least one pixel transistor T and / or at least one wire (or a portion of the at least one wire). Figure 4In the embodiment, the bottom metal layer BML may overlap only the first active layer ACT1 of the first thin film transistor TFT1 and the first capacitor electrode CAE1 and the second capacitor electrode CAE2 of the capacitor Cst, but the present disclosure may not be limited thereto. For example, the bottom metal layer BML may also be patterned into an appropriate size and / or shape as needed, and may be provided in a portion of the pixel circuit PXC, or may be provided in the entire pixel circuit PXC. In an embodiment, the bottom metal layer BML may be used as a light blocking pattern and / or a back gate electrode of at least one pixel transistor T.

[0092] The buffer layer 122 may be disposed on the bottom conductive layer BCDL to cover the bottom conductive layer BCDL. The buffer layer 122 may include at least one inorganic layer including an inorganic insulating material.

[0093] The first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may be disposed on the buffer layer 122. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second thin film transistor TFT2 may include a second active layer ACT2 and a plurality of second gate electrodes G2. In an embodiment, the second thin film transistor TFT2 may include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0094] The first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1.

[0095] The first active layer ACT1 may be provided in the first semiconductor layer SCL1, and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a first channel region CH1, a first source region S1, and a first drain region D1. The first channel region CH1 may overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 may be disposed on one side of the first channel region CH1, and the first drain region D1 may be disposed on the other side of the first channel region CH1. The first source region S1 and the first drain region D1 may be regions formed to have conductivity by doping a semiconductor used to form the first active layer ACT1 with ions or impurities. In an embodiment, the first source region S1 may be a source electrode of the first thin film transistor TFT1. In an embodiment, the first thin film transistor TFT1 may include a separate source electrode electrically connected to the first source region S1. In an embodiment, the first drain region D1 may be a drain electrode of the first thin film transistor TFT1. In an embodiment, the first thin film transistor TFT1 may include a separate drain electrode electrically connected to the first drain region D1.

[0096] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1. The first insulating layer 123 may cover the first semiconductor layer SCL1.

[0097] The first conductive layer CDL1 may be disposed on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may overlap a portion of the first active layer ACT1 (e.g., the first channel region CH1). In an embodiment, the first conductive layer CDL1 may further include at least one line (or a portion of the at least one line), a metal pattern (e.g., a bridge pattern), and / or a capacitor electrode. For example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0098] In an embodiment, the first capacitor electrode CAE1 may be integrally formed with a gate electrode of at least one first thin film transistor TFT1. For example, the first capacitor electrode CAE1 and the gate electrode of the first thin film transistor TFT1 may be formed as one conductive pattern, and the second capacitor electrode CAE2 may be disposed to overlap the conductive pattern.

[0099] The second insulating layer 124 may be disposed on the first conductive layer CDL1. The second insulating layer 124 may cover the first conductive layer CDL1.

[0100] The second conductive layer CDL2 may be disposed on the second insulating layer 124. The second conductive layer CDL2 may include one electrode of the capacitor Cst, for example, the second capacitor electrode CAE2. In an embodiment, the second conductive layer CDL2 may further include at least one electrode, at least one line (or a portion of the at least one line) and / or a metal pattern (for example, a bridge pattern). For example, the second conductive layer CDL2 may further include a back gate electrode BG electrically connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0101] The third insulating layer 125 may be disposed on the second conductive layer CDL2. The third insulating layer 125 may cover the second conductive layer CDL2.

[0102] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2.

[0103] The second active layer ACT2 may be provided in the second semiconductor layer SCL2 and may include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0104] The second active layer ACT2 may include a second channel region CH2, a second source region S2, and a second drain region D2. The second channel region CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 may be disposed on one side of the second channel region CH2, and the second drain region D2 may be disposed on the other side of the second channel region CH2. The second source region S2 and the second drain region D2 may be regions formed to have conductivity by doping a semiconductor used to form the second active layer ACT2 with ions or impurities. In an embodiment, the second source region S2 may be a source electrode of the second thin film transistor TFT2. In an embodiment, the second thin film transistor TFT2 may include a separate source electrode electrically connected to the second source region S2. In an embodiment, the second drain region D2 may be a drain electrode of the second thin film transistor TFT2. In an embodiment, the second thin film transistor TFT2 may include a separate drain electrode electrically connected to the second drain region D2.

[0105] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2. The fourth insulating layer 126 may cover the second semiconductor layer SCL2.

[0106] The third conductive layer CDL3 may be disposed on the fourth insulating layer 126. The third conductive layer CDL3 may include a plurality of second gate electrodes G2 of the second thin film transistor TFT2. One of the plurality of second gate electrodes G2 may overlap a portion of the second active layer ACT2 (e.g., the second channel region CH2). In an embodiment, the third conductive layer CDL3 may further include at least one line (or a portion of the at least one line), a metal pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0107] In an embodiment, each of the electrodes, conductive patterns and / or wires provided in the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), other metals, alloys thereof and other conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and / or wires provided in the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include molybdenum (Mo) or other metal materials. At least two of the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include the same material or different materials. The material of each of the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may not be limited and may be changed according to the embodiment.

[0108] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3. The fifth insulating layer 127 may cover the third conductive layer CDL3.

[0109] In an embodiment, each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be an inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, other inorganic insulating materials, or a combination thereof), and may have a single-layer or multi-layer structure. At least two of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may include the same material or different materials. The material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may vary according to the embodiment.

[0110] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first thin film transistor TFT1), a first bridge electrode BE1 (or a source electrode of the second thin film transistor TFT2), and a second bridge electrode BE2 (or a drain electrode of the second thin film transistor TFT2). The first connection electrode CNE1 may be provided in the fourth conductive layer CDL4 and electrically connected to the first drain region D1 of the first active layer ACT1 through a first contact hole CT1 penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first bridge electrode BE1 may be provided in the fourth conductive layer CDL4 and electrically connected to the second source region S2 of the second active layer ACT2 through a second contact hole CT2 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. The second bridge electrode BE2 may be electrically connected to the second drain region D2 of the second active layer ACT2 through a third contact hole CT3 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. In an embodiment, the fourth conductive layer CDL4 may further include at least one line (or a portion of the at least one line) and / or a metal pattern (e.g., a bridge pattern). For example, the fourth conductive layer CDL4 may include a portion of a power line (e.g., a first pixel power line and / or a second pixel power line) provided inside and / or outside the display area DA.

[0111] The sixth insulating layer 128 may be disposed on the fourth conductive layer CDL4. The sixth insulating layer 128 may cover the fourth conductive layer CDL4.

[0112] The fifth conductive layer CDL5 may be disposed on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 may be provided in the fifth conductive layer CDL5 and electrically connected to the first connection electrode CNE1 through a fourth contact hole CT4 (or a first via hole) penetrating the sixth insulating layer 128. In an embodiment, the fifth conductive layer CDL5 may further include at least one line (or a portion of the at least one line) and / or a metal pattern (e.g., a bridge pattern). For example, the fifth conductive layer CDL5 may include a portion of a power line (e.g., a first pixel power line and / or a second pixel power line) provided inside and / or outside the display area DA.

[0113] In an embodiment, each of the electrodes, conductive patterns and / or wires provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), other metals, alloys thereof, and other conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and / or wires provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may have a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include the same material or different materials. The material of each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may vary depending on the embodiment.

[0114] The seventh insulating layer 129 may be disposed on the fifth conductive layer CDL5. The seventh insulating layer 129 may cover the fifth conductive layer CDL5.

[0115] In an embodiment, each of the sixth insulating layer 128 and the seventh insulating layer 129 may be an organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, other organic insulating materials, or a combination thereof) to planarize the circuit layer 120, and may have a single-layer or multi-layer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same material or different materials. The material of each of the sixth insulating layer 128 and the seventh insulating layer 129 may vary according to the embodiment.

[0116] The light emitting element layer 130 may include a pixel defining layer 131 defining an emission area EA of a pixel and a plurality of light emitting elements EL respectively positioned in the plurality of emission areas EA. In an embodiment, the light emitting element layer 130 may further include a spacer 132 disposed on a portion of the pixel defining layer 131 .

[0117] Each light emitting element EL may include a first electrode ET1 (e.g., an anode) electrically connected to at least one pixel transistor T (e.g., a first thin film transistor TFT1) included in a corresponding sub-pixel through a first connection electrode CNE1 and / or a second connection electrode CNE2, a light emitting layer EML sequentially disposed on the first electrode ET1, and a second electrode ET2 (e.g., a cathode). In an embodiment, each light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) disposed between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) disposed between the light emitting layer EML and the second electrode ET2.

[0118] The first electrode ET1 of each light emitting element EL may include a conductive material and may be disposed on the circuit layer 120. For example, the first electrode ET1 may be disposed on the seventh insulating layer 129 in each emission area EA. The first electrode ET1 may be electrically connected to the second connection electrode CNE2 through a fifth contact hole CT5 (or a second via hole) penetrating the seventh insulating layer 129.

[0119] In an embodiment, the first electrode ET1 may include a metal material having high reflectivity or a transparent conductive metal oxide. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or a combination thereof, or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni) or a combination thereof (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO).

[0120] The light-emitting layer EML of each light-emitting element EL may include a polymer material or a low-molecular material. In an embodiment, a light-emitting layer EML may be provided for each sub-pixel, and the light-emitting layer EML of each sub-pixel may emit visible light of a color corresponding to the sub-pixel. In an embodiment, the light-emitting layer EML may be a common layer shared by sub-pixels of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light to be emitted from each sub-pixel may be provided in the emission area EA of at least some of the plurality of sub-pixels.

[0121] The second electrode ET2 of each light emitting element EL may include a conductive material and may be electrically connected to a second pixel power supply line. In an embodiment, the second electrode ET2 may be a common layer formed throughout the entire display area DA to cover the plurality of light emitting layers EML and the pixel defining layer 131. In an embodiment, the second electrode ET2 may be made of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO), or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). In the case where the second electrode ET2 is made of a semi-transmissive conductive material, it can be expected that the light output efficiency can be improved by the microcavity effect.

[0122] The pixel defining layer 131 may have a plurality of openings corresponding to the plurality of emission regions EA, respectively, and may surround the plurality of emission regions EA. For example, the pixel defining layer 131 may be formed to cover the edge of the first electrode ET1 of each light emitting element EL, and may include an opening exposing another portion of the first electrode ET1. The region where the exposed first electrode ET1 and the light emitting layer EML overlap (or the region including them) may be defined as the emission region EA of each pixel or each sub-pixel.

[0123] In an embodiment, the pixel defining layer 131 may include at least one organic layer including an organic insulating material. For example, the pixel defining layer 131 may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene (BCB), other organic insulating materials, or a combination thereof.

[0124] The spacer 132 may be disposed on a portion of the pixel defining layer 131. The spacer 132 may include at least one organic layer including an organic insulating material. The spacer 132 may include the same material as that of the pixel defining layer 131, or may include a material different from that of the pixel defining layer 131. In an embodiment, the pixel defining layer 131 and the spacer 132 may be sequentially formed by corresponding mask processes. In an embodiment, the pixel defining layer 131 and the spacer 132 may be synchronously formed using a halftone mask. The pixel defining layer 131 and the spacer 132 may be regarded as an integrated insulating layer. The organic insulating material forming the spacer 132 may not be particularly limited and may be changed according to the embodiment.

[0125] The encapsulation layer 140 may be disposed on the light emitting element layer 130 in the main area MA. For example, the encapsulation layer 140 may be disposed in the display area DA and the non-display area NA to cover the light emitting element layer 130. The encapsulation layer 140 may block oxygen or moisture from penetrating into the light emitting element layer 130, and reduce electrical or physical impact on the circuit layer 120 and the light emitting element layer 130.

[0126] In an embodiment, the encapsulation layer 140 may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143 sequentially disposed on the light emitting element layer 130. The first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 may include an inorganic insulating material, and the organic encapsulation layer 142 may include an organic material. Examples of inorganic insulating materials included in each of the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. Examples of organic materials included in the organic encapsulation layer 142 may include, but are not limited to, polymers such as acrylic resins, epoxy resins, polyimides, polyethylene, or combinations thereof.

[0127] Although an embodiment of the encapsulation layer 140 in which the organic encapsulation layer 142 may be disposed between two different inorganic encapsulation layers (i.e., the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143) has been described, the present disclosure may not be limited thereto. In some embodiments, the organic encapsulation layer 142 may be omitted, and the encapsulation layer 140 may have a structure in which one or more inorganic encapsulation layers may be stacked on each other.

[0128] Figure 5 is a schematic diagram of an encapsulation layer 140 of a display device 10 according to an embodiment. Figure 6 yes Figure 5 An enlarged view of part B.

[0129] Reference Figure 5 and Figure 6 In the display device 10, the second inorganic encapsulation layer 143 of the encapsulation layer 140 may have a structure in which a plurality of inorganic insulating layers may be stacked on each other. Although the second inorganic encapsulation layer 143 has a structure in which a plurality of layers may be stacked on each other, it may be relatively thin. In the display device 10, the second inorganic encapsulation layer 143 including a plurality of inorganic insulating layers may have a thin thickness and is used to encapsulate the display panel 100.

[0130] The second inorganic encapsulation layer 143 may include a first inorganic layer IL1 disposed on the organic encapsulation layer 142, a second inorganic layer IL2 disposed on the first inorganic layer IL1, and a third inorganic layer IL3 disposed on the second inorganic layer IL2. A lower surface of the first inorganic layer IL1 may contact the organic encapsulation layer 142, and an upper surface of the first inorganic layer IL1 may contact the second inorganic layer IL2. A lower surface of the second inorganic layer IL2 may contact the first inorganic layer IL1, and an upper surface of the second inorganic layer IL2 may contact the third inorganic layer IL3. A lower surface of the third inorganic layer IL3 may contact the second inorganic layer IL2. An upper surface of the third inorganic layer IL3 may contact the sensor layer or the color filter layer 150.

[0131] According to an embodiment, the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may include the same material, but may differ in some physical properties or basic characteristics. The first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may be formed under different manufacturing processes or conditions, and therefore, some of their physical properties may be different from each other.

[0132] For example, the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may each include silicon nitride (SiN x). The first inorganic layer IL1 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process or a plasma enhanced atomic layer deposition (PEALD) process, and the second inorganic layer IL2 and the third inorganic layer IL3 may be formed by a PECVD process. The PECVD process conditions (e.g., deposition rates) of the second inorganic layer IL2 and the third inorganic layer IL3 may be different from each other.

[0133] The first inorganic layer IL1 may have a relatively high density and a small thickness t1. The film density of the first inorganic layer IL1 may be greater than the film density of the second inorganic layer IL2. The thickness t1 of the first inorganic layer IL1 may be significantly smaller than the thickness t2 of the second inorganic layer IL2 and the thickness t3 of the third inorganic layer IL3. In an embodiment, the thickness t1 of the first inorganic layer IL1 may be in the range of about 0.1 nm to about 1.5 nm. Within the above range, a high-density first inorganic layer IL1 can be formed within a short tact time.

[0134] The second inorganic layer IL2 may have a relatively low density and a large thickness t2. The film density of the second inorganic layer IL2 may be less than the film density of the first inorganic layer IL1 and the film density of the third inorganic layer IL3. The thickness t2 of the second inorganic layer IL2 may be significantly greater than the thickness t1 of the first inorganic layer IL1 and the thickness t3 of the third inorganic layer IL3. The thickness t2 of the second inorganic layer IL2 may be greater than the sum of the thickness t1 of the first inorganic layer IL1 and the thickness t3 of the third inorganic layer IL3. In an embodiment, the thickness t2 of the second inorganic layer IL2 may be in the range of about 50nm to about 150nm. In an embodiment, the thickness t2 of the second inorganic layer IL2 may be in the range of about 100nm to about 150nm. Within the above range, the low-density second inorganic layer IL2 can have an excellent planarization function.

[0135] The film density of the third inorganic layer IL3 may be greater than the film density of the second inorganic layer IL2 and similar to the film density of the first inorganic layer IL1. The thickness t3 of the third inorganic layer IL3 may be greater than the thickness t1 of the first inorganic layer IL1 and less than the thickness t2 of the second inorganic layer IL2. In an embodiment, the thickness t3 of the third inorganic layer IL3 may be in the range of about 50 nm to about 100 nm. Within the above range, the third inorganic layer IL3 can have sufficient encapsulation properties with a thin thickness.

[0136] The thickness of the second inorganic encapsulation layer 143 may be about 210nm or less. In an embodiment, the sum of the thicknesses of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 (t1+t2+t3) may be about 210nm or less. In an embodiment, the sum of the thicknesses of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 (t1+t2+t3) may be about 130nm or more. In an embodiment, the sum of the thicknesses of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 (t1+t2+t3) may be in the range of about 150nm to about 210nm. The total thickness of the second inorganic encapsulation layer 143 and the total thickness of the encapsulation layer 140 may be reduced. In addition, the total thickness of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 and the thickness ratio of each layer having different thicknesses may be adjusted within the above range. Therefore, even if the second inorganic encapsulation layer 143 has a thin thickness, it can have sufficient encapsulation properties.

[0137] The refractive index of each of the first, second, and third inorganic layers IL1, IL2, and IL3 may be in the range of about 1.90 to about 2.10. The refractive indexes of the first, second, and third inorganic layers IL1, IL2, and IL3 may be the same as or different from each other.

[0138] The refractive indexes of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may be the same or similar to each other. In an embodiment, the difference in refractive index between the first inorganic layer IL1 and the second inorganic layer IL2 may be less than or equal to about 0.2, the difference in refractive index between the second inorganic layer IL2 and the third inorganic layer IL3 may be less than or equal to about 0.2, and the difference in refractive index between the third inorganic layer IL3 and the first inorganic layer IL1 may be less than or equal to about 0.2. The difference in refractive index between the first inorganic layer IL1 and the second inorganic layer IL2 may not exceed about 0.2, the difference in refractive index between the second inorganic layer IL2 and the third inorganic layer IL3 may not exceed about 0.2, and the difference in refractive index between the third inorganic layer IL3 and the first inorganic layer IL1 may not exceed about 0.2. In an embodiment, each of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may differ from the adjacent inorganic layer in refractive index by less than about 0.1. The difference in refractive index between each of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 and the adjacent inorganic layer may not exceed about 0.1. In an embodiment, the refractive indexes of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may be the same. In the case where the refractive indexes of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may be the same or similar to each other, light reflection at the interface between the layers can be reduced, and light efficiency can be improved.

[0139] The second inorganic layer IL2 may have a relatively low film density but have a refractive index of about 1.9 or more. In an embodiment, the refractive index of the first inorganic layer IL1 may be equal to or less than that of the second inorganic layer IL2.

[0140] In the specification, an X-ray reflectometer (XRR) (Bruker's D8 ADVANCEPlus) device can be used to measure film density and thickness. In the specification, the refractive index can be measured using an optical measuring instrument such as an ellipsometer or a spectroscopic reflectometer. The ellipsometer can measure the refractive index by measuring the polarization change of light incident on and reflected from the inorganic layer to calculate the thickness and complex refractive index of the inorganic layer. The spectroscopic reflectometer can measure the refractive index of the inorganic layer by comparing the intensity of light obtained by changing the wavelength. The refractive index can be a value measured at room temperature and room pressure.

[0141] In an embodiment, the water vapor transmission rate (WVTR) of the second inorganic encapsulating layer 143 may be about 9*10 -4 g / m 2 The second inorganic encapsulation layer 143 can effectively prevent moisture from penetrating from the outside with a thin thickness as described above.

[0142] In the specification, WVTR is a numerical value indicating the moisture permeability of the amount of water vapor passing through a specific film or layer per unit time per unit area. WVTR can be measured according to the provisions in ASTM F1249. WVTR can be measured using Mocon's AQUATRAN 2 or AQUATRAN 3 equipment.

[0143] The display device 10 may include a color filter layer 150 disposed on the encapsulation layer 140. The color filter layer 150 may include a plurality of color filters. Each of the plurality of color filters may include a filter pattern region and a light blocking region. The filter pattern region may be formed to overlap with the emission region EA, and may form an output region from which light emitted from the emission region EA may be output. The light blocking region may be a region through which light cannot pass because a plurality of color filters may be stacked on each other.

[0144] The plurality of color filters may include a first color filter 151, a second color filter 152, and a third color filter 153, respectively arranged to correspond to different emission areas EA. Each of the first color filter 151 to the third color filter 153 may include a colorant (such as a dye or a pigment) that absorbs light in a wavelength band other than light in a specific wavelength band, and may be arranged to correspond to the color of light emitted from the emission area EA. For example, the first color filter 151 may be a red color filter that transmits only red first light. The second color filter 152 may be a green color filter that transmits only green second light, and the third color filter 153 may be a blue color filter that transmits only blue third light. Figure 4 In the embodiment, only the filter pattern area of ​​the second color filter 152 overlaps with the emission area EA. However, the emission area EA of the adjacent sub-pixel may overlap with the filter pattern area of ​​the first color filter 151 or the filter pattern area of ​​the third color filter 153.

[0145] Since the first to third color filters 151 to 153 overlap each other, the display device 10 can reduce the intensity of the reflected light caused by the external light. In addition, the color of the reflected light caused by the external light can be controlled by adjusting the arrangement, shape and area of ​​the first to third color filters 151 to 153 in a plan view.

[0146] An overcoat layer OC may be disposed on the color filter layer 150 to planarize the tops of the first to third color filters 151 to 153. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as acrylic resin.

[0147] A method of manufacturing the display device 10 will now be described with reference to other drawings.

[0148] Figure 7 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. Figure 8 It is shown in detail that Figure 7 Flow chart of the process of the second inorganic encapsulation layer in FIG.

[0149] Reference Figure 7 and Figure 8, the method of manufacturing the display device 10 according to the embodiment may include forming a plurality of light emitting elements EL on a substrate (operation S10), forming a first inorganic encapsulation layer 141 on the plurality of light emitting elements EL (operation S20), forming an organic encapsulation layer 142 on the first inorganic encapsulation layer 141 (operation S30), and forming a second inorganic encapsulation layer 143 on the organic encapsulation layer 142 (operation S40). Forming the second inorganic encapsulation layer 143 (operation S40) may include forming a first inorganic layer IL1 (operation S41), forming a second inorganic layer IL2 on the first inorganic layer IL1 (operation S42), and forming a third inorganic layer IL3 on the second inorganic layer IL2 (operation S43). In the display device 10, the second inorganic encapsulation layer 143 may include first to third inorganic layers IL1 to IL3 formed by different deposition processes.

[0150] Figures 9 to 14 are views sequentially illustrating a process of manufacturing a display device according to an embodiment.

[0151] Reference Fig. 9 , a plurality of light emitting elements EL may be formed on the substrate 110 (operation S10) to form a light emitting element layer 130. A pixel defining layer 131 may be formed on the substrate 110, and the light emitting element EL may be formed in an opening of the pixel defining layer 131. The structures of the pixel defining layer 131 and the light emitting element EL may be the same as described above. Each of the pixel defining layer 131 and the light emitting element EL may be formed by a typical patterning process or a deposition process.

[0152] Reference Fig.10 , a first inorganic encapsulation layer 141 may be formed on the plurality of light emitting elements EL (operation S20). The first inorganic encapsulation layer 141 may be composed of one inorganic insulating layer, but the present disclosure may not be limited thereto. The first inorganic encapsulation layer 141 may also include a plurality of inorganic insulating layers.

[0153] Reference Fig.11 , an organic encapsulation layer 142 may be formed on the first inorganic encapsulation layer 141 (operation S30). The organic encapsulation layer 142 may include an organic insulating material. The process of forming the organic encapsulation layer 142 may not be particularly limited. For example, the organic encapsulation layer 142 may be formed by a chemical vapor deposition (CVD) method or an inkjet printing process.

[0154] Reference Figure 12 to Figure 14 , a second inorganic encapsulating layer 143 may be formed on the organic encapsulating layer 142 (operation S40). Forming the second inorganic encapsulating layer 143 may include Fig.12 The first inorganic layer IL1 is formed as shown in FIG. 4 (operation S41 ), Fig.13 forming a second inorganic layer IL2 on the first inorganic layer IL1 as shown in FIG. 4 (operation S42 ), and Fig.14A third inorganic layer IL3 is formed on the second inorganic layer IL2 as shown in FIG. 4 (operation S43 ).

[0155] In an embodiment, forming the first inorganic layer IL1 (operation S41) may be performed by a plasma enhanced atomic layer deposition (PEALD) or PECVD process. Forming the second inorganic layer IL2 (operation S42) and forming the third inorganic layer IL3 (operation S43) may be performed by a PECVD process.

[0156] When forming the first inorganic layer IL1 (operation S41), the first inorganic layer IL1 may be formed at a first deposition rate. When forming the second inorganic layer IL2 (operation S42), the second inorganic layer IL2 may be formed at a second deposition rate. When forming the third inorganic layer IL3 (operation S43), the third inorganic layer IL3 may be formed at a third deposition rate.

[0157] In an embodiment, the second deposition rate may be greater than the first deposition rate and the third deposition rate. The second deposition rate may be about 30 nm / min or more, and the first deposition rate and the third deposition rate may be about 30 nm / min or less. Therefore, the film density of the first inorganic layer IL1 formed when forming the first inorganic layer IL1 (operation S41) and the film density of the third inorganic layer IL3 formed when forming the third inorganic layer IL3 (operation S43) may be greater than the film density of the second inorganic layer IL2 formed when forming the second inorganic layer IL2 (operation S42). For example, the film density of the first inorganic layer IL1 and the film density of the third inorganic layer IL3 may each be about 2.00 g / cm 3 or more, and the film density of the second inorganic layer IL2 may be about 2.00 g / cm 3 or smaller.

[0158] The first to third inorganic layers IL1 to IL3 may all be formed using the same precursor in the same chamber. In an embodiment, the first to third inorganic layers IL1 to IL3 may include silicon nitride (SiN x ), and the precursor used in the deposition process for forming them may be an aminosilyl compound having a Si-N bond as a core structure. For example, the precursor used in the process of forming the first inorganic layer IL1 to the third inorganic layer IL3 may include, but is not limited to, at least one of cyclosilazane, trisilylamine, bis(diethylamino)silane, bis(tert-butylamino)silane, tris(dimethylamino)silane, tris(isopropylamino)silane, tetrakis(dimethylamino)silane, tris(isopropyl)cyclotrisilazane, and tetramethyldisilazane.

[0159] Fig.15 is a perspective view of a head mounted display device 1000 according to an embodiment. Fig.16 yes Fig.15 1 is an exploded perspective view of an example of a head mounted display device 1000.

[0160] Reference Fig.15 and Fig.16 According to an embodiment, a head-mounted display device 1000 includes a first display device 11, a second display device 12, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600 and a connector.

[0161] The first display device 11 provides an image to the left eye of the user, and the second display device 12 provides an image to the right eye of the user. Each of the first display device 11 and the second display device 12 may be connected to the reference Figure 1 The display devices 10 described are substantially the same. Therefore, description of the first display device 11 and the second display device 12 will be omitted.

[0162] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0163] The middle frame 1400 may be disposed between the first display device 11 and the control circuit board 1600, and may be disposed between the second display device 12 and the control circuit board 1600. The middle frame 1400 may support and fix the first display device 11, the second display device 12, and the control circuit board 1600.

[0164] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be electrically connected to the first display device 11 and the second display device 12 through a connector. The control circuit board 1600 may convert an image source received from the outside into digital video data and transmit the digital video data to the first display device 11 and the second display device 12 through the connector.

[0165] The control circuit board 1600 may transmit digital video data corresponding to a left-eye image optimized for the left eye of the user to the first display device 11, and transmit digital video data corresponding to a right-eye image optimized for the right eye of the user to the second display device 12. As another example, the control circuit board 1600 may transmit the same digital video data to the first display device 11 and the second display device 12.

[0166] The display device housing 1100 accommodates the first display device 11, the second display device 12, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 may be placed to cover the open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 on which the user's left eye may be placed and a second eyepiece 1220 on which the user's right eye may be placed. Fig.15 and Fig.16 The first eyepiece 1210 and the second eyepiece 1220 may be separately provided, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may also be combined into one.

[0167] The first eyepiece 1210 may be aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 12 and the second optical member 1520. Therefore, the user can observe the image of the first display device 11 that can be magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can observe the image of the second display device 12 that can be magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0168] The head-mounted strap 1300 fixes the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be kept placed on the user's left eye and right eye, respectively. In the case where the display device housing 1100 is implemented to be lightweight and small, the head-mounted display device 1000 may include a Fig.17 , rather than the head-mounted strap 1300 .

[0169] The head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0170] Fig.17 is a perspective view of a head mounted display device 1000_1 according to an embodiment.

[0171] Reference Fig.17The head mounted display device 1000_1 according to the embodiment may be a display device in which the display device housing 1200_1 may be implemented as a lightweight and small glasses form. The head mounted display device 1000_1 according to the embodiment may include a display device 13, a left lens 1010, a right lens 1020, a support frame 1030, glasses frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0172] The display device housing 1200_1 may include the display device 13, the optical member 1060, and the optical path conversion member 1070. The image displayed on the display device 13 may be magnified by the optical member 1060, its optical path may be converted by the optical path conversion member 1070, and may be provided to the right eye of the user through the right lens 1020. Therefore, the user is able to observe an augmented reality image through the right eye, and the virtual image displayed on the display device 13 and the real image observed through the right lens 1020 may be combined into the augmented reality image.

[0173] Despite Fig.17 The display device housing 1200_1 may be disposed at the right end of the support frame 1030, but the present disclosure may not be limited thereto. For example, the display device housing 1200_1 may also be disposed at the left end of the support frame 1030. The image of the display device 13 may be provided to the left eye of the user. As another example, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030. The user can observe the image displayed on the display device 13 through both the left eye and the right eye.

[0174] In the display device according to the embodiment, the inorganic encapsulation layer of the encapsulation layer can have excellent encapsulation properties with a thin thickness.

[0175] However, the effects of the present disclosure may not be limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims.

[0176] Although the present disclosure has been particularly shown and described with reference to the embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. The embodiments should be considered in a descriptive sense only and not for purposes of limitation.

Claims

1. A display device, comprising: A light emitting element layer, which is disposed on the substrate and includes a plurality of light emitting elements; as well as An encapsulation layer, the encapsulation layer comprising a first inorganic encapsulation layer disposed on the light emitting element layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer, wherein: The second inorganic encapsulation layer comprises: a first inorganic layer, the first inorganic layer being disposed on the organic encapsulation layer; a second inorganic layer, the second inorganic layer being disposed on the first inorganic layer; and a third inorganic layer, the third inorganic layer being disposed on the second inorganic layer, The thickness of the second inorganic layer is greater than the thickness of the third inorganic layer, The thickness of the third inorganic layer is greater than the thickness of the first inorganic layer, and The refractive index of the second inorganic layer is 1.9 or greater.

2. The display device according to claim 1, wherein: The difference in refractive index between the first inorganic layer and the second inorganic layer is less than or equal to 0.2, The difference in refractive index between the second inorganic layer and the third inorganic layer is less than or equal to 0.2, and A difference in refractive index between the third inorganic layer and the first inorganic layer is less than or equal to 0.

2.

3. The display device according to claim 1, wherein: Each of the first inorganic layer, the second inorganic layer, and the third inorganic layer includes silicon nitride.

4. The display device according to claim 1, wherein: The film density of the first inorganic layer is greater than the film density of the second inorganic layer, and The film density of the third inorganic layer is greater than the film density of the second inorganic layer.

5. The display device according to claim 1, wherein: The thickness of the second inorganic layer is greater than the sum of the thickness of the first inorganic layer and the thickness of the third inorganic layer.

6. The display device according to claim 5, wherein: A sum of the thickness of the first inorganic layer, the thickness of the second inorganic layer, and the thickness of the third inorganic layer is 210 nm or less.

7. The display device according to claim 5, wherein: The thickness of the first inorganic layer is in the range of 0.1 nm to 1.5 nm, The thickness of the second inorganic layer is in the range of 50 nm to 150 nm, and The thickness of the third inorganic layer is in the range of 50 nm to 100 nm.

8. The display device according to claim 1, wherein: The water vapor permeability of the second inorganic encapsulation layer is 9*10 -4 g / m 2 daily or less.

9. The display device according to claim 2, wherein: A refractive index of each of the first inorganic layer, the second inorganic layer, and the third inorganic layer is in the range of 1.90 to 2.

10.

10. The display device according to claim 9, wherein: The refractive index of the first inorganic layer, the refractive index of the second inorganic layer, and the refractive index of the third inorganic layer are the same.

11. The display device according to claim 1, further comprising: A circuit layer is arranged between the substrate and the light-emitting element layer, and includes a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer sequentially arranged on the substrate.

12. A display device, comprising: A light emitting element layer, which is disposed on the substrate and includes a plurality of light emitting elements; as well as An encapsulation layer, the encapsulation layer comprising a first inorganic encapsulation layer disposed on the light emitting element layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer, wherein: The second inorganic encapsulation layer comprises: a first inorganic layer, the first inorganic layer being disposed on the organic encapsulation layer; a second inorganic layer, the second inorganic layer being disposed on the first inorganic layer; and a third inorganic layer, the third inorganic layer being disposed on the second inorganic layer, The film density of the first inorganic layer is greater than the film density of the second inorganic layer, and The refractive index of the first inorganic layer is equal to or lower than the refractive index of the second inorganic layer.

13. The display device according to claim 12, wherein: The thickness of the first inorganic layer is in the range of 0.1 nm to 1.5 nm.

14. The display device according to claim 12, wherein: The difference in refractive index between the first inorganic layer and the second inorganic layer is less than or equal to 0.2, The difference in refractive index between the second inorganic layer and the third inorganic layer is less than or equal to 0.2, and A difference in refractive index between the third inorganic layer and the first inorganic layer is less than or equal to 0.

2.

15. A method for manufacturing a display device, the method comprising: forming a light-emitting element layer on a substrate, wherein the light-emitting layer includes a plurality of light-emitting elements; forming a first inorganic encapsulation layer on the light emitting element layer; forming an organic encapsulation layer on the first inorganic encapsulation layer; as well as A second inorganic encapsulation layer is formed on the organic encapsulation layer, wherein: Forming the second inorganic encapsulation layer includes: forming a first inorganic layer on the organic encapsulation layer at a first deposition rate; forming a second inorganic layer on the first inorganic layer at a second deposition rate; and forming a third inorganic layer on the second inorganic layer at a third deposition rate, and The second deposition rate is greater than the first deposition rate and the third deposition rate.

16. The method for manufacturing a display device according to claim 15, wherein: The second deposition rate is 30 nm / min or greater, and The first deposition rate and the third deposition rate are 30 nm / min or less.

17. The method for manufacturing a display device according to claim 15, wherein: Forming the first inorganic layer, forming the second inorganic layer, and forming the third inorganic layer are performed in the same chamber.

18. The method for manufacturing a display device according to claim 17, wherein: The same precursor is used to form the first inorganic layer, to form the second inorganic layer, and to form the third inorganic layer.

19. The method for manufacturing a display device according to claim 18, wherein: The precursor includes at least one of cyclosilazane, trisilylamine, bis(diethylamino)silane, bis(tert-butylamino)silane, tris(dimethylamino)silane, tris(isopropylamino)silane, tetrakis(dimethylamino)silane, tris(isopropyl)cyclotrisilazane and tetramethyldisilazane.

20. The method for manufacturing a display device according to claim 15, wherein: The forming of the first inorganic layer is performed by a plasma enhanced atomic layer deposition process or a plasma enhanced chemical vapor deposition process, and The forming of the second inorganic layer and the forming of the third inorganic layer are performed by a plasma enhanced chemical vapor deposition process.

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