Laser measurement circuit based on FPGA and measurement method thereof

Abstract

The invention relates to the technical field of laser measurement, in particular to an FPGA-based laser measurement circuit and a measurement method thereof, and the circuit comprises a laser emission circuit, a first voltage threshold configuration circuit, a second voltage threshold configuration circuit and an FPGA. The method comprises the steps that a laser transmitting circuit generates a transmitting feedback signal and a receiving signal, and when the laser transmitting circuit generates the transmitting feedback signal, if the difference between the voltage value of a first input signal point and the voltage value of a first detection signal point is larger than a difference threshold value, an FPGA detects a first positive pulse with a fixed pulse width; when the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of a second input signal point and the voltage value of a second detection signal point is greater than a difference threshold value, the FPGA detects a second positive pulse of which the pulse width changes along with the change of the ratio of signal intensity; distance detection is carried out based on the first positive pulse and the second positive pulse through the FPGA; according to the invention, the ranging precision, stability and anti-interference capability can be improved, and the cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of laser measurement, and in particular to a laser measurement circuit based on FPGA and a measurement method thereof. Background Art

[0002] In the fields of industrial production, construction, geological exploration, etc., the requirements for measurement accuracy are getting higher and higher. Traditional measurement methods such as rulers, tape measures, levels, etc. have limitations in accuracy, efficiency and safety, and laser measurement technology has emerged. With the development of industry, automation equipment has become more and more mature. With the advancement of technology, laser measurement technology is developing towards higher accuracy, smaller size, more intelligent and more networked. For example, the emergence of new measurement equipment such as 3D laser scanners and laser radars has brought revolutionary changes to the field of measurement.

[0003] Traditional laser measurement technology uses a TDC (time-to-digital converter) dedicated chip plus an MCU solution. The premise of using TDC measurement is that the received signal needs to output a STOP signal through a high-speed comparator, but the high-speed comparator has a high propagation delay and is expensive, and the propagation delay of the comparator will affect the measurement accuracy. Summary of the invention

[0004] In view of this, the purpose of the embodiments of the present invention is to provide a laser measurement circuit based on FPGA and a measurement method thereof to solve one or more technical problems existing in the prior art and provide at least one beneficial option or create conditions.

[0005] On the one hand, an embodiment of the present invention provides a laser measurement circuit based on FPGA, wherein the laser measurement circuit includes a laser emission circuit, a first voltage threshold configuration circuit, a second voltage threshold configuration circuit and an FPGA; The laser emission circuit comprises an emission feedback signal terminal and a receiving signal terminal, wherein the emission feedback signal terminal is connected to a first voltage threshold configuration circuit, and the receiving signal terminal is connected to a second voltage threshold configuration circuit; the laser emission circuit is used to generate an emission feedback signal and a receiving signal, wherein the emission feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with the signal strength; the emission feedback signal is input into the first voltage threshold configuration circuit via the emission feedback signal terminal, and the receiving signal is input into the second voltage threshold configuration circuit via the receiving signal terminal; The first input signal point and the first detection signal point of the first voltage threshold configuration circuit correspond to two pins connected to the FPGA. When the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the emission feedback signal. The second input signal point and the second detection signal point of the second voltage threshold configuration circuit are connected to the other two pins of the FPGA correspondingly. When the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal; The FPGA performs distance detection based on the first positive pulse and the second positive pulse.

[0006] Optionally, the first voltage threshold configuration circuit configures the voltage threshold of the first input signal point to be a first DC voltage value, and configures the voltage value of the first detection signal point to be a second DC voltage value; The first voltage threshold configuration circuit is used to obtain the voltage value of the first input signal point by superimposing the voltage value of the transmission feedback signal and the first DC voltage value; If the difference between the voltage value of the first input signal point and the second DC voltage value is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

[0007] Optionally, the first voltage threshold configuration circuit includes a first voltage dividing circuit and a second voltage dividing circuit; The voltage dividing end of the first voltage dividing circuit is connected to the transmission feedback signal end and the first input signal point respectively, and the voltage dividing end of the second voltage dividing circuit is connected to the first detection signal point; The voltage dividing end of the first voltage dividing circuit provides a third DC voltage value, and after the third DC voltage value and the voltage value of the transmission feedback signal end are superimposed, a voltage value of the first input signal point is obtained; the voltage dividing end of the second voltage dividing circuit provides a second DC voltage value to the first detection signal point; When the difference between the voltage value of the first input signal point and the second DC voltage value is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

[0008] Optionally, the first voltage divider circuit includes a first resistor and a second resistor, one end of the first resistor is connected to the first power supply end, the other end of the first resistor is respectively connected to the transmission feedback signal end, the first input signal point and one end of the second resistor, and the other end of the second resistor is grounded; The second voltage divider circuit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the second power supply end, the other end of the third resistor is respectively connected to the transmission feedback signal end and one end of the fourth resistor, and the other end of the fourth resistor is grounded.

[0009] Optionally, the first voltage threshold configuration circuit further includes a first filtering circuit and a second filtering circuit, the first filtering circuit includes a first capacitor and a second capacitor, and the first capacitor, the second capacitor and the second resistor are connected in parallel; The first voltage threshold configuration circuit also includes that the second filtering circuit includes a third capacitor and a fourth capacitor, and the third capacitor, the fourth capacitor and the fourth resistor are connected in parallel.

[0010] Optionally, the second voltage threshold configuration circuit configures the voltage threshold of the second input signal point to be a third DC voltage value, and configures the voltage value of the second detection signal point to be a fourth DC voltage value; The second voltage threshold configuration circuit is used to obtain the voltage value of the second input signal point by superimposing the voltage value of the received signal and the third DC voltage value; If the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

[0011] Optionally, the second voltage threshold configuration circuit includes a third voltage dividing circuit and a fourth voltage dividing circuit; The voltage dividing end of the third voltage dividing circuit is connected to the receiving signal end and the second input signal point respectively, and the voltage dividing end of the fourth voltage dividing circuit is connected to the second detection signal point; The voltage dividing end of the third voltage dividing circuit provides a third DC voltage value, and after the third DC voltage value and the voltage value of the receiving signal end are superimposed, a voltage value of the second input signal point is obtained; the voltage dividing end of the fourth voltage dividing circuit provides a fourth DC voltage value to the second detection signal point; When the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

[0012] Optionally, the third voltage divider circuit includes an eighth resistor and a ninth resistor, one end of the eighth resistor is connected to the third power supply terminal, the other end of the eighth resistor is respectively connected to the signal receiving terminal, the second input signal point and one end of the ninth resistor, and the other end of the ninth resistor is grounded; The fourth voltage divider circuit includes a tenth resistor and an eleventh resistor, one end of the tenth resistor is connected to the fourth power supply end, the other end of the tenth resistor is respectively connected to the signal receiving end and one end of the eleventh resistor, and the other end of the eleventh resistor is grounded.

[0013] Optionally, the first voltage threshold configuration circuit further includes a third filtering circuit and a fourth filtering circuit, the third filtering circuit includes a seventh capacitor and an eighth capacitor, and the seventh capacitor, the eighth capacitor and the ninth resistor are connected in parallel; The fourth filtering circuit includes a ninth capacitor and a tenth capacitor, and the ninth capacitor, the tenth capacitor and the tenth resistor are connected in parallel.

[0014] On the other hand, an embodiment of the present invention provides an FPGA-based laser measurement method, which is applied to any of the above-mentioned FPGA-based laser measurement circuits, and the method comprises the following steps: S100, generating a transmission feedback signal and a receiving signal through the laser transmission circuit, wherein the transmission feedback signal is input into a first voltage threshold configuration circuit through a transmission feedback signal terminal, and the receiving signal is input into a second voltage threshold configuration circuit through a receiving signal terminal; wherein the transmission feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with a change in signal strength; S200, when the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the emission feedback signal; when the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal; S300, performing distance detection based on the first positive pulse and the second positive pulse by the FPGA.

[0015] The embodiments of the present invention include the following beneficial effects: the embodiments provided by the present invention generate a transmission feedback signal and a receiving signal through a laser transmission circuit, set the transmission feedback signal to a negative pulse with a fixed pulse width, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, then the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the transmission feedback signal; the receiving signal is set to be a negative pulse whose pulse width changes with the change of signal strength; if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, then the FPGA detects a second positive pulse whose pulse width changes with the ratio of signal strength, and the second positive pulse corresponds to the receiving signal; the FPGA performs distance detection based on the first positive pulse and the second positive pulse. The FPGA processes the receiving signal in real time and accurately calculates the pulse width change, thereby improving the measurement accuracy, reducing the cost, and realizing efficient and intelligent laser measurement. FPGA is used to replace the traditional comparator plus TDC (time digital converter) chip solution, and a laser transmission circuit is used to generate a transmission feedback signal and a receiving signal, combined with a first voltage threshold configuration circuit, a second voltage threshold configuration circuit and an FPGA. Not only can the ranging accuracy, stability and anti-interference ability be improved, but also the cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 It is a structural schematic diagram of a laser measurement circuit based on FPGA provided in an embodiment of the present invention; Figure 2 is a circuit schematic diagram of a first voltage threshold configuration circuit in an embodiment of the present invention; Figure 3 is a circuit schematic diagram of a second voltage threshold configuration circuit in an embodiment of the present invention; Figure 4 The figure is a schematic flow chart of the steps of a laser measurement method based on FPGA provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] It should be noted that, although the device schematic diagram is divided into modules and the flow chart shows a logical order, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flow chart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0021] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0022] The block diagrams shown in the accompanying drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or in one or more hardware charging modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0023] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0024] The TDC measurement unit in the related art is triggered by the STOP1 signal and stops when the STOP2 signal is received. Between the STOP1 and STOP2 signals, the signal passes through the gate circuit inside the chip. Each gate circuit has a fixed propagation delay time, and the TDC measurement unit determines the time interval between the STOP1 and STOP2 signals by counting the number of gate circuits that the signal passes through.

[0025] The present invention is applied to short-distance visible laser ranging, which has high requirements on laser measurement accuracy. FPGA has the characteristics of high speed, high precision, high stability and reliability, and can realize real-time processing of various signals in the laser ranging system, improve ranging accuracy, stability and anti-interference ability.

[0026] The purpose of the present invention is to improve the accuracy of laser ranging and reduce the influence of measurement temperature drift. To this end, the present invention provides a laser measurement circuit based on FPGA and a measurement method thereof. The circuit uses FPGA to replace the traditional comparator plus TDC (time digital converter) chip solution, uses a laser transmitting circuit to generate a transmitting feedback signal and a receiving signal, and combines a first voltage threshold configuration circuit, a second voltage threshold configuration circuit and FPGA. Not only can the ranging accuracy, stability and anti-interference ability be improved, but also the cost can be reduced.

[0027] like Figure 1As shown, an embodiment of the present invention provides a laser measurement circuit based on FPGA, wherein the laser measurement circuit includes a laser emission circuit, a first voltage threshold configuration circuit, a second voltage threshold configuration circuit and an FPGA; The laser emission circuit comprises an emission feedback signal terminal and a receiving signal terminal, wherein the emission feedback signal terminal is connected to a first voltage threshold configuration circuit, and the receiving signal terminal is connected to a second voltage threshold configuration circuit; the laser emission circuit is used to generate an emission feedback signal and a receiving signal, wherein the emission feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with the signal strength; the emission feedback signal is input into the first voltage threshold configuration circuit via the emission feedback signal terminal, and the receiving signal is input into the second voltage threshold configuration circuit via the receiving signal terminal; The first input signal point and the first detection signal point of the first voltage threshold configuration circuit correspond to two pins connected to the FPGA. When the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the emission feedback signal. The second input signal point and the second detection signal point of the second voltage threshold configuration circuit are connected to the other two pins of the FPGA correspondingly. When the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal; The FPGA performs distance detection based on the first positive pulse and the second positive pulse.

[0028] refer to Figure 1 , Figure 1 The circuit includes FPGA and voltage threshold configuration circuit. STOP1+ is a transmission feedback signal. The transmission feedback signal STOP1+ is a negative pulse with a fixed pulse width of 5ns and an amplitude of about -1V. STOP2+ is a receiving signal. The amplitude of the receiving signal STOP2+ is a negative pulse of about -1V, and the pulse width changes with the change of signal strength.

[0029] The first input signal point STOP1N is configured as a DC voltage of 1.3V through the first voltage threshold configuration circuit, and the first detection signal point STOP1P is configured as a DC voltage of 0.8V. When there is no transmission feedback signal, the potential detected by the FPGA is a low level. When the transmission feedback signal is input to the FPGA through the first input signal point STOP1N, the FPGA detects the first positive pulse, and the pulse width of the first positive pulse is fixed.

[0030] Similarly, the second input signal point STOP2N is configured as a DC voltage of 1.3V through the second voltage threshold configuration circuit, and the second detection signal point STOP2P is configured as a DC voltage of 0.8V. When there is no receiving signal, the potential detected by the FPGA is a low level. When the receiving signal generated by the laser transmitting circuit is input to the FPGA through the second input signal point STOP2N, the FPGA detects a second positive pulse, and the pulse width of the second positive pulse changes with the ratio of the signal strength. It should be noted that, since the pulse width of the transmitted feedback signal is fixed, the pulse width of the signal at the first input signal point is also fixed, and the first positive pulse is also fixed; since the pulse width of the received signal changes with the signal strength, the pulse width of the signal at the second input signal point also changes with the signal strength, and the second positive pulse also changes with the signal strength. The FPGA performs distance detection by comparing the time difference between the rising edge of the first positive pulse and the rising edge of the second positive pulse, and accurately calibrates the detected distance by the pulse width of the second positive pulse. The present invention ensures signal stability and detection accuracy through precise voltage division and filtering design.

[0031] In some embodiments, the first voltage threshold configuration circuit configures the voltage threshold of the first input signal point to be a first DC voltage value, and configures the voltage value of the first detection signal point to be a second DC voltage value; The first voltage threshold configuration circuit is used to obtain the voltage value of the first input signal point by superimposing the voltage value of the transmission feedback signal and the first DC voltage value; If the difference between the voltage value of the first input signal point and the second DC voltage value is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

[0032] It should be noted that if the difference between the voltage value of the first input signal point and the second DC voltage value is less than or equal to the difference threshold, the potential detected by the FPGA is a low level. The accuracy and stability of distance detection are ensured. The difference threshold can be flexibly adjusted according to actual application requirements to optimize detection sensitivity and anti-interference ability. Through the pulse width detection mechanism, the FPGA can efficiently handle complex signal environments and ensure the accuracy and real-time performance of data acquisition.

[0033] like Figure 2 As shown, in some embodiments, the first voltage threshold configuration circuit includes a first voltage dividing circuit and a second voltage dividing circuit; The voltage dividing end of the first voltage dividing circuit is connected to the transmission feedback signal end and the first input signal point respectively, and the voltage dividing end of the second voltage dividing circuit is connected to the first detection signal point; The voltage dividing end of the first voltage dividing circuit provides a third DC voltage value, and after the third DC voltage value and the voltage value of the transmission feedback signal end are superimposed, a voltage value of the first input signal point is obtained; the voltage dividing end of the second voltage dividing circuit provides a second DC voltage value to the first detection signal point; It should be noted that the third DC voltage value is precisely adjusted to ensure that the voltage value of the first input signal point is within the ideal range, such as 0.3V to 1.5V, thereby improving the detection sensitivity of the FPGA to the first positive pulse; at the same time, the stability design of the second voltage divider circuit effectively reduces the impact of external interference on the second DC voltage value, further enhancing the reliability and accuracy of distance detection. Through this dual voltage divider circuit design, the FPGA can stably identify signals in complex environments and ensure the real-time and accuracy of data processing. The FPGA achieves high-precision distance detection through precise time difference measurement and pulse width calibration.

[0034] When the difference between the voltage value of the first input signal point and the second DC voltage value is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

[0035] It should be noted that the ground terminal of the first voltage-dividing circuit and the ground terminal of the second voltage-dividing circuit are grounded together, and the power supply terminal of the first voltage-dividing circuit and the power supply terminal of the second voltage-dividing circuit are respectively connected to the power supply terminal; the difference threshold is 0.5V; the voltage comparison circuit built into the FPGA compares the voltage value of the first input signal point with the second DC voltage value. If the difference exceeds 0.5V, the pulse width detection logic is triggered, and the FPGA records the pulse time and combines the built-in clock to accurately calculate the distance. This design effectively filters out noise, ensures stable and reliable measurement results, and is suitable for a variety of complex environments. Through this precise voltage comparison and pulse width detection mechanism, the FPGA can complete distance calculation within milliseconds, improve the system's response speed and measurement accuracy, and meet high-precision application requirements.

[0036] In some embodiments, the first voltage divider circuit includes a first resistor and a second resistor, one end of the first resistor is connected to the first power supply end, the other end of the first resistor is respectively connected to the transmission feedback signal end, the first input signal point and one end of the second resistor, and the other end of the second resistor is grounded; The second voltage divider circuit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the second power supply end, the other end of the third resistor is respectively connected to the transmission feedback signal end and one end of the fourth resistor, and the other end of the fourth resistor is grounded.

[0037] It should be noted that the first power supply terminal is grounded through the fifth capacitor, and the first power supply terminal is grounded through the sixth capacitor; in some embodiments, the capacitance of the fifth capacitor and the sixth capacitor are both set to 0.1μF, and the fifth capacitor and the sixth capacitor are used to filter out power supply noise to improve circuit stability. By optimizing the capacitor configuration, the purity of the voltage signal is ensured, thereby improving the detection accuracy of the FPGA and the overall performance of the system.

[0038] In some embodiments, the first voltage threshold configuration circuit further includes a first filtering circuit and a second filtering circuit, the first filtering circuit includes a first capacitor and a second capacitor, and the first capacitor, the second capacitor and the second resistor are connected in parallel; The first voltage threshold configuration circuit also includes that the second filtering circuit includes a third capacitor and a fourth capacitor, and the third capacitor, the fourth capacitor and the fourth resistor are connected in parallel.

[0039] It should be noted that a fifth resistor is further connected between the first input signal point and the transmission feedback signal end, a sixth resistor is further connected between the first input signal point and the voltage dividing end of the first voltage dividing circuit, and a seventh resistor is further connected between the first detection signal point and the voltage dividing end of the second voltage dividing circuit. The fifth resistor, the sixth resistor and the seventh resistor all play a role in current limiting.

[0040] like Figure 3 As shown, in some embodiments, the second voltage threshold configuration circuit configures the voltage threshold of the second input signal point to be a third DC voltage value, and configures the voltage value of the second detection signal point to be a fourth DC voltage value; The second voltage threshold configuration circuit is used to obtain the voltage value of the second input signal point by superimposing the voltage value of the received signal and the third DC voltage value; If the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

[0041] It should be noted that if the difference between the voltage value of the second input signal point and the fourth DC voltage value is less than or equal to the difference threshold, the potential detected by the FPGA is a low level, and the FPGA will not detect a pulse value.

[0042] In some embodiments, the second voltage threshold configuration circuit includes a third voltage dividing circuit and a fourth voltage dividing circuit; The voltage dividing end of the third voltage dividing circuit is connected to the receiving signal end and the second input signal point respectively, and the voltage dividing end of the fourth voltage dividing circuit is connected to the second detection signal point; The voltage dividing end of the third voltage dividing circuit provides a third DC voltage value, and after the third DC voltage value and the voltage value of the receiving signal end are superimposed, a voltage value of the second input signal point is obtained; the voltage dividing end of the fourth voltage dividing circuit provides a fourth DC voltage value to the second detection signal point; When the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

[0043] It should be noted that the grounding end of the third voltage-dividing circuit and the grounding end of the fourth voltage-dividing circuit are grounded together, the power supply end of the first voltage-dividing circuit and the power supply end of the second voltage-dividing circuit are connected to the power supply end respectively; the difference threshold is 0.5V.

[0044] In some embodiments, the third voltage divider circuit includes an eighth resistor and a ninth resistor, one end of the eighth resistor is connected to the third power supply terminal, the other end of the eighth resistor is respectively connected to the signal receiving terminal, the second input signal point and one end of the ninth resistor, and the other end of the ninth resistor is grounded; The fourth voltage divider circuit includes a tenth resistor and an eleventh resistor, one end of the tenth resistor is connected to the fourth power supply end, the other end of the tenth resistor is respectively connected to the signal receiving end and one end of the eleventh resistor, and the other end of the eleventh resistor is grounded.

[0045] It should be noted that the third power supply terminal is grounded through an eleventh capacitor, and the fourth power supply terminal is grounded through a twelfth capacitor.

[0046] In some embodiments, the first voltage threshold configuration circuit further includes a third filtering circuit and a fourth filtering circuit, the third filtering circuit includes a seventh capacitor and an eighth capacitor, and the seventh capacitor, the eighth capacitor and the ninth resistor are connected in parallel; The fourth filtering circuit includes a ninth capacitor and a tenth capacitor, and the ninth capacitor, the tenth capacitor and the tenth resistor are connected in parallel.

[0047] It should be noted that a twelfth resistor is also connected between the second input signal point and the receiving signal end, a thirteenth resistor is also connected between the second input signal point and the voltage dividing end of the third voltage dividing circuit, and a fourteenth resistor is also connected between the second detection signal point and the voltage dividing end of the fourth voltage dividing circuit.

[0048] like Figure 4 As shown, an FPGA-based laser measurement method provided by an embodiment of the present invention is applied to the FPGA-based laser measurement system in any of the above embodiments, and the method includes the following steps: S100, generating a transmission feedback signal and a receiving signal through the laser transmission circuit, wherein the transmission feedback signal is input into a first voltage threshold configuration circuit through a transmission feedback signal terminal, and the receiving signal is input into a second voltage threshold configuration circuit through a receiving signal terminal; wherein the transmission feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with a change in signal strength; S200, when the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the emission feedback signal; when the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal; S300, performing distance detection based on the first positive pulse and the second positive pulse by the FPGA.

[0049] It can be seen that the contents of the above circuit embodiments are all applicable to the present method embodiments, the functions specifically implemented by the present method embodiments are the same as those of the above circuit embodiments, and the beneficial effects achieved are also the same as those achieved by the above circuit embodiments.

[0050] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the charging modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0051] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional charging modules / units in the systems and devices may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0052] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example: a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0054] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0055] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0056] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0057] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0058] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A laser measurement circuit based on FPGA, characterized in that: The laser measurement circuit includes a laser transmitting circuit, a receiving circuit, a first voltage threshold configuration circuit, a second voltage threshold configuration circuit and an FPGA; The laser emission circuit comprises an emission feedback signal terminal and a receiving signal terminal, wherein the emission feedback signal terminal is connected to a first voltage threshold configuration circuit, and the receiving signal terminal is connected to a second voltage threshold configuration circuit; the laser emission circuit is used to generate an emission feedback signal and a receiving signal, wherein the emission feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with the signal strength; The transmission feedback signal is input into a first voltage threshold configuration circuit via a transmission feedback signal terminal, and the reception signal is input into a second voltage threshold configuration circuit via a reception signal terminal; The first input signal point and the first detection signal point of the first voltage threshold configuration circuit correspond to two pins connected to the FPGA. When the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the emission feedback signal. The second input signal point and the second detection signal point of the second voltage threshold configuration circuit are connected to the other two pins of the FPGA correspondingly. When the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal; The FPGA performs distance detection based on the first positive pulse and the second positive pulse.

2. The laser measurement circuit according to claim 1, characterized in that: The first voltage threshold configuration circuit configures the voltage threshold of the first input signal point to be a first DC voltage value, and configures the voltage value of the first detection signal point to be a second DC voltage value; The first voltage threshold configuration circuit is used to obtain the voltage value of the first input signal point by superimposing the voltage value of the transmission feedback signal and the first DC voltage value; If the difference between the voltage value of the first input signal point and the second DC voltage value is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

3. The laser measurement circuit according to claim 2, characterized in that: The first voltage threshold configuration circuit includes a first voltage dividing circuit and a second voltage dividing circuit; The voltage dividing end of the first voltage dividing circuit is connected to the transmission feedback signal end and the first input signal point respectively, and the voltage dividing end of the second voltage dividing circuit is connected to the first detection signal point; The voltage dividing end of the first voltage dividing circuit provides a third DC voltage value, and the voltage value of the first input signal point is obtained by superimposing the third DC voltage value and the voltage value of the transmission feedback signal end; The voltage dividing end of the second voltage dividing circuit provides a second DC voltage value to the first detection signal point; When the difference between the voltage value of the first input signal point and the second DC voltage value is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

4. The laser measurement circuit according to claim 3, characterized in that: The first voltage divider circuit includes a first resistor and a second resistor, one end of the first resistor is connected to the first power supply end, the other end of the first resistor is respectively connected to the transmission feedback signal end, the first input signal point and one end of the second resistor, and the other end of the second resistor is grounded; The second voltage divider circuit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the second power supply end, the other end of the third resistor is respectively connected to the transmission feedback signal end and one end of the fourth resistor, and the other end of the fourth resistor is grounded.

5. The laser measurement circuit according to claim 4, characterized in that: The first voltage threshold configuration circuit further includes a first filtering circuit and a second filtering circuit, the first filtering circuit includes a first capacitor and a second capacitor, and the first capacitor, the second capacitor and the second resistor are connected in parallel; The first voltage threshold configuration circuit also includes that the second filtering circuit includes a third capacitor and a fourth capacitor, and the third capacitor, the fourth capacitor and the fourth resistor are connected in parallel.

6. The laser measurement circuit according to claim 1, characterized in that: The second voltage threshold configuration circuit configures the voltage threshold of the second input signal point to be a third DC voltage value, and configures the voltage value of the second detection signal point to be a fourth DC voltage value; The second voltage threshold configuration circuit is used to obtain the voltage value of the second input signal point by superimposing the voltage value of the received signal and the third DC voltage value; If the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

7. The laser measurement circuit according to claim 6, characterized in that: The second voltage threshold configuration circuit includes a third voltage dividing circuit and a fourth voltage dividing circuit; The voltage dividing end of the third voltage dividing circuit is connected to the receiving signal end and the second input signal point respectively, and the voltage dividing end of the fourth voltage dividing circuit is connected to the second detection signal point; The voltage dividing end of the third voltage dividing circuit provides a third DC voltage value, and after the third DC voltage value and the voltage value of the receiving signal end are superimposed, a voltage value of the second input signal point is obtained; the voltage dividing end of the fourth voltage dividing circuit provides a fourth DC voltage value to the second detection signal point; When the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

8. The laser measurement circuit according to claim 7, characterized in that: The third voltage divider circuit includes an eighth resistor and a ninth resistor, one end of the eighth resistor is connected to the third power supply terminal, the other end of the eighth resistor is respectively connected to the signal receiving terminal, the second input signal point and one end of the ninth resistor, and the other end of the ninth resistor is grounded; The fourth voltage divider circuit includes a tenth resistor and an eleventh resistor, one end of the tenth resistor is connected to the fourth power supply end, the other end of the tenth resistor is respectively connected to the signal receiving end and one end of the eleventh resistor, and the other end of the eleventh resistor is grounded.

9. The laser measurement circuit according to claim 8, characterized in that: The first voltage threshold configuration circuit further includes a third filtering circuit and a fourth filtering circuit, the third filtering circuit includes a seventh capacitor and an eighth capacitor, and the seventh capacitor, the eighth capacitor and the ninth resistor are connected in parallel; The fourth filtering circuit includes a ninth capacitor and a tenth capacitor, and the ninth capacitor, the tenth capacitor and the tenth resistor are connected in parallel.

10. A laser measurement method based on FPGA, characterized in that: Applied to the FPGA-based laser measurement circuit according to any one of claims 1 to 9, the method comprises the following steps: S100, generating a transmission feedback signal and a receiving signal through the laser transmission circuit, wherein the transmission feedback signal is input into a first voltage threshold configuration circuit through a transmission feedback signal terminal, and the receiving signal is input into a second voltage threshold configuration circuit through a receiving signal terminal; wherein the transmission feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with a change in signal strength; S200, when the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the emission feedback signal; when the laser emission circuit generates an emission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal; S300, performing distance detection based on the first positive pulse and the second positive pulse by the FPGA.

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