ASIC chip for high-performance aoip network audio streaming

Abstract

The application discloses an ASIC chip for high-performance AOIP network audio stream transmission, which internally comprises a functional analog circuit subsystem, a sensor controller, a clock and reset control module, a high-speed peripheral interface subsystem arranged on a first bus, a hardware acceleration subsystem arranged on a second bus, and a low-speed peripheral interface subsystem arranged on a third bus, the second bus being connected with the first bus and the third bus respectively, and the functional analog circuit subsystem being connected with the third bus through the sensor controller; the hardware acceleration subsystem comprises a plurality of processor cores, two gigabit or megabit media independent interfaces and a real-time transmission protocol (RTP) transceiving engine; the two gigabit or megabit media independent interfaces are compatible with simplified media independent interfaces, one of the two gigabit or megabit media independent interfaces is used as a main network interface, and the other is used as a backup network interface. The reliability of AOIP network audio stream transmission is solved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip architecture design, and particularly relates to an ASIC chip for high-performance AOIP network audio stream transmission. BACKGROUND

[0002] With the rapid development of technologies such as cloud computing, Internet of Things, big data, artificial intelligence and mobile Internet, the professional audio industry field has ushered in an important development opportunity for digitization, networking and intelligentization. At present, professional audio equipment and systems are in an important development stage of transformation and upgrading from analog systems and digital systems to networking. The high-performance AOIP network audio stream transmission technology solves the problem of networking of analog audio and digital audio, simplifying the complexity of the professional audio system architecture and device connection.

[0003] However, the high-performance AOIP network audio stream transmission chips currently used in the professional audio industry field are all SoC chips. Such chips are obviously inferior to hardware circuit implementation in terms of timeliness, reliability, stability and security. In addition, such chips are based on ARM architecture single-core processing, with single function and serious defects in information security protection and comprehensive processing capability, which cannot meet the needs of the rapid development of the digital economy. SUMMARY

[0004] The embodiment of the application provides an ASIC chip for high-performance AOIP network audio stream transmission, which at least solves the problem of single function of the chip in the related art and serious defects in information security protection and comprehensive processing capability.

[0005] The embodiment of the application provides an ASIC chip for high-performance AOIP network audio stream transmission, which at least solves the problem of single function of the chip in the related art and serious defects in information security protection and comprehensive processing capability.

[0006] The hardware acceleration subsystem includes a plurality of processor cores, two gigabit or hundred-megabit media independent interfaces and a real-time transport protocol (RTP) transceiver engine.

[0007] The plurality of processor cores are implemented by an instruction set of 32 bits or more.

[0008] The two gigabit or megabit media independent interfaces are compatible with the simplified media independent interface, one of the two gigabit or megabit media independent interfaces is used as a main network interface, and the other is used as a backup network interface.

[0009] The RTP transceiving engine is configured to encapsulate and send network RTP data packets of the digital audio stream, and to parse and restore network audio stream RTP data packets.

[0010] The ASIC chip for high-performance AOIP network audio stream transmission in the embodiment of the application has strong autonomous controllability and avoids the adverse factors of being subject to the constraints of an industrial chain and a supply chain, based on a high-performance AOIP network audio stream transmission chip constructed by a kernel of a 32-bit or higher instruction set; the special chip (ASIC) architecture designed has great advantages in processing speed compared with a SoC chip, and is the first special chip design for high-performance AOIP network audio stream transmission; a multi-core processing architecture is adopted to realize digital audio processing on the basis of realizing high-performance AOIP network audio stream transmission, and to provide safe and reliable, high-quality audio signals; two gigabit or megabit media independent interfaces are used on the special chip to transmit high-performance AOIP network audio streams, and the special chip is compatible with a simplified media independent interface, can be connected to a gigabit or megabit external physical layer chip, and supports main and backup network redundancy, so that seamless switching can be realized, and the reliability of AOIP network audio stream transmission is well solved. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed to be used in the embodiments of the application will be briefly introduced. Those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0012] Figure 1 FIG. 1 is a schematic diagram of an internal structure of an ASIC chip for high-performance AOIP network audio stream transmission provided by the embodiments of the application. DETAILED DESCRIPTION

[0013] The features and exemplary embodiments of various aspects of the application will be described in detail below, in order to make the purposes, technical solutions and advantages of the application more clear and apparent, the application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the application, but not to limit the application. The application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the application by showing examples of the application.

[0014] It is to be noted that the relative terms such as first and second and the like in this context are used only to differentiate one entity or action from another, and do not necessarily require or imply any such actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... " does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0015] AoIP (Audio over IP) refers to a technology for real-time transmission of high-fidelity digital audio signals in the form of IP (Internet Protocol) streams on a common Ethernet network, which can be applied to many professional audio fields including live sound reinforcement. The high-fidelity of AoIP means a sampling rate of 44.1 kHz or higher, linear quantization of 16 bits or higher (usually 48 kHz sampling and 24-bit quantization), and low latency (hundreds of microseconds to milliseconds), without using any lossy or lossless compression processing.

[0016] With the increasing development of artificial intelligence algorithms and application technologies, and the gradual maturation of the artificial intelligence special chip ASIC industry environment, the fully customized artificial intelligence ASIC also gradually shows its own advantages. ASIC chip is an integrated circuit (ASIC, Application Specific Integrated Circuit) chip technology for special applications, which is considered in the integrated circuit industry as an integrated circuit designed for a specific purpose.

[0017] With the rapid development of technologies such as cloud computing, Internet of Things, big data, artificial intelligence, and mobile Internet, the professional audio industry has ushered in an important development opportunity for digitalization, networking, and intelligentization. Currently, professional audio equipment and systems are in an important development stage of transition and upgrading from analog systems and digital systems to networking. The high-performance AOIP network audio stream (sampling rate not less than 44.1 kHz, quantization precision not less than 16 bits, latency less than 10 ms, using linear PCM encoding) transmission technology solves the problem of networking of analog audio and digital audio, simplifies the complexity of the architecture of professional audio systems and device connections, and enables intelligent monitoring, control, management, and maintenance of systems at remote ends, which not only improves the work efficiency of user operation and maintenance personnel, but also enhances the user experience.

[0018] However, the high-performance AOIP network audio stream transmission chips currently used in the field of professional audio industry are all SoC chips, and the functions of RTP audio stream transceiver engine, network clock synchronization, digital media clock management, digital audio processing, peripheral interface and system control management are realized through software on general SoC chips. Therefore, such chips are obviously inferior to hardware circuit implementation in terms of timeliness, reliability, stability and security, and the chips are based on ARM single-core processing, which is single in function and lacks digital audio processing and decryption functions, and has serious defects in information security guarantee and comprehensive processing capability, which cannot meet the needs of the rapid development of digital economy.

[0019] To solve the problems in the related art, the embodiments of the present application provide an ASIC chip for high-performance AOIP network audio stream transmission.

[0020] The ASIC chip for high-performance AOIP network audio stream transmission provided by the embodiments of the present application will be described in detail below in combination with the drawings, specific embodiments and application scenarios.

[0021] Reference Figure 1 is a schematic diagram of the internal structure of an ASIC chip for high-performance AOIP network audio stream transmission according to an embodiment of the present application. As Figure 1 shown, the ASIC chip for high-performance AOIP network audio stream transmission internally includes a high-speed peripheral interface subsystem, a hardware acceleration subsystem, a low-speed peripheral interface subsystem, a functional analog circuit subsystem, a sensor controller (SSC), and a clock and reset control module (Clk / Reset). Based on the clock and reset control module, the digital audio signals entering and exiting from each node in the network are accurately synchronized.

[0022] Specifically, the high-speed peripheral interface subsystem is arranged on a first bus, the hardware acceleration subsystem is arranged on a second bus, and the low-speed peripheral interface subsystem is arranged on a third bus. The second bus is connected to the first bus and the third bus respectively.

[0023] Optionally, as Figure 1 shown, the first bus is an AHB high-speed bus (Advanced High_performence Bus), the second bus is an AXI bus (Advanced eXtensible Interface), and the third bus is an APB 32bit 100MHz bus (Advanced Peripheral Bus).

[0024] AHB bus is a bus interface, the chip uses a bus width of 32 bits or more, and is mainly used for communication between the chip processor kernel, DMA and external MCU, DSP. The AHB bus is composed of a master module, a slave module and a basic structure. Transmission is issued by the master module, the slave module is responsible for responding, and the basic structure is composed of an arbitrator, a multiplexer from the master module to the slave module, a multiplexer from the slave module to the master module, a decoder, a virtual slave module and a virtual master module.

[0025] AXI bus is a bus for high performance, high bandwidth and low delay within a chip. The chip uses a bus width of 128 bits or more, does not need to use a complex bridge, and the protocol can achieve high frequency operation. Its address control and data stage are separated, supports address misaligned data transmission, and only needs the first address in burst-based transmission. There are five independent channels in total, and significant transmission access and out-of-order access are supported. It is easy to add pipeline stages to obtain high frequency timing.

[0026] APB 32bit bus is mainly used for connection between low-bandwidth peripheral devices. Its bus architecture does not support multiple master modules like AHB. The only master module in APB is APB bridge. Its characteristics include: two clock cycle transmission, no waiting period and response signal, simple control logic, and only four control signals.

[0027] It should be noted that the first bus and the second bus are converted by a protocol conversion bridge. The protocol conversion bridge includes a data conversion processing module and a protocol analysis module corresponding to the first bus and the second bus. Taking the first bus as an AHB high-speed bus and the second bus as an AXI bus as an example, the AHB and the AXI bus need to be converted by a protocol conversion bridge (APB AXI Bridge), which includes a data conversion processing module and a protocol analysis module of each bus.

[0028] In some embodiments, the hardware acceleration subsystem includes a plurality of processor (CPU) cores, i.e., processor core 1 and processor core 2 in Figure 1 Specifically, the plurality of processor (CPU) cores are implemented based on an instruction set of 32 bits or more, support single and double precision floating point operations, and can respectively undertake corresponding functions such as system management and DSP processing according to needs.

[0029] Among the plurality of processor (CPU) cores, the processor core 1 is built-in with ICache and DCache, and is used for external interface and internal control. Users can interact and manage the CPU through standard SPI (slave mode) and UART interfaces to realize different function settings: the external interface realizes control and management of user's routing, event and security access, the internal interface realizes RTP packet delay, sampling rate control, PTP clock deviation control and digital audio interface control, and a JTAG interface is reserved, which can use GDB for code debugging to improve development and debug efficiency.

[0030] The processor core 2 supports single and double precision floating point operations, and can be used as a floating point operation unit FPU to perform gain, inversion, equalization and limiting on the multi-channel digital audio signals input by I2S or TDM.

[0031] In some embodiments, the hardware acceleration subsystem includes two gigabit or megabit media independent interfaces (RGMII / RMII, Reduced Gigabit Media Independent Interface / Reduced Media Independent Interface) in RGMII_1 and RGMII_2. Figure 1 Specifically, both of the two gigabit or megabit media independent interfaces use a 4-bit data interface, and the working clock is 125MHz, and data is transmitted at the rising and falling edges at the same time, so the transmission rate can reach 1000Mbps, and can be used for communication between the media access control layer MAC and the physical layer PHY.

[0032] As an optional embodiment, one of the two gigabit or megabit media independent interfaces is used as a primary network interface, and the other is used as a backup network interface.

[0033] As an optional embodiment, both of the two gigabit or megabit media independent interfaces are compatible with the reduced media independent interface (RMII interface), so they can be connected with the external gigabit or megabit PHY chip, support primary and backup network redundancy, and realize seamless switching.

[0034] As an optional embodiment, the two gigabit or megabit media independent interfaces are also connected with the APB bus, which is mainly used for connecting and configuring low-speed peripherals and IP registers.

[0035] Further, in some embodiments, the hardware acceleration subsystem includes a real-time transport protocol (RTP) transceiver engine. Specifically, the RTP transceiver engine, which employs a dedicated hardware circuit (ASIC), is a layer between the kernel and the RTP stack. The kernel provides a series of callback interfaces to complete different transactions (such as audio output, etc.), and the RTP engine needs to adapt these interfaces, i.e., to encapsulate or decapsulate the RTP stack. Therefore, the RTP transceiver engine can be used to encapsulate and send network RTP packets of a digital audio stream, and to parse and restore network audio stream RTP packets.

[0036] Optionally, the sampling frequency of the digital audio signal received and sent by the RTP transceiver engine should at least support 44.1 kHz, 48 kHz, 96 kHz, and 192 kHz, and the quantization precision should at least support 16 bits, 24 bits, and 32 bits.

[0037] In this way, the hardware acceleration subsystem, based on the above-mentioned components included therein, can be used to encapsulate a digital audio stream accessed through the low-speed peripheral interface subsystem into a network RTP packet according to the RTP network protocol through the RTP transceiver engine, and send it to the medium access control layer, and transmit it to an external physical layer chip through the gigabit media independent interface, and parse a network audio stream RTP packet entered through the gigabit media independent interface into a digital audio stream through the RTP transceiver engine to output through the low-speed peripheral interface subsystem.

[0038] That is, the digital audio stream is transmitted to the network audio stream RTP packet encapsulation IP core through the TDM / I2S interface of the low-speed peripheral interface subsystem, encapsulated into a network RTP packet according to the RTP network protocol, sent to the MAC layer, entered into the external PHY chip through the RGMII interface, and the sending of the high-performance network audio stream is realized; the network audio stream RTP packet is parsed into a digital audio stream after entering the network audio stream RTP packet decapsulation IP core through the PHY and RGMII interfaces, and output through the TDM / I2S interface, so as to realize the reception of the network audio stream.

[0039] Therefore, the special-purpose chip (ASIC) architecture designed has great advantages in processing speed compared with SoC chips, and is the first special-purpose chip design for high-performance AOIP network audio stream transmission; a multi-core processing architecture is adopted to realize digital audio processing on the basis of realizing high-performance AOIP network audio stream transmission, and a safe and reliable, high-quality audio signal can be provided; two gigabit or hundred-megabit media independent interfaces are adopted on the special-purpose chip to transmit high-performance AOIP network audio streams, and a simplified media independent interface is also compatible, so that the chip can be connected to a gigabit or hundred-megabit external physical layer chip, and supports primary and backup network redundancy, can realize seamless switching, and well solves the reliability problem of AOIP network audio stream transmission.

[0040] Further, in some embodiments, the hardware acceleration subsystem includes an encryption module and a decryption module. The encryption module is configured to encrypt the digital audio signal, and the decryption module is configured to decrypt the digital audio signal. Specifically, the encryption module and the decryption module support at least the following algorithms: AES128 F8, AES CTR, SM2, SM3, and SM4.

[0041] In some optional embodiments, the hardware acceleration subsystem includes two direct memory access (DMA) controllers, namely DMA controller 1 and DMA controller 2 in FIG. 6. Specifically, a direct memory access controller is a unique peripheral device for transferring data within a system, which can be regarded as a controller that connects internal and external memories with each DMA-capable peripheral device through a dedicated bus. The controller performs the transfer under the programming control of a processor. The memory access technology for directly accessing data in memory is composed of a kernel and a DMA control interface logic chip. Only peripherals with large data traffic, such as audio, video, and network interfaces, need to support DMA capability. Figure 1

[0042] It should be noted that one of the two direct memory access controllers is matched with the primary network interface, and the other is matched with the backup network interface. That is, the two direct memory access controllers are used in pairs with the primary network interface and the backup network interface, respectively.

[0043] As an optional embodiment, the two direct memory access controllers also set the corresponding registers through the AHB bus.

[0044] In some optional embodiments, the hardware acceleration subsystem includes a static random access memory (SRAM), an automatic forwarding FIFO, and a true random number generator (TRNG). The static random access memory can maintain the stored data constantly as long as it is powered on, and the data will disappear after the power supply is stopped. The automatic forwarding FIFO is a first-in, first-out data buffer for RTP data forwarding. The true random number generator is a device for generating random numbers, and the output random numbers are generated based on physical random phenomena or processes that have inherent randomness.

[0045] In another embodiment, the true random number generator also sets the true random number register through the APB bus.

[0046] ​In some alternative embodiments, the hardware acceleration subsystem comprises an IEEE 1588 network precision clock synchronization module for time stamping outgoing or received packets. Optionally, a special clock synchronization packet detector and time stamp marking unit is installed at the media independent interface (RGMII) interface connecting the media access control layer (MAC) and the physical layer (PHY) to implement time stamping of each special packet (e.g. Sync and Delay_Req) sent or received. PTP (Precise Time Protocol) can achieve sub-microsecond time synchronization accuracy, mainly through the Delay Request-Response Mechanism.

[0047] It can be understood that IEEE 1588, i.e. the precision clock synchronization protocol of the network measurement and control system, can realize frequency and phase synchronization between the master and slave nodes through the sending and error measurement of time packets, with an accuracy better than 100 ns. Therefore, the application of this technology in the media clock delivery of AoIP can achieve precise synchronization.

[0048] In some alternative embodiments, the hardware acceleration subsystem can implement digital media clock management. Specifically, the digital media clock management performs frequency division processing on the synchronized local clock to provide a standard clock to the TDM / I2S, so that each audio device using the network transmission chip closely tracks and synchronizes to the reference clock, ensuring that nodes at any location in the network can output the same sampling frequency source signal at the same reference time, so that audio data is not lost due to synchronization loss caused by buffer data overload (or buffer bypass caused by too little data).

[0049] Optionally, for digital media clock management, the supported sampling frequencies should at least include 44.1 kHz, 48 kHz, 96 kHz and 192 kHz.

[0050] As can be seen from the above, the hardware acceleration subsystem, based on the processor core 1, the processor core 2, the SRAM, the automatic forwarding FIFO, the encryption module, the decryption module, the true random number generator, the IEEE 1588 network precision clock synchronization module, the RGMII interface 1, the RGMII interface 2, the RTP transceiver engine, the DMA controller 1 and the DMA controller 2 and other modules contained therein, and the fact that these modules are all mounted on the AXI 128-bit bus, can realize hardware acceleration processing of service data, i.e. through ASIC hardware acceleration to realize functions such as digital audio signal encryption and decryption, RTP audio stream transceiving, network clock synchronization, digital media clock management, digital audio processing and system control management.

[0051] In some embodiments, the high-speed peripheral interface subsystem includes a memory interface (ROM), a first serial peripheral interface (i.e. Figure 1 master SPI), a second serial peripheral interface (i.e. Figure 1 slave SPI), and a serial FLASH controller (SFC). Specifically, the memory interface is configured to store a secure boot program; the first serial peripheral interface is configured to provide high-speed, full-duplex synchronous serial communication for controlling transmission and reception of audio data and generation of a clock signal; the second serial peripheral interface is configured to provide high-speed, full-duplex synchronous serial communication for receiving audio data and a clock signal transmitted by the master device (i.e. the first serial peripheral interface) and performing audio data transmission under the control of the master device; and the serial FLASH controller is configured to communicate with and control an external SPI FLASH and to store and read audio data.

[0052] In this way, the high-speed peripheral interface subsystem, based on the ROM, SFC interface, master SPI, slave SPI interface, etc. contained therein, and the fact that these interfaces are all mounted on the AHB 32-bit high-speed bus, can achieve system control and management of data reception, transmission, storage, and read-write control within and outside the dedicated chip.

[0053] Further, in some embodiments, the low-speed peripheral interface subsystem is configured to perform chip state monitoring, control and management of data communication, burn-in protection, system control authority, real-time clock control, timing, counting, digital audio signal input and output, etc. and mainly includes some low-speed peripheral interface modules and system management modules, such as but not limited to: an OTP (one time programmable) interface, a SysCtrl, a GPIO (General-Purpose Input / Output) interface, an I2C (Inter-Integrated Circuit) interface, a UART (Universal Asynchronous Receiver / Transmitter) interface, a Watchdog, an RTC (Real-Time-Clock) interface, a TIMER, an I2S (Inter-IC Sound) interface, and a TDM (Time Division Multiplexing) interface. These modules are all mounted on an APB 32-bit 100MHz bus, which is connected to the corresponding AXI 128-bit bus of the hardware acceleration subsystem.

[0054] The following describes each module in the low-speed peripheral interface subsystem in detail:

[0055] OTP, used to store data that cannot be changed or can only be programmed once, ensures that the code at device startup is unchangeable, can also store a unique serial number or device ID to prevent device copying or impersonation, can also store device configuration parameters such as calibration data and network settings, which are not changed after factory, can also store encryption keys or security authentication keys for encrypted communication or device authentication to improve security.

[0056] Sysctrl, mainly used for system control (responsible for managing various on-chip peripherals, including peripheral reset, clock management (such as clock source, frequency setting, gating, etc.), DMA planning, etc.), power management (through access to the power management unit PMU, responsible for managing the power supply of the chip, including voltage regulation, clock control and reset), clock management (responsible for generating and managing the chip's clock signal, including high-speed clock HSI, low-speed clock LSI, external clock HSE and internal oscillator MSI), reset management (through the reset controller RST to detect and handle reset events, including external reset, internal reset and watchdog reset) and other aspects, mainly through access to a series of registers and bit fields to control the chip's functions, ensuring stable and efficient operation of the chip, handling chip freezing or system crash and other issues.

[0057] GPIO, is the basic module for the chip to interact with external devices, can be configured as input mode (read external device level state) or output mode (output high or low level, control external device), supports multiple modes (input mode, output mode, analog mode, multiplexing function mode) and configuration options (no pull-up or pull-down mode, pull-up or pull-down mode), can also be configured as interrupt mode (respond to external events, improve system response speed and efficiency), also usually contains protection diode (protect the chip from being damaged) and pull-up and pull-down resistors (set the default state of the pin, avoid the influence of the pin in an indeterminate state), GPIO is mainly used for communication between the chip and external devices, control hardware devices, data acquisition, etc.

[0058] I2C, is a bidirectional, two-wire serial communication interface, mainly used to realize communication between the chip and other peripheral devices such as sensors, memories and displays, etc., can realize bidirectional communication, can connect multiple slave devices, up to 128, each connected device has a unique address, can send data to the slave device through broadcast, the slave device can confirm reception through the response signal after receiving the data, supports standard mode (100kHz) and fast mode (400kHz), and supports power management function, can work in low power mode.

[0059] UART, mainly used to realize the data transmission and communication between chips, is an asynchronous serial communication interface, which can realize bidirectional transmission, and the working process is divided into three stages of data encoding (the sending end converts parallel data into serial data), data transmission (data is sent through the serial interface, and the receiving end detects the change of baud rate and bit period to judge the transmission of data) and data decoding (the receiving end converts the received serial data into parallel data, which will use parity check or cyclic redundancy check to detect and correct errors). This interface can also be connected to printers, sensors, industrial automation equipment, etc., and can also be used for program debugging, etc.

[0060] Watchdog, mainly used to prevent system from running away due to accidental system paralysis, monitors the running state of the system through the timer mechanism to ensure that the system can automatically restart when an exception occurs. This interface usually contains a timer (Watchdog Time, abbreviated as WDT), which has an input end (dog feeding end) and an output end. Under normal circumstances, the system will periodically send a signal to the dog feeding end to reset the timer. If the system stops sending signals for some reason, the timer will trigger after reaching the preset time and send a reset signal to the system reset end, thus restarting the system, which can effectively prevent the system from entering a dead loop or dead state due to program errors or hardware failures.

[0061] RTC, access to external precise clock signal, provides more accurate time information for the chip, maintains time accuracy after system power failure or restart.

[0062] TIMER, mainly used for periodic task processing and event timing, controls the operation of the counter through internal clock source or external trigger signal to realize timing function. Mainly based on the operation and overflow mechanism of the counter, when the counter reaches the preset value, it will overflow and trigger an interrupt to execute the related timing task. There are Oneshot mode (the counter stops after reaching the preset value and needs to be restarted), Auto reload mode (the counter automatically reloads and continues counting after reaching the preset value), UP mode (the counter starts from 0 and increments to the preset value), DOWN mode (the counter decreases from the preset value to 0).

[0063] I2S, mainly used for digital audio data transmission, is a serial bus standard, mainly including clock signal (SCK, providing clock reference for data transmission, controlling the rate of data transmission), word selection signal (WS, used to distinguish left and right channel data, low level transmits left channel data, high level transmits right channel data), data signal (transmits actual audio data).

[0064] TDM, mainly used for transmitting multiple audio channel data on a single data line at the same time, thereby reducing the number of chip pins, using time division multiplexing to distribute multiple audio channel data to different time slots, and each channel data occupies 1 / N of the frame time, where N is a power of 2.

[0065] Further, in some embodiments, the functional analog circuit subsystem includes an internal RC oscillator (IRC), a phase-locked loop (PLL), a low dropout regulator (LDO), an analog-to-digital converter (ADC SENSOR), a power-on reset circuit (POR), and a power-off reset circuit (BOR). Specifically, the internal RC oscillator is used to provide a stable clock signal and frequency source at low cost; the phase-locked loop is used to lock the phase and frequency of the input signal to the reference signal to generate an output signal consistent with the phase and frequency of the reference signal, mainly used for high-frequency running of the chip; the low dropout regulator is used to stabilize the input voltage to a constant DC voltage, i.e., to stabilize the input voltage to a constant output voltage, to provide a stable DC voltage to ensure that the system can operate normally under various working conditions; the analog-to-digital converter is used to convert analog signals to digital signals.

[0066] The power-on reset circuit mainly ensures that after applying power, the analog and digital modules can be initialized to a known state, thereby avoiding the "race" phenomenon and making the device static until the power supply voltage reaches a threshold value that can ensure normal operation, mainly including power-on detection (when the chip is powered on, the power supply voltage will gradually rise), delay (after the power-on detection circuit detects that the power supply voltage reaches the threshold value, a certain time is needed for the internal circuits of the chip to adapt to the change of the power supply voltage) and reset operation (after the delay ends, the reset circuit inside the chip starts to execute the reset operation).

[0067] The power-off reset circuit mainly protects the system from potential damage caused by low voltage, mainly by detecting changes in the power supply voltage, and triggering a reset signal when the power supply voltage drops to a certain threshold. This mechanism ensures that when the power supply voltage is below the preset threshold, the system can automatically enter a reset state, thereby preventing system errors or damage caused by low voltage.

[0068] In this way, the functional analog circuit subsystem can realize functions such as providing high-precision clock, phase-locked loop control, power-on / power-off reset, temperature voltage sensing, and direct current voltage stabilization for the chip based on the analog circuit modules (IRC, PLL, POR, BOR, ADC sensor, and LDO, etc.) contained therein, and all data are mainly connected through the SSC (sensor controller) and the corresponding APB 32bit 100MHz bus of the low-speed peripheral interface subsystem.

[0069] In addition, in some embodiments, the functional analog circuit subsystem is connected with the third bus through the sensor controller. The sensor controller is configured to perform signal type conversion of an audio signal between a sensing module of the functional analog circuit subsystem and the third bus.

[0070] Therefore, the ASIC chip for high-performance AOIP network audio stream transmission in the embodiments of the present application is the first to realize high-performance AOIP network audio transmission by using a dedicated chip (ASIC), and the core functions are accelerated and realized on a hardware circuit, so that the processing speed is fast and the timeliness is prominent. Multi-core processing is adopted, and the first to realize high-performance AOIP network audio transmission, digital audio processing, and digital audio encryption and decryption functions. The first to use a double RGMII interface to transmit high-performance AOIP network audio stream, and at the same time, compatible with the RMII interface, can be connected with a gigabit or megabit external PHY chip, and supports master and standby network redundancy, and can realize seamless switching.

[0071] It should be noted that, for the convenience of description, the above device or system is described as various modules by function. Of course, in the implementation of the present application, the functions of each module can be realized in the same or multiple software and / or hardware.

[0072] The functional blocks shown in the structure block diagram described above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, etc. When implemented in software, the elements of the present application are program or code segments used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. The "machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segments can be downloaded via a computer network such as the Internet, an intranet, etc.

[0073] It should also be noted that the example embodiments mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiments, or in an order different from the embodiments, or several steps can be performed simultaneously.

[0074] The above generally describes aspects of the present application with reference to a flowchart and / or a block diagram of the method, the device (system) and the computer program product according to embodiments of the present application. It should be understood that each block of the flowchart and / or the block diagram, as well as a combination of blocks in the flowchart and / or the block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus enable the implementation of the functions / acts specified in one or more blocks of the flowchart and / or the block diagram. The processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It should also be understood that each block of the block diagram and / or the flowchart, as well as a combination of blocks in the block diagram and / or the flowchart, can also be implemented by special-purpose hardware to perform the specified functions or acts, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0075] The above is only a specific implementation of the present application, and those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, module and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here. It should be understood that the protection scope of the present application is not limited to this, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be covered within the protection scope of the present application.

Claims

1. An ASIC chip for high performance AOIP network audio streaming, characterized in that, The chip internally comprises: a functional analog circuit subsystem, a sensor controller, a clock and reset control module, and a high-speed peripheral interface subsystem arranged on a first bus, a hardware acceleration subsystem arranged on a second bus, and a low-speed peripheral interface subsystem arranged on a third bus, the second bus being connected with the first bus and the third bus respectively, and the functional analog circuit subsystem being connected with the third bus through the sensor controller; The hardware acceleration subsystem comprises a plurality of processor cores, two gigabit or megabit media independent interfaces, and a real-time transmission protocol (RTP) transceiving engine. Each of the plurality of processor cores is implemented by a 32-bit or higher instruction set. Each of the two gigabit or megabit media independent interfaces is compatible with a simplified media independent interface, one of the two gigabit or megabit media independent interfaces serving as a primary network interface, and the other serving as a backup network interface. The RTP transceiving engine is configured to encapsulate and send network RTP data packets of a digital audio stream, and to parse and restore network audio stream RTP data packets.

2. The ASIC chip for high performance AOIP network audio streaming according to claim 1, wherein, The hardware acceleration subsystem is configured to encapsulate a digital audio stream accessed through the low-speed peripheral interface subsystem into RTP data packets according to an RTP network protocol through the RTP transceiving engine, and send the RTP data packets to a medium access control layer and to an external physical layer chip through the gigabit media independent interface, and to parse network audio stream RTP data packets entered through the gigabit media independent interface into a digital audio stream through the RTP transceiving engine, and output the digital audio stream through the low-speed peripheral interface subsystem.

3. The ASIC chip for high performance AOIP network audio streaming according to claim 1, wherein, The hardware acceleration subsystem further comprises a static random access memory, an automatic forwarding FIFO, a true random number generator, and two dispersion controllers. One of the two dispersion controllers cooperates with the primary network interface, and the other cooperates with the backup network interface.

4. The ASIC chip for high performance AOIP network audio streaming of claim 1, wherein, The hardware acceleration subsystem further comprises an IEEE 1588 network precision clock synchronization module configured to time stamp outgoing or received messages.

5. The ASIC chip for high performance AOIP network audio streaming according to claim 1, wherein, The hardware acceleration subsystem further comprises an encryption module and a decryption module. The encryption module is configured to perform encryption processing on a digital audio signal. The decryption module is configured to perform decryption processing on a digital audio signal.

6. The ASIC chip for high performance AOIP network audio streaming according to claim 5, wherein, The encryption module and the decryption module support at least the following algorithms: AES128 F8, AES CTR, SM2, SM3, and SM4.

7. The ASIC chip for high performance AOIP network audio streaming according to claim 1, wherein, The high-speed peripheral interface subsystem comprises a memory interface, a first serial peripheral interface, a second serial peripheral interface, and a serial FLASH controller. The memory interface is configured to store a secure boot program. The first serial peripheral interface is configured to control sending and receiving of audio data and generation of a clock signal. The second serial peripheral interface is configured to receive audio data and a clock signal sent by the first serial peripheral interface, and to perform audio data transmission under the control of the first serial peripheral interface. The serial FLASH controller is configured to store and read audio data.

8. The ASIC chip for high performance AOIP network audio streaming of claim 1, wherein, The sensor controller is configured to perform signal type conversion of the audio signal between the functional analog circuit subsystem and a third bus.

9. The ASIC chip for high performance AOIP network audio streaming according to claim 1, wherein, The functional analog circuit subsystem comprises an internal RC oscillator, a phase-locked loop, a low-dropout linear regulator, an analog-to-digital converter, a power-on reset circuit and a power-off reset circuit. The internal RC oscillator is configured to provide a stable clock signal and a frequency source. The phase-locked loop is configured to lock the phase and frequency of an input signal to a reference signal to generate an output signal consistent with the phase and frequency of the reference signal. The low-dropout linear regulator is configured to stabilize an input voltage to output a constant direct current voltage. The analog-to-digital converter is configured to convert an analog signal into a digital signal.

10. The ASIC chip for high performance AOIP network audio streaming of claim 1, wherein, The first bus and the second bus are converted to each other through a protocol conversion bridge, wherein the protocol conversion bridge comprises a data conversion processing module and protocol analysis modules corresponding to the first bus and the second bus respectively.

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