SOC data transmission control device based on 8051 kernel
By designing new bus and cache registers in SOC based on 8051 cores, the direct interaction between peripherals and RAM is achieved, and the inefficiency problem caused by frequent participation of the kernel during SOC data transmission is solved, and efficient and real-time data transmission is achieved.
Patent Information
- Application Number
- CN202411921744.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-04-22
AI Technical Summary
During the data transmission process of SOC based on the 8051 core, it is necessary to frequently participate in memory operations, resulting in low program operation efficiency, large space waste, or DMA technology is required for data transmission, and the transmission efficiency and design circuit overhead are large.
A SOC data transmission control device based on the 8051 core is designed to directly interact with the RAM by adding a new bus, with a lower priority than the 8051 core, to avoid the core from frequently participating in data transmission, and to use the data request controller, send cache register and receive buffer to avoid data blocking when RAM is occupied by the kernel.
There is no need to use programs for data transmission, which saves chip program overhead and improves operating efficiency; there is no need to design DMA separately, the overall design is simple, and the overhead of designing the gate circuit is small, real-time data transmission is realized.
Smart Images
Figure CN119862047A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of industrial control computers, and in particular to a SOC data transmission control device based on an 8051 core. Background Art
[0002] The application of system-on-chip (SOC) based on 8051 core in the field of industrial control computers has become more and more widespread. The 8051 core is widely used in various industrial control systems due to its simplicity, high efficiency and easy programming. These SOCs based on 8051 core not only have high processing power, but also have rich peripheral interfaces to meet various needs in industrial control.
[0003] Some peripheral modules of SOC based on 8051 core need to store a large amount of data in RAM. For example, ADC needs to store a large amount of data for noise filtering, and SPI needs to fill the transmission data. Generally, these data are stored in RAM and transmitted through software running programs. This method requires the kernel to be frequently involved, resulting in poor overall program running efficiency and huge waste of program space. It needs to be operated through programs or DMA technology for data transmission, which has relatively high efficiency and overhead.
[0004] Prior art 1: Run the program and store it in RAM through software. After the module generates data, it informs the kernel. The kernel runs the program and stores the generated data in RAM through software execution, completing the temporary storage of multiple groups of data.
[0005] Prior art 2: DMA technology (Direct Memory Access), DMA technology manages data transfer through a device called a DMA controller. When the peripheral is ready for data, it sends a transfer request to the DMA controller. After the kernel receives this request, it suspends the current task and hands over the control of the memory bus to the DMA controller. After the DMA controller takes over the bus, it reads the data from the peripheral and stores it at the target address in the memory. After the data transfer is completed, the DMA controller releases the bus control and notifies the kernel.
[0006] The above-mentioned technology 1 requires running a program to achieve the data transmission effect. This method requires the use of program space and will cause the program running in the total thread to be interrupted by the request. The existing technology 2 is DMA technology (direct memory access). This solution requires a DMA controller and needs to release the bus to the DMA controller for data transmission. The normal kernel processing of data will be suspended, resulting in the suspension of kernel processing, and the effect of synchronous processing cannot be achieved, affecting the operation of the kernel. For this reason, we propose a SOC data transmission control device based on the 8051 core. Summary of the invention
[0007] The purpose of the present invention is to solve the problem that some peripheral modules of SOC based on 8051 core need to store a large amount of data in RAM, such as ADC needs to store a large amount of data for noise filtering, SPI needs to fill transmission data, etc. Generally, these data are stored in RAM and transmitted by running a program through software. Such method requires the kernel to participate frequently, resulting in poor overall program running efficiency and huge waste of program space; or DMA technology is used for data transmission, and the transmission efficiency and design circuit overhead are relatively large. The present invention provides a SOC data transmission control device based on 8051 core.
[0008] In order to achieve the above-mentioned purpose, the present invention specifically adopts the following technical solutions:
[0009] A SOC data transmission control device based on an 8051 core comprises an 8051 core, a program memory, a data memory RAM and peripherals. The program memory, the data memory RAM and the peripherals all transmit data with the 8051 core via a data bus. The memory RAM and the peripherals exchange data via a newly added bus. The priority of the peripherals accessing the data memory RAM via the newly added bus is lower than the priority of the 8051 core accessing the data memory RAM, and the normal operation of the core is not affected.
[0010] Furthermore, the peripheral device is provided with a data request controller, a sending buffer register and a receiving buffer. The data request controller can directly send a use request to the data memory RAM without going through the 8051 core. The sending buffer register and the receiving buffer can effectively avoid data blocking when the data memory RAM3 is occupied by the 8051 core.
[0011] Furthermore, the peripherals include but are not limited to ADC / SPI.
[0012] Furthermore, the depth of the sending buffer register and the receiving buffer can be adjusted according to design requirements, and the sending buffer register and the receiving buffer can be multiplexed according to the form of peripheral modules.
[0013] The beneficial effects of the present invention are as follows:
[0014] 1. The present invention does not need to use a program to perform data transmission operations, which effectively saves chip program overhead. Because there is no need to use program participation, the chip operation efficiency is also improved.
[0015] 2. The present invention does not need to perform DMA design separately. It relies on the core characteristics for design. The overall design is simpler than DMA, the design gate circuit overhead is small, and real-time transmission effect can also be achieved.
[0016] 3. The present invention does not modify any characteristics of the kernel and is compatible with various 8051 kernels. The technology uses RAM to replace registers, reduces the use of data storage registers, and saves design overhead. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a block diagram of the device system structure of the present invention;
[0018] Figure 2 It is a schematic diagram of the newly added path interaction method of the present invention.
[0019] Figure numerals: 1. 8051 core; 2. Program area; 3. RAM; 4. Peripheral. DETAILED DESCRIPTION
[0020] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.
[0021] See also Figure 1-Figure 2 The present invention provides a SOC data transmission control device based on the 8051 core, comprising an 8051 core 1, a program memory 2, a data memory RAM3 and a peripheral 4. The program memory 2, the data memory RAM3 and the peripheral 4 all transmit data with the 8051 core 1 through a data bus. The memory RAM3 and the peripheral 4 exchange data through a newly added bus. The priority of the peripheral accessing the data memory RAM3 through the newly added bus is lower than the priority of the 8051 core 1 accessing the data memory RAM3, and does not affect the normal operation of the core.
[0022] In this embodiment, preferably, a data request controller, a sending buffer register and a receiving buffer are provided in the peripheral 4. The data request controller can directly send a use application to the data memory RAM3 without going through the 8051 core 1. The sending buffer register and the receiving buffer can effectively avoid data blocking when the data memory RAM3 is occupied by the 8051 core.
[0023] In this embodiment, preferably, the peripheral device 4 includes but is not limited to ADC / SPI.
[0024] In this embodiment, preferably, the depth of the sending buffer register and the receiving buffer can be adjusted according to the design requirements, and the sending buffer register and the receiving buffer can be multiplexed according to the form of the peripheral module. For example, when the peripheral module is an ADC, the depth of the sending buffer register can be designed to be shallower to reduce the delay in data processing; while for high-speed and large-data-volume SPI communication, the receiving buffer requires a larger depth to avoid data overflow. In this way, the cache depth can be flexibly configured according to different application scenarios, thereby optimizing the overall data transmission efficiency and system performance. In addition, the multiplexing mechanism allows cache resources to be shared between different peripheral modules, which not only improves the utilization of hardware resources, but also reduces the design cost, so that the SOC data transmission control device has better adaptability and economy in a variety of application scenarios.
[0025] When the device is in use, the priority of the newly added path is lower than the priority of the 8051 core 1 accessing RAM3. Under normal circumstances, it does not affect the normal operation of the 8051 core 1, and can allow mutual access to data between RAM3 and peripheral 4 without the participation of the 8051 core 1 and program area 2. In special circumstances, when peripheral 4 generates data or has data needs, since the core occupies RAM3 for a long time, peripheral 4 can send an application to the 8051 core 1 to use RAM3, and the storage of one byte of data can be completed in one cycle.
[0026] The present invention does not need to use a program to perform data transmission operations, effectively saving chip program overhead. Because there is no need to use program participation, the chip operation efficiency is also improved. In addition, there is no need to perform DMA design separately. It relies on the kernel characteristics for design. The overall design is simpler than DMA, the gate circuit design overhead is small, and real-time transmission effect can also be achieved. At the same time, it does not modify any kernel characteristics and is compatible with various 8051 kernels. The technology uses RAM instead of registers to reduce the use of data storage registers, which can save design overhead.
[0027] Example 1
[0028] The data of peripheral 4 is stored in RAM3. The cache register on peripheral 4, when peripheral 4 has data to be stored in RAM3, the data is first placed in a 4-byte cache area, and the interval of RAM3 used by peripheral 4 is specified. The use of RAM3 is issued. It can query whether the 8051 core 1 has any use demand for peripheral 4. If there is no demand, the data of peripheral 4 is stored in RAM3, and the cache use of peripheral 4 is cleared to 0. If RAM3 is in a busy state, peripheral 4 uses waiting until the data is stored in RAM3.
[0029] Example 2
[0030] When peripheral 4 needs data input, a specific function is generated through the input data, and peripheral 4 initiates the need to fetch data from RAM3. When RAM3 is idle, it can continuously fetch 4 of its own data and put them in a 4-byte cache area of the cache register of peripheral 4. Peripheral 4 can then use the cache data. This is repeated until all the data pre-set in RAM3 are fetched.
[0031] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A SOC data transmission control device based on 8051 core, characterized in that: The invention comprises an 8051 core (1), a program memory (2), a data memory RAM (3) and a peripheral device (4); the program memory (2), the data memory RAM (3) and the peripheral device (4) all perform data transmission with the 8051 core (1) via a data bus; the memory RAM (3) and the peripheral device (4) perform data exchange via a newly added bus; the priority of the peripheral device accessing the data memory RAM (3) via the newly added bus is lower than the priority of the 8051 core (1) accessing the data memory RAM (3), and does not affect the normal operation of the core device.
2. The SOC data transmission control device based on 8051 core according to claim 1, characterized in that: The peripheral device (4) is provided with a data request controller, a sending buffer register and a receiving buffer. The data request controller can directly send a use request to the data memory RAM (3) without going through the 8051 core (1). The sending buffer register and the receiving buffer can effectively avoid data blocking when the data memory RAM3 is occupied by the 8051 core.
3. The SOC data transmission control device based on 8051 core according to claim 1, characterized in that: The peripherals (4) include but are not limited to ADC and SPI.
4. The SOC data transmission control device based on 8051 core according to claim 2, characterized in that: The depth of the sending buffer register and the receiving buffer can be adjusted according to design requirements, and the sending buffer register and the receiving buffer can be multiplexed according to the form of peripheral modules.