Display method of display system and display system

Abstract

The invention provides a display method of a display system and the display system. The method comprises the steps that a host receives a master-slave selection signal to the host and sends a generated reference clock signal to a slave in response to the received master-slave selection signal, and the slave is other sequential control chips except the host in a plurality of sequential control chips; in a touch mode of the display screen, the host sends a row / frame synchronizing signal to the slave, and the slave responds to the received row / frame synchronizing signal and controls the host to synchronously transmit data to the display screen, so that any two display areas of the display screen synchronously display; in the non-touch mode of the display screen, the host and the slave synchronously drive the row / frame synchronizing signal according to the reference clock signal, so that each host synchronously transmits data to the display screen, and any two display areas of the display screen synchronously display. According to the method, the problem that correct display of a high-resolution and high-refresh-rate display screen cannot be met in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular, to a display method and a display system of a display system. Background Art

[0002] As various consumer electronic products (eg, mobile phones, laptops, desktop computers, tablet computers, televisions, etc.) play an increasingly important role in our work and life, displays with both display and touch functions have become an essential key component.

[0003] In order to meet people's ever-increasing work and life needs, the resolution and refresh rate of display screens are constantly improving. However, the problem that follows is that it is limited by the performance factors of a single TCON, including chip transmission rate and area. It becomes difficult to use a traditional single TCON to control a high-resolution and high-refresh-rate display screen to complete the display.

[0004] Taking the current 8k4k resolution and 60hz refresh rate display as an example, the bandwidth corresponding to 30 bits for each pixel is 8100 megabytes per second, and the current mainstream input interface display interface 4lane 5.4G bandwidth is 2160 megabytes, so 4 interfaces are needed for transmission. The mainstream inside the chip is the 4-pixel processing bus. The frequency of mainstream chips is generally around 300 megabytes. The bandwidth of a single chip is only 1200 megapixels per second, while the pixel bandwidth of 8k4k resolution and 60hz refresh rate is 2160 megapixels. If you want to support 5:5 touch function, the bandwidth must be doubled to 4320 megapixels, so 4 chips are also needed to complete it. The output interface is also a huge challenge. The mainstream CEDS interface of the output interface has a 10-bit bandwidth of 172,800 megabits per second, while the current mainstream CEDS bandwidth is around 2500 megabits. Therefore, 70 high-speed transmission lines are required to connect to the display screen, which is impossible to achieve on a single timing controller chip (TCON). This means that it is difficult to control high-resolution and high-refresh-rate displays to achieve correct display.

[0005] Therefore, there is an urgent need for a method for correctly displaying a display screen that can meet the requirements of high resolution and high refresh rate. Summary of the invention

[0006] The main purpose of the present application is to provide a display method and a display system of a display system, so as to at least solve the problem in the prior art that a display screen that cannot meet the requirements of high resolution and high refresh rate can not display correctly.

[0007] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a display method of a display system is provided, wherein a host receives a master-slave selection signal to the host, and in response to the received master-slave selection signal, sends a generated reference clock signal to a slave, wherein the slave is other timing control chips among the plurality of timing control chips except the host; in the touch mode of the display screen, the host sends a row / frame synchronization signal to the slave, and the slave controls the transmission of data to the display screen synchronously with the host in response to the received row / frame synchronization signal, so that any two display areas of the display screen are displayed synchronously; in the non-touch mode of the display screen, the host and the slave synchronously drive the row / frame synchronization signal according to the reference clock signal, so that each of the hosts synchronously transmits data to the display screen, thereby making any two display areas of the display screen displayed synchronously.

[0008] Optionally, the method also includes: after each of the timing control chips is powered on, each of the timing control chips controls the working mode signal to be in a low level state, and the working mode signal is used to indicate the working mode of the timing control chip; after the register configuration of each of the timing control chips is loaded, each of the timing control chips controls the working mode signal to be in a high level state; when the working mode signal is in the high level state for a predetermined number of consecutive reference clock signal cycles, each of the timing control chips controls the hot plug signal to be in the high level state, and triggers each of the timing control chips to control the working mode signal to be in the low level state until data needs to be transmitted to the display screen.

[0009] Optionally, the method also includes: when any one of the timing control chips enters the target operating mode, triggering the operating mode signal to be in a target level state and synchronously sending the operating mode signal to other timing control chips, the target operating mode is one of the following: a safe operating mode, a normal display mode, and the target level state is a low level state or a high level state; the other timing control chips enter the target operating mode in response to the received operating mode signal in the target level state.

[0010] Optionally, the method also includes: when each of the slave machines enters the safe working mode and each of the slave machines receives a non-target instruction, the slave machine enters the waiting phase of the safe working mode and does not enter the protection screen phase, the non-target instruction is an instruction issued by a non-host machine to control the slave machine to enter the protection screen phase, and the safe working mode includes the waiting phase and the protection screen phase.

[0011] Optionally, the method further comprises: when the lookup table parameters of the video processing units of the timing control chips are loaded completely, starting the video processing units of the timing control chips simultaneously.

[0012] Optionally, the method also includes: after the host sends a frame synchronization signal, when none of the timing control chips receive valid line video data, each of the timing control chips controls the line synchronization signal to a low level state; when the host receives the valid line video data, and any one of the slaves does not receive the valid line video data, each of the timing control chips controls the line synchronization signal to the low level state, and the host caches the received valid line video data in an internal delay buffer; after the host receives the valid line video data, when all of the slaves do not receive the valid line video data, each of the timing control chips controls the line synchronization signal to a high level state, and the host and the slaves simultaneously transmit the valid line video data to the display.

[0013] Optionally, each of the timing control chips includes a processor, and the method further includes: in the case where there is a need to transmit data to be transmitted to a first predetermined timing control chip, the processor of the first predetermined timing control chip receives a checksum of the data to be transmitted sent by the transmission channel between the host and the slave, and the first predetermined timing control chip is the host or the slave; the processor of the first predetermined timing control chip detects whether there is an error in the data to be transmitted based on the checksum; in the case of an error, the processor of the first predetermined timing control chip modifies the erroneous data to be transmitted to obtain the modified data to be transmitted, and sends the modified data to be transmitted to the transmission channel.

[0014] Optionally, each of the timing control chips includes a processor, and the method further includes: the processor detects whether the line spacing between the valid line video data received by the timing control chip to which it belongs and any one of the timing control chips exceeds two lines; when it exceeds two lines, the processor controls the timing control chip to which it belongs to enter a safe working mode / no signal mode, and triggers the working mode signal to enter a low level state; the timing control chip synchronizes the working mode signal in the low level state to other timing control chips, and the other timing control chips enter the safe working mode / no signal mode in response to the received working mode signal in the low level state.

[0015] According to another aspect of the present application, a display system is provided, which includes multiple timing control chips and a display, each of the timing control chips is electrically connected to the display, the display includes a display screen, the display screen includes multiple display areas, the timing control chips correspond to the display areas one by one, and the display system is used to execute any one of the display methods described above.

[0016] Optionally, a processor; a master-slave selection pin, which is communicatively connected to the processor and is used to receive a master-slave selection signal; a reference clock signal pin, which is connected to the reference clock signal pins of any two timing control chips; an operating mode pin, which is used to indicate the operating mode of the timing control chip; a row start pin, which is connected to the row start pins of any two timing control chips and is used to output a row start signal; a frame start pin, which is connected to the frame start pins of any two timing control chips and is used to output a frame start signal; a first synchronization data pin and a second synchronization data pin, in two adjacent timing control chips, the first synchronization data pin of one is connected to the first synchronization data pin of the other, and is used to transmit first data and second data between the corresponding two timing control chips; a first clock synchronization pin and a second clock synchronization pin, in two adjacent timing control chips, the first clock synchronization pin of one is connected to the second clock synchronization pin of the other, and the first clock synchronization pin and the second clock synchronization pin are used to synchronize the transmission of the first data and the transmission of the second data, respectively.

[0017] By applying the technical solution of the present application, first, the host receives a master-slave selection signal to the host, and sends a reference clock signal generated after receiving the master-slave selection signal to the slave; secondly, in the touch mode of the display screen, the host sends a row / frame synchronization signal to the slave, and after the slave receives the row / frame synchronization signal, controls the transmission of data to the display screen synchronously with the host, so that any two display areas of the display screen are displayed synchronously; finally, in the non-touch mode of the display screen, the host and the slave synchronously drive the row / frame synchronization signal according to the reference clock signal, so that each of the hosts synchronously transmits data to the display screen, thereby making any two display areas of the display screen displayed synchronously. Compared with the prior art, the solution of the present application can synchronize the working modes and line / frame image display characteristics of each timing control chip through data transmission between the host and the slave, thereby ensuring the synchronous display of each area of ​​the display screen, thereby ensuring that the high refresh rate display screen can be displayed correctly. At the same time, compared with the solution with only one timing control chip, the present application provides multiple timing control chips and divides the display screen into multiple areas, each area is controlled by an independent timing control chip, thus reducing the number of pixels that each timing control chip needs to process, thereby improving the bandwidth utilization of each timing control chip, ensuring that the high refresh rate display screen can be displayed correctly, thereby solving the problem that the prior art cannot meet the correct display of high resolution and high refresh rate display screens. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 A hardware structure block diagram of a mobile terminal for executing a display method of a display system provided in an embodiment of the present application is shown;

[0020] Figure 2 A schematic diagram of a flow chart of a display method of a display system provided according to an embodiment of the present application is shown;

[0021] FIG3( a ) is a schematic diagram showing data transmission within a blanking period in a touch display mode (Touch) of a display method of a display system provided according to an embodiment of the present application;

[0022] FIG3( b ) shows an enlarged schematic diagram of point a in FIG3( a );

[0023] FIG3( c ) shows an enlarged schematic diagram of point b in FIG3( a );

[0024] FIG3( d ) shows an enlarged schematic diagram of point c in FIG3( a );

[0025] FIG4( a ) is a schematic diagram showing data transmission in a blanking period in a non-touch display mode (non-Touch) of a display method of a display system provided according to an embodiment of the present application;

[0026] FIG4( b ) shows an enlarged schematic diagram of point a in FIG4( a );

[0027] FIG4(c) shows an enlarged schematic diagram of point b in FIG4(a);

[0028] Figure 5 A schematic diagram showing changes in hot plug (HPD) signals of multiple multi-timing control chips (TCON) during a power-on process of a display method of a display system provided in an embodiment of the present application is shown;

[0029] Figure 6 A schematic diagram showing a plurality of TCON synchronous control SYNC STATEs of a display method of a display system provided according to an embodiment of the present application;

[0030] Figure 7 A schematic diagram showing a display method of a display system according to an embodiment of the present application, in which multiple TCONs are switched from a safe working (FAIL / SAFE) mode to a normal display (NORMAL) mode;

[0031] Figure 8 A schematic diagram showing a display method of a display system according to an embodiment of the present application, wherein multiple TCONs are switched from a NORMAL mode to a FAIL / SAFE mode;

[0032] Fig. 9 A schematic diagram showing a display method of a display system according to an embodiment of the present application, wherein multiple TCONs synchronously control SYNC_VHSYNC;

[0033] Fig.10 A schematic diagram showing a display method of a display system provided according to an embodiment of the present application, in which multiple TCONs synchronously control SYNC_VHSYNC_1 and output a data enable signal to a panel driver;

[0034] Fig.11 A structural schematic diagram of a TCON cascade synchronous display of a display method of a display system provided in an embodiment of the present application is shown;

[0035] Fig.12A schematic diagram of simulation waveforms of input data enable of a host TCON and a slave TCON and data enable output to a panel driver in a display method of a display system provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0039] As introduced in the background technology, the prior art cannot satisfy the problem of correct display of display screens with high resolution and high refresh rate. To solve the above problem, the embodiments of the present application provide a display method and a display system of a display system.

[0040] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0041] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a mobile terminal of a display method of a display system according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is for illustration only and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0042] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the display method of device information in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the above method is implemented. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The transmission device 106 is used to receive or send data via a network. The above-mentioned specific examples of the network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0043] In this embodiment, a display method for a display system running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0044] Figure 2 is a flow chart of a display method of a display system according to an embodiment of the present application. Figure 2 As shown, the method comprises the following steps:

[0045] In step S201, the host receives a master-slave selection signal to the host, and in response to the received master-slave selection signal, sends a generated reference clock signal to a slave, where the slave is other timing control chips among the plurality of timing control chips except the host.

[0046] Specifically, a display screen is collaboratively controlled by multiple timing control chips, which determine a certain timing control chip as the master and the other timing control chips as slaves based on the master-slave selection signal (PIN_MS_SL). The host then sends a reference clock signal (REF_CLK) to the slave through a customized IIC interface.

[0047] Step S202, in the touch mode of the above-mentioned display screen, the above-mentioned host sends a line / frame synchronization signal to the above-mentioned slave, and the above-mentioned slave responds to the above-mentioned line / frame synchronization signal received, controls the transmission of data to the above-mentioned display screen synchronously with the above-mentioned host, so that any two of the above-mentioned display areas of the above-mentioned display screen are displayed synchronously.

[0048] Specifically, the host will also send the line / frame synchronization signal (SYNC_VHSYNC_1) in this mode to the slave to meet the special timing in this mode. Through the above data transmission between the host and the slave, the working mode and line / frame display characteristics of each timing control chip are synchronized, thereby ensuring that each area of ​​the display screen can display the picture synchronously.

[0049] Specifically, regarding the specific information transmitted on SYNC_DATA0 and SYNC_DATA1: In touch mode, the vertical information will be divided into DPRX / BIST and touch, where the DPRX / BIST part contains 9 bits of data, see Table 1 for details, and the touch contains 12 bits of data, see Table 2 for details. When the row information is synchronized, 13 bits of data will be transmitted in each horizontal blanking period, see Table 3 for details.

[0050] Specifically, as shown in Figure 3(a), Figure 3(b) is an enlarged schematic diagram of point a in Figure 3(a), Figure 3(c) is an enlarged schematic diagram of point b in Figure 3(a), and Figure 3(d) is an enlarged schematic diagram of point c in Figure 3(a), wherein D0 to D12 are all valid data.

[0051] Table 1

[0052]

[0053]

[0054] Table 2

[0055]

[0056] Table 3

[0057]

[0058] Step S203, in the non-touch mode of the above-mentioned display screen, the above-mentioned host and the above-mentioned slave synchronously drive the above-mentioned line / frame synchronization signal according to the above-mentioned reference clock signal, so that each of the above-mentioned hosts synchronously transmits data to the above-mentioned display screen, so that any two of the above-mentioned display areas of the above-mentioned display screen are displayed synchronously.

[0059] Specifically, in non-touch mode, the host and slave use a reference clock signal to synchronously drive the row / frame synchronization signal, so they determine when to send data to the display based on the same clock signal. In this way, each host can transmit data to the display at the same time point, ensuring that each area of ​​the display is displayed synchronously.

[0060] Specifically, in the blanking period in the vertical or horizontal direction in the non-touch mode, the SYNC_VHSYNC and SYNC_VHSYNC_1 signals will be pulled high, and the transmitter of TCON sends information through SYNC_DATA0 and SYNC_DATA1 at the falling edges of SYNC_CLK0 and SYNC_CLK1 respectively, and the receiver receives the information at the rising edges of SYNC_CLK0 and SYNC_CLK1, as shown in Figure 4(a). Point a in Figure 4(a) is the Vsync signal at the beginning of the Nth frame, and its enlarged schematic diagram is shown in Figure 4(b). Point b in Figure 4(a) is the last valid row of the Nth frame in the sent row buffer, and its enlarged schematic diagram is shown in Figure 4(c), wherein D0 to D70 are all valid data.

[0061] Specifically, regarding the specific information transmitted on SYNC_DATA0 and SYNC_DATA1: During the vertical blanking period in the non-touch mode, 71 bits of data will be transmitted, as shown in Table 4 for details.

[0062] Table 4

[0063]

[0064]

[0065] In the above embodiment, first, the host receives the master-slave selection signal to the above host, and sends the reference clock signal generated after receiving the above master-slave selection signal to the slave; secondly, in the touch mode of the above display screen, the above host sends the line / frame synchronization signal to the above slave, and after the above slave receives the above line / frame synchronization signal, controls the transmission of data to the above display screen synchronously with the above host, so that any two of the above display areas of the above display screen are displayed synchronously; finally, in the non-touch mode of the above display screen, the above host and the above slave synchronously drive the above line / frame synchronization signal according to the above reference clock signal, so that each of the above hosts synchronously transmits data to the above display screen, thereby making any two of the above display areas of the above display screen display synchronously. Compared with the prior art, the solution of the present application can synchronize the working modes and line / frame image display characteristics of each timing control chip through data transmission between the host and the slave, thereby ensuring the synchronous display of each area of ​​the display screen, thereby ensuring that the high refresh rate display screen can be displayed correctly. At the same time, compared with the solution with only one timing control chip, the present application provides multiple timing control chips and divides the display screen into multiple areas, each area is controlled by an independent timing control chip, thus reducing the number of pixels that each timing control chip needs to process, thereby improving the bandwidth utilization of each timing control chip, ensuring that the high refresh rate display screen can be displayed correctly, thereby solving the problem that the prior art cannot meet the correct display of high resolution and high refresh rate display screens.

[0066] In one embodiment of the present application, the method further includes: after each of the above-mentioned timing control chips is powered on, each of the above-mentioned timing control chips controls the working mode signal to be in a low level state, and the above-mentioned working mode signal is used to indicate the working mode of the above-mentioned timing control chip; after the register configuration of each of the above-mentioned timing control chips is loaded, each of the above-mentioned timing control chips controls the above-mentioned working mode signal to be in a high level state; when the above-mentioned working mode signal is in the above-mentioned high level state for a predetermined number of consecutive reference clock signal cycles, each of the above-mentioned timing control chips controls the hot plug signal to be in the above-mentioned high level state, and triggers each of the above-mentioned timing control chips to control the above-mentioned working mode signal to be in the above-mentioned low level state until data needs to be transmitted to the display screen. In this method, by controlling the level state of the working mode signal and the hot plug signal, it is further ensured that the timing control chip works normally in different states.

[0067] After all the timing control chips are powered on, the working mode signal is pulled low by all the timing control chips. After the register configuration of each timing control chip is loaded, it will release its own internal synchronization status signal. When the register configuration of all the timing control chips is loaded, the level state of the working mode signal will be pulled high. When the level state of the working mode signal is continuously pulled high for more than 4 reference clock signal cycles, each timing control chip will pull up the level state of its own hot plug signal. After the level state of the hot plug signal is pulled high, each timing control chip will jointly pull down the level state of the working mode signal until video data is output to the panel driver. The level state of the clock synchronization signal is always in a low state during the above process, and the above process is only executed once after the timing control chip is powered on. For the specific process, please refer to Figure 5 , Figure 5 At time point B, the host's register configuration is loaded and SYNC_STATE is released. Between time points C and D, SYNC_STATE is pulled high. At time point D, the host and slave detect that SYNC_STATE has been pulled high for 4 REF_CLK cycles, so they pull SYNC_STATE low.

[0068] In order to further ensure that all timing control chips in the system are in a consistent working state, in one embodiment of the present application, the above method also includes: when any one of the above timing control chips enters the target working mode, triggering the working mode signal to be in the target level state and synchronously sending the above working mode signal to other above timing control chips, the above target working mode is one of the following: safe working mode, normal display mode, and the above target level state is a low level state or a high level state; the other above timing control chips enter the above target working mode in response to the above working mode signal received in the above target level state.

[0069] Specifically, as long as any timing control chip in the host or slave enters the target working mode (wherein the safe working mode includes the waiting stage BLACK / protection screen stage BIST), all timing control chips will enter the target working mode through the working mode signal, and in the target working mode, as long as the host does not send a frame synchronization signal to the slave, the slave will not output video data. The specific process can be referred to Figure 6 .

[0070] Specifically, it should be noted that the slave will ignore any instructions to enter the protection screen stage, including pin_rbf1, pin_rbf2 and Aux channel commands. When the slaves do not receive valid video data from the eDP input, they can enter the black screen waiting stage. Only the host can enter the protection screen stage and indicate which working mode the slave should currently be in during each vertical blanking period. The host will generate a frame synchronization signal during the vertical blanking period (regardless of safe working mode or normal display mode) and synchronize it to the slave. If the slave does not receive a frame synchronization signal from the host in the safe working mode, the slave will not output any data.

[0071] Specifically, the synchronization between the timing control chips within the mode switching time can be ensured through the working mode signal, MS_FAIL_SAFE_TO_NORMAL, and SL_FAIL_SAFE_TO_NORMAL signals. Figure 7 and Figure 8 That is, the switching process from the safe working (FAIL / SAFE) mode to the normal display (NORMAL) mode and from the normal display (NORMAL) mode to the safe working (FAIL / SAFE) mode are respectively shown.

[0072] In order to further prevent the slave from entering the protection screen stage prematurely due to erroneous operation, in one embodiment of the present application, the above method also includes: when each of the above slaves enters the safe working mode and each of the above slaves receives a non-target instruction, the above slave enters the waiting stage of the above safe working mode and does not enter the protection screen stage, the above non-target instruction is an instruction issued by the non-host to control the above slave to enter the above protection screen stage, and the above safe working mode includes the above waiting stage and the above protection screen stage.

[0073] In another embodiment, the method further comprises: when the lookup table parameters of the video processing units of the timing control chips are loaded, the video processing units of the timing control chips are started simultaneously. In this method, each video processing unit starts processing the video signal at the same time, which further ensures the synchronization and coordination between them, thereby further enabling the high-resolution and high-refresh rate display screen to display correctly.

[0074] Specifically, as long as the Look Up Table parameters have not been loaded, the timing control chip will be in the target working mode, and when the data in the EEPROM has not been loaded, the video processing unit that needs to use the LUT parameters will be shielded. Through the above two measures, it is ensured that all video processing units that need the LUT parameters in multiple timing control chips can be started at the same time.

[0075] In another embodiment, the method further includes: after the host sends a frame synchronization signal, when none of the timing control chips receives valid row video data (i.e., valid video data input by eDP), each of the timing control chips controls the row synchronization signal to be in a low level state; when the host receives the valid row video data, and any of the slaves does not receive the valid row video data, each of the timing control chips controls the row synchronization signal to be in the low level state, and the host caches the received valid row video data in an internal delay buffer; after the host receives the valid row video data, when all of the slaves do not receive the valid row video data, each of the timing control chips controls the row synchronization signal to be in a high level state, and the host and the slave simultaneously transmit the valid row video data to the display. In the method, when the transmission starts, the host sends a frame synchronization signal, and each of the timing control chips keeps the row synchronization signal in a low level state when valid row video data is not received. When the host receives valid line video data, but a slave does not receive valid data, each timing control chip will keep the line synchronization signal at a low level and cache the data in the internal buffer. When all slaves receive valid data, the timing control chip will set the line synchronization signal to a high level. At this time, the host and slave simultaneously transmit valid video data to the display. This further ensures the synchronization between the host and slave during the data transmission process.

[0076] Specifically, the FAIL / SAFE images (including black images / protection images) output by multiple TCONs to the panel driver are not delayed, and the number and mode of protection images should be consistent in each TCON. Multiple TCONs can handle the offset of 2 lines of images within eDP (2-line offset refers to the line spacing between the fastest line and the slowest line), and can output video images without delay to the panel driver.

[0077] Specifically, Hsync is generated by the host and slave to solve the problem of video asynchrony between multiple timing control chips. The delayed video data in the host and slave can be cached through the buffer. Fig. 9As shown in the figure, between time point F and time point A', the host releases SYNC_STATE to indicate the start of a new frame (Vsync) of the slave, and transmits 62-bit data between the two; between time point A and B after Vsync is pulled high, no valid row video data is received from the eDP input, and the host and the slave will pull SYNC_VHSYNC low; at time point B, a new row of valid video data is sent from the eDP input of the host, the host will release SYNC_VHSYNC, but the slave is still pulling SYNC_STATE high. TE is pulled low, and the video data that has arrived in the host will be cached in the delay buffer; at time point C, the eDP input of the slave will send a new line of video data, and the slave will release SYNC_VHSYNC; between time points C and D, SYNC_VHSYNC will be pulled high, and 13-bit data will be transmitted between the host and the slave; at time point D, the host and the slave will simultaneously output video data to the panel driver; after the Hsync of the last valid line (time point E), the slave will release SYNC_VHSYNC until time point A'. For the safe working mode, the synchronization method is the same as above.

[0078] Specifically, Fig. 9 , Fig.10 ,like Fig.11 As shown in FIG. 1 , the information transmitted during the first Hsync period (POL, BINV_DATA / RINV_DATA) is not used, but is only used to synchronize the delay data between the timing control chips. Fig.10 As shown, after each Hsync time point D (falling edge), the data in the delay buffer will be read out and written into the line buffer. When there is a whole line of data in the line buffer, the data will be output from the line buffer to the panel driver.

[0079] Specifically, Fig.10As shown, the synchronization method of multiple timing control chips can ensure that the data enable (DE) signal at the panel driver end is synchronized, and all timing control chips can add redundant lines (dummy lines) after the last valid line in the vertical blanking period. All timing control chips use the data enable signal at the panel driver end to generate gate timing signals including POL, and the host will pass the values ​​of POL_SEL and POL2_SEL to the slave during the Vsync period, so the POL and gate timing signals of the Multi-Chip will be synchronized through the synchronization of their panel driver end data enable signals. There are two ways for the slave to generate POL, one is to generate it internally, and the other is to pass the value of POL from the host during each Hsync period, and then generate the final POL value for each output port based on the value of EPI_POL_SEL[14:0] (TCON internal signal, responsible for controlling the POL value of different output ports). As for the selection of these two methods of generating POL signals, they can be selected through the 1-bit register inside the timing control chip.

[0080] Specifically, Fig.12 As shown, during the transmission of a frame of the picture, that is, after the Vsync of the waveform in the figure is pulled high for one cycle, the input data enable signals of the host and slave 1 start to flip after a period of time (skew in the figure), while the data enable signals output by the host and slave 1 to the panel driver start to flip synchronously after being cascaded and synchronized by multiple timing control chips, proving that this method has played the expected role.

[0081] In another embodiment, each of the above-mentioned timing control chips includes a processor, and the above-mentioned method further includes: in the case of transmitting the data to be transmitted to the first predetermined timing control chip, the above-mentioned processor of the above-mentioned first predetermined timing control chip receives the checksum of the above-mentioned data to be transmitted sent by the transmission channel between the above-mentioned host and the above-mentioned slave, and the above-mentioned first predetermined timing control chip is the above-mentioned host or the above-mentioned slave; the above-mentioned processor of the above-mentioned first predetermined timing control chip detects whether the above-mentioned data to be transmitted has an error according to the checksum; in the case of an error, the above-mentioned processor of the above-mentioned first predetermined timing control chip modifies the erroneous data to be transmitted, obtains the modified data to be transmitted, and sends the modified data to be transmitted to the above-mentioned transmission channel. In this method, first, the processor of the first predetermined timing control chip receives the checksum of the data to be transmitted, and this checksum can be used to detect whether an error occurs in the data during the transmission process. If an error is found in the detection of the checksum, the processor will modify the erroneous data to ensure that the transmitted data is correct. Then, the modified data will be sent to the transmission channel, thereby further ensuring that the transmission of data between the host and the slave is safe and accurate.

[0082] Specifically, in order to more flexibly control the transmission process of the host and slave, and to be able to more promptly discover and modify errors in the transmission process, RISC-V CPU and checksum play an important role. Through the checksum, errors in the data transmission process between the host and the slave can be quickly discovered, and at the same time, the RISC-V CPU can modify the erroneous data to further ensure the accuracy of data transmission.

[0083] Specifically, a customized IIC interface is also used for mutual control and data transmission between multiple TCONs. By combining different state machines for control, the transmission of control signals and data signals between different timing control chips can be completed more efficiently and flexibly than the traditional IIC interface. Among them, the names of different state machines are idle state (DDC_IDLE), start state (DDC_START), first slave address sending state (DDC_SLA_ADDR), first write flag state (DDC_WR_FLAG), first slave address sending response state (DDC_1ST_ACK), register address sending state (DDC_REG_ADDR), second response state (DDC_2ND_ACK), restart state (DDC_RE_START), second slave address sending state (DDC_SLA_ADDR_2), second write flag state (DDC_WR_FLAG_2), third response state (DDC_3RD_ACK), single-byte data read state (DDC_BYTE_RD), single-byte data read response state (D I2C_BR_ACK), single-byte data write status (DDC_BYTE_WR), single-byte data write response status (DDC_BW_ACK), read operation status (DDC_CRNT_RD), read operation response status (DDC_CRNT_RD_ACK), write operation status (DDC_CRNT_WR), write operation response status (DDC_CRNT_WR_ACK), stop status (DDC_STOP), error status (DDC_ACC_ERROR), restart start status (I2C_RST_START), write stretch wait status (I2C_STRE_WAIT_WR), read stretch wait status (I2C_STRE_WAIT_RD), second byte register address send status (I2C_DDC_REG_ADDR_2), second byte register address send response status (I2C_DDC_ADDR_2_ACK) and restart status (ADV_RST_STAGE), among which clock stretching is an operation of the I2C protocol, and the last two states are effective when 2-byte address reading and writing are required.

[0084] Specifically, the timing control chip can configure the control signal or data signal of the host or slave through the central processing unit (CPU) in any transmission stage under the multi-timing control chip cascade mode (Multi-Chip) to ensure that the CPU can correct and compensate for the transmission error as soon as it is discovered.

[0085] In order to further ensure that the entire system can synchronously enter the safe working mode, in one embodiment of the present application, each of the above-mentioned timing control chips includes a processor, and the above-mentioned method also includes: the above-mentioned processor detects whether the line spacing between the above-mentioned timing control chip to which it belongs and the valid line video data received by any one of the above-mentioned timing control chips exceeds two lines; when it exceeds two lines, the above-mentioned processor controls the above-mentioned timing control chip to which it belongs to enter the safe working mode / no signal mode, and triggers the above-mentioned working mode signal to enter the above-mentioned low level state; the above-mentioned timing control chip synchronizes the above-mentioned working mode signal in the above-mentioned low level state to other above-mentioned timing control chips, and the other above-mentioned timing control chips enter the above-mentioned safe working mode / above-mentioned no signal mode in response to the above-mentioned working mode signal in the above-mentioned low level state received.

[0086] Specifically, the video data will be cached in a special data queue, and the data readout is related to the synchronization signal (hsync) between the two cascaded chips. When the synchronization signal is delayed, causing the amount of data in the data queue of the chip at the front of the transmission link to exceed the set value (2line), a corresponding two-line offset error indication signal will be generated, causing the state synchronization signal (sync state) to be pulled low.

[0087] Specifically, when there are more than two rows, the processor controls the timing control chip to enter a safe working mode / no signal mode, the chip that detects the offset pulls the state synchronization signal (sync state) low, and other chips enter one of the two modes after detecting that the signal is low.

[0088] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the display method of the display system of the present application will be described in detail below in combination with specific embodiments.

[0089] This embodiment relates to a specific display method of a display system, comprising the following steps:

[0090] Step 1: According to the master-slave indication signal (PIN_MS_SL), the master-slave relationship between the TCONs is determined, one TCON is determined as the master (Master), and the remaining TCONs are determined as slaves (Slave).

[0091] Step 2: In non-touch mode, the Master sends a reference clock signal (REF_CLK) to the Slave, and controls the synchronization state signal (SYNC_STATE) and the line / frame synchronization signal (SYNC_VHSYNC / SYNC_VHSYNC_1) together with the Slave. At the same time, the synchronization clock (SYNC_CLK0 / 1) and the synchronization data signal (SYNC_DATA0 / 1) are used to transmit the TCON working mode, test vector, polarity selection and other information to each other.

[0092] Step 3: Signal transmission in touch mode: In touch mode, the Master additionally sends a specific line / frame synchronization signal (SYNC_VHSYNC_1) to the Slave to meet the special timing requirements of this mode.

[0093] Step 4: After each timing control chip is powered on, the control working mode signal is in a low level state, which is used to indicate the working mode of the timing control chip. When the register configuration is completed, the working mode signal is in a high level state.

[0094] Step 5: Trigger the working mode signal to enter the target working mode, and synchronously send the signal to other timing control chips to achieve synchronous entry into the target working mode.

[0095] Step 6: After the parameters of the video processing unit are loaded, the video processing unit is started at the same time.

[0096] Step 7: The processor detects whether the line spacing exceeds two lines. If so, the control enters the safe working mode / no signal mode to ensure normal display.

[0097] Step 8: Control and modify the configuration of the master and slave machines through the RISC-V CPU, promptly correct the erroneous signals or video data that occur during transmission, and ensure the correctness of data transmission through checksum.

[0098] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0099] An embodiment of the present invention provides a display system, the display system includes a plurality of timing control chips and a display, each of the timing control chips is electrically connected to the display, the display includes a display screen, the display screen includes a plurality of display areas, the timing control chips correspond to the display areas one by one, and the display method of the display system is applied to the display system, wherein each timing control chip in the display system includes:

[0100] processor;

[0101] A master-slave selection pin, connected to the processor for receiving a master-slave selection signal;

[0102] Reference clock signal pin, any two of the above-mentioned reference clock signal pins of the above-mentioned timing control chips are connected;

[0103] Working mode pin, used to indicate the working mode of the above timing control chip;

[0104] A row start pin, the row start pins of any two of the above timing control chips are connected to output a row start signal;

[0105] A frame start pin, the frame start pins of any two of the above timing control chips are connected to output a frame start signal;

[0106] A first synchronization data pin and a second synchronization data pin, wherein the first synchronization data pin of one of the two adjacent timing control chips is connected to the first synchronization data pin of the other, and is used to transmit the first data and the second data between the two corresponding timing control chips;

[0107] A first clock synchronization pin and a second clock synchronization pin, in two adjacent timing control chips, the first clock synchronization pin of one is connected to the second clock synchronization pin of the other, and the first clock synchronization pin and the second clock synchronization pin are respectively used to synchronize the transmission of the first data and the transmission of the second data.

[0108] Specifically, as shown in Table 5, Table 5 shows the input and output pin descriptions of the timing control chip.

[0109] Table 5

[0110]

[0111] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0112] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0113] In the above embodiment, first, the host receives the master-slave selection signal to the above host, and sends the reference clock signal generated after receiving the above master-slave selection signal to the slave; secondly, in the touch mode of the above display screen, the above host sends the line / frame synchronization signal to the above slave, and after the above slave receives the above line / frame synchronization signal, controls the transmission of data to the above display screen synchronously with the above host, so that any two of the above display areas of the above display screen are displayed synchronously; finally, in the non-touch mode of the above display screen, the above host and the above slave synchronously drive the above line / frame synchronization signal according to the above reference clock signal, so that each of the above hosts synchronously transmits data to the above display screen, thereby making any two of the above display areas of the above display screen display synchronously. Compared with the prior art, the solution of the present application can synchronize the working modes and line / frame image display characteristics of each timing control chip through data transmission between the host and the slave, thereby ensuring the synchronous display of each area of ​​the display screen, thereby ensuring that the high refresh rate display screen can be displayed correctly. At the same time, compared with the solution with only one timing control chip, the present application provides multiple timing control chips and divides the display screen into multiple areas, each area is controlled by an independent timing control chip, thus reducing the number of pixels that each timing control chip needs to process, thereby improving the bandwidth utilization of each timing control chip, ensuring that the high refresh rate display screen can be displayed correctly, thereby solving the problem that the prior art cannot meet the correct display of high resolution and high refresh rate display screens.

[0114] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display method of a display system, characterized in that: The display system includes a plurality of timing control chips and a display, each of the timing control chips is electrically connected to the display, the display includes a display screen, the display screen includes a plurality of display areas, the timing control chips correspond to the display areas one by one, and the display method includes: The host receives a master-slave selection signal to the host, and in response to the received master-slave selection signal, sends the generated reference clock signal to the slave, wherein the slave is the other timing control chips among the plurality of timing control chips except the host; In the touch mode of the display screen, the host sends a line / frame synchronization signal to the slave, and the slave controls the transmission of data to the display screen synchronously with the host in response to the received line / frame synchronization signal, so that any two display areas of the display screen are displayed synchronously; In the non-touch mode of the display screen, the host and the slave synchronously drive the row / frame synchronization signal according to the reference clock signal, so that each host synchronously transmits data to the display screen, thereby making any two display areas of the display screen display synchronously.

2. The display method according to claim 1, characterized in that: The method further comprises: After each of the timing control chips is powered on, each of the timing control chips controls the working mode signal to be in a low level state, and the working mode signal is used to indicate the working mode of the timing control chip; After the register configurations of the timing control chips are loaded, the timing control chips control the working mode signal to be in a high level state; When the operating mode signal is in the high level state for a predetermined number of consecutive reference clock signal cycles, each timing control chip controls the hot plug signal to be in the high level state, and triggers each timing control chip to control the operating mode signal to be in the low level state until data needs to be transmitted to the display screen.

3. The display method according to claim 1, characterized in that: The method further comprises: When any one of the timing control chips enters the target working mode, the working mode signal is triggered to be in the target level state and the working mode signal is synchronously sent to the other timing control chips, the target working mode is one of the following: safe working mode, normal display mode, and the target level state is a low level state or a high level state; The other timing control chips enter the target working mode in response to the received working mode signal in the target level state.

4. The display method according to claim 1, characterized in that: The method further comprises: When each of the slaves enters the safe working mode and each of the slaves receives a non-target instruction, the slave enters the waiting phase of the safe working mode and does not enter the protection screen phase. The non-target instruction is an instruction issued by a non-host to control the slave to enter the protection screen phase. The safe working mode includes the waiting phase and the protection screen phase.

5. The display method according to claim 1, characterized in that: The method further comprises: When the lookup table parameters of the video processing units of the timing control chips are loaded completely, the video processing units of the timing control chips are started simultaneously.

6. The display method according to claim 1, characterized in that: The method further comprises: After the host sends a frame synchronization signal, when each of the timing control chips does not receive valid line video data, each of the timing control chips controls the line synchronization signal to a low level state; When the host receives the valid line video data and any of the slaves does not receive the valid line video data, each of the timing control chips controls the line synchronization signal to be in the low level state, and the host caches the received valid line video data in an internal delay buffer; After the host receives the valid line video data, if all the slaves have not received the valid line video data, each of the timing control chips controls the line synchronization signal to a high level state, and the host and the slave simultaneously transmit the valid line video data to the display.

7. The display method according to claim 1, characterized in that: Each of the timing control chips includes a processor, and the method further includes: In the case where there is a need to transmit data to be transmitted to a first predetermined timing control chip, the processor of the first predetermined timing control chip receives a checksum of the data to be transmitted sent by a transmission channel between the host and the slave, and the first predetermined timing control chip is the host or the slave; The processor of the first predetermined timing control chip detects whether the data to be transmitted has errors according to the checksum; In the event of an error, the processor of the first predetermined timing control chip modifies the erroneous data to be transmitted to obtain the modified data to be transmitted, and sends the modified data to be transmitted to the transmission channel.

8. The display method according to claim 1, characterized in that: Each of the timing control chips includes a processor, and the method further includes: The processor detects whether the line spacing between the valid line video data received by the timing control chip to which it belongs and any one of the timing control chips exceeds two lines; In the case of more than two rows, the processor controls the timing control chip to enter a safe working mode / no signal mode, and triggers the working mode signal to enter a low level state; The timing control chip synchronizes the working mode signal in the low level state to other timing control chips, and the other timing control chips enter the safe working mode / the no-signal mode in response to the received working mode signal in the low level state.

9. A display system, characterized in that: The display system includes multiple timing control chips and a display, each of the timing control chips is electrically connected to the display, the display includes a display screen, the display screen includes multiple display areas, the timing control chips correspond to the display areas one by one, and the display system is used to execute the display method described in any one of claims 1 to 8.

10. The display system according to claim 9, characterized in that: Each of the timing control chips comprises: processor; A master-slave selection pin, connected to the processor for receiving a master-slave selection signal; A reference clock signal pin, to which the reference clock signal pins of any two timing control chips are connected; A working mode pin, used to indicate the working mode of the timing control chip; A row start pin, the row start pins of any two timing control chips are connected to output a row start signal; A frame start pin, the frame start pins of any two timing control chips are connected to output a frame start signal; A first synchronization data pin and a second synchronization data pin, wherein the first synchronization data pin of one of the two adjacent timing control chips is connected to the first synchronization data pin of the other, and is used to transmit the first data and the second data between the corresponding two timing control chips; A first clock synchronization pin and a second clock synchronization pin, in two adjacent timing control chips, the first clock synchronization pin of one is connected to the second clock synchronization pin of the other, and the first clock synchronization pin and the second clock synchronization pin are respectively used to synchronize the transmission of the first data and the transmission of the second data.

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