Comparator offset voltage error correction structure

Abstract

The application discloses a comparator offset voltage error correction structure, comprising a short circuit unit, an accumulator, a counter, a digital correction module and an error compensation unit, the digital correction module is used for adjusting the output level value according to the output value of the accumulator when the count value of the counter reaches the preset count threshold, and the error compensation unit is used for generating a corresponding compensation signal to compensate the offset error of the comparator according to the level value output by the digital correction module. In the application, the polarity of the offset voltage is judged according to the number of high levels, and the correction of the comparator offset voltage is completed, so that the offset voltage of the comparator can always be kept within 1 / 4LSB, thereby effectively inhibiting the systematic error caused by the comparator offset.

Description

Technical Field

[0001] This invention belongs to the field of comparator error correction, and in particular relates to a comparator offset voltage error correction structure. Background Technology

[0002] With the development of high-precision ADCs, the systematic offset caused by transistor size mismatch in comparators has become a significant problem. For comparators, an offset error greater than 1 / 2 LSB can lead to serious comparison errors, ultimately affecting the accuracy and output of the entire ADC. Therefore, error correction is needed to correct the comparator's offset voltage. This design, based on an accumulator and counter, combined with a matching DAC module, presents a background algorithm for comparator offset voltage error correction. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a comparator offset voltage error correction structure.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0005] A comparator offset voltage error correction structure, including

[0006] The shorting unit is used to short-circuit the input terminals of the comparator when calibrating the comparator;

[0007] An accumulator is used to accumulate the number of high-level signals in the comparator's output signal;

[0008] A counter is used to count the output signals of a comparator;

[0009] A digital correction module is used to adjust the output level based on the accumulator's output value when the counter's count value reaches a preset count threshold; and

[0010] The error compensation unit is used to generate a corresponding compensation signal based on the level value output by the digital correction module to compensate for the offset error of the comparator.

[0011] Furthermore, the digital correction module includes

[0012] The judgment unit is used to compare the output value of the accumulator with the preset high-level value range when the count value of the counter reaches the preset count threshold, and output the corresponding adjustment signal to the parameter adjustment unit according to the comparison result.

[0013] The parameter adjustment unit is used to adjust the level parameters accordingly based on the received adjustment signal and then output the result to the control code generation unit; and

[0014] The correction level generation unit is used to output the corresponding level value to the error compensation unit according to the level parameter.

[0015] Furthermore, when the output value of the accumulator is higher than the upper limit of the preset high-level value range, the judgment unit outputs a first adjustment signal; when the output value of the accumulator is lower than the lower limit of the preset high-level value range, the judgment unit outputs a second adjustment signal; when the output value of the accumulator is within the preset high-level value range, the judgment unit outputs a third adjustment signal.

[0016] When the parameter adjustment unit receives the first adjustment signal, it steps the level parameter downward and outputs it to the control code generation unit; when the parameter adjustment unit receives the second adjustment signal, it steps the level parameter upward and outputs it to the control code generation unit.

[0017] Furthermore, the correction level generation unit includes

[0018] The control code generation unit is used to generate corresponding control codes based on the level parameters and provide them to the correction level generation unit.

[0019] A DAC unit is used to generate multi-level equally differential level signals; and

[0020] The level selection unit is used to select the corresponding level signal from the level signals generated by the DAC unit according to the control code and send it to the error compensation unit.

[0021] Furthermore, the DAC unit includes comparator amplifier A1, comparator amplifier A2, PMOS transistor M21, NMOS transistor M22, capacitor C1, capacitor C2, resistor R35, resistor R36, resistor R37, resistor R38, and N adjustment resistors with the same resistance value; the non-inverting input terminal of comparator amplifier A1 is used to connect to the positive supply voltage V+, the inverting input terminal of comparator amplifier A1 is electrically connected to its output terminal through capacitor C1, and the inverting input terminal of comparator amplifier A1 is also grounded through resistor R36;

[0022] The output terminal of the comparator amplifier A1 is electrically connected to the gate of the PMOS transistor M21, the source of the PMOS transistor M21 is connected to the supply voltage VDD, and the drain of the PMOS transistor M21 is electrically connected to the inverting input terminal of the comparator amplifier A1 through the resistor R35.

[0023] The drain of the PMOS transistor M21 is also electrically connected to the drain of the NMOS transistor M22 through N series-connected adjustment resistors. The connection terminals of every two adjacent adjustment resistors output a level of equal differential level signal to the level selection unit.

[0024] The drain of the NMOS transistor M22 is electrically connected to the non-inverting input terminal of the comparator amplifier A2 through resistor R37; the source of the NMOS transistor M22 is grounded, and the gate of the NMOS transistor M22 is electrically connected to the output terminal of the comparator amplifier A2.

[0025] The non-inverting input terminal of the comparator amplifier A2 is electrically connected to its output terminal through capacitor C2, and the non-inverting input terminal of the comparator amplifier A2 is also grounded through resistor R38; the inverting input terminal of the comparator amplifier A2 is used to connect to the negative power supply voltage V-.

[0026] Furthermore, the voltage difference between the positive supply voltage V+ and the negative supply voltage V- is 200mV.

[0027] Furthermore, the level values ​​output by the digital correction module include a first level value REF_T1 and a second level value REF_T2. The first level value REF_T1 is obtained based on level parameters, and the second level value REF_T2 is a fixed value. The error compensation unit generates corresponding current signals based on the first level value REF_T1 and the second level value REF_T2 to adjust the charging and discharging speed of the comparator, thereby compensating for the offset error of the comparator.

[0028] Furthermore, the error compensation unit includes NMOS transistors NM7 and NMOS transistors NM8. The gate of NMOS transistor NM7 is connected to a first voltage level value REF_T1, the source of NMOS transistor NM7 is grounded, and the drain of NMOS transistor NM7 is connected to a comparator. The gate of NMOS transistor NM8 is connected to a second voltage level value REF_T2, the source of NMOS transistor NM8 is grounded, and the drain of NMOS transistor NM8 is connected to a comparator.

[0029] Furthermore, the comparator includes inverter D1, inverter D2, PMOS transistors PM1, PM2, PM3, PM4, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, NMOS transistors NM6, NMOS transistors NM9, and NMOS transistors NM10;

[0030] The sources of PMOS transistors PM1, PM2, PM3, and PM4 are all connected to the power supply voltage VDD. The gate of PMOS transistor PM1 is electrically connected to the gate of NMOS transistor NM1 and the drain of PMOS transistor PM2, respectively. The drain of PMOS transistor PM1 is electrically connected to the input terminal of inverter D1 and the drain of NMOS transistor NM1, respectively. The output terminal of inverter D1 serves as the first output terminal of the comparator.

[0031] The gate of PMOS transistor PM2 is electrically connected to the gate of NMOS transistor NM2 and the drain of PMOS transistor PM1, respectively. The drain of PMOS transistor PM2 is electrically connected to the input of inverter D2 and the drain of NMOS transistor NM2, respectively. The output of inverter D2 serves as the second output of comparator.

[0032] The gates of PMOS transistors PM3 and PM4 are both connected to the clock signal CLK. The drain of PMOS transistor PM3 is electrically connected to the source of NMOS transistor NM1, the drain of NMOS transistor NM3, the drain of NMOS transistor NM5, and the drain of NMOS transistor NM8, respectively. The drain of PMOS transistor PM4 is electrically connected to the source of NMOS transistor NM2, the drain of NMOS transistor NM4, the drain of NMOS transistor NM6, and the drain of NMOS transistor NM7, respectively.

[0033] The gate of NMOS transistor NM3 is connected to the input signal Vip, and the gate of NMOS transistor NM4 is connected to the reference voltage signal V. REF14 The sources of NMOS transistors NM3 and NM4 are both electrically connected to the drain of NMOS transistor NM9. The gate of NMOS transistor NM9 is connected to the clock signal CLK, and the source of NMOS transistor NM9 is grounded.

[0034] The gate of the NMOS transistor NM5 is connected to the reference voltage signal V. REF0 The gate of NMOS transistor NM6 is connected to the input signal Vin; the sources of NMOS transistors NM5 and NM6 are both electrically connected to the drain of NMOS transistor NM10; the gate of NMOS transistor NM10 is connected to the clock signal CLK; and the source of NMOS transistor NM10 is grounded.

[0035] Furthermore, the shorting unit includes PMOS transistors PM5, PM6, NMOS transistors NM11 and NM12. The gate of NMOS transistor NM3 is electrically connected to the drain of PMOS transistor PM5 and the source of NMOS transistor NM11, respectively. The gate of NMOS transistor NM4 is electrically connected to the source of PMOS transistor PM5 and the drain of NMOS transistor NM11, respectively. The gate of PMOS transistor PM5 is connected to the clock signal CLK_P, and the gate of NMOS transistor NM11 is connected to the clock signal CLK_N. The gate of NMOS transistor NM5 is also electrically connected to the drain of PMOS transistor PM6 and the source of NMOS transistor NM12, respectively. The gate of NMOS transistor NM6 is also electrically connected to the source of PMOS transistor PM6 and the drain of NMOS transistor NM12, respectively. The gate of PMOS transistor PM6 is connected to the clock signal CLK_P, and the gate of NMOS transistor NM12 is connected to the clock signal CLK_N.

[0036] In this invention, the polarity of the offset voltage is determined by accumulating the number of high and low levels. Then, the current of the correction transistor is controlled by selecting the gate voltage of the correction transistor to correct the comparator offset voltage. This ensures that the comparator offset voltage is always kept within 1 / 4 LSB. Furthermore, the correction range can be adjusted by adjusting the values ​​of the positive supply voltage V+ and the negative supply voltage V- in the DAC unit, as well as by adjusting the number of resistors. This effectively suppresses the systematic error caused by the comparator offset. Attached Figure Description

[0037] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0038] Figure 1 This is a structural block diagram of an embodiment of the comparator offset voltage error correction structure of the present invention.

[0039] Figure 2 This is the circuit diagram of the DAC unit.

[0040] Figure 3 This is a code value diagram of the control code generated during correction in an example.

[0041] Figure 4 This is a circuit diagram of the comparator, shorting unit, and error compensation unit.

[0042] Figure 5 The image shows the simulation data of the comparator before digital correction.

[0043] Figure 6 The image shows the simulation data of the comparator after digital correction. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0045] Please see Figure 1 , Figure 1 This is a structural block diagram of an embodiment of the comparator offset voltage error correction structure of the present invention. The comparator offset voltage error correction structure of this embodiment includes a shorting unit, an accumulator, a counter, a digital correction module, and an error compensation unit. The shorting unit is used to short-circuit the input terminal of the comparator during comparator correction. The accumulator is used to accumulate the number of high-level signals (i.e., signal "1") in the comparator's output signal. The counter is used to count the output signal of the comparator. The digital correction module is used to adjust the output level value according to the output value of the accumulator when the counter's count value reaches a preset counting threshold (e.g., 128 times). The error compensation unit is used to generate a corresponding compensation signal based on the level value output by the digital correction module to compensate for the comparator's offset error.

[0046] Please continue reading. Figure 1 The digital correction module may include a judgment unit, a parameter adjustment unit, and a correction level generation unit. The judgment unit compares the output value of the accumulator with a preset high-level value range when the counter's count value reaches a preset count threshold, and outputs a corresponding adjustment signal to the parameter adjustment unit based on the comparison result. Specifically, when the accumulator's output value is higher than the upper limit of the preset high-level value range, the judgment unit outputs a first adjustment signal; when the accumulator's output value is lower than the lower limit of the preset high-level value range, the judgment unit outputs a second adjustment signal; and when the accumulator's output value is within the preset high-level value range, the judgment unit outputs a third adjustment signal. At this time, the counter and accumulator are restored to their initial state, awaiting the start of the next correction process. The high-level value range can be set according to accuracy requirements. Specifically, when high accuracy is required, the high-level value range can be set to a smaller range. For example, when the count threshold is 128 counts, the high-level value range can be set to 44–84; if high accuracy is required, the high-level value range can be set to 56–72.

[0047] The parameter adjustment unit is used to adjust the level parameter accordingly based on the received adjustment signal and then output it to the control code generation unit. Specifically, when the parameter adjustment unit receives the first adjustment signal, it steps the level parameter downward and then outputs it to the control code generation unit; when the parameter adjustment unit receives the second adjustment signal, it steps the level parameter upward and then outputs it to the control code generation unit.

[0048] The correction level generation unit is used to output a corresponding level value to the error compensation unit according to the level parameters. Please refer to [link / reference]. Figure 2 The correction level generation unit may include a control code generation unit, a DAC unit, and a level selection unit. The control code generation unit is used to generate corresponding control codes for the correction level generation unit based on the level parameters. (See also...) Figure 3 This is a code value diagram of the control code generated in an example, where the correction port signal is the level code value of the correction tube input, and the input signal B... <0> The high and low level signals output by the comparator are used to generate multi-level differential level signals. The level selection unit is used to select the level signal of the corresponding level from the level signals generated by the DAC unit according to the control code and send it to the error compensation unit.

[0049] Please continue reading. Figure 2 In this embodiment, the DAC unit includes comparator amplifier A1, comparator amplifier A2, PMOS transistor M21, NMOS transistor M22, capacitor C1, capacitor C2, resistors R35, R36, R37, R38, and N adjustment resistors with the same resistance value. Comparator amplifiers A1 and A2 are both LDO amplifiers; PMOS transistor M21 and NMOS transistor M22 are both large-size current transistors. In this embodiment, a total of 34 adjustment resistors are provided, namely adjustment resistor R0, adjustment resistor R1, adjustment resistor R2, ..., adjustment resistor R32 and adjustment resistor R33.

[0050] The non-inverting input of the comparator amplifier A1 is connected to the positive supply voltage V+. The inverting input of the comparator amplifier A1 is electrically connected to its output through capacitor C1. The inverting input of the comparator amplifier A1 is also grounded through resistor R36.

[0051] The output terminal of the comparator amplifier A1 is electrically connected to the gate of the PMOS transistor M21. The source of the PMOS transistor M21 is connected to the power supply voltage VDD. The drain of the PMOS transistor M21 is electrically connected to the inverting input terminal of the comparator amplifier A1 through a resistor R35.

[0052] The drain of the PMOS transistor M21 is also electrically connected to the drain of the NMOS transistor M22 through 34 series-connected adjustment resistors. Each pair of adjacent adjustment resistors outputs a level-gradient signal to the level selection unit, thus forming V. <0> 0~V <0> There are 32 levels of voltage level signals in total. The voltage division can be controlled by adjusting the resistance value of resistor R, thereby adjusting the accuracy of the calibration. In this embodiment, the resistance value of a single resistor is preferably 10.69 ohms.

[0053] The drain of the NMOS transistor M22 is electrically connected to the non-inverting input of the comparator amplifier A2 through a resistor R37; the source of the NMOS transistor M22 is grounded, and the gate of the NMOS transistor M22 is electrically connected to the output of the comparator amplifier A2.

[0054] The non-inverting input terminal of the comparator amplifier A2 is electrically connected to its output terminal through capacitor C2, and the non-inverting input terminal of the comparator amplifier A2 is also grounded through resistor R38; the inverting input terminal of the comparator amplifier A2 is used to connect to the negative power supply voltage V-.

[0055] In this embodiment, the voltage difference between the positive supply voltage V+ and the negative supply voltage V- is 200mV. For example, V+ can be set to 650mV and V- to 450mV. This allows for a correction error voltage adjustment of 6.25mV at each stage, with a total adjustment range of ±100mV.

[0056] The digital correction module outputs a level value including a first level value REF_T1 and a second level value REF_T2. The first level value REF_T1 is selected by the level selection unit based on the level parameter V. <0> 0~V <0> The second level value REF_T2 is obtained by selecting a first-level signal from 32, and is a fixed value that does not change with the level parameter. The level selection unit generally selects the middle first-level signal as the second level value REF_T2, such as in this embodiment where the second level value REF_T2 is V. <0> 16. Of course, the initial value of the first level value REF_T1 can also be V. <0> 16. Then, adjust to the previous or next level signal based on the calibration results.

[0057] The error compensation unit generates corresponding current signals based on the first level value REF_T1 and the second level value REF_T2, respectively, to adjust the charging and discharging speed of the comparator, thereby compensating for the comparator's offset error. Please refer to [link / reference]. Figure 4In this embodiment, the error compensation unit includes a pair of correction transistors, namely, NMOS transistor NM7 and NMOS transistor NM8. The gate of NMOS transistor NM7 is connected to a first voltage level value REF_T1, the source of NMOS transistor NM7 is grounded, and the drain of NMOS transistor NM7 is connected to a comparator. The gate of NMOS transistor NM8 is connected to a second voltage level value REF_T2, the source of NMOS transistor NM8 is grounded, and the drain of NMOS transistor NM8 is connected to a comparator.

[0058] Please continue reading. Figure 4 The comparator includes inverters D1 and D2, PMOS transistors PM1, PM2, PM3, and PM4, and NMOS transistors NM1, NM2, NM3, NM4, NM5, NM6, NM9, and NM10. NMOS transistors NM3, NM4, NM5, and NM6 are the input pair, and inverters D1 and D2 are the output shaping inverters.

[0059] Specifically, the sources of PMOS transistors PM1, PM2, PM3, and PM4 are all connected to the power supply voltage VDD. The gate of PMOS transistor PM1 is electrically connected to the gate of NMOS transistor NM1 and the drain of PMOS transistor PM2, respectively. The drain of PMOS transistor PM1 is electrically connected to the input terminal of inverter D1 and the drain of NMOS transistor NM1, respectively. The output terminal of inverter D1 serves as the first output terminal of the comparator.

[0060] The gate of PMOS transistor PM2 is electrically connected to the gate of NMOS transistor NM2 and the drain of PMOS transistor PM1, respectively. The drain of PMOS transistor PM2 is electrically connected to the input of inverter D2 and the drain of NMOS transistor NM2, respectively. The output of inverter D2 serves as the second output of comparator.

[0061] The gates of PMOS transistors PM3 and PM4 are both connected to the clock signal CLK. The drain of PMOS transistor PM3 is electrically connected to the source of NMOS transistor NM1, the drain of NMOS transistor NM3, the drain of NMOS transistor NM5, and the drain of NMOS transistor NM8, respectively. The drain of PMOS transistor PM4 is electrically connected to the source of NMOS transistor NM2, the drain of NMOS transistor NM4, the drain of NMOS transistor NM6, and the drain of NMOS transistor NM7, respectively.

[0062] The gate of NMOS transistor NM3 is connected to the input signal Vip, and the gate of NMOS transistor NM4 is connected to the reference voltage signal V.REF14 The sources of NMOS transistors NM3 and NM4 are electrically connected to the drain of NMOS transistor NM9. The gate of NMOS transistor NM9 is connected to the clock signal CLK, and the source of NMOS transistor NM9 is grounded.

[0063] The gate of the NMOS transistor NM5 is connected to the reference voltage signal V. REF0 The gate of NMOS transistor NM6 is connected to the input signal Vin; the sources of NMOS transistors NM5 and NM6 are both electrically connected to the drain of NMOS transistor NM10; the gate of NMOS transistor NM10 is connected to the clock signal CLK; and the source of NMOS transistor NM10 is grounded.

[0064] Please continue reading. Figure 4 The shorting unit includes PMOS transistors PM5, PM6, NMOS transistors NM11 and NMOS transistors NM12. PMOS transistors PM5, PM6, NMOS transistors NM11 and NMOS transistors NM12 form a switching structure for controlling the shorting of the input pair transistors. The gate of NMOS transistor NM3 is electrically connected to the drain of PMOS transistor PM5 and the source of NMOS transistor NM11, respectively. The gate of NMOS transistor NM4 is electrically connected to the source of PMOS transistor PM5 and the drain of NMOS transistor NM11, respectively. The gate of PMOS transistor PM5 is connected to the clock signal CLK_P, and the gate of NMOS transistor NM11 is connected to the clock signal CLK_N. The gate of NMOS transistor NM5 is also electrically connected to the drain of PMOS transistor PM6 and the source of NMOS transistor NM12, respectively. The gate of NMOS transistor NM6 is also electrically connected to the source of PMOS transistor PM6 and the drain of NMOS transistor NM12, respectively. The gate of PMOS transistor PM6 is connected to the clock signal CLK_P, and the gate of NMOS transistor NM12 is connected to the clock signal CLK_N. The clock signals CLK_P and CLK_N are used to short-circuit the input terminals of the comparator during calibration.

[0065] The working principle of this embodiment is as follows:

[0066] Please see Figures 1 to 4 Taking a counting threshold of 128 and a high-level value range of 56 to 72 as an example, when the calibration starts, the clock signals CLK_P and CLK_N short-circuit the input pair of the comparator, the counter counts the output signal of the comparator, and at the same time, the accumulator accumulates the number of high-level signals (i.e. "1") in the output signal of the comparator.

[0067] When the counter reaches 128, the judgment unit compares the accumulator output value with the high-level value range. If the accumulator output value is greater than 72, the level parameter is stepped down to generate a control code. The level selection unit selects the next stage level value of the DAC unit as the first level value REF_T1 based on the control code, thus setting the first level value REF_T1 from V... <0> 16 adjusted to V <0> 15. By changing the input voltage of the gate of NMOS transistor NM7, the output current of the drain of NMOS transistor NM7 can be changed. By changing the current at node B, the charging and discharging speed of the comparator can be changed, thereby performing the first compensation for the offset error of the comparator.

[0068] Then, the second correction process begins. If the accumulator output value is still greater than 72, the level parameter continues to step down, causing the first level value REF_T1 to decrease from V. <0> 15 adjusted to V <0> 14. Change the current at node B again to compensate for the comparator's offset error. Then perform correction again until the accumulator's output value is within the high-level range, thus completing the compensation for the comparator's offset error. During this process, since the second level value REF_T2 is always V... <0> 16. Therefore, the current at node A remains unchanged.

[0069] Similarly, if the accumulator output value is less than 56 during the first calibration, the level parameter will be stepped up to generate a control code, thereby causing the first level value REF_T1 to change from V... <0> 16 adjusted to V <0> 17; Then perform the correction again until the accumulator output value is within the high-level value range, thus completing the compensation for the comparator's offset error. Because V <0> 16 is the middle level value, and there are only 16 levels of level values ​​above or below it. Therefore, at most 16 corrections are needed to complete the offset voltage error correction process of the comparator.

[0070] Please see Figure 5 and Figure 6 Tcpar_I and Tcpar_Q are the analog signals after the comparator output has been requantized by the DAC. ENOB is the number of effective bits of the post-simulation data of the comparator. After the correction structure in this embodiment, ENOB is improved from 3.61dB to 3.82dB, thereby effectively improving the linearity of the comparator.

[0071] In this embodiment, the polarity of the offset voltage is determined by accumulating the number of high and low levels. Then, the current of the correction transistor is controlled by selecting the gate voltage of the correction transistor to correct the comparator offset voltage. By introducing an offset voltage correction algorithm, the comparator offset voltage can be kept within 1 / 4 LSB, and the offset voltage correction range can achieve a voltage difference of ±100mV. Furthermore, the correction range can be adjusted by changing the values ​​of the positive and negative supply voltages V+ and V- in the DAC unit, as well as adjusting the number of resistors. Therefore, the comparator offset voltage correction algorithm in this embodiment can effectively suppress the systematic error caused by comparator offset.

[0072] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A comparator offset voltage error correction structure, characterized in that: include The shorting unit is used to short-circuit the input terminals of the comparator when calibrating the comparator; An accumulator is used to accumulate the number of high-level signals in the comparator's output signal; A counter is used to count the output signals of a comparator; The digital correction module is used to adjust the output level based on the output value of the accumulator when the counter value reaches a preset counting threshold. as well as The error compensation unit is used to generate a corresponding compensation signal based on the level value output by the digital correction module to compensate for the offset error of the comparator. The digital correction module includes The judgment unit is used to compare the output value of the accumulator with the preset high-level value range when the count value of the counter reaches the preset count threshold, and output the corresponding adjustment signal to the parameter adjustment unit according to the comparison result; The parameter adjustment unit is used to adjust the level parameters accordingly based on the received adjustment signal and then output the result to the control code generation unit. as well as The correction level generation unit is used to output the corresponding level value to the error compensation unit according to the level parameter. The digital correction module outputs a level value including a first level value REF_T1 and a second level value REF_T2. The first level value REF_T1 is obtained based on level parameters, and the second level value REF_T2 is a fixed value. The error compensation unit generates corresponding current signals based on the first level value REF_T1 and the second level value REF_T2 to adjust the charging and discharging speed of the comparator, thereby compensating for the offset error of the comparator.

2. The comparator offset voltage error correction structure as described in claim 1, characterized in that: When the output value of the accumulator is higher than the upper limit of the preset high-level value range, the judgment unit outputs a first adjustment signal; when the output value of the accumulator is lower than the lower limit of the preset high-level value range, the judgment unit outputs a second adjustment signal; when the output value of the accumulator is within the preset high-level value range, the judgment unit outputs a third adjustment signal. When the parameter adjustment unit receives the first adjustment signal, it steps the level parameter downward and outputs it to the control code generation unit; when the parameter adjustment unit receives the second adjustment signal, it steps the level parameter upward and outputs it to the control code generation unit.

3. The comparator offset voltage error correction structure as described in claim 1, characterized in that: The correction level generation unit includes The control code generation unit is used to generate corresponding control codes based on the level parameters and provide them to the correction level generation unit. The DAC unit is used to generate multi-level equal-differential level signals; as well as The level selection unit is used to select the corresponding level signal from the level signals generated by the DAC unit according to the control code and send it to the error compensation unit.

4. The comparator offset voltage error correction structure as described in claim 3, characterized in that: The DAC unit includes comparator amplifier A1, comparator amplifier A2, PMOS transistor M21, NMOS transistor M22, capacitor C1, capacitor C2, resistor R35, resistor R36, resistor R37, resistor R38, and N adjustment resistors with the same resistance value. The non-inverting input terminal of comparator amplifier A1 is used to connect to the positive supply voltage V+, the inverting input terminal of comparator amplifier A1 is electrically connected to its output terminal through capacitor C1, and the inverting input terminal of comparator amplifier A1 is also grounded through resistor R36. The output terminal of the comparator amplifier A1 is electrically connected to the gate of the PMOS transistor M21, the source of the PMOS transistor M21 is connected to the supply voltage VDD, and the drain of the PMOS transistor M21 is electrically connected to the inverting input terminal of the comparator amplifier A1 through the resistor R35. The drain of the PMOS transistor M21 is also electrically connected to the drain of the NMOS transistor M22 through N series-connected adjustment resistors. The connection terminals of every two adjacent adjustment resistors output a level of equal differential level signal to the level selection unit. The drain of the NMOS transistor M22 is electrically connected to the non-inverting input terminal of the comparator amplifier A2 through resistor R37. The source of the NMOS transistor M22 is grounded, and the gate of the NMOS transistor M22 is electrically connected to the output terminal of the comparator amplifier A2. The non-inverting input terminal of the comparator amplifier A2 is electrically connected to its output terminal through capacitor C2, and the non-inverting input terminal of the comparator amplifier A2 is also grounded through resistor R38; the inverting input terminal of the comparator amplifier A2 is used to connect to the negative power supply voltage V-.

5. The comparator offset voltage error correction structure as described in claim 4, characterized in that: The voltage difference between the positive supply voltage V+ and the negative supply voltage V- is 200mV.

6. The comparator offset voltage error correction structure as described in any one of claims 1 to 5, characterized in that: The error compensation unit includes NMOS transistors NM7 and NMOS transistors NM8. The gate of NMOS transistor NM7 is connected to a first voltage level value REF_T1, the source of NMOS transistor NM7 is grounded, and the drain of NMOS transistor NM7 is connected to a comparator. The gate of NMOS transistor NM8 is connected to a second voltage level value REF_T2, the source of NMOS transistor NM8 is grounded, and the drain of NMOS transistor NM8 is connected to a comparator.

7. The comparator offset voltage error correction structure as described in claim 6, characterized in that: The comparator includes inverter D1, inverter D2, PMOS transistor PM1, PMOS transistor PM2, PMOS transistor PM3, PMOS transistor PM4, NMOS transistor NM1, NMOS transistor NM2, NMOS transistor NM3, NMOS transistor NM4, NMOS transistor NM5, NMOS transistor NM6, NMOS transistor NM9 and NMOS transistor NM10; The sources of PMOS transistors PM1, PM2, PM3, and PM4 are all connected to the power supply voltage VDD. The gate of PMOS transistor PM1 is electrically connected to the gate of NMOS transistor NM1 and the drain of PMOS transistor PM2, respectively. The drain of PMOS transistor PM1 is electrically connected to the input terminal of inverter D1 and the drain of NMOS transistor NM1, respectively. The output terminal of inverter D1 serves as the first output terminal of the comparator. The gate of PMOS transistor PM2 is electrically connected to the gate of NMOS transistor NM2 and the drain of PMOS transistor PM1, respectively. The drain of PMOS transistor PM2 is electrically connected to the input of inverter D2 and the drain of NMOS transistor NM2, respectively. The output of inverter D2 serves as the second output of comparator. The gates of PMOS transistors PM3 and PM4 are both connected to the clock signal CLK. The drain of PMOS transistor PM3 is electrically connected to the source of NMOS transistor NM1, the drain of NMOS transistor NM3, the drain of NMOS transistor NM5, and the drain of NMOS transistor NM8, respectively. The drain of PMOS transistor PM4 is electrically connected to the source of NMOS transistor NM2, the drain of NMOS transistor NM4, the drain of NMOS transistor NM6, and the drain of NMOS transistor NM7, respectively. The gate of NMOS transistor NM3 is connected to the input signal Vip, and the gate of NMOS transistor NM4 is connected to the reference voltage signal V. REF14 The sources of NMOS transistors NM3 and NM4 are both electrically connected to the drain of NMOS transistor NM9. The gate of NMOS transistor NM9 is connected to the clock signal CLK, and the source of NMOS transistor NM9 is grounded. The gate of the NMOS transistor NM5 is connected to the reference voltage signal V. REF0 The gate of NMOS transistor NM6 is connected to the input signal Vin; the sources of NMOS transistors NM5 and NM6 are both electrically connected to the drain of NMOS transistor NM10; the gate of NMOS transistor NM10 is connected to the clock signal CLK; and the source of NMOS transistor NM10 is grounded.

8. The comparator offset voltage error correction structure as described in claim 7, characterized in that: The shorting unit includes PMOS transistors PM5, PM6, NMOS transistors NM11 and NM12. The gate of NMOS transistor NM3 is electrically connected to the drain of PMOS transistor PM5 and the source of NMOS transistor NM11, respectively. The gate of NMOS transistor NM4 is electrically connected to the source of PMOS transistor PM5 and the drain of NMOS transistor NM11, respectively. The gate of PMOS transistor PM5 is connected to the clock signal CLK_P, and the gate of NMOS transistor NM11 is connected to the clock signal CLK_N. The gate of NMOS transistor NM5 is also electrically connected to the drain of PMOS transistor PM6 and the source of NMOS transistor NM12, respectively. The gate of NMOS transistor NM6 is also electrically connected to the source of PMOS transistor PM6 and the drain of NMOS transistor NM12, respectively. The gate of PMOS transistor PM6 is connected to the clock signal CLK_P, and the gate of NMOS transistor NM12 is connected to the clock signal CLK_N.

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