Clock synchronization method, device, equipment and industrial network system
By sending clock synchronization messages to target slaves in the industrial network system and updating synchronization parameters, the problem of inaccurate clock synchronization caused by delay asymmetry between the master and slaves is solved, and high-precision clock synchronization is achieved.
Patent Information
- Application Number
- CN202510010476.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-22
AI Technical Summary
In the prior art, the round-trip delay difference between the master station and the slave station in the industrial network system is very large, resulting in inaccurate clock synchronization and large errors.
By sending a clock synchronization message to the target slave station, including synchronization parameters and time delay errors, the target slave station calculates the reference reception time and corrects the time delay error based on these parameters. The main station updates the synchronization parameters based on the corrected time delay error. Until the time delay meets the error threshold, the timing message is sent for clock synchronization.
Through gradual approximation, the accuracy of clock synchronization is improved, effectively solving the problems of inaccurate clock synchronization and large errors caused by round-trip delay asymmetry.
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Figure CN119865272A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of clock synchronization technology, and in particular to a clock synchronization method, device, equipment and industrial network system. Background Art
[0002] Currently, there are many ways to synchronize clocks. For example, according to the number of steps, it can be divided into single-step clock synchronization and two-step clock synchronization, or according to the device role, it can be divided into E2E, P2P and other methods.
[0003] Whether it is single-step clock synchronization, two-step clock synchronization, E2E clock synchronization or P2P clock synchronization, the calculation is based on the premise that the path delays from master->slave and slave->master are the same. However, the round-trip delay between the master station and the slave station in the industrial network system is very different, which leads to inaccurate clock synchronization and large errors. Summary of the invention
[0004] In view of this, the embodiments of the present application provide a clock synchronization method, device, equipment and industrial network system, which can effectively solve the problems of inaccurate clock synchronization and large errors caused by asymmetric round-trip delay in the prior art.
[0005] In a first aspect, an embodiment of the present application provides a clock synchronization method, applicable to a master station, comprising:
[0006] Sending a clock synchronization message to a target slave station; the clock synchronization message includes synchronization parameters and delay error;
[0007] The clock synchronization message is used for the target slave station to calculate a reference receiving time of the clock synchronization message according to the synchronization parameter and the delay error, and to correct the delay error according to the reference receiving time and the local receiving time of the clock synchronization message;
[0008] updating the synchronization parameter according to the corrected delay error returned by the target slave station;
[0009] Repeat sending a clock synchronization message to the target slave station until the latest delay error returned by the target slave station meets the error threshold, then send a timing message to the target slave station according to the synchronization parameter corresponding to the latest delay error, and the timing message is used for the target slave station to synchronize its own clock.
[0010] In some embodiments, the synchronization parameters include a basic link delay, a standard clock deviation, and a message sending time corresponding to the clock synchronization message;
[0011] The message sending time is used to calculate the reference receiving time with the basic link delay, the standard clock deviation and the delay error;
[0012] The updating of the synchronization parameter according to the corrected delay error returned by the target slave station comprises:
[0013] Updating the basic link delay according to the corrected delay error returned by the target slave station;
[0014] The sending a timing message to the target slave station according to the synchronization parameter corresponding to the latest delay error includes:
[0015] A timing message is constructed according to the sending time of the timing message, the updated basic link delay, the standard clock deviation and the corrected delay error, and is sent to the target slave station.
[0016] In some embodiments, the method further comprises:
[0017] Sending a pulse request signal to the target slave station through a single-line communication line and receiving a pulse response signal fed back by the target slave station, and correspondingly recording the sending time and the receiving time to obtain a third time and a sixth time; wherein the pulse request signal includes at least two pulse signals;
[0018] Sending time request information to the target slave station via a two-wire communication line; the time request information is used for each slave station to verify whether it is the target slave station, and to instruct the target slave station to feed back time response information to the master station; the time response information includes a fourth time and a fifth time; the fourth time is the time when the target slave station receives the pulse request signal; the fifth time is the time when the target slave station sends the pulse response signal;
[0019] The standard clock deviation is calculated according to the third time, the fourth time, the fifth time and the sixth time.
[0020] In some embodiments, the method further comprises:
[0021] Recording the sending time of the time request information to obtain the first time;
[0022] Record the receiving time of the time response information to obtain an eighth time; the time response information also includes a second time and a seventh time; the second time is the time when the target slave station receives the time request information; the seventh time is the time when the target slave station sends the time response information;
[0023] The basic link delay is calculated according to the first time, the second time, the seventh time and the eighth time.
[0024] In some embodiments, the method further comprises:
[0025] Determining whether the round-trip delay between the master station and the target slave station is symmetrical according to the seventh time, the eighth time, the basic link delay and the standard clock deviation;
[0026] If it is determined that the round-trip delay is asymmetric, it is determined to send a clock synchronization message to the target slave station.
[0027] In some embodiments, sending the time request information to the target slave station through the two-wire communication line includes:
[0028] Filling the first message type value into the message field included in the precision clock protocol frame to be generated;
[0029] According to the precise clock protocol frame format, time request information is generated and sent to the target slave station through the two-wire communication line.
[0030] In some embodiments, the precision clock protocol frame further includes a data area;
[0031] The time response information is also generated according to the precise clock protocol frame format; wherein the data area includes four time fields; the second message type is stored in the message field; the four time fields are used to correspondingly store the fourth time, the fifth time, the second time and the seventh time;
[0032] The method further includes: identifying the time response information according to the second message type, and parsing the time response information to obtain the fourth time, the fifth time, the second time, and the seventh time.
[0033] In a second aspect, an embodiment of the present application provides a clock synchronization device, applicable to a master station, including:
[0034] A message sending module, configured to send a clock synchronization message to the target slave station; the clock synchronization message includes a synchronization parameter and a delay error; the clock synchronization message is used for the target slave station to calculate a reference receiving time of the clock synchronization message according to the synchronization parameter and the delay error, and to correct the delay error according to the reference receiving time and the local receiving time of the clock synchronization message;
[0035] A parameter updating module, used for updating the synchronization parameter according to the corrected delay error returned by the target slave station;
[0036] The error judgment and timing module is used to repeatedly send clock synchronization messages to the target slave station until the latest delay error returned by the target slave station meets the error threshold, and then send a timing message to the target slave station according to the synchronization parameters corresponding to the latest delay error, and the timing message is used for the target slave station to synchronize its own clock.
[0037] In a third aspect, an embodiment of the present application provides a terminal device, the terminal device comprising a processor and a memory, the memory storing a computer program, and the processor being used to execute the computer program to implement a clock synchronization method provided in the first aspect of the present application.
[0038] In a fourth aspect, an embodiment of the present application provides an industrial network system, comprising: a master station and at least one slave station; the master station and the at least one slave station are both provided with a clock pulse signal port;
[0039] The master station and the adjacent slave station are connected via a single-line communication line through corresponding clock pulse signal ports; if there are two or more slave stations, each slave station is also connected in sequence via a single-line communication line through its own clock pulse signal port; the master station is also connected to at least one slave station via a two-line communication line;
[0040] The master station is used to implement a clock synchronization method provided in the first aspect of the present application to synchronize the clocks of each of the slave stations.
[0041] The embodiments of the present application have the following beneficial effects:
[0042] The present application sends a clock synchronization message to the target slave station; the clock synchronization message includes synchronization parameters and delay error; the clock synchronization message is used for the target slave station to calculate the reference reception time of the clock synchronization message according to the synchronization parameters and the delay error, and correct the delay error according to the reference reception time and the local reception time of the clock synchronization message; the synchronization parameters are updated according to the corrected delay error returned by the target slave station; the clock synchronization message is repeatedly sent to the target slave station until the latest delay error returned by the target slave station meets the error threshold, and then a timing message is sent to the target slave station according to the synchronization parameters corresponding to the latest delay error, and the timing message is used for the target slave station to synchronize its own clock. The present application repeatedly sends clock synchronization messages to the slave station, and corrects the delay error multiple times, gradually approaching, thereby ensuring simultaneous synchronization between the master station and the slave station, which can effectively solve the problems of inaccurate clock synchronization and large errors caused by asymmetric round-trip delays in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0044] Figure 1 A schematic diagram of a single-step clock synchronization process involved in an embodiment of the present application is shown;
[0045] Figure 2 A schematic diagram of a two-step clock synchronization process involved in an embodiment of the present application is shown;
[0046] Figure 3 A schematic diagram of an E2E clock synchronization process involved in an embodiment of the present application is shown;
[0047] Figure 4 A schematic diagram of a PTP clock synchronization process involved in an embodiment of the present application is shown;
[0048] Figure 5 A structural block diagram of an industrial network system according to an embodiment of the present application is shown;
[0049] Figure 6 A schematic diagram of the PTP protocol frame format in the clock synchronization method in an embodiment of the present application is shown;
[0050] Figure 7 A flow chart of a clock synchronization method according to an embodiment of the present application is shown;
[0051] Figure 8 The first timing diagram in the clock synchronization method of the embodiment of the present application is shown;
[0052] Fig. 9 A schematic diagram of a frame format corresponding to a clock synchronization request message in a clock synchronization method according to an embodiment of the present application is shown;
[0053] Fig.10 A schematic diagram of a frame format corresponding to a clock synchronization response message in a clock synchronization method according to an embodiment of the present application is shown;
[0054] Fig.11 A schematic diagram showing an output of a pulse request signal and a pulse response signal in a clock synchronization method according to an embodiment of the present application is shown;
[0055] Fig.12 A second timing diagram in the clock synchronization method according to an embodiment of the present application is shown;
[0056] Fig.13A schematic diagram of a frame format corresponding to time response information of a clock synchronization method according to an embodiment of the present application is shown;
[0057] Fig.14 A schematic diagram of the frame format corresponding to the time request information of the clock synchronization method according to an embodiment of the present application is shown. DETAILED DESCRIPTION
[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0059] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0060] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.
[0061] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.
[0062] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0063] like Figure 1The figure shows the single-step clock synchronization process, which specifically includes: the master sends a Sync packet to the slave, which contains the current time t1 of the master when the packet is sent. If the transmission time required for the packet to be transmitted from the master to the slave is D, then when the slave receives the information, the current time of the master has become t1+D. If the current time of the slave is t2, then the time difference between them is offset=t2-(t1+D). If the master sends a Sync packet when its current time is 15:00, which contains the time t1, i.e., 15:00, and the slave receives the Sync packet when its current time is 15:40, and the receiving time is t2. The slave sees that the data in the packet shows that the sending time of the Sync packet is 15:00 of the master. If the slave already knows that it takes 30 minutes to transmit messages between it and the master, then it can easily calculate that it is now 10 minutes faster than the master, otherwise it should be 15:30 now.
[0064] like Figure 2 The figure shows the two-step clock synchronization process. In the one-step clock synchronization process, the Sync packet directly carries the sending time of the Sync packet. The only difference between the two-step clock synchronization process and the one-step clock synchronization process is that the sending time of the Sync packet is no longer directly placed in the Sync packet. Instead, a follow-up packet (follow_up packet) is sent immediately after the Sync packet is sent, and the sending time of the Sync packet is placed in the follow_up packet. For example, the master sends a synchronization packet (Sync packet) to the slave when its current time is 15:00, but the Sync packet does not contain the sending time. The slave receives the Sync packet when its current time is 15:40, and the time point is t2. So far, the slave does not know when the Sync packet was sent (t1). Everything else is exactly the same as the one-step process, so it will continue to wait for the subsequent follow_up packet. The master sent a follow_up packet at 15:10, so the slave received the follow_up packet at 15:50. However, the slave does not care about the sending and receiving time of the follow_up packet at all, because now the only difference is the sending time of the Sync packet, and the sending time of the Sync is included in the follow_up packet.
[0065] like Figure 3The E2E clock synchronization process shown in the figure assumes that the message delivery time D is known in time synchronization, but in fact, this first time is unknown, so it needs to be calculated. E2E means End to End. As the name suggests, it goes from one end point to another. E2E must be accompanied by a time synchronization package (Sync package) (if it is a two-step process, it also includes a follow-up package (follow_up) package)). Its calculation is also very simple. The master sends a Sync packet to the slave at t1. The slave receives the Sync packet at t2. The slave knows t1 and t2, so t2-t1=D+offset. The slave sends a delay request packet (Delay_Req) to the master at t3. The master receives it at t4. Then the master fills the receiving time t4 into the delay response packet Delay_Resp and sends it back to the slave. The slave knows t4 and t3. According to t4-t3=D+(-offset), t4-t3+t2-t1=2D, thus eliminating the offset. You only need to divide it by 2 to calculate the time of D. Or from the above figure, t-ms is the path delay from the master to the slave, and t-sm is the path delay from the slave to the master. The value of t-ms+t-sm can be calculated by using t4-t1-(t3-t2). When t-ms=t-sm, D=t-ms=t-sm, so we only need to divide the result by 2. Figure 4 The P2P clock synchronization process is shown.
[0066] In order to solve the clock synchronization problem caused by asymmetric round-trip delay, the present application proposes a clock synchronization method, device, equipment and industrial network system, which adopts a step-by-step approximation method to achieve clock synchronization requirements according to the clock accuracy set according to the user threshold.
[0067] Figure 5 A structural block diagram of an industrial network system according to an embodiment of the present application is shown. Exemplarily, the industrial network system comprises: a master station and at least one slave station; the master station and the at least one slave station are both provided with a clock pulse signal port.
[0068] The master station and the adjacent slave station are connected via a single-line communication line through the corresponding clock pulse signal ports; for example, each device of the master station and the slave station reserves a single-cable clock pulse signal port, and the clock pulse signal port is used for clock synchronization. If there are two or more slave stations, each slave station is also connected in sequence through its own clock pulse signal port via a single-line communication line. The single-line communication line is a fiber core used to carry pulse group signals. If there are multiple slave stations, the slave station reserves another single-cable channel for outputting pulse signals, which is used to send the pulse group signal to the next slave station until the last slave station. Among them, the pulse group signal includes at least two pulse signals. Exemplarily, a 100Mbps network cable uses a reserved single line for carrying pulse groups, and 1000Mbps requires an additional cable to carry pulse groups.
[0069] The master station is also connected to the at least one slave station via a two-wire communication line, such as a network cable, optical fiber, etc.
[0070] The master station is used to implement the clock synchronization method of the embodiment of the present application to synchronize the clock of the slave station. The master station and the slave station communicate through a two-wire communication line using a precision clock protocol PTP (Precision Timing Protocol). The PTP protocol frame format is as follows: Figure 6 As shown, the description of the specific fields is shown in Table 1 and Table 2:
[0071] Table 1 PTP protocol frame format
[0072]
[0073]
[0074]
[0075]
[0076] Table 2 Flag field interpretation
[0077]
[0078] The clock synchronization method is described below in conjunction with some specific embodiments.
[0079] Figure 7 A flow chart of a clock synchronization method according to an embodiment of the present application is shown. Exemplarily, the clock synchronization method comprises the following steps:
[0080] S100, sending a clock synchronization message to the target slave station; the clock synchronization message includes synchronization parameters and delay error. The synchronization parameters and delay error are used by the target slave station to calculate a reference receiving time for receiving the clock synchronization message. The clock synchronization message is generated in a precise clock protocol frame format according to the synchronization parameters and the delay error.
[0081] The clock synchronization message is used by the target slave station to calculate a reference receiving time of the clock synchronization message according to the synchronization parameter and the delay error, and to correct the delay error according to the reference receiving time and the local receiving time of the clock synchronization message. After the target slave station receives the clock synchronization message, it calculates a reference receiving time for receiving the clock synchronization message according to the synchronization parameter and the delay error, and corrects the delay error according to the difference between the reference receiving time and the local receiving time for receiving the clock synchronization message.
[0082] S200: Update the synchronization parameter according to the corrected delay error returned by the target slave station.
[0083] Since it is uncertain whether the round-trip delay between the master station and the target slave station is symmetrical, the basic link delay cannot represent the downlink delay. This application corrects the delay error by gradually correcting the basic link delay to obtain an accurate downlink delay. The downlink delay is the link delay from the master station to the target slave station. Among them, the basic link delay in the clock synchronization message sent for the first time is half of the round-trip link delay.
[0084] S300, repeatedly sending a clock synchronization message to the target slave station until the latest delay error returned by the target slave station meets the error threshold, and then sending a timing message to the target slave station according to the synchronization parameter corresponding to the latest delay error, wherein the timing message is used for the target slave station to synchronize its own clock.
[0085] When the delay error does not meet the error threshold, it is necessary to send a clock synchronization message to the target slave station again based on the corrected delay error and synchronization parameters. The target slave station needs to correct the delay error again based on the local receiving time and the reference receiving time calculated this time until the delay error meets the error threshold. Therefore, the present application improves the accuracy of clock synchronization by a step-by-step approach. Among them, the error threshold can be set to 0. That is, the difference between the local receiving time and the reference receiving time is 0.
[0086] In one embodiment, Figure 8As shown, the synchronization parameters include the basic link delay, the standard clock deviation and the message sending time corresponding to the clock synchronization message. The message sending time is used to calculate the reference receiving time with the basic link delay, the standard clock deviation and the delay error. The calculation formula of the reference receiving time is as follows:
[0087] T th =T1”+T Offset +T1' delay +T diff
[0088] Among them, T th is the reference receiving time; T1” is the message sending time; T Offset is the standard clock deviation; T1' delay is the basic link delay. The basic link delay in the first sent clock synchronization message is half of the round-trip link delay. diff is the delay error received by the target slave from the master.
[0089] In step S200, updating the synchronization parameter according to the corrected delay error returned by the target slave station includes:
[0090] The basic link delay is updated according to the corrected delay error returned by the target slave station. The target slave station subtracts the reference reception time from the local reception time to obtain the difference, indicating that the one-way link delay is inaccurate, and it is necessary to correct the delay error according to the difference, that is, the delay error is equal to the above difference; then the master station adds the corrected delay error to the basic link delay. If the difference is positive, it means that the corresponding downlink link delay from the master station to the target slave station is too small, then the link time is added with the difference. If the difference is negative, it means that the corresponding downlink link delay from the master station to the target slave station is too large, then the link time is added with the negative difference.
[0091] In step S300, sending a timing message to the target slave station according to the synchronization parameter corresponding to the latest delay error includes:
[0092] According to the sending time of the timing message, the updated basic link delay, the standard clock deviation and the corrected delay error, a timing message is constructed and sent to the target slave station. After multiple timings, an accurate downlink delay (final basic link delay) and a small delay error are obtained, for example, the delay error is equal to 0. When the target slave station synchronizes the clock, the sending time of the timing message + the final basic link delay + the standard clock deviation + the delay error is equal to the time point of receiving the timing message of the target slave station.
[0093] In the embodiment of the present application, both the master and the target slave have their own clocks. Figure 8 As shown in the figure, the master time is 00:00 and the slave time is 18:00. Assuming that the round-trip delay between the master station and the target slave station is asymmetric, the downlink delay corresponding to master->slave is 15 minutes, and the uplink delay corresponding to slave->master is 5 minutes. Specifically, the clock synchronization process includes the following steps:
[0094] Step 01, the master sends a clock synchronization message to the slave, where the clock synchronization message contains the master's sending timestamp T1", T Offset , basic link delay and delay error T diff , the master sends the message at T1", T1" is 00:10, T Offset is 18:00, the basic link delay is 10 minutes, T diff is 0min.
[0095] The format of the clock synchronization request message sent by the master is as follows Fig. 9 The clock synchronization request message sent by the master only uses the reserved value 0x6 of the PTP v2 messageId. The data area includes four fields: SendTime, Offset, Delay, and Diff. The explanation of each field is shown in Table 3.
[0096] Table 3 Description of key fields of clock synchronization request message
[0097]
[0098]
[0099] Step 02, the slave receives the clock synchronization message sent by the master. The local receiving time of the slave receiving the master synchronization message is 18:25. Because the round-trip delay from the master to the slave is asymmetric, according to the master sending timestamps T1", T Offset 、T1' delay and T diff The calculated reference receiving time is 18:20 (T1" + T Offset +T1' delay +T diff ), the local receiving time 18:25 is greater than the theoretically calculated reference receiving time 18:20, indicating that the time consumed by the master->slave clock synchronization message transmission is greater than 5 minutes (18:25-18:20). Correction of delay error T diff , T diff =5min.
[0100] Step 03, the slave responds to the clock synchronization message sent by the master, that is, sends a clock synchronization response message to the master. The parameters carried in the clock synchronization response message include T2" (second time), T3" (seventh time) and T diff (corrected delay error), where T2" is the time when the slave receives the master's clock synchronization message, T3" is the time when the slave sends the master's clock synchronization response message, T diff The difference between the local reception time calculated by the slave and the reference reception time.
[0101] The slave responds to the master's clock response message in the following format: Fig.10 As shown:
[0102] The clock synchronization response message sent by the slave uses the reserved value 0x7 of the PTP v2 messageId, and the DATA field includes three fields: ReceiveTime, SendTime, and Diff. The meaning of each field is shown in Table 4.
[0103] Table 4 Description of key fields of clock synchronization response message
[0104]
[0105] Step 04, after receiving the slave's clock synchronization response message, the master records the receiving time as T4" (eighth time). If the round-trip delay is equal, according to T3" and T diff Check, theoretically T4” and (T3”+T Offset +T diff ) must be equal. If they are not equal, it means that the slave has a large clock accuracy error or other time error problems.
[0106] Step 05, determine the corrected delay error T returned by the target slave station diff If it is greater than the error threshold, the corrected delay error T returned by the target slave station is diff Update the basic link delay, i.e. T1' delay =T1' delay (Local storage of the master station)+T diff , T1' delay Save the file back to local computer and execute Step 06.
[0107] Step 07, the master sends a clock synchronization message for secondary synchronization. The secondary clock synchronization message sent by the master contains the master sending timestamp T1”’, TOffset 、T1' delay Parameters and updated T diff ), repeat the operations of Step 01 to Step 05 until the target slave returns T diff is 0.
[0108] In one embodiment, the method further comprises:
[0109] S010, sending a pulse request signal to the target slave station through a single-line communication line and receiving a pulse response signal fed back by the target slave station, and recording the sending time and the receiving time accordingly to obtain a third time and a sixth time. In order to improve safety and prevent slave device misdetection, the pulse request signal includes at least two pulse signals.
[0110] like Fig.11 , Fig.12 As shown, after the master station device system is powered on and stabilized, the clock synchronization task of the master station is started by an external trigger (such as the operator operating the device command line or device button). At this time, the master station will trigger a pulse group signal (edge triggering), and the master station records the sending time T1 when sending; when the target slave station receives the pulse group signal from the master station, it records T2, and the target slave station returns a pulse group signal (pulse response signal) to the master station, and the target slave station records the time T3 of sending the pulse response signal; when the master station receives the pulse response signal from the target slave station, it records the time T4.
[0111] S020, sending time request information to the target slave station through a two-wire communication line; the time request information is used for each slave station to verify whether it is the target slave station, and to instruct the target slave station to feed back time response information to the master station; the time response information includes a fourth time and a fifth time; the fourth time is the time when the target slave station receives the pulse request signal; the fifth time is the time when the target slave station sends the pulse response signal. The time request information includes the slave station identification of the target slave station, for example, the slave station identification can be a slave station ID, a slave station MAC address or a slave station IP address. Compare the slave station identification with the slave station ID, slave station MAC address or slave station IP address stored by itself, and if they are consistent, determine that it is the target slave station. The slave station identification is stored in the Slave Info field.
[0112] For example, Fig.11As shown, when at least one slave is powered on and the system is stable, the master sends a clock acquisition request message, which carries a slave identifier (or MAC address, IP address) to identify the slave that needs to be acquired; when the slave receives the clock acquisition request message, it then matches the slave identifier (MAC address, or IP address), and if the match is successful, it identifies the slave as the slave that needs to be synchronized; then, the master starts the clock synchronization through an external trigger (such as an operator operating the device command line or a device button), and the master triggers a pulse group signal at this time, for example. The pulse group signal is edge-triggered, which is a continuous 5-pulse signal. When the master sends it, it records the sending time T1, and when the slave receives the pulse group signal from the master, it records the time T2, and the slave returns a pulse group signal to the master and records the return time T3.
[0113] When the master station receives the pulse group signal returned by the slave station, it records the receiving time T4; then the slave station collects the times T2 and T3 and sends them to the master station via a message. At this point, the process of collecting clock information through the pulse group signal is completed.
[0114] Further, in step S020, sending the time request information to the target slave station through the two-wire communication line includes:
[0115] Fill the first message type value into the message field contained in the precision clock protocol frame to be generated; generate the time request information according to the precision clock protocol frame format, and send it to the target slave station through the two-wire communication line. The frame format of the time request information is as follows: Fig.14 As shown, the first message type value is used to represent the time request information. For example, time request information = 0x6; message type messageId = 0x6. The field explanation of the time request information collected by the master station for T2 and T3 is shown in Table 5:
[0116] Table 5 Description of key fields in time request information
[0117]
[0118] The frame format corresponding to the time response information of slave returning T2 and T3 data is as follows Fig.13 shown.
[0119] S030, calculating the standard clock deviation according to the third time, the fourth time, the fifth time and the sixth time, and calculating the standard link delay according to the third time T1, the fourth time T2, the fifth time T3 and the sixth time T4. Fig.12As shown in the figure, the master time is 00:00, and the corresponding target slave time is 18:00. The master sends a pulse request signal at 00:31; the target slave receives the pulse request signal at 18:35 and feeds back a pulse response signal to the master at 18:36; the master receives the pulse response signal at 00:40. The standard link delay T is calculated using the following formula: Delay and standard clock deviation T Offset :
[0120] T Delay =[(T2-T1)+(T4-T3)] / 2
[0121] =(T2-T1+T4-T3) / 2
[0122] =(T4-T1+T2-T3) / 2
[0123] =(00:40-00:31+18:35-18:36) / 2
[0124] =(9min-1min) / 2
[0125] =4min; half of the round-trip delay of the clock pulse group signal is 4min.
[0126] T Offset =[(T2-T1)-(T4-T3)] / 2
[0127] =(T2-T1-T4+T3) / 2
[0128] =[T2+T3-(T1+T4)] / 2
[0129] =[18:35+18:36-(00:31+00:40)] / 2
[0130] =(37:11-01:11) / 2
[0131] =18:00
[0132] Furthermore, the precision clock protocol frame also includes a data area;
[0133] The time response information is also generated according to the precise clock protocol frame format; wherein the data area includes four time fields; the second message type is stored in the message field; the four time fields are used to store the fourth time, the fifth time, the second time and the seventh time correspondingly; the frame structure corresponding to the time response information includes a data area, and the frame format of the time response information is as follows Fig.13 The specific field description is shown in Table 6.
[0134] Table 6 Description of key fields of time response information
[0135]
[0136] The method further includes: identifying the time response information according to the second message type, and parsing the time response information to obtain the fourth time, the fifth time, the second time, and the seventh time. Further, the method further includes:
[0137] S040, recording the sending time of the time request information (College_Req) to obtain the first time T1', such as Fig.12 shown.
[0138] S050, record the receiving time of the time response information (College_Rsp) to obtain the eighth time; the time response information also includes the second time T2' and the seventh time T3'; the second time T2' is the time when the target slave station receives the time request information; the seventh time T3' is the time when the target slave station sends the time response information.
[0139] S060, according to the first time T1', the second time T2', the seventh time T3' and the eighth time T4', half of the round-trip delay (average link delay) is calculated as the initial basic link delay, so as to be updated according to the delay error returned by the target slave station; and the clock deviation is also calculated according to the first time T1', the second time T2', the seventh time T3' and the eighth time T4'. Fig.12 As shown, the master station of this application first sends a time request message (College_Req), then sends a pulse request signal, then the target slave station feeds back a pulse response signal, and finally the target slave station feeds back a time response message (College_Rsp). The master station sends a time request message (College_Req) at 00:10; the target slave station receives the time request message (College_Req) at 18:25, and feeds back the time response message (College_Rsp) to the master station at 18:39; the master station receives the feedback time response message (College_Rsp) at 00:44. The average link delay T' is calculated using the following formula: Delay and clock deviation T' Offset :
[0140] T' Delay =[(T2'–T1')+(T4'–T3')] / 2
[0141] =(T2'–T1'+T4'–T3') / 2
[0142] =(T4'–T1'+T2'–T3') / 2
[0143] =(00:44–00:10+18:25–18:39) / 2
[0144] =(34min–14min) / 2
[0145] =10min (indicates that half of the round-trip delay is 10min, and the one-way delay is not equal to 10min in an asymmetric case).
[0146] T' Offset =[(T2'–T1')-(T4'–T3')] / 2
[0147] =(T2'–T1'-T4'+T3') / 2
[0148] =[T2'+T3'–(T1'+T4')] / 2
[0149] =[18:25+18:39–(00:10+00:44)] / 2
[0150] =(37:04–00:54) / 2
[0151] =18:05.
[0152] Furthermore, the method further comprises:
[0153] S070, determining whether the round-trip delay between the master station and the target slave station is symmetrical based on the seventh time T3', the eighth time T4', the basic link delay and the standard clock deviation; if it is determined that the round-trip delay is asymmetrical, determining to send a clock synchronization message to the target slave station.
[0154] If the round-trip delay is symmetrical, then T4” and (T3”-T Offset +T diff ) should be equal, where T diff If they are not equal, it means that there is round-trip asymmetry, and calibration is required using the approximation method of this application.
[0155] The embodiment of the present application also provides a clock synchronization device. Exemplarily, the clock synchronization device includes:
[0156] A message sending module, configured to send a clock synchronization message to the target slave station; the clock synchronization message includes a synchronization parameter and a delay error; the clock synchronization message is used for the target slave station to calculate a reference receiving time of the clock synchronization message according to the synchronization parameter and the delay error, and to correct the delay error according to the reference receiving time and the local receiving time of the clock synchronization message;
[0157] A parameter updating module, used for updating the synchronization parameter according to the corrected delay error returned by the target slave station;
[0158] The error judgment and timing module is used to repeatedly send clock synchronization messages to the target slave station until the latest delay error returned by the target slave station meets the error threshold, and then send a timing message to the target slave station according to the synchronization parameters corresponding to the latest delay error, and the timing message is used for the target slave station to synchronize its own clock.
[0159] It can be understood that the device of this embodiment corresponds to the clock synchronization method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.
[0160] The present application also provides a terminal device, which exemplarily includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the terminal device to execute the functions of each module in the above-mentioned clock synchronization method or the above-mentioned clock synchronization device. For example, the terminal device is a master station.
[0161] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.
[0162] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.
[0163] The present application also provides a computer-readable storage medium for storing the computer program used in the above-mentioned terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0164] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.
[0165] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
[0166] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.
[0167] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
Claims
1. A clock synchronization method, characterized in that: Applicable to master stations, including: Sending a clock synchronization message to a target slave station; the clock synchronization message includes synchronization parameters and delay error; The clock synchronization message is used for the target slave station to calculate a reference receiving time of the clock synchronization message according to the synchronization parameter and the delay error, and to correct the delay error according to the reference receiving time and the local receiving time of the clock synchronization message; updating the synchronization parameter according to the corrected delay error returned by the target slave station; Repeat sending a clock synchronization message to the target slave station until the latest delay error returned by the target slave station meets the error threshold, then send a timing message to the target slave station according to the synchronization parameter corresponding to the latest delay error, and the timing message is used for the target slave station to synchronize its own clock.
2. The clock synchronization method according to claim 1, characterized in that: The synchronization parameters include basic link delay, standard clock deviation and message sending time corresponding to the clock synchronization message; The message sending time is used to calculate the reference receiving time with the basic link delay, the standard clock deviation and the delay error; The updating of the synchronization parameter according to the corrected delay error returned by the target slave station comprises: Updating the basic link delay according to the corrected delay error returned by the target slave station; The sending a timing message to the target slave station according to the synchronization parameter corresponding to the latest delay error includes: According to the sending time of the timing message, the updated basic link delay, the standard clock deviation and the corrected delay error, a timing message is constructed and sent to the target slave station.
3. The clock synchronization method according to claim 2, characterized in that: The method further comprises: Sending a pulse request signal to the target slave station through a single-line communication line and receiving a pulse response signal fed back by the target slave station, and correspondingly recording the sending time and the receiving time to obtain a third time and a sixth time; wherein the pulse request signal includes at least two pulse signals; Sending time request information to the target slave station via a two-wire communication line; the time request information is used for each slave station to verify whether it is the target slave station, and to instruct the target slave station to feed back time response information to the master station; The time response information includes a fourth time and a fifth time; The fourth time is the time when the target slave station receives the pulse request signal; The fifth time is the time when the target slave station sends the impulse response signal; The standard clock deviation is calculated according to the third time, the fourth time, the fifth time and the sixth time.
4. The clock synchronization method according to claim 3, characterized in that: The method further comprises: Recording the sending time of the time request information to obtain the first time; Record the receiving time of the time response information to obtain an eighth time; the time response information also includes a second time and a seventh time; the second time is the time when the target slave station receives the time request information; the seventh time is the time when the target slave station sends the time response information; The basic link delay is calculated according to the first time, the second time, the seventh time and the eighth time.
5. The clock synchronization method according to claim 4, characterized in that: The method further comprises: Determining whether the round-trip delay between the master station and the target slave station is symmetrical according to the seventh time, the eighth time, the basic link delay and the standard clock deviation; If it is determined that the round trip delay is asymmetric, it is determined to send a clock synchronization message to the target slave station.
6. The clock synchronization method according to claim 4 or 5, characterized in that: The sending of time request information to the target slave station through a two-wire communication line comprises: Filling the first message type value into the message field included in the precision clock protocol frame to be generated; According to the precise clock protocol frame format, time request information is generated and sent to the target slave station through the two-wire communication line.
7. The clock synchronization method according to claim 6, characterized in that: The precision clock protocol frame also includes a data area; The time response information is also generated according to the precise clock protocol frame format; wherein the data area includes four time fields; the second message type is stored in the message field; the four time fields are used to correspondingly store the fourth time, the fifth time, the second time and the seventh time; The method further includes: identifying the time response information according to the second message type, and parsing the time response information to obtain the fourth time, the fifth time, the second time, and the seventh time.
8. A clock synchronization device, suitable for a master station, characterized in that: include: A message sending module, used for sending a clock synchronization message to the target slave station; The clock synchronization message includes a synchronization parameter and a delay error; the clock synchronization message is used for the target slave station to calculate a reference receiving time for receiving the clock synchronization message according to the synchronization parameter and the delay error, and is used for the target slave station to correct the delay error according to the reference receiving time and the local receiving time of receiving the clock synchronization message; A parameter updating module, used for updating the synchronization parameter according to the corrected delay error of the target slave station; The error judgment and timing module is used to repeatedly send clock synchronization messages to the target slave station until the delay error returned by the target slave station meets the error threshold, and then send a timing message to the target slave station according to the synchronization parameter so that the target slave station can synchronize its own clock.
9. A terminal device, characterized in that: The terminal device comprises a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the clock synchronization method according to any one of claims 1 to 7.
10. An industrial network system, characterized in that: include: A master station and at least one slave station; The master station and the at least one slave station are both provided with a clock pulse signal port; The master station and the adjacent slave station are connected via a single-line communication line through corresponding clock pulse signal ports; if there are two or more slave stations, each slave station is also connected in sequence via a single-line communication line through its own clock pulse signal port; the master station is also connected to at least one slave station via a two-line communication line; The master station is used to implement the clock synchronization method according to any one of claims 1 to 7 to synchronize the clocks of each of the slave stations.