Pixel driving circuit, driving method thereof and display device

Abstract

The invention relates to a pixel driving circuit and a driving method thereof, and a display device, the pixel driving circuit comprises a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a storage sub-circuit, the third control sub-circuit is electrically connected with a first reset signal line (Reset1), an auxiliary signal line (VX) and a third node (N3), and the second control sub-circuit is electrically connected with a second reset signal line (Reset2). The control circuit is configured to control a signal of a third node (N3) under the control of a signal of a first reset signal line (Reset1) and the driving of a signal of an auxiliary signal line (VX); the storage sub-circuit is configured to store a voltage difference of a signal between the first node (N1) and the third node (N3).

Description

Pixel driving circuit and driving method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and specifically to a pixel driving circuit and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, comprising: a driving subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit, and a storage subcircuit;

[0006] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node;

[0007] The first control subcircuit is electrically connected to the first scan signal line, the second scan signal line, the data signal line, the reference signal line and the first node, and is configured to provide a signal of the data signal line or the reference signal line to the first node under the control of the signal of the first scan signal line and the second scan signal line;

[0008] The second control subcircuit is electrically connected to the first light emitting signal line, the second light emitting signal line, the first power line, the second node, the third node, and the fourth node, respectively, and is configured to provide a signal from the first power line to the second node and a signal from the third node to the fourth node under the control of signals from the first light emitting signal line and the second light emitting signal line;

[0009] The third control sub-circuit is electrically connected to the first reset signal line, the auxiliary signal line and the third node respectively, and is configured to control the signal of the third node under the control of the signal of the first reset signal line and the signal of the auxiliary signal line;

[0010] The storage sub-circuit is electrically connected to the first node and the third node, respectively, and is configured to store a voltage difference of a signal between the first node and the third node.

[0011] In an exemplary embodiment, the third control subcircuit includes: a sixth transistor and a second capacitor;

[0012] a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the auxiliary signal line, and a second electrode of the sixth transistor electrically connected to the fifth node;

[0013] A first end of the second capacitor is electrically connected to the fifth node, and a second end of the second capacitor is electrically connected to the third node.

[0014] In an exemplary embodiment, the third control subcircuit is further electrically connected to the third reset signal line and the initial signal line, and is configured to provide the signal of the initial signal line to the fourth node under the control of the signal of the third reset signal line.

[0015] In an exemplary embodiment, the third control subcircuit further includes: an eighth transistor, a control electrode of the eighth transistor being electrically connected to the third reset signal line, a first electrode of the eighth transistor being electrically connected to the initial signal line, and a second electrode of the eighth transistor being electrically connected to the fourth node;

[0016] The signal of the auxiliary signal line is a non-DC signal and is electrically connected to the fourth node.

[0017] In an exemplary embodiment, the third control sub-circuit is further electrically connected to the second reset signal line, and is further configured to provide the signal of the fifth node to the third node under the control of the signal of the second reset signal line.

[0018] In an exemplary embodiment, the third control subcircuit includes: a sixth transistor, a seventh transistor, and a second capacitor;

[0019] a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the auxiliary signal line, and a second electrode of the sixth transistor electrically connected to the fifth node;

[0020] a control electrode of the seventh transistor electrically connected to the second reset signal line, a first electrode of the seventh transistor electrically connected to the fifth node, and a second electrode of the seventh transistor electrically connected to the third node;

[0021] A first end of the second capacitor is electrically connected to the fifth node, and a second end of the second capacitor is electrically connected to the third node.

[0022] In an exemplary embodiment, the signal of the auxiliary signal line is a DC signal, and is the same as the signal of any one of the initial signal line, the reference signal line, and the first power line.

[0023] In an exemplary embodiment, the third control subcircuit includes: a sixth transistor and a second capacitor;

[0024] A first end of the second capacitor is electrically connected to the auxiliary signal line, and a second end of the second capacitor is electrically connected to the fifth node;

[0025] The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node, and the second electrode of the sixth transistor is electrically connected to the third node.

[0026] In an exemplary embodiment, the third control subcircuit is further electrically connected to the third reset signal line and the initial signal line, and is configured to provide the signal of the initial signal line to the fourth node under the control of the signal of the third reset signal line.

[0027] In an exemplary embodiment, the third control subcircuit further includes: an eighth transistor, a control electrode of the eighth transistor being electrically connected to the third reset signal line, a first electrode of the eighth transistor being electrically connected to the initial signal line, and a second electrode of the eighth transistor being electrically connected to the fourth node;

[0028] The signal of the auxiliary signal line is a DC signal, and the signal of the auxiliary signal line is the same as the signal of any one of the initial signal line, the reference signal line and the first power line;

[0029] Alternatively, the signal of the auxiliary signal line is a non-DC signal, and the signal of the auxiliary signal line is electrically connected to the fourth node.

[0030] In an exemplary embodiment, the first control subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the second control subcircuit includes: a fourth transistor and a fifth transistor, and the storage subcircuit includes: a first capacitor;

[0031] A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node;

[0032] A control electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the reference signal line, and a second electrode of the second transistor is electrically connected to the first node;

[0033] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0034] The control electrode of the fourth transistor is electrically connected to the first light emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node;

[0035] a control electrode of the fifth transistor electrically connected to the second light emitting signal line, a first electrode of the fifth transistor electrically connected to the third node, and a second electrode of the fifth transistor electrically connected to the fourth node;

[0036] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node.

[0037] In an exemplary embodiment, the first control subcircuit includes a first transistor and a second transistor, the driving subcircuit includes a third transistor, the second control subcircuit includes a fourth transistor and a fifth transistor, the storage subcircuit includes a first capacitor, the third control subcircuit includes a second capacitor and a sixth transistor, and the third control subcircuit further includes at least one of a seventh transistor and an eighth transistor;

[0038] A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node;

[0039] A control electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the reference signal line, and a second electrode of the second transistor is electrically connected to the first node;

[0040] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0041] The control electrode of the fourth transistor is electrically connected to the first light emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node;

[0042] a control electrode of the fifth transistor electrically connected to the second light emitting signal line, a first electrode of the fifth transistor electrically connected to the third node, and a second electrode of the fifth transistor electrically connected to the fourth node;

[0043] a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the auxiliary signal line, and a second electrode of the sixth transistor electrically connected to the fifth node;

[0044] a control electrode of the seventh transistor electrically connected to the second reset signal line, a first electrode of the seventh transistor electrically connected to the fifth node, and a second electrode of the seventh transistor electrically connected to the third node;

[0045] a control electrode of the eighth transistor electrically connected to the third reset signal line, a first electrode of the eighth transistor electrically connected to the initial signal line, and a second electrode of the eighth transistor electrically connected to the fourth node;

[0046] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node;

[0047] A first end of the second capacitor is electrically connected to the fifth node, and a second end of the second capacitor is electrically connected to the third node;

[0048] Any transistor among the first to eighth transistors is an N-type transistor.

[0049] In an exemplary embodiment, the third control subcircuit includes: a sixth transistor, a seventh transistor, and a second capacitor:

[0050] During a partial time period when the signal of the first reset signal line is a valid level signal, the signals of the second reset signal line and the second light-emitting signal line are valid level signals, and the signal of the second reset signal line is a valid level signal for at least a partial time period after a writing time period, and the writing time period is a time period when the first scanning signal line is a valid level signal.

[0051] In an exemplary embodiment, the third control subcircuit includes: a sixth transistor, an eighth transistor, and a second capacitor:

[0052] During a partial time period when the signal of the third reset signal line is a valid level signal, the signal of the second light-emitting signal line is a valid level signal, and the signals of the first reset signal line and the second light-emitting signal line are both valid level signals during at least a partial time period after a writing time period, and the writing time period is a time period when the first scanning signal line is a valid level signal.

[0053] In an exemplary embodiment, the third control subcircuit includes: a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor:

[0054] When the signal of the first reset signal line is a valid level signal, the signal of the third reset signal line is a valid level signal, and the signal of the second reset signal line is an invalid level signal. When the signal of the second reset signal line is a valid level signal, the signal of the first reset signal line is an invalid level signal, and during a partial time period when the signal of the third reset signal line is a valid level signal, the signal of the second light-emitting signal line is a valid level signal. The signal of the second reset signal line is a valid level signal for at least a partial time period after the writing time period, and the writing time period is the time period when the first scanning signal line is a valid level signal.

[0055] In an exemplary embodiment, the first control subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the second control subcircuit includes: a fourth transistor and a fifth transistor, the storage subcircuit includes: a first capacitor, and the third control subcircuit includes: a second capacitor, a sixth transistor, and an eighth transistor;

[0056] A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node;

[0057] A control electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the reference signal line, and a second electrode of the second transistor is electrically connected to the first node;

[0058] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0059] The control electrode of the fourth transistor is electrically connected to the first light emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node;

[0060] a control electrode of the fifth transistor electrically connected to the second light emitting signal line, a first electrode of the fifth transistor electrically connected to the third node, and a second electrode of the fifth transistor electrically connected to the fourth node;

[0061] a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the third node;

[0062] a control electrode of the eighth transistor electrically connected to the third reset signal line, a first electrode of the eighth transistor electrically connected to the initial signal line, and a second electrode of the eighth transistor electrically connected to the fourth node;

[0063] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node;

[0064] A first end of the second capacitor is electrically connected to the auxiliary signal line, and a second end of the second capacitor is electrically connected to the fifth node;

[0065] Any one of the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor is an N-type transistor.

[0066] In an exemplary embodiment, during a partial time period when the signal of the third reset signal line is a valid level signal, the signal of the second light-emitting signal line is a valid level signal, and the signal of the first reset signal line is an invalid level signal during a time period after a writing time period, and the writing time period is a time period when the first scanning signal line is a valid level signal.

[0067] In a second aspect, the present disclosure further provides a display device having a display area, wherein a plurality of the above-mentioned pixel driving circuits are provided in the display area.

[0068] In a third aspect, the present disclosure further provides a driving method for a pixel driving circuit, configured to drive the above-mentioned pixel driving circuit, the method comprising:

[0069] The driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node;

[0070] The first control subcircuit provides a signal of the data signal line or the reference signal line to the first node under the control of the signal of the first scan signal line and the second scan signal line;

[0071] The second control subcircuit provides the signal of the first power line to the second node and provides the signal of the third node to the fourth node under the control of the signals of the first light emitting signal line and the second light emitting signal line;

[0072] The third control sub-circuit controls the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line;

[0073] The storage sub-circuit stores a voltage difference of a signal between the first node and the third node.

[0074] In a fourth aspect, the present disclosure further provides a driving method for a pixel driving circuit, which is configured to drive the above-mentioned pixel driving circuit. The working process of the pixel driving circuit includes: a first stage to a fifth stage, and the method includes:

[0075] In the first phase, an effective level signal is provided to the second scan signal line, the second light emitting signal line, the first reset signal line, and the second reset signal line; the first control subcircuit provides a signal of the reference signal line to the first node; the third control subcircuit provides a signal of the auxiliary signal line to the fifth node and provides a signal of the fifth node to the third node; and the second control subcircuit provides a signal of the fourth node to the third node;

[0076] In the second phase, an effective level signal is provided to the first reset signal line, the second scan signal line, and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores a voltage difference of the signal between the first node and the third node;

[0077] In the third phase, the signals to the first reset signal line and the first scan signal line are high level signals, the first control subcircuit provides the signal of the data signal line to the first node, and the third control subcircuit provides the signal of the auxiliary signal line to the fifth node;

[0078] In the fourth phase, an effective level signal is provided to the second reset signal line and the second light emitting signal line, the third control subcircuit provides a signal of the third node to the fifth node, and the second control subcircuit provides a signal of the fourth node to the third node;

[0079] In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line and the second light-emitting signal line, the second control sub-circuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node. The driving sub-circuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control sub-circuit provides the signal of the third node to the fifth node.

[0080] In a fifth aspect, the present disclosure further provides a driving method for a pixel driving circuit, which is configured to drive the above-mentioned pixel driving circuit. The working process of the pixel driving circuit includes: a first stage to a fifth stage, and the method includes:

[0081] In the first phase, active level signals are provided to the second scan signal line, the second light emitting signal line, the first reset signal line, and the third reset signal line; the first control subcircuit provides a signal of the reference signal line to the first node; the third control subcircuit provides a signal of the auxiliary signal line to the fifth node and provides a signal of the initial signal line to the fourth node; and the second control subcircuit provides a signal of the fourth node to the third node;

[0082] In the second phase, an effective level signal is provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light-emitting signal line; the first control subcircuit provides a signal of the reference signal line to the first node; the third control subcircuit provides a signal of the auxiliary signal line to the fifth node and provides a signal of the initial signal line to the fourth node; the second control subcircuit provides a signal of the first power line to the second node to charge the first node; and the storage subcircuit stores a voltage difference of the signal between the first node and the third node;

[0083] In the third phase, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node;

[0084] In the fourth phase, an effective level signal is provided to the first reset signal line, the third reset signal line, and the second light-emitting signal line, the third control subcircuit provides a signal of the initial signal line to the fourth node, provides a signal of the auxiliary signal line to the fifth node, and the second control subcircuit provides a signal of the fourth node to the third node;

[0085] In the fifth stage, a valid level signal is provided to the first reset signal line, the first light-emitting signal line and the second light-emitting signal line, the second control sub-circuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node. The driving sub-circuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node.

[0086] In a sixth aspect, the present disclosure further provides a driving method for a pixel driving circuit, which is configured to drive the above-mentioned pixel driving circuit. The working process of the pixel driving circuit includes: a first stage to a fifth stage. The method includes:

[0087] In the first phase, active level signals are provided to the second scan signal line, the second light emitting signal line, the first reset signal line, and the third reset signal line; the first control subcircuit provides a signal of the reference signal line to the first node; the third control subcircuit provides a signal of the auxiliary signal line to the fifth node and provides a signal of the initial signal line to the fourth node; and the second control subcircuit provides a signal of the fourth node to the third node;

[0088] In the second phase, an effective level signal is provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light-emitting signal line; the first control subcircuit provides a signal of the reference signal line to the first node; the third control subcircuit provides a signal of the auxiliary signal line to the fifth node and provides a signal of the initial signal line to the fourth node; the second control subcircuit provides a signal of the first power line to the second node to charge the first node; and the storage subcircuit stores a voltage difference of the signal between the first node and the third node;

[0089] In the third phase, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node;

[0090] In the fourth phase, an effective level signal is provided to the second reset signal line, the third reset signal line, and the second light-emitting signal line, the third control subcircuit provides the signal of the initial signal line to the fourth node, provides the signal of the third node to the fifth node, and the second control subcircuit provides the signal of the fourth node to the third node;

[0091] In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line and the second light-emitting signal line, the second control sub-circuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node. The driving sub-circuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control sub-circuit provides the signal of the third node to the fifth node.

[0092] In a seventh aspect, the present disclosure further provides a driving method for a pixel driving circuit, which is configured to drive the above-mentioned pixel driving circuit. The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The method includes:

[0093] In the first phase, an effective level signal is provided to the signals of the second scanning signal line, the second light-emitting signal line, the first reset signal line, and the third reset signal line; the first control subcircuit provides the signal of the reference signal line to the first node; the third control subcircuit provides the signal of the third node to the fifth node and the signal of the initial signal line to the fourth node; and the second control subcircuit provides the signal of the fourth node to the third node;

[0094] In the second phase, an effective level signal is provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light-emitting signal line; the first control subcircuit provides a signal of the reference signal line to the first node; the third control subcircuit provides a signal of the third node to the fifth node and provides a signal of the initial signal line to the fourth node; the second control subcircuit provides a signal of the first power line to the second node to charge the first node; and the storage subcircuit stores a voltage difference of the signal between the first node and the third node;

[0095] In the third phase, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the initial signal line to the fourth node, and provides the signal of the third node to the fifth node;

[0096] In the fourth phase, an effective level signal is provided to the third reset signal line and the second light emitting signal line, the third control subcircuit provides a signal of the initial signal line to the fourth node, and the second control subcircuit provides a signal of the fourth node to the third node;

[0097] In the fifth stage, a valid level signal is provided to the first light-emitting signal line and the second light-emitting signal line, the second control sub-circuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node. The driving sub-circuit provides a driving current to the third node under the control of the signals of the first node and the second node.

[0098] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0099] Summary of the Figures

[0100] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0101] FIG1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0102] FIG2 is an equivalent circuit diagram 1 of the third control subcircuit;

[0103] FIG3 is a second equivalent circuit diagram of the third control subcircuit;

[0104] FIG4 is a third equivalent circuit diagram of the third control subcircuit;

[0105] FIG5 is a fourth equivalent circuit diagram of the third control subcircuit;

[0106] FIG6 is a fifth equivalent circuit diagram of the third control sub-circuit;

[0107] FIG7 is a sixth equivalent circuit diagram of the third control sub-circuit;

[0108] FIG8 is a partial equivalent circuit diagram of a pixel driving circuit;

[0109] FIG9 is an equivalent circuit diagram 1 of a pixel driving circuit;

[0110] FIG10 is a second equivalent circuit diagram of a pixel driving circuit;

[0111] FIG11 is a third equivalent circuit diagram of a pixel driving circuit;

[0112] FIG12 is a fourth equivalent circuit diagram of a pixel driving circuit;

[0113] FIG13 is a fifth equivalent circuit diagram of a pixel driving circuit;

[0114] FIG14 is an equivalent circuit diagram of a pixel driving circuit;

[0115] FIG15 is an operation timing diagram of the pixel driving circuit provided in FIG9 and FIG10;

[0116] FIG16 is an operation timing diagram of the pixel driving circuit provided in FIG11 ;

[0117] FIG17 is an operation timing diagram of the pixel driving circuit provided in FIG12 ;

[0118] FIG18 is an operation timing diagram of the pixel driving circuit provided in FIG13 and FIG14 .

[0119] Details

[0120] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0121] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0122] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0123] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0124] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0125] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0126] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0127] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0128] With the development of OLED display technology, oxide processes are often used in OLED display products due to their high uniformity. However, the coupling effect of some capacitors in pixel driver circuits made using oxide processes can introduce noise during the display phase, making the output drive current of the pixel driver circuit unstable and affecting its reliability.

[0129] Figure 1 is a schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in Figure 1, the pixel driving circuit provided by an embodiment of the present disclosure may include: a driving subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit, and a storage subcircuit.

[0130] As shown in FIG1 , the driving subcircuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving current to the third node N3 under the control of the signals of the first node N1 and the second node N2; the first control subcircuit is electrically connected to the first scan signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF and the first node N1, respectively, and is configured to provide a signal of the data signal line Data or the reference signal line REF to the first node N1 under the control of the signals of the first scan signal line G1 and the second scan signal line G2; the second control subcircuit is electrically connected to the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first power line VDD, the second The node N2, the third node N3 and the fourth node N4 are electrically connected, and are configured to provide the signal of the first power line VDD to the second node N2 and the signal of the third node N3 to the fourth node N4 under the control of the signal of the first light-emitting signal line EM1 and the second light-emitting signal line EM2; the third control sub-circuit is electrically connected to the first reset signal line Reset1, the auxiliary signal line VX and the third node N3, respectively, and is configured to control the signal of the third node N3 under the control of the signal of the first reset signal line Reset1 and the drive of the signal of the auxiliary signal line VX; the storage sub-circuit is electrically connected to the first node N1 and the third node N3, respectively, and is configured to store the voltage difference of the signal between the first node N1 and the third node N3.

[0131] In an exemplary embodiment, as shown in FIG. 1 , the pixel driving circuit is electrically connected to the light emitting device L through the fourth node N4 .

[0132] In an exemplary embodiment, the light emitting device L may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). Exemplarily, the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the second power line VSS.

[0133] In an exemplary embodiment, the light-emitting device L may include a current-driven device, and may be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED). A typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0134] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0135] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the signal of the first power line VDD is a DC signal.

[0136] In an exemplary embodiment, the second power line VSS continuously provides a low-level signal, and the signal of the second power line VSS is a DC signal.

[0137] In an exemplary embodiment, the reference signal line REF continuously provides a low-level signal. The signal of the reference signal line REF is a DC signal. Exemplarily, the voltage of the signal of the reference signal line REF may be 0V.

[0138] In an exemplary embodiment, the pixel driving circuit is located in a display substrate, and the content displayed by the display substrate includes multiple display frames. In any display frame, the signal of the first scanning signal line G1 is a pulse signal, and the signal of the second scanning signal line G2 is a pulse signal. The time period in which the second scanning signal line G2 is a valid level signal occurs before the time period in which the first scanning signal line G1 is a valid level signal.

[0139] The embodiment of the present disclosure provides a pixel driving circuit, comprising: a driving subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit, and a storage subcircuit; the driving subcircuit is electrically connected to a first node, a second node, and a third node, respectively, and is configured to provide a driving current to the third node under the control of signals from the first node and the second node; the first control subcircuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and a first node, respectively, and is configured to provide a signal from a data signal line or a reference signal line to the first node under the control of signals from the first scan signal line and the second scan signal line; the second control subcircuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and a first node, respectively, and is configured to provide a signal from a data signal line or a reference signal line to the first node under the control of signals from the first scan signal line and the second scan signal line; The circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power line, the second node, the third node and the fourth node, respectively, and is configured to provide the signal of the first power line to the second node and the signal of the third node to the fourth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line; the third control subcircuit is electrically connected to the first reset signal line, the auxiliary signal line and the third node, respectively, and is configured to control the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line; the storage subcircuit is electrically connected to the first node and the third node, respectively, and is configured to store the voltage difference of the signal between the first node and the third node. The present disclosure can control the signal of the third node through the signals of the first reset signal line and the auxiliary signal line by setting the third control subcircuit, thereby avoiding the introduction of noise in the display stage, maintaining the stability of the driving current output by the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0140] In an exemplary embodiment, the operation process of the pixel driving circuit includes a display phase, which includes a write phase and a light-emitting phase. The light-emitting phase occurs after the write phase, and the signal of the first scanning signal line G1 is an active-level signal during the write phase. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are both active-level signals during the light-emitting phase, and the time during which the write phase occurs is a write time period.

[0141] FIG2 is an equivalent circuit diagram of the third control subcircuit. As shown in FIG2 , in an exemplary embodiment, the third control subcircuit may also be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide the initial signal line signal to the fourth node N4 under the control of the signal of the third reset signal line Reset3. Exemplarily, the third control subcircuit may include: a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3; the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0142] In an exemplary embodiment, as shown in FIG. 2 , the signal of the auxiliary signal line VX is a non-DC signal and is electrically connected to the fourth node N4 .

[0143] In an exemplary embodiment, as shown in FIG2 , the present disclosure ensures display uniformity of the pixel driving circuit by resetting the third node N3 and the fourth node N4 before the write period by ensuring that the signal on the second light-emitting signal line EM2 is at an active level for at least a portion of the time period during which the signal on the third reset signal line Reset3 is at an active level. Furthermore, the present disclosure ensures that the signals on the first reset signal line Reset1 and the second light-emitting signal line EM2 are at an active level for at least a portion of the time period after the write period. This ensures that the voltage values ​​of the signals across the second capacitor C2 during the light-emitting phase are the same, thereby preventing the second capacitor C2 from affecting the third node N3 during the light-emitting phase and thus preventing noise from being introduced into the third node N3. This maintains the stability of the drive current output by the pixel driving circuit and improves the reliability of the pixel driving circuit.

[0144] Figure 3 is a second equivalent circuit diagram of the third control subcircuit. As shown in Figure 3, in an exemplary embodiment, the third control subcircuit can also be electrically connected to the second reset signal line Reset2, and is also configured to provide a signal of the fifth node N5 to the third node N3 under the control of the signal of the second reset signal line Reset2. Exemplarily, the third control subcircuit may include: a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. Among them, the first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset3, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3;

[0145] In an exemplary embodiment, as shown in FIG. 3 , the signal of the auxiliary signal line VX may be a DC signal and be the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power line VDD.

[0146] In an exemplary embodiment, as shown in FIG3 , the present disclosure ensures display uniformity of the pixel driver circuit by resetting the third node N3 and the fourth node N4 before the write period by ensuring that the second reset signal line Reset2 and the second emission signal line EM2 are active level signals during a portion of the time period when the first reset signal line Reset1 is active level. This ensures that the second reset signal line Reset2 is active level signals for at least a portion of the time period after the write period. This ensures that the voltage values ​​of the signals across the second capacitor C2 during the light-emitting phase are the same, thereby preventing the second capacitor C2 from affecting the third node N3 during the light-emitting phase and thus preventing noise from being introduced during the display phase. This maintains the stability of the drive current output by the pixel driver circuit and improves the reliability of the pixel driver circuit.

[0147] Figure 4 is a third equivalent circuit diagram of the third control subcircuit, and Figure 5 is a fourth equivalent circuit diagram of the third control subcircuit. In exemplary embodiments, as shown in Figures 4 and 5 , the third control subcircuit may also be electrically connected to a third reset signal line Reset3 and an initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to a fourth node N4 under control of a signal on the third reset signal line Reset3. Exemplarily, the third control subcircuit may further include an eighth transistor T8, wherein a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the initial signal line, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0148] In an exemplary embodiment, the signal of the auxiliary signal line VX is a DC signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF, and the first power supply line VDD. Alternatively, the signal of the auxiliary signal line VX is a non-DC signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N4. FIG4 illustrates the auxiliary signal line VX signal as a DC signal, and FIG5 illustrates the auxiliary signal line VX signal as a non-DC signal.

[0149] In an exemplary embodiment, as shown in Figures 4 and 5, when the signal of the first reset signal line Reset1 is an active level signal, the signal of the third reset signal line is an active level signal, and the signal of the second reset signal line is an inactive level signal. When the signal of the second reset signal line is an active level signal, the signal of the first reset signal line is an inactive level signal. The present disclosure resets the third node N3 and the fourth node N4 before the write period by ensuring that the signal of the second light-emitting signal line EM2 is an active level signal during a portion of the time period when the signal of the third reset signal line Reset3 is an active level signal. This ensures display uniformity of the pixel driving circuit. By ensuring that the second reset signal line Reset2 is an active level signal for at least a portion of the time period after the write period, the voltage values ​​of the signals at both ends of the second capacitor C2 during the light-emitting phase are the same, thereby avoiding the influence of the second capacitor C2 on the third node N3 during the light-emitting phase and preventing the introduction of noise during the display phase. This maintains the stability of the drive current output by the pixel driving circuit and improves the reliability of the pixel driving circuit.

[0150] Figure 6 is a fifth equivalent circuit diagram of the third control subcircuit, and Figure 7 is a sixth equivalent circuit diagram of the third control subcircuit. In exemplary embodiments, as shown in Figures 6 and 7, the third control subcircuit may also be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to the fourth node N4 under control of a signal from the third reset signal line Reset3. Exemplarily, the third control subcircuit may further include: a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; and the first end of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and the second end of the second capacitor C2 is electrically connected to the fifth node N5.

[0151] In an exemplary embodiment, the signal of the auxiliary signal line VX is a DC signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF, and the first power line VDD. Alternatively, the signal of the auxiliary signal line VX is a non-DC signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N4. FIG. 6 illustrates the auxiliary signal line VX as a DC signal, and FIG. 7 illustrates the auxiliary signal line VX as a non-DC signal.

[0152] In exemplary embodiments, as shown in Figures 6 and 7 , the present disclosure resets the third node N3 and the fourth node N4 before the write period by maintaining the second light-emitting signal line EM2 at a valid level during a portion of the time period when the third reset signal line Reset3 is at a valid level, thereby ensuring display uniformity of the pixel driver circuit. By maintaining the first reset signal line Reset1 at an inactive level during the period after the write period, the present disclosure prevents the second capacitor C2 from affecting the third node N3, thereby avoiding the introduction of noise during the display phase, maintaining the stability of the drive current output by the pixel driver circuit, and improving the reliability of the pixel driver circuit.

[0153] In an exemplary embodiment, the initial signal line INIT continuously provides a low-level signal, and the signal of the initial signal line INIT is a DC signal.

[0154] In an exemplary embodiment, the voltage value of the signal of the initial signal line INIT may be lower than the voltage value of the signal of the second power line VSS, which may prevent the light emitting device L from emitting light inadvertently and improve the reliability of the pixel driving circuit.

[0155] FIG2 to FIG7 only show six exemplary structures of the third control sub-circuit. Those skilled in the art will readily appreciate that the implementation of the third control sub-circuit is not limited thereto.

[0156] Figure 8 is a partial equivalent circuit diagram of a pixel driving circuit. As shown in Figure 8, in an exemplary embodiment, the first control subcircuit may include: a first transistor T1 and a second transistor T2, the driving subcircuit may include: a third transistor T3, the second control subcircuit may include: a fourth transistor T4 and a fifth transistor T5, and the storage subcircuit may include: a first capacitor C1. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the The second electrode is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, the first electrode of the fifth transistor T5 is electrically connected to the third node N3, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3.

[0157] Figure 8 only shows an exemplary structure of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit. Those skilled in the art can easily understand that the implementation of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit is not limited to this.

[0158] In an exemplary embodiment, FIG9 is an equivalent circuit diagram 1 of a pixel driving circuit, FIG10 is an equivalent circuit diagram 2 of a pixel driving circuit, FIG11 is an equivalent circuit diagram 3 of a pixel driving circuit, and FIG12 is an equivalent circuit diagram 4 of a pixel driving circuit. As shown in FIG9 to FIG12 , in an exemplary embodiment, a first control subcircuit in the pixel driving circuit includes a first transistor T1 and a second transistor T2, a driving subcircuit includes a third transistor T3, a second control subcircuit includes a fourth transistor T4 and a fifth transistor T5, a storage subcircuit includes a first capacitor C1, a third control subcircuit includes a second capacitor C2 and a sixth transistor T6, and the third control subcircuit further includes at least one of a seventh transistor T7 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, and the first electrode of the fifth transistor T5 is electrically connected to the third node N3 a first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the third node N3; a first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a second terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a second terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3.9 and 10 are explained by taking the example that the third control sub-circuit further includes: a seventh transistor T7 and an eighth transistor T8, FIG11 is explained by taking the example that the third control sub-circuit further includes: a seventh transistor T7, and FIG12 is explained by taking the example that the third control sub-circuit further includes: an eighth transistor T8.

[0159] In an exemplary embodiment, as shown in Figures 9 and 10, the third control sub-circuit further includes: the signal of the auxiliary signal line VX in the pixel driving circuit of the seventh transistor T7 and the eighth transistor T8 can be a DC signal, or can be a non-DC signal. Figure 9 is explained by taking the example that the signal of the auxiliary signal line VX in the pixel driving circuit is a DC signal and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power line VDD. Figure 10 is explained by taking the example that the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4.

[0160] In an exemplary embodiment, as shown in FIG11 , the signal of the auxiliary signal line VX in the pixel driving circuit in which the third control sub-circuit further includes the seventh transistor T7 is a DC signal and is the same as the signal of any one of the initial signal line, the reference signal line, and the first power line.

[0161] In an exemplary embodiment, as shown in FIG. 12 , the signal of the auxiliary signal line VX in the pixel driving circuit in which the third control subcircuit further includes an eighth transistor T8 is a non-DC signal and is electrically connected to the fourth node N4 .

[0162] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0163] In an exemplary embodiment, any of the first to eighth transistors T1 to T8 may be an oxide thin film transistor, the active layer of which is made of an oxide semiconductor (Oxide), which has advantages such as low leakage current.

[0164] In an exemplary embodiment, any one of the first to eighth transistors T1 to T8 is an N-type transistor.

[0165] In an exemplary embodiment, FIG13 is a fifth equivalent circuit diagram of a pixel driving circuit, and FIG14 is a sixth equivalent circuit diagram of a pixel driving circuit. As shown in FIG13 and FIG14 , the first control subcircuit in the pixel driving circuit may include a first transistor T1 and a second transistor T2, the driving subcircuit may include a third transistor T3, the second control subcircuit may include a fourth transistor T4 and a fifth transistor T5, the storage subcircuit may include a first capacitor C1, and the third control subcircuit may include a second capacitor C2, a sixth transistor T6, and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and the second end of the second capacitor C2 is electrically connected to the fifth node N5.

[0166] In an exemplary embodiment, as shown in Figures 13 and 14, the third control sub-circuit includes: the signal of the auxiliary signal line VX in the pixel driving circuit of the sixth transistor T6, the eighth transistor T8 and the second capacitor C2 can be a DC signal, or can be a non-DC signal. Figure 13 is explained by taking the example that the signal of the auxiliary signal line VX in the pixel driving circuit is a DC signal and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF and the first power line VDD. Figure 14 is explained by taking the example that the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4.

[0167] In an exemplary embodiment, any of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be an oxide thin film transistor. The active layer of the oxide thin film transistor is made of an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current.

[0168] In an exemplary embodiment, any one of the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the eighth transistor T8 is an N-type transistor.

[0169] In an exemplary embodiment, in the pixel driving circuits provided in FIG. 9 to FIG. 14 , the number of the first transistor T1 , the second transistor T2 , and the fourth transistor T4 may be at least one.

[0170] In an exemplary embodiment, when the number of the first transistors T1 may be at least two, the control electrodes of all the first transistors are electrically connected to the first scan signal line, at least two first transistors are arranged in series, the first electrode of the first first transistor is electrically connected to the data signal line, and the second electrode of the last first transistor is electrically connected to the first node N1.

[0171] In an exemplary embodiment, when the number of the second transistors T2 may be at least two, the control electrodes of all the second transistors T2 are electrically connected to the second scan signal line, at least two second transistors are arranged in series, the first electrode of the first second transistor is electrically connected to the reference signal line, and the second electrode of the last second transistor is electrically connected to the second node N2.

[0172] Figure 15 is an operating timing diagram of the pixel driving circuit provided in Figures 9 and 10. The following describes exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit illustrated in Figures 9 and 10. The pixel driving circuit in Figures 9 and 10 includes eight transistors (first transistor T1 to eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). All eight transistors are N-type transistors.

[0173] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG9 and FIG10 may include:

[0174] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second luminescence signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1, the first luminescence signal line EM1, and the second reset signal line Reset2 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the signal on the second node N2 and clearing the existing charge on the second node N2. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1, the first light-emitting signal line EM1, and the second reset signal line Reset2 are low-level signals, and the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned off. At this stage, the light-emitting device L does not emit light.

[0175] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the second node N2, the signal on the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the signal on the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. During this phase, the light-emitting device L does not emit light.

[0176] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, while the signals on the second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second reset signal line Reset2, the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low. The second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0177] In the fourth phase P4, referred to as the second reset phase, the second reset signal line Reset2, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second light-emitting signal line EM2 is high, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initial signal line. At this time, the first node N1 is pulled low by the first capacitor C1, so that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the second reset signal line Reset2 is high, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off. In this stage, the light-emitting device L does not emit light.

[0178] In the fifth phase P5, i.e., the light-emitting phase, the signals on the second reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals. The fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0179] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0180] I=K*(Vgs-Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0181] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0182] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0183] FIG16 is an operating timing diagram of the pixel driving circuit shown in FIG11. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit shown in FIG11. The pixel driving circuit in FIG11 includes seven transistors (first transistor T1 to seventh transistor T7) and two capacitors (first capacitor C1 and second capacitor C2). All seven transistors are N-type transistors.

[0184] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG11 may include:

[0185] The first phase P1, referred to as the first reset phase, is characterized by high-level signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the second reset signal line Reset2. The signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the signal on the second node N2 and clearing the existing charge on the second node N2. The signals on the first reset signal line Reset1, the second reset signal line Reset2, and the second light-emitting signal line EM2 are high-level signals. The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on, and the signal on the auxiliary signal line VX is sequentially written to the fifth node N5, the third node N3, and the fourth node N4. This initializes (resets) the signals on the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charge on the third node N3, the fourth node N4, and the fifth node N5. The signals of the first scanning signal line G1 and the first light emitting signal line EM1 are low level signals, and the first transistor T1 and the fourth transistor T4 are turned off. In this stage, the light emitting device L does not emit light.

[0186] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the second node N2, the signal on the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the signal on the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. During this phase, the light-emitting device L does not emit light.

[0187] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1 and the first scan signal line G1 are high-level signals, the signals on the second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 at the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 at the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second reset signal line Reset2, the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low. The second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0188] In the fourth phase P4, referred to as the second reset phase, the second reset signal line Reset2 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initial signal line. At this time, the first node N1 is pulled down by the first capacitor C1, such that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. In this stage, the light emitting device L does not emit light.

[0189] In the fifth phase P5, i.e., the light-emitting phase, the signals on the second reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals. The fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off. In this phase, the light-emitting device L emits light.

[0190] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]- Vth] 2 =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0191] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0192] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0193] FIG17 is an operating timing diagram of the pixel driving circuit shown in FIG12. The following describes exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit shown in FIG12. The pixel driving circuit in FIG12 includes seven transistors (first transistor T1 to sixth transistor T6, and eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). All seven transistors are N-type transistors.

[0194] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG12 may include:

[0195] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the signal on the second node N2 and clearing the existing charge on the second node N2. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0196] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the second node N2, the signal on the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0197] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0198] In the fourth phase P4, referred to as the second reset phase, the first reset signal line Reset1, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initialization signal line. At this time, the first node N1 is pulled down by the first capacitor C1, so that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 are kept consistent. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off. In this stage, the light emitting device L does not emit light.

[0199] In the fifth phase P5, i.e., the light-emitting phase, the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals. The fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0200] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]- Vth] 2 =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0201] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0202] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0203] For the pixel driving circuit provided in Figures 9 to 12, in the fourth and fifth stages, the signals of the third node N3 and the fifth node N5 at both ends of the second capacitor C2 remain consistent, so that the third node of the pixel driving circuit will not be affected by the coupling effect of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0204] FIG18 is an operating timing diagram of the pixel driving circuit provided in FIG13 and FIG14. The following describes exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit illustrated in FIG13 and FIG14. The pixel driving circuit in FIG13 and FIG14 includes seven transistors (first transistor T1 to sixth transistor T6, and eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). All seven transistors are N-type transistors.

[0205] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG. 13 and FIG. 14 may include:

[0206] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the second node N2, initializing (resetting) the signal on the second node N2 and clearing the existing charge on the second node N2. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0207] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the second node N2, the signal on the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0208] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0209] The fourth phase P4, referred to as the second reset phase, is characterized by the high-level signals of the third reset signal line Reset3 and the second light-emitting signal line EM2, while the signals of the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal of the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal of the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The signal of the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal at the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal of the initialization signal line. At this time, the first node N1 is pulled low by the action of the first capacitor C1, so that the voltage V1 of the signal at the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. In this stage, the light emitting device L does not emit light.

[0210] In the fifth phase P5, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0211] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]- Vth] 2 =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0212] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0213] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0214] For the pixel driving circuit provided in FIG13 and FIG14 , in the fourth stage and the fifth stage, the sixth transistor T6 whose second capacitor C2 is disconnected from the third node N3 is disconnected, so that the third node of the pixel driving circuit will not be affected by the coupling effect of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0215] The embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit. The driving method of the pixel driving circuit may include:

[0216] Step 100: The driving sub-circuit provides a driving current to the third node under the control of the signals at the first node and the second node.

[0217] Step 200 : The first control sub-circuit provides a signal of a data signal line or a reference signal line to a first node N1 under the control of signals of a first scan signal line and a second scan signal line.

[0218] Step 300: Under the control of the signals of the first light-emitting signal line and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node and provides the signal of the third node to the fourth node.

[0219] Step 400: The third control sub-circuit controls the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line.

[0220] Step 500: The storage sub-circuit stores a voltage difference of a signal between a first node and a third node.

[0221] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuit shown in FIG11 . The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The driving method for the pixel driving circuit shown in FIG11 may include:

[0222] Step 110. In the first stage, valid level signals are provided to the signals of the second scanning signal line, the second light-emitting signal line, the first reset signal line, and the second reset signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the fifth node to the third node, and the second control sub-circuit provides the signal of the fourth node to the third node.

[0223] Step 120. In the second stage, a valid level signal is provided to the first reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores the voltage difference of the signal between the first node and the third node.

[0224] Step 130 , in the third stage, the signals to the first reset signal line and the first scan signal line are high level signals, the first control subcircuit provides the signal of the data signal line to the first node, and the third control subcircuit provides the signal of the auxiliary signal line to the fifth node.

[0225] Step 140: In the fourth stage, provide an effective level signal to the second reset signal line and the second light-emitting signal line, the third control subcircuit provides the signal of the third node to the fifth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0226] Step 150. In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node, the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides the signal of the third node to the fifth node.

[0227] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuit shown in FIG12 . The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The driving method for the pixel driving circuit shown in FIG12 may include:

[0228] Step 210: In the first stage, valid level signals are provided to the second scan signal line, the second light-emitting signal line, the first reset signal line, and the third reset signal line; the first control subcircuit provides a signal of the reference signal line to the first node; the third control subcircuit provides a signal of the auxiliary signal line to the fifth node and provides a signal of the initial signal line to the fourth node; and the second control subcircuit provides a signal of the fourth node to the third node.

[0229] Step 220. In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, and provides a signal of the initial signal line to the fourth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores the voltage difference of the signal between the first node and the third node.

[0230] Step 230. In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node.

[0231] Step 240. In the fourth stage, a valid level signal is provided to the first reset signal line, the third reset signal line and the second light-emitting signal line, the third control subcircuit provides the signal of the initial signal line to the fourth node, provides the signal of the auxiliary signal line to the fifth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0232] Step 250. In the fifth stage, a valid level signal is provided to the first reset signal line, the first light-emitting signal line, and the second light-emitting signal line, the second control subcircuit provides a signal of the first power line to the second node, and provides a signal of the third node to the fourth node, the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides a signal of the auxiliary signal line to the fifth node.

[0233] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuits shown in FIG9 and FIG10. The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The driving method for the pixel driving circuits shown in FIG9 and FIG10 may include:

[0234] Step 310. In the first stage, valid level signals are provided to the signals of the second scanning signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0235] Step 320. In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, and provides a signal of the initial signal line to the fourth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores the voltage difference of the signal between the first node and the third node.

[0236] Step 330. In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node.

[0237] Step 340. In the fourth stage, a valid level signal is provided to the second reset signal line, the third reset signal line and the second light-emitting signal line, the third control subcircuit provides the signal of the initial signal line to the fourth node, provides the signal of the third node to the fifth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0238] Step 350. In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node, the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides the signal of the third node to the fifth node.

[0239] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuits shown in FIG13 and FIG14 . The operation process of the pixel driving circuit includes: a first stage to a fifth stage. The driving method for the pixel driving circuits shown in FIG13 and FIG14 may include:

[0240] Step 410. In the first stage, valid level signals are provided to the signals of the second scanning signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the third node to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0241] Step 420. In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the third node to the fifth node, and provides the signal of the initial signal line to the fourth node, the second control subcircuit provides the signal of the first power line to the second node to charge the first node, and the storage subcircuit stores the voltage difference of the signal between the first node and the third node.

[0242] Step 430. In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the initial signal line to the fourth node, and provides the signal of the third node to the fifth node.

[0243] Step 440: In the fourth stage, provide an effective level signal to the third reset signal line and the second light-emitting signal line, the third control subcircuit provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node.

[0244] Step 450. In the fifth stage, a valid level signal is provided to the first light-emitting signal line and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node, and the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node.

[0245] An embodiment of the present disclosure further provides a display device having a display area, where a plurality of pixel driving circuits are provided.

[0246] The pixel driving circuit is the pixel driving circuit provided by any of the aforementioned embodiments, and its implementation method and implementation effect are similar, which will not be repeated here.

[0247] In an exemplary embodiment, a display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array, wherein the timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines, respectively. The scan driver is connected to a plurality of scan signal lines, respectively. The light-emitting driver is connected to a plurality of light-emitting signal lines, respectively. The pixel array may include a plurality of sub-pixels, at least one of which may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively.

[0248] The scanning signal lines include: a first scanning signal line, a second scanning signal line, a first reset signal line, a second reset signal line and a third reset signal line. The light emitting signal lines include: a first light emitting signal line and a second light emitting signal line.

[0249] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, can provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver.

[0250] In an exemplary embodiment, the data driver may generate a data voltage to be supplied to the data signal line using a grayscale value and a control signal received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.

[0251] In an exemplary embodiment, the scan driver may generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the scan signal line. For example, the scan driver may be configured in the form of a shift register and may generate the scan signal by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal.

[0252] In an exemplary embodiment, the light emitting driver may generate an emission signal to be provided to the light emitting signal line by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light emitting driver may sequentially provide emission signals having an off-level pulse to the light emitting signal line. For example, the light emitting driver may be configured in the form of a shift register and may generate emission signals by sequentially transmitting the emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal.

[0253] In an exemplary embodiment, a display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel that emits light of a first color, a second subpixel that emits light of a second color, and a third subpixel that emits light of a third color. The first, second, and third subpixels each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first, second, and third subpixels are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first, second, and third subpixels are respectively connected to the pixel driving circuits of their respective subpixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of their respective subpixels.

[0254] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal.

[0255] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0256] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0257] In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a base, a light-emitting structure layer disposed on a side of the driving structure layer away from the base, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the base. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0258] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0259] In an exemplary embodiment, the driving structure layer may include multiple transistors and storage capacitors that constitute a pixel driving circuit, and the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the drain electrode of the transistor therein through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding color under the drive of the anode and the cathode.

[0260] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0261] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0262] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0263] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0264] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0265] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A pixel driving circuit, comprising: a driving subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit and a storage subcircuit; The driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node; The first control subcircuit is electrically connected to the first scan signal line, the second scan signal line, the data signal line, the reference signal line and the first node, respectively, and is configured to provide a signal of the data signal line or the reference signal line to the first node under the control of the signal of the first scan signal line and the second scan signal line; The second control subcircuit is electrically connected to the first light emitting signal line, the second light emitting signal line, the first power line, the second node, the third node and the fourth node respectively, and is configured to provide the signal of the first power line to the second node and provide the signal of the third node to the fourth node under the control of the signal of the first light emitting signal line and the second light emitting signal line; The third control subcircuit is electrically connected to the first reset signal line, the auxiliary signal line and the third node respectively, and is configured to control the signal of the third node under the control of the signal of the first reset signal line and the signal of the auxiliary signal line; The storage sub-circuit is electrically connected to the first node and the third node, respectively, and is configured to store a voltage difference of a signal between the first node and the third node.

2. The pixel driving circuit according to claim 1, wherein: The third control subcircuit includes: a sixth transistor and a second capacitor; The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node; The first end of the second capacitor is electrically connected to the fifth node, and the second end of the second capacitor is electrically connected to the third node.

3. The pixel driving circuit according to claim 2, wherein: The third control subcircuit is also electrically connected to the third reset signal line and the initial signal line respectively, and is configured to provide the signal of the initial signal line to the fourth node under the control of the signal of the third reset signal line.

4. The pixel driving circuit according to claim 3, wherein: The third control subcircuit further includes: an eighth transistor, a control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the initial signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node; The signal of the auxiliary signal line is a non-DC signal and is electrically connected to the fourth node.

5. The pixel driving circuit according to claim 1, wherein: The third control subcircuit is also electrically connected to the second reset signal line, and is further configured to provide the signal of the fifth node to the third node under the control of the signal of the second reset signal line.

6. The pixel driving circuit according to claim 5, wherein: The third control subcircuit includes: a sixth transistor, a seventh transistor and a second capacitor; The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the third node; The first end of the second capacitor is electrically connected to the fifth node, and the second end of the second capacitor is electrically connected to the third node.

7. The pixel driving circuit according to claim 6, wherein: The signal of the auxiliary signal line is a direct current signal, and is the same as the signal of any one of the initial signal line, the reference signal line and the first power line.

8. The pixel driving circuit according to claim 2, wherein: The third control subcircuit includes: a sixth transistor and a second capacitor; A first end of the second capacitor is electrically connected to the auxiliary signal line, and a second end of the second capacitor is electrically connected to the fifth node; The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node, and the second electrode of the sixth transistor is electrically connected to the third node.

9. The pixel driving circuit according to claim 6 or 8, wherein: The third control subcircuit is also electrically connected to the third reset signal line and the initial signal line respectively, and is configured to provide the signal of the initial signal line to the fourth node under the control of the signal of the third reset signal line.

10. The pixel driving circuit according to claim 9, wherein: The third control subcircuit further includes: an eighth transistor, a control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the initial signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node; The signal of the auxiliary signal line is a DC signal, and the signal of the auxiliary signal line is the same as the signal of any one of the initial signal line, the reference signal line and the first power line; Alternatively, the signal of the auxiliary signal line is a non-DC signal, and the signal of the auxiliary signal line is electrically connected to the fourth node.

11. The pixel driving circuit according to claim 1, wherein: The first control subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the second control subcircuit includes: a fourth transistor and a fifth transistor, and the storage subcircuit includes: a first capacitor; A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the second scanning signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the first light emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the second light emitting signal line, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node; The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the third node.

12. The pixel driving circuit according to claim 1, wherein: The first control subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the second control subcircuit includes: a fourth transistor and a fifth transistor, the storage subcircuit includes: a first capacitor, the third control subcircuit includes: a second capacitor and a sixth transistor, and the third control subcircuit also includes: at least one transistor of the seventh transistor and the eighth transistor; A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the second scanning signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the first light emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the second light emitting signal line, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the third node; The control electrode of the eighth transistor is electrically connected to the third reset signal line, the first electrode of the eighth transistor is electrically connected to the initial signal line, and the second electrode of the eighth transistor is electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the fifth node, and a second end of the second capacitor is electrically connected to the third node. connect; Any transistor among the first transistor to the eighth transistor is an N-type transistor.

13. The pixel driving circuit according to claim 12, wherein: The third control subcircuit includes: a sixth transistor, a seventh transistor and a second capacitor: During a partial time period when the signal of the first reset signal line is a valid level signal, the signals of the second reset signal line and the second light-emitting signal line are valid level signals, and the signal of the second reset signal line is a valid level signal during at least a partial time period after a write time period, and the write time period is a time period when the first scanning signal line is a valid level signal.

14. The pixel driving circuit according to claim 12, wherein: The third control subcircuit includes: a sixth transistor, an eighth transistor and a second capacitor: During a partial time period when the signal of the third reset signal line is a valid level signal, the signal of the second light-emitting signal line is a valid level signal, and the signals of the first reset signal line and the second light-emitting signal line are both valid level signals during at least a partial time period after a write time period, and the write time period is a time period when the first scan signal line is a valid level signal.

15. The pixel driving circuit according to claim 12, wherein: The third control subcircuit includes: a sixth transistor, a seventh transistor, an eighth transistor and a second capacitor: When the signal of the first reset signal line is a valid level signal, the signal of the third reset signal line is a valid level signal, and the signal of the second reset signal line is an invalid level signal. When the signal of the second reset signal line is a valid level signal, the signal of the first reset signal line is an invalid level signal, and during a partial time period when the signal of the third reset signal line is a valid level signal, the signal of the second light-emitting signal line is a valid level signal, and the signal of the second reset signal line is a valid level signal during at least a partial time period after a writing time period, and the writing time period is a time period when the first scanning signal line is a valid level signal.

16. The pixel driving circuit according to claim 1, wherein: The first control subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the second control subcircuit includes: a fourth transistor and a fifth transistor, the storage subcircuit includes: a first capacitor, and the third control subcircuit includes: a second capacitor, a sixth transistor and an eighth transistor; A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the second scanning signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the first light emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the second light emitting signal line, and the first electrode of the fifth transistor is electrically connected to the The third node is electrically connected, and the second electrode of the fifth transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node, and the second electrode of the sixth transistor is electrically connected to the third node; The control electrode of the eighth transistor is electrically connected to the third reset signal line, the first electrode of the eighth transistor is electrically connected to the initial signal line, and the second electrode of the eighth transistor is electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the auxiliary signal line, and a second end of the second capacitor is electrically connected to the fifth node; Any one of the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor is an N-type transistor.

17. The pixel driving circuit according to claim 16, wherein: During the partial time period when the signal of the third reset signal line is a valid level signal, the signal of the second light-emitting signal line is a valid level signal, and the signal of the first reset signal line is an invalid level signal during the time period after the writing time period, and the writing time period is the time period when the first scanning signal line is a valid level signal.

18. A display device comprising a display area, wherein a plurality of pixel driving circuits according to any one of claims 1 to 17 are provided in the display area.

19. A driving method for a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 17, the method comprising: The driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node; The first control subcircuit provides a signal of a data signal line or a reference signal line to the first node under the control of a signal of the first scan signal line and a signal of the second scan signal line; The second control subcircuit provides the signal of the first power line to the second node and provides the signal of the third node to the fourth node under the control of the signals of the first light emitting signal line and the second light emitting signal line; The third control subcircuit controls the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line; The storage sub-circuit stores a voltage difference of a signal between the first node and the third node.

20. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit as claimed in claim 13, wherein the working process of the pixel driving circuit comprises: From the first stage to the fifth stage, the method comprises: In the first stage, an effective level signal is provided to the signals of the second scanning signal line, the second light emitting signal line, the first reset signal line and the second reset signal line, the first control subcircuit provides a signal of the reference signal line to the first node, and the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, and providing a signal of the fifth node to the third node, and the second control subcircuit providing a signal of the fourth node to the third node; In the second stage, an effective level signal is provided to the first reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores a voltage difference of the signal between the first node and the third node; In the third stage, the signals to the first reset signal line and the first scan signal line are high level signals, the first control subcircuit provides the signal of the data signal line to the first node, and the third control subcircuit provides the signal of the auxiliary signal line to the fifth node; In the fourth stage, an effective level signal is provided to the second reset signal line and the second light emitting signal line, the third control subcircuit provides a signal of the third node to the fifth node, and the second control subcircuit provides a signal of the fourth node to the third node; In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node. The driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides the signal of the third node to the fifth node.

21. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit as claimed in claim 14, wherein the working process of the pixel driving circuit comprises: From the first stage to the fifth stage, the method comprises: In the first stage, an effective level signal is provided to the signals of the second scanning signal line, the second light emitting signal line, the first reset signal line and the third reset signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node; In the second stage, an effective level signal is provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, and provides a signal of the initial signal line to the fourth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores a voltage difference of the signal between the first node and the third node; In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node; In the fourth stage, an effective level signal is provided to the first reset signal line, the third reset signal line and the second light-emitting signal line, the third control subcircuit provides a signal of the initial signal line to the fourth node, provides a signal of the auxiliary signal line to the fifth node, and the second control subcircuit provides a signal of the fourth node to the third node; In the fifth stage, a valid level signal is provided to the first reset signal line, the first light-emitting signal line and the second light-emitting signal line, the second control subcircuit provides a signal of the first power line to the second node, and provides a signal of the third node to the fourth node. The driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides a signal of the auxiliary signal line to the fifth node.

22. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit as claimed in claim 15, wherein the working process of the pixel driving circuit comprises: From the first stage to the fifth stage, the method comprises: In the first stage, an effective level signal is provided to the signals of the second scanning signal line, the second light emitting signal line, the first reset signal line and the third reset signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node; In the second stage, an effective level signal is provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the auxiliary signal line to the fifth node, and provides a signal of the initial signal line to the fourth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores a voltage difference of the signal between the first node and the third node; In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node; In the fourth stage, an effective level signal is provided to the second reset signal line, the third reset signal line and the second light-emitting signal line, the third control subcircuit provides a signal of the initial signal line to the fourth node, provides a signal of the third node to the fifth node, and the second control subcircuit provides a signal of the fourth node to the third node; In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line and the second light-emitting signal line, the second control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node. The driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the third control subcircuit provides the signal of the third node to the fifth node.

23. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit as claimed in claim 17, wherein the working process of the pixel driving circuit comprises: From the first stage to the fifth stage, the method comprises: In the first stage, an effective level signal is provided to the signals of the second scanning signal line, the second light emitting signal line, the first reset signal line and the third reset signal line, the first control subcircuit provides the signal of the reference signal line to the first node, the third control subcircuit provides the signal of the third node to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control subcircuit provides the signal of the fourth node to the third node; In the second stage, an effective level signal is provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control subcircuit provides a signal of the reference signal line to the first node, the third control subcircuit provides a signal of the third node to the fifth node, and provides a signal of the initial signal line to the fourth node, the second control subcircuit provides a signal of the first power line to the second node to charge the first node, and the storage subcircuit stores a voltage difference of the signal between the first node and the third node; In the third stage, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high level signals, the first control subcircuit provides the signal of the data signal line to the first node, the third control subcircuit provides the signal of the initial signal line to the fourth node, and provides the signal of the third node to the fifth node; In the fourth stage, an effective level signal is provided to the third reset signal line and the second light emitting signal line, the third control subcircuit provides a signal of the initial signal line to the fourth node, and the second control subcircuit provides a signal of the fourth node to the third node; In the fifth stage, a valid level signal is provided to the first light-emitting signal line and the second light-emitting signal line, the second control subcircuit provides a signal of the first power line to the second node, and provides a signal of the third node to the fourth node, and the driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node.

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