Sub-block skipping method for affine motion search for video coding

Abstract

Encoding and decoding video data using an affine decoder-side motion vector refinement (DMVR) mode includes receiving a block of video data to be decoded using the affine DMVR mode, and dividing the block into a plurality of sub-blocks. The video encoder and video decoder may determine a final offset for the affine DMVR mode using a first subset of the plurality of sub-blocks. The video encoder and video decoder may codec the block of video data using the final offset to generate a coded block of video data.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 467,513, filed on September 14, 2023, and U.S. Provisional Application No. 63 / 377,659, filed on September 29, 2022, the entire contents of each of which are incorporated herein by reference. U.S. Patent Application No. 18 / 467,513, filed on September 14, 2023, claims the benefit of U.S. Provisional Application No. 63 / 377,659, filed on September 29, 2022. Technical Field

[0002] The present disclosure relates to video encoding and video decoding. Background Art

[0003] Digital video capabilities may be incorporated into a variety of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite broadcast phones, so-called "smart phones", video teleconferencing devices, video streaming devices, and similar devices. Digital video devices implement video codec technologies, such as those developed by MPEG-2, MPEG-4, ITU-TH.263, ITU-TH.264 / MPEG-4, Part 10, Advanced Video Coding (AVC), ITU-TH.265 / High Efficiency Video Coding (HEVC), ITU-TH.266 / Volatile Video Coding (VVC), extensions of these standards, and proprietary video codecs / formats such as AOMedia Video 1 (AV1) developed by the Alliance for Open Media. By implementing these video codec technologies, video devices can more efficiently send, receive, encode, decode, and / or store digital video information.

[0004] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or eliminate redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video picture or a portion of a video picture) may be partitioned into video blocks, which may also be referred to as codec tree units (CTUs), codec units (CUs), and / or codec nodes. Video blocks in an intra-codec (I) slice of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in an inter-codec (P or B) slice of a picture may use spatial prediction with respect to reference samples in neighboring blocks in the same picture, or temporal prediction with respect to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames. Summary of the invention

[0005] In general, the present disclosure describes inter prediction techniques in video codecs. More specifically, the present disclosure describes techniques involving affine decoder side motion vector refinement (DMVR). Compared to other affine DMVR techniques involving bi-directionally predicted affine merge candidates, the techniques disclosed herein may be less complex and more practical. For example, the techniques disclosed herein include: using a subset of sub-blocks of a block, determining an offset for an affine DMVR process.

[0006] In general, the video codec can be configured to skip at least one sub-block of a block for affine motion compensation. Accordingly, those skipped sub-blocks are excluded from the motion compensation process, and when determining a final offset (e.g., a motion vector offset determined using DMVR) to be applied to control motion vectors, a distortion between the generated predictors (e.g., a bilateral matching cost) is calculated using a predefined cost criterion. In other words, the video codec is configured to use a subset of the sub-blocks of the block when calculating the distortion during an affine motion search (e.g., a DMVR process in an affine merge mode).

[0007] The disclosed technique can reduce the computational complexity of the sub-block based affine motion search process without significantly reducing the codec efficiency. That is, testing has shown that using only a subset of the sub-blocks of a block to determine the final offset of the affine DMVR pattern results in substantially the same codec efficiency as using all sub-blocks. Therefore, the final offset can be determined faster with fewer computational resources.

[0008] In one example, the present disclosure describes a method for decoding video data, the method comprising: receiving a block of video data to be decoded using an affine DMVR pattern; dividing the block into a plurality of sub-blocks; determining a final offset of the affine DMVR pattern using a first subset of the plurality of sub-blocks; and decoding the block of video data using the final offset to generate a decoded block of video data.

[0009] In another example, the present disclosure describes an apparatus configured to decode video data, the apparatus comprising: a memory configured to store a block of video data; and a processing circuit in communication with the memory, the processing circuit being configured to: receive a block of video data to be decoded using an affine DMVR pattern; divide the block into a plurality of sub-blocks; determine a final offset of the affine DMVR pattern using a first subset of the plurality of sub-blocks; and decode the block of video data using the final offset to generate a decoded block of video data.

[0010] In another example, the present disclosure describes an apparatus configured to decode video data, the apparatus comprising: a component for receiving a block of video data to be decoded using an affine DMVR pattern; a component for dividing the block into a plurality of sub-blocks; a component for determining a final offset of the affine DMVR pattern using a first subset of the plurality of sub-blocks; and a component for decoding the block of video data using the final offset to generate a decoded block of video data.

[0011] In another example, the present disclosure describes a non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors of a device configured to decode video data to: receive a block of video data to be decoded using an affine DMVR pattern; divide the block into a plurality of sub-blocks; determine a final offset of the affine DMVR pattern using a first subset of the plurality of sub-blocks; and decode the block of video data using the final offset to generate a decoded block of video data.

[0012] In another example, the present disclosure describes a method for encoding video data, the method comprising: receiving a block of video data to be encoded using an affine DMVR mode; dividing the block into a plurality of sub-blocks; determining a final offset of the affine DMVR mode using a first subset of the plurality of sub-blocks; and encoding the block of video data using the final offset to generate an encoded block of video data.

[0013] In another example, the present disclosure describes an apparatus configured to encode video data, the apparatus comprising: a memory configured to store a block of video data, and a processing circuit in communication with the memory, the processing circuit being configured to: receive a block of video data to be encoded using an affine DMVR pattern; divide the block into a plurality of sub-blocks; determine a final offset of the affine DMVR pattern using a first subset of the plurality of sub-blocks; and encode the block of video data using the final offset to generate an encoded block of video data.

[0014] In another example, the present disclosure describes an apparatus configured to encode video data, the apparatus comprising: a component for receiving a block of video data to be encoded using an affine DMVR mode; a component for dividing the block into a plurality of sub-blocks; a component for determining a final offset of the affine DMVR mode using a first subset of the plurality of sub-blocks; and a component for encoding the block of video data using the final offset to generate an encoded block of video data.

[0015] In another example, the present disclosure describes a non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors of a device configured to encode video data to: receive a block of video data to be encoded using an affine DMVR mode; divide the block into a plurality of sub-blocks; determine a final offset of the affine DMVR mode using a first subset of the plurality of sub-blocks; and encode the block of video data using the final offset to generate an encoded block of video data.

[0016] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a block diagram illustrating an example video encoding and decoding system that may perform the disclosed techniques.

[0018] Figure 2 is a conceptual diagram illustrating example bilateral matching for decoder-side motion vector refinement according to the disclosed techniques.

[0019] Figure 3A and Figure 3B An example of a sub-block skip mode for affine motion search according to the disclosed technique is shown.

[0020] Figure 4A and 4B Another example of a sub-block skip mode for affine motion search according to the disclosed technique is shown.

[0021] Figure 5A and 5BAnother example of a sub-block skip mode for affine motion search according to the disclosed technique is shown.

[0022] Figure 6 FIG. 4 is another example showing a sub-block skip mode for affine motion search according to the disclosed technique.

[0023] Figure 7 is a block diagram illustrating an example video codec that may perform the disclosed techniques.

[0024] Figure 8 is a block diagram illustrating an example video decoder that may perform the disclosed techniques.

[0025] Fig. 9 is a flowchart illustrating an example method of encoding a current data block according to the disclosed technology.

[0026] Fig.10 is a flowchart illustrating an example method of decoding a current data block according to the disclosed technology.

[0027] Fig.11 is a flowchart illustrating another example method of encoding video data according to the disclosed technology.

[0028] Fig.12 is a flow chart illustrating another example method of decoding video data according to the disclosed techniques. DETAILED DESCRIPTION

[0029] Sub-block based motion compensation can be used for affine motion compensation for affine motion search (e.g., at encoder side affine motion estimation or decoder side affine motion refinement). Certain techniques for decoder side motion vector refinement (DMVR) for bi-predictive affine merge candidates increase the complexity of the video codec implementing such techniques because the motion compensation and cost calculation process will be performed for each sub-block of the video data block. Compared to certain techniques for affine DMVR, the present disclosure describes less complex and more practical techniques. The disclosed techniques can make it easier to implement DMVR techniques and / or save processing power.

[0030] In general, a video codec may be configured to skip at least one sub-block of a block for affine motion compensation. Accordingly, those skipped sub-blocks are excluded from the motion compensation process, and when determining a final offset (e.g., a motion vector offset determined using DMVR) to be applied to control motion vectors, a distortion between the generated predictors (e.g., a bilateral matching cost) is calculated using a predefined cost criterion. In other words, the video codec is configured to use a subset of the sub-blocks of the block when calculating distortion during an affine motion search (e.g., a DMVR process in an affine merge mode).

[0031] The disclosed technique can reduce the computational complexity of the sub-block based affine motion search process without significantly reducing the codec efficiency. That is, testing has shown that using only a subset of the sub-blocks of a block to determine the final offset of the affine DMVR pattern results in substantially the same codec efficiency as using all sub-blocks. Therefore, the final offset can be determined faster with fewer computational resources.

[0032] Figure 1 1 is a block diagram illustrating an example video encoding and decoding system 100 that can perform the disclosed techniques. The disclosed techniques are generally directed to encoding and decoding (encoding and / or decoding) of video data. Generally speaking, video data includes any data used to process video. Thus, video data can include original, unencoded video, encoded video, decoded (e.g., reconstructed) video, and video metadata (such as signaling data).

[0033] like Figure 1 As shown, system 100 includes source device 102, which in this example provides encoded video data to be decoded and displayed by destination device 116. Specifically, source device 102 provides video data to destination device 116 via computer-readable medium 110. Source device 102 and destination device 116 can be or include any of a variety of devices, such as a desktop computer, a notebook (i.e., laptop) computer, a sports device, a tablet computer, a set-top box, a telephone handset (such as a smart phone), a television, a camera, a display device, a digital media player, a video game controller, a video streaming device, a broadcast receiving device, or the like. In some cases, source device 102 and destination device 116 can be equipped for wireless communication, and thus can be referred to as wireless communication devices.

[0034] exist Figure 1In the example of, source device 102 comprises video source 104, memory 106, video encoder 200 and output interface 108. Destination device 116 comprises input interface 122, video decoder 300, memory 120 and display device 118. According to the present disclosure, the video encoder 200 of source device 102 and the video decoder 300 of destination device 116 can be configured to apply affine motion search technology. Therefore, source device 102 represents an example of video encoding device, and destination device 116 represents an example of video decoding device. In other examples, source device and destination device may include other components or arrangements. For example, source device 102 may receive video data from an external video source (such as an external camera). Similarly, destination device 116 may be docked with an external display device instead of including an integrated display device.

[0035] Figure 1 The system 100 shown is only an example. In general, any digital video encoding and / or decoding device can perform affine motion search technology. The source device 102 and the destination device 116 are only examples of such codec devices, wherein the source device 102 generates encoded and decoded video data for sending to the destination device 116. The present disclosure refers to a "codec" device as a device that performs data encoding and decoding (encoding and / or decoding). Therefore, the video encoder 200 and the video decoder 300 represent examples of codec devices, specifically, video encoders and video decoders, respectively. In some examples, the source device 102 and the destination device 116 can operate in a substantially symmetrical manner, so that each device of the source device 102 and the destination device 116 includes a video encoding and decoding component. Therefore, the system 100 can support one-way or two-way video transmission between the source device 102 and the destination device 116, for example, for video streaming, video playback, video broadcasting or video telephony.

[0036] In general, the video source 104 represents a source of video data (i.e., raw, unencoded video data), and provides a series of consecutive pictures (also referred to as "frames") of the video data to the video encoder 200, which encodes the picture data. The video source 104 of the source device 102 may include a video capture device (such as a camera), a video archive containing previously captured raw video, and / or a video feed interface receiving video from a video content provider. As a further alternative, the video source 104 may generate computer graphics-based data as the source video, or a combination of live video, archived video, and computer-generated video. In each case, the video encoder 200 encodes the captured, pre-captured, or computer-generated video data. The video encoder 200 may rearrange the pictures from the received order (sometimes referred to as "display order") to the codec order for encoding and decoding. The video encoder 200 may generate a bitstream including the encoded video data. The source device 102 may then output the encoded video data to a computer-readable medium 110 via an output interface 108 for reception and / or retrieval by, for example, an input interface 122 of a destination device 116.

[0037] The memory 106 of the source device 102 and the memory 120 of the destination device 116 represent general purpose memory. In some examples, the memories 106, 120 can store original video data, such as original video from the video source 104 and original decoded video data from the video decoder 300. In addition or as an alternative, the memories 106 and 120 can also store software instructions executable by the video encoder 200 and the video decoder 300, respectively. Although in this example, the memory 106 and the memory 120 are shown separately from the video encoder 200 and the video decoder 300, it should be understood that the video encoder 200 and the video decoder 300 can also include internal memory for similar or equivalent functional purposes. In addition, the memories 106, 120 can store encoded video data, such as the output of the video encoder 200 and the input of the video decoder 300. In some examples, a portion of the memories 106, 120 can be allocated as one or more video buffers, for example, for storing original, decoded and / or encoded video data.

[0038] The computer-readable medium 110 may represent any type of medium or device capable of transmitting the encoded video data from the source device 102 to the destination device 116. In one example, the computer-readable medium 110 represents a communication medium that enables the source device 102 to transmit the encoded video data to the destination device in real time, for example, via a radio frequency (RF) network or a computer-based network. According to a communication standard (such as a wireless communication protocol), the output interface 108 can modulate a transmission signal including the encoded video data, and the input interface 122 can demodulate the received transmission signal. The communication medium may include any wireless or wired communication medium, such as a radio frequency spectrum or one or more physical transmission lines. The communication medium may constitute part of a packet-based network, such as a local area network, a wide area network, or a global network (such as the Internet). The communication medium may include a router, a switch, a base station, or any other device that helps facilitate communication from the source device 102 to the destination device 116.

[0039] In some examples, source device 102 may output the encoded data from output interface 108 to storage device 112. Likewise, destination device 116 may access the encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media, such as a hard disk, Blu-ray disc, DVD, CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data.

[0040] In some examples, source device 102 may output the encoded video data to file server 114 or another intermediate storage device, which may store the encoded video data generated by source device 102. Destination device 116 may access the stored video data via streaming or downloading.

[0041] The file server 114 may be any type of server device capable of storing encoded video data and sending the encoded video data to the destination device 116. The file server 114 may represent a network server (e.g., for a website), a server configured to provide a file transfer protocol service (such as a File Transfer Protocol (FTP) or a File Delivery over Unidirectional (FLUTE) protocol), a content delivery network (CDN) device, a hypertext transfer protocol (HTTP) server, a Multimedia Broadcast Multicast Service (MBMS) or an enhanced MBMS (eMBMS) server, and / or a network attached storage (NAS) device. Additionally or alternatively, the file server 114 may implement one or more HTTP streaming protocols, such as HTTP Dynamic Adaptive Streaming (DASH), HTTP Live Streaming (HLS), Real Time Streaming Protocol (RTSP), HTTP Dynamic Streaming, or similar protocols.

[0042] The destination device 116 may access the encoded video data from the file server 114 through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both suitable for accessing encoded video data stored on the file server 114. The input interface 122 may be configured to operate according to any one or more of the various protocols discussed above for retrieving or receiving media data from the file server 114 or other such protocols for retrieving media data.

[0043] Output interface 108 and input interface 122 may represent a wireless transmitter / receiver, a modem, a wired network component (e.g., an Ethernet card), a wireless communication component that operates according to any of the various IEEE 802.11 standards, or other physical components. In examples where output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to transmit data (such as encoded video data) according to a cellular communication standard (such as 4G, 4G-LTE (Long Term Evolution), Advanced LTE, 5G, or similar standards). In some examples where output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may be configured to transmit data (such as encoded video data) according to other wireless standards (such as IEEE 802.11 specifications, IEEE802.15 specifications (e.g., ZigBee™), Bluetooth™ standards, or similar standards). In some examples, source device 102 and / or destination device 116 may include corresponding system-on-chip (SoC) devices. For example, source device 102 may include a SoC device to perform functions attributed to video encoder 200 and / or output interface 108 , and destination device 116 may include a SoC device to perform functions attributed to video decoder 300 and / or input interface 122 .

[0044] The disclosed technology can be applied to video encoding to support any of a variety of multimedia applications, such as over-the-air television broadcasting, cable television transmission, satellite television transmission, Internet streaming video transmission (such as Dynamic Adaptive Streaming over HTTP (DASH)), encoding digital video to a data storage medium, decoding digital video stored on a data storage medium, or other applications.

[0045] The input interface 122 of the destination device 116 receives an encoded video bitstream from the computer-readable medium 110 (e.g., a communication medium, a storage device 112, a file server 114, or a similar device). The encoded video bitstream may include signaling information defined by the video encoder 200, which is also used by the video decoder 300, such as syntax elements with values ​​describing characteristics and / or processing of video blocks or other coded and decoded units (e.g., slices, pictures, groups of pictures, sequences, or similar units). The display device 118 displays the decoded pictures of the decoded video data to the user. The display device 118 may represent any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or other types of display devices.

[0046] Although in Figure 1Not shown, but in some examples, the video encoder 200 and the video decoder 300 may be integrated with an audio encoder and / or an audio decoder, respectively, and may include appropriate MUX-DEMUX units or other hardware and / or software to process a multiplexed stream including both audio and video in a common data stream.

[0047] The video encoder 200 and the video decoder 300 may be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When the technology is partially implemented in software, the device may store the software instructions in a suitable non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the disclosed technology. Each of the video encoder 200 and the video decoder 300 may be included in one or more encoders or decoders, any of which may be integrated in a corresponding device as part of a combined encoder / decoder (CODEC). A device including the video encoder 200 and / or the video decoder 300 may implement the video encoder 200 and / or the video decoder 300 in a processing circuit such as an integrated circuit and / or a microprocessor. Such a device may be a wireless communication device, such as a cellular phone, or any other type of device as described herein.

[0048] The video encoder 200 and the video decoder 300 may operate according to a video coding standard such as ITU-TH.265, also known as High Efficiency Video Coding (HEVC) or an extension thereof such as a multi-view and / or scalable video coding extension. In addition, the video encoder 200 and the video decoder 300 may operate according to other proprietary or industry standards such as ITU-TH.266, also known as Versatile Video Coding (VVC). In other examples, the video encoder 200 and the video decoder 300 may operate according to a proprietary video codec / format such as AOMedia Video 1 (AV1), an extension of AV1, and / or a subsequent version of AV1 (e.g., AV2). In other examples, the video encoder 200 and the video decoder 300 may operate according to other proprietary formats or industry standards. However, the disclosed technology is not limited to any particular coding standard or format. In general, the video encoder 200 and the video decoder 300 may be configured to perform the disclosed technology in conjunction with any video coding and decoding technology using inter-prediction based on affine motion.

[0049] In general, the video encoder 200 and the video decoder 300 can perform block-based encoding on the picture. The term "block" generally refers to a structure that includes data to be processed (e.g., encoded, decoded, or other data used in the encoding and / or decoding process). For example, a block may include a two-dimensional matrix of luminance and / or chrominance data samples. In general, the video encoder 200 and the video decoder 300 can encode and decode video data represented in YUV (e.g., Y, Cb, Cr) format. That is, the video encoder 200 and the video decoder 300 can encode and decode luminance and chrominance components instead of encoding and decoding red, green, and blue (RGB) data sampled from the picture, where the chrominance component may include both red hue and blue hue chrominance components. In some examples, the video encoder 200 converts the received RGB format data into a YUV representation before encoding, and the video decoder 300 converts the YUV identification method into an RGB format. In addition, pre-processing and post-processing units (not shown) may also perform these conversions.

[0050] The present disclosure generally refers to the encoding and decoding of pictures (e.g., encoding and decoding), including the encoding or decoding process of picture data. Similarly, the present disclosure may also refer to the encoding and decoding of picture blocks, including the data encoding or decoding process of the blocks, such as prediction and / or residual encoding and decoding. The encoded video bitstream generally includes a series of syntax element values ​​representing the encoding and decoding decisions (e.g., the encoding and decoding mode), and the partitioning of the picture into blocks. Therefore, when referring to the encoding and decoding of a picture or a block, it should generally be understood as the encoding and decoding values ​​of the syntax elements that form the picture or block.

[0051] HEVC defines various blocks, including codec units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video codec (such as the video encoder 200) partitions a coding tree unit (CTU) into CUs according to a quadtree structure. That is, the video codec partitions the CTU and CU into four equal, non-overlapping squares, and each node of the quadtree has 0 or 4 child nodes. A node without child nodes may be referred to as a "leaf node", and the CU of such a leaf node may include one or more PUs and / or one or more TUs. The video codec may further partition the PU and TU. For example, in HEVC, the residual quadtree (RQT) represents the partitioning of a TU. In HEVC, a PU represents inter-prediction data, and a TU represents residual data. An intra-predicted CU includes intra-prediction information, such as an intra-mode indication.

[0052] As another example, the video encoder 200 and the video decoder 300 can be configured to operate according to VVC. According to VVC, a video codec (such as the video encoder 200) partitions a picture into multiple CTUs. The video encoder 200 can partition the CTU according to a tree structure, such as a quad binary tree (QTBT) structure or a multi-type tree (MTT) structure. The QTBT structure eliminates the concept of multiple partition types, such as the separation between CU, PU, ​​and TU in HEVC. The QTBT structure includes two levels: the first level is partitioned according to a quadtree, and the second level is partitioned according to a binary tree. The root node of the QTBT structure corresponds to the CTU. The leaf nodes of the binary tree correspond to the CU.

[0053] In the MTT partitioning structure, blocks can be partitioned using quadtree (QT) partitioning, binary tree (BT) partitioning, and one or more types of ternary tree (TT) (also known as ternary tree (TT)) partitioning. A ternary tree or ternary tree partitioning is a partitioning that divides a block into three sub-blocks. In some examples, a ternary tree or ternary tree partitioning divides a block into three sub-blocks without dividing the original block through the center. The partitioning types in MTT (e.g., QT, BT, and TT) can be symmetric, or asymmetric.

[0054] When running according to the AV1 codec, the video encoder 200 and the video decoder 300 can be configured to encode and decode video data in blocks. In AV1, the largest codec block that can be processed is called a superblock. In AV1, a superblock can be 128×128 luminance samples or 64×64 luminance samples. However, in subsequent video codec formats (e.g., AV2), superblocks can be defined by different (such as, larger) luminance sample sizes. In some examples, the superblock is the top level of the block quadtree. The video encoder 200 can further divide the superblock into smaller codec blocks. The video encoder 200 can divide superblocks and other codec blocks into smaller blocks using square or non-square partitioning. Non-square blocks may include N / 2×N, N×N / 2, N / 4×N, and N×N / 4 blocks. The video encoder 200 and the video decoder 300 can perform separate prediction and transform processing on each of the codec blocks.

[0055] AV1 also defines tiles of video data. A tile is a rectangular array of super blocks that can be encoded and decoded independently of other tiles. That is, the video encoder 200 and the video decoder 300 can encode and decode the codec blocks within a tile, respectively, without using the video data of other tiles. However, the video encoder 200 and the video decoder 300 can perform filtering across the boundaries of the tile array. The size of the tile can be uniform, or non-uniform. Tile-based encoding and decoding can enable the encoder and decoder to implement parallel processing and / or multi-threading.

[0056] In some examples, the video encoder 200 and the video decoder 300 may use a single QTBT or MTT structure to represent each of the luma and chroma components, while in other examples, the video encoder 200 and the video decoder 300 may use two or more QTBT or MTT structures, such as one QTBT / MTT structure for the luma component and another QTBT / MTT structure for both chroma components (or two QTBT / MTT structures for corresponding chroma components).

[0057] The video encoder 200 and the video decoder 300 may be configured to use quadtree partitioning, QTBT partitioning, MTT partitioning, super block partitioning, or other partitioning structures.

[0058] In some examples, a CTU includes a coding tree block (CTB) of luma samples, two corresponding chroma sample CTBs for a picture with three sample arrays, or a sample CTB for a monochrome picture or a picture encoded and decoded using three separate color planes and syntax structures for encoding and decoding samples. A CTB can be an N×N block of samples, and for some values ​​of N, the division of components into CTBs is a partitioning. A component is one of the three arrays (one chroma array and two chroma arrays) that make up a 4:2:0, 4:2:2, or 4:4:4 color format picture, or an array or a single sample in an array that makes up a monochrome format picture. In some examples, a codec block is an M×N block of samples, and for some values ​​of M and N, the division of the CTB into codec blocks is a partitioning.

[0059] Blocks (e.g., CTUs or CUs) can be grouped in various ways in a picture. For example, a brick can refer to a rectangular area of ​​a CTU row within a specific tile in a picture. A tile can be a rectangular area of ​​a CTU within a specific tile column and a specific tile row in a picture. A tile column refers to a rectangular area of ​​a CTU with a height equal to the picture height and a width specified by a syntax element (e.g., such as a picture parameter set). A tile row refers to a rectangular area of ​​a CTU with a height specified by a syntax element (e.g., such as a picture parameter set) and a width equal to the picture width.

[0060] In some examples, a tile may be partitioned into multiple blocks, each of which may include one or more CTU rows within the tile. A tile that is not partitioned into multiple blocks may also be referred to as a tile. However, a block that is a true subset of a tile may not be referred to as a tile. The blocks in a picture may also be arranged in slices. A slice may be an integer number of blocks in a picture that may be completely contained in a single network abstraction layer (NAL) unit. In some examples, a slice includes a continuous sequence of multiple complete tiles or only complete blocks of one tile.

[0061] The present disclosure may use "N×N" and "N by N" interchangeably to refer to the sampling dimensions of a block (such as a CU or other video block) in the vertical and horizontal dimensions, for example, 16×16 samples or 16 by 16 samples. In general, a 16×16 CU will have 16 samples in the vertical direction (y=16) and 16 samples in the horizontal direction (x=16). Similarly, an N×N CU typically has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. The samples in a CU may be arranged in rows and columns. In addition, the number of samples in the horizontal direction of a CU is not necessarily the same as the number of samples in the vertical direction. For example, a CU may include N×M samples, where M is not necessarily equal to N.

[0062] The video encoder 200 encodes the video data of a CU, which represents prediction and / or residual information and other information. The prediction information indicates how to predict the CU to form the prediction block of the CU. The residual information generally represents the sample-by-sample differences between the CU samples before encoding and the prediction block.

[0063] In order to predict a CU, the video encoder 200 may generally form a prediction block of the CU through inter-prediction or intra-prediction. Inter-prediction generally refers to predicting a CU based on data of a previously coded picture, while intra-prediction generally refers to predicting a CU based on previously coded data of the same picture. To perform inter-prediction, the video encoder 200 may generate a prediction block using one or more motion vectors. The video encoder 200 may generally perform a motion search to determine a reference block that closely matches the CU, for example, based on the difference between the CU and the reference block. The video encoder 200 may calculate a difference metric using the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), or other such difference calculations to determine whether the reference block closely matches the current CU. In some examples, the video encoder 200 may use unidirectional prediction or bidirectional prediction to predict the current CU.

[0064] Some examples of VVC also provide an affine motion compensation mode, which can be considered an inter-prediction mode. In the affine motion compensation mode, the video encoder 200 can determine two or more motion vectors representing non-translational motion, such as zooming in or out, rotation, perspective motion, or other irregular motion types.

[0065] To perform intra prediction, the video encoder 200 can select an intra prediction mode to generate a prediction block. Some examples of VVC provide sixty-seven intra prediction modes, including various directional modes as well as planar modes and direct current modes. In general, the video encoder 200 selects an intra prediction mode that predicts neighboring samples of a current block (e.g., a block of a CU) from which the samples of the current block are predicted. Assuming that the video encoder 200 encodes CTUs and CUs in raster scan order (from left to right, from top to bottom), such samples may generally be above, above and to the left of the current block, or to the left in the same picture as the current block.

[0066] The video encoder 200 encodes data representing the prediction mode of the current block. For example, for inter-prediction mode, the video encoder 200 may encode data representing which mode of various available inter-prediction modes is used, as well as motion information for the corresponding mode. For example, for unidirectional or bidirectional inter-prediction, the video encoder 200 may encode motion vectors using advanced motion vector prediction (AMVP) or merge mode. The video encoder 200 may encode motion vectors using a similar mode for affine motion compensation mode.

[0067] AV1 includes two general techniques for encoding and decoding codec blocks of video data. These two general techniques are intra prediction (e.g., intra-frame prediction or spatial prediction) and inter prediction (e.g., inter-frame prediction or temporal prediction). In the case of AV1, when an intra-frame prediction mode is used to predict a block of video data of the current frame, the video encoder 200 and the video decoder 300 do not use video data from other frames of video data. For most intra-prediction modes, the video encoder 200 encodes a block of the current frame based on the difference between the sample value in the current block and the predicted value generated by the reference sample in the same frame. The video encoder 200 determines the predicted value generated by the reference sample based on the intra-prediction mode.

[0068] After prediction (such as intra-prediction or inter-prediction), the video encoder 200 can calculate residual data for the block. The residual data (such as a residual block) represents the sample-by-sample difference between the block and the predicted block of the block formed using the corresponding prediction mode. The video encoder 200 can apply one or more transforms to the residual block to produce transform data in a transform domain rather than a sampling domain. For example, the video encoder 200 can apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a similar conceptual transform to the residual video data. In addition, the video encoder 200 can also apply a second transform after the first transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal-dependent transform, a Karhunen-Loeve transform (KLT), or a similar transform. The video encoder 200 generates transform coefficients after applying one or more transforms.

[0069] As described above, after performing any transforms to produce transform coefficients, the video encoder 200 may perform quantization on the transform coefficients. Quantization generally refers to the process of quantizing the transform coefficients to potentially reduce the amount of data used to represent the transform coefficients, providing further compression. By performing the quantization process, the video encoder 200 may reduce the bit depth associated with some or all of the transform coefficients. For example, the video encoder 200 may round down an n-bit value to an m-bit value during the quantization process, where n is greater than m. In some examples, to perform quantization, the video encoder 200 may perform a bitwise right shift on the value to be quantized.

[0070] After quantization, the video encoder 200 may scan the transform coefficients to produce a one-dimensional vector from a two-dimensional matrix including quantization of the transform coefficients. The scan may be specified to place transform coefficients with higher energy (and therefore lower frequency) in front of the vector and transform coefficients with lower energy (and therefore higher frequency) in the back of the vector. In some examples, the video encoder 200 may scan the quantized transform coefficients using a predefined scan order to generate a serialized vector, and then entropy encode the quantized transform coefficients of the vector. In other examples, the video encoder 200 may perform adaptive scanning. After scanning the quantized transform coefficients to form a one-dimensional vector, the video encoder 200 may entropy encode the one-dimensional vector, for example, according to context adaptive binary arithmetic coding (CABAC). The video encoder 200 may also entropy encode the values ​​of the syntax elements describing metadata associated with the encoded video data for use by the video decoder 300 when decoding the video data.

[0071] To perform CABAC, the video encoder 200 may assign context to symbols to be sent in a context model. For example, the context may involve whether the neighboring values ​​of the symbol are zero values. The probability determination may be based on the context assigned to the symbol.

[0072] The video encoder 200 may further generate syntax data (such as block-based syntax data, picture-based syntax data, and sequence-based syntax data) to the video decoder 300, for example, in a picture header, a block header, a slice header, or other syntax data, such as a sequence parameter set (SPS), a picture parameter set (PPS), or a video parameter set (VPS). The video decoder 300 may also decode such syntax data to determine how to decode the corresponding video data.

[0073] In this way, the video encoder 200 can generate a bitstream including encoded video data, for example, describing the syntax elements for dividing a picture into blocks (e.g., CUs) and prediction and / or residual information of the blocks. Finally, the video decoder 300 can receive the bitstream and decode the encoded video data.

[0074] In general, the video decoder 300 performs processing that is inverse to that performed by the video encoder 200 to decode the encoded video data of the bitstream. For example, the video decoder 300 may use CABAC to decode syntax element values ​​of the bitstream in a manner substantially similar (albeit equivalent) to the CABAC encoding process of the video encoder 200. The syntax elements may define partitioning information for partitioning a picture into CTUs, and partitioning each CTU according to a corresponding partitioning structure (such as a QTBT structure) to define CUs of the CTU. The syntax elements may further define prediction and residual information for a block of video data (e.g., a CU).

[0075] The residual information may be represented by, for example, quantized transform coefficients. The video decoder 300 may inverse quantize and inverse transform the quantized transform coefficients of the block to regenerate a residual block of the block. The video decoder 300 uses the signal prediction mode (intra-prediction or inter-prediction) and related prediction information (e.g., motion information for inter-prediction) to form a prediction block of the block. The video decoder 300 may then combine the prediction block and the residual block (on a sample-by-sample basis) to regenerate the original block. The video decoder 300 may perform additional processing, such as performing a deblocking process, to reduce visual artifacts along block boundaries.

[0076] The present disclosure may generally refer to "signaling" certain information, such as syntax elements. The term "signaling" may generally refer to the communication of syntax element values ​​and / or other data used to decode encoded video data. That is, the video encoder 200 may signal syntax element values ​​in a bitstream. In general, signaling refers to generating values ​​in a bitstream. As described above, the source device 102 may transmit the bitstream to the destination device 116 in substantially real time or in non-real time, such as may occur when storing syntax elements to the storage device 112 for subsequent retrieval by the destination device 116.

[0077] According to the disclosed technology, as will be explained in detail below, the video encoder 200 and the video decoder 300 can be configured to encode and decode video data using an affine DMVR mode. For example, the video encoder 200 and the video decoder 300 can be configured to: receive a block of video data to be encoded and decoded using an affine DMVR mode; divide the block into a plurality of sub-blocks; and determine a control point motion vector (CPMV) offset using a first subset of the plurality of sub-blocks. To determine the CPMV offset, the video encoder 200 and the video decoder 300 can skip at least one motion compensation process or bilateral matching cost calculation on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks. The video encoder 200 and the video decoder 300 can encode the video data block using the CPMV offset. More details about the disclosed technology will be described below.

[0078] Affine Inter-Mode Prediction

[0079] In some examples, the affine motion model can be described as follows:

[0080] ,

[0081] in,( ) is the motion vector at the coordinate (x, y), and a, b, c, d, e, and f are six affine parameters. The above affine motion mode affine motion model may be referred to as a 6-parameter affine motion model. In some examples, the video encoder 200 and the video decoder 300 may be configured to partition a picture into blocks for block-based encoding and decoding. The affine motion model of a block may also be composed of three motion vectors (MVs) at three different positions that are not in the same row. , and These three locations are often called control points, and the three motion vectors are called control point motion vectors (CPMVs). When the three control points are located at the three corners of the block, the affine motion can be described as follows:

[0082]

[0083] in and are the width and height of the block.

[0084] In affine mode, video encoder 200 and video decoder 300 may be configured to derive different motion vectors for each pixel in a block according to an associated affine motion model. Accordingly, motion compensation may be performed on a per-pixel basis. However, to reduce the complexity of the implementation, sub-block based motion compensation may be performed, where the block is divided into multiple sub-blocks (with a smaller block size), and each sub-block is associated with a motion vector for block-based motion compensation.

[0085] Video encoder 200 and video decoder 300 may be configured to derive the motion vector for each sub-block using the representative coordinates of the sub-block. In some examples, the center position of the sub-block is used as the representative coordinate. In one example, video encoder 200 and video decoder 300 may divide the block into non-overlapping sub-blocks. The width of the block is blkW, the height of the block is blkH, the width of the sub-block is sbW, and the height of the sub-block is sbH. In this example, the sub-block has blkH / sbH rows, and each row has blkW / sbW sub-blocks.

[0086] For a six-parameter affine motion model, the sub-block motion vector (referred to as sub-block MV) at the i-th row (0 <= i < blkW / sbW) and the j-th column (0 <= j < blkH / sbH) is derived as follows:

[0087]

[0088] Video encoder 200 and video decoder 300 may be configured to round the sub-block MV to a predefined precision and store the motion vector in a motion buffer for motion compensation and motion vector prediction.

[0089] A simplified four-parameter affine model (for scaling and rotation motion) is described as follows:

[0090]

[0091] Similar to the six-parameter affine model, the four-parameter affine model of the block may be described by two CPMVs: at two corners of the block (usually the upper left corner and the upper right corner) and . Then, the motion field is described as follows:

[0092]

[0093] The sub-block MV at the i-th row and the j-th column is derived as follows:

[0094]

[0095] Prediction refinement of affine models

[0096] After performing sub-block based affine motion compensation, the video encoder 200 and the video decoder 300 may be configured to refine the prediction signal. Refining the prediction signal may include adding an offset derived based on pixel motion and the prediction signal gradient. The offset at It can be calculated as:

[0097] ,

[0098] in, is the horizontal gradient of the prediction signal, and is the vertical gradient of the prediction signal. and At the pixel position The difference between the motion vector calculated at and the x and y components of the sub-block MV. The coordinates of the upper left sample of the sub-block may be ). In this case, the center of the sub-block is Given the affine motion parameters a, b, c and d, and It can be deduced as follows:

[0099]

[0100]

[0101] In the control point based affine motion model, the video encoder 200 and the video decoder 300 may calculate affine motion parameters a, b, c, and d according to the CPMV as follows:

[0102]

[0103]

[0104]

[0105]

[0106] Decoder-side motion vector refinement

[0107] In some example video codecs, such as the Versatile Video Coding (VVC) standard, the video encoder 200 and the video decoder 300 may be configured to apply a decoder-side motion vector refinement (DMVR) based on bilateral matching (BM) to improve the accuracy of the MV of the bi-predictive merging candidate. When performing the example BM method, the video encoder 200 and the video decoder 300 may be configured to calculate the sum of absolute differences (SAD) between two candidate blocks in the reference picture list L0 (e.g., the first prediction direction) and the reference picture list L1 (e.g., the second prediction direction).

[0108] like Figure 2 As shown, the video encoder 200 and the video decoder 300 can be configured to calculate the SAD between block 500 and block 502 based on each MV candidate block around the initial MV. SAD can be called distortion cost calculation or bilateral matching cost calculation. The candidate MV with the lowest SAD will become the refined MV and is used to generate the bilateral prediction signal. In some examples, the SAD of the initial MV will be subtracted by 1 / 4 of the SAD value as a regularization term. Figure 2 In the example of , the temporal distances (eg, picture order count (POC) differences) from the two reference pictures to the current picture should be the same, so the motion vector difference (MVD0) of MV0 and the motion vector difference (MVD1) of MV1 have opposite signs.

[0109] The refinement search range is two integer brightness samples of the initial MV. The search includes an integer sample offset search stage and a fractional sample refinement stage. A 25-point full search is applied to the integer sample offset search. First, the SAD of the initial MV pair is calculated. If the SAD of the initial MV pair is less than the threshold, the integer sample stage of the DMVR is terminated. Otherwise, the SAD of the remaining 24 points is calculated and checked in raster scan order. The point with the smallest SAD is selected as the output of the integer sample offset search stage.

[0110] The integer sampling search is followed by fractional sampling refinement. To reduce computational complexity, the fractional sampling refinement can be derived using the parameter error surface equation instead of an additional search using SAD comparison. In one example, the fractional sampling refinement is conditionally invoked based on the output of the integer sampling search stage. When the integer sampling search stage ends at the center with the minimum SAD in the first or second iteration search, the fractional sampling refinement is further applied.

[0111] In the sub-pixel offset estimation based on the parameter error surface, the cost at the center position and the costs at the four positions adjacent to the center are used to fit the two-dimensional parabolic error surface equation of the following form:

[0112] , (1)

[0113] in,( corresponds to the fractional position with the minimum cost, and C corresponds to the minimum cost value. Solving the above equation using the cost values ​​of the five search points, ( Calculated as:

[0114] (2)

[0115] (3)

[0116] Will and The value of is automatically limited to between -8 and 8, because all cost values ​​are positive and the minimum value is This is equivalent to a half-pel offset for the 1 / 16 MV accuracy in VVC. The calculated fractional value ( Added to the integer distance refinement MV to get the refinement deltaMV with sub-pixel accuracy.

[0117] In VVC, the resolution of MV is 1 / 16 luma sample. Samples at fractional positions are interpolated using an 8-tap interpolation filter. In DMVR mode, the search points are around the initial fractional-frequency MV with an integer sample offset. Therefore, in the DMVR search process, the samples at these fractional positions are interpolated. In order to reduce computational complexity, a bilinear interpolation filter is used to generate fractional samples in the DMVR search process. Another effect of using a bilinear filter is that the DVMR process does not access more reference samples within a search range of 2 samples compared to ordinary motion compensation processing. After the refined MV is obtained through the DMVR search process, an ordinary 8-tap interpolation filter is applied to generate the final prediction result. In order not to access more reference samples in normal motion compensation processing, samples that are not required for the interpolation process based on the initial MV but are required for the interpolation process based on the refined MV will be filled from these available samples.

[0118] When the width and / or height of a CU is greater than 16 luma samples, the CU will be further divided into sub-blocks with a width and / or height equal to 16 luma samples for DMVR processing.

[0119] In VVC, DMVR processing can be applied to CUs encoded and decoded in the following modes and features:

[0120] -CU layer merge mode with bi-prediction MV

[0121] - Relative to the current picture, one reference picture is in the past and the other reference picture is in the future

[0122] - The distances from both reference pictures to the current picture (i.e., POC differences) are the same

[0123] - Both reference images are short-term reference images

[0124] -CU has more than 64 luma samples

[0125] -CU height and CU width are both greater than or equal to 8 luma samples

[0126] - Bi-prediction (BCW) weight index with CU level weights indicates equal weight

[0127] - Weighted Prediction (WP) is not enabled for the current block

[0128] -The current block does not use the Combined Intra Prediction (CIIP) mode

[0129] Decoder-side motion vector refinement for affine merge mode

[0130] An example DMVR process for a bi-directional predictive affine merge candidate mode is proposed. In this example, the video encoder 200 and the video decoder 300 are configured to add a translational MV offset (e.g., a final offset or a CPMV offset) to all CPMVs of the candidate in the affine merge list if the candidate satisfies the DMVR condition. The video encoder 200 and the video decoder 300 can derive the MV offset (e.g., the final offset) by minimizing the cost of bilateral matching, which is similar to the traditional DMVR process. The difference is that affine motion compensation is performed to generate predictors in both directions. The MV offset search process is the same as the first channel (prediction unit level) of multi-channel DMVR in enhanced compression mode (ECM). A 3×3 square search pattern is used to cyclically search the possible candidate offset range (e.g., [-8, +8] in the horizontal direction and [-8, +8] in the vertical direction) to find the best integer MV offset. Then, a half-frequency search is performed around the best integer position, and finally an error surface estimation is performed to determine the MV offset with 1 / 16 accuracy.

[0131] To compute the bilateral matching cost (or more generally, the distortion cost) for a given bidirectional affine motion, the following procedure can be applied:

[0132] 1) Add the candidate offsets to both directions of each bidirectional CPMV to update the CPMV.

[0133] 2) Apply affine motion compensation based on the updated CPMV to generate predictions in two directions.

[0134] 3) Calculate the distortion between the generated predictors using a predefined cost criterion.

[0135] The candidate offset with the lowest bilateral matching cost is selected as the final offset and added to the CPMV. Typically, affine motion compensation is based on sub-blocks, where the current block is split into non-overlapping sub-blocks. Regular motion compensation is performed on each sub-block, where all samples in the sub-block share the same motion. In VVC, after sub-block-based motion compensation, optical flow prediction refinement (PROF) can be applied to further improve the predictor.

[0136] Sub-block based motion compensation

[0137] Sub-block based motion compensation can be used for affine motion compensation for affine motion search (eg, in encoder-side affine motion estimation or decoder-side affine motion refinement). This disclosure describes sub-block skipping / subsampling techniques for reducing the complexity of affine motion compensation.

[0138] In general, the video encoder 200 and the video decoder 300 can be configured to skip at least one sub-block in a block (e.g., CU) for affine motion compensation. Therefore, as described above, when determining the final offset of the CPMV, those skipped sub-blocks are excluded from the motion compensation process and the distortion (e.g., bilateral matching cost) between the generated predictors calculated using a predefined cost criterion. In other words, the video encoder 200 and the video decoder 300 are configured to use a subset of the sub-blocks of the block when calculating the distortion during the affine motion search (e.g., DMVR processing of the affine merge mode). The disclosed technology can reduce the computational complexity of the sub-block-based affine motion search process, but will not substantially reduce the codec efficiency. That is, testing has shown that using only a subset of the sub-blocks of the block to determine the final offset of the affine DMVR mode results in a codec efficiency that is substantially the same as the codec efficiency using all sub-blocks. Accordingly, the final offset can be determined with fewer computing resources and faster.

[0139] Sub-block skipping can be implemented by sub-sampling the sub-blocks that will be used for affine DMVR processing to determine the final offset value. In one example, a sampling rate of ½ can be used for the sub-blocks in the horizontal or vertical direction or in both directions. That is, for a sampling rate of 1 / 2, the resulting subset of sub-blocks can include every other sub-block in the horizontal and vertical directions. However, the disclosed technology can be extended to other sampling rates, including 1 / 4 and 1 / 8, as some examples. For a 1 / 4 sub-sampling rate, every four sub-blocks can be used in either or both of the horizontal and vertical directions. Similarly, for a 1 / 8 sub-sampling rate, every eight sub-blocks can be used in either or both of the horizontal and vertical directions.

[0140] The video encoder 200 and the video decoder 300 may be configured to receive a block of video data to be decoded using an affine DMVR mode. Although described with reference to affine DMVR, the disclosed techniques may be applied to any prediction mode using sub-block based motion compensation. In one example, the inter-prediction mode is an affine motion compensation mode, including affine mode DMVR. The disclosed techniques may also be used for encoder-side affine motion estimation.

[0141] The video encoder 200 and the video decoder 300 may be configured to divide the block into a plurality of sub-blocks. In some examples, the video encoder 200 and the video decoder 300 may be configured to divide the plurality of sub-blocks into a first subset of sub-blocks and a second subset of sub-blocks. As will be described in detail below, the video encoder 200 and the video decoder 300 may determine the final offset of the affine DMVR mode using only the first subset of sub-blocks. To determine the first subset of sub-blocks to be used in the affine DMVR process, the video encoder 200 and the video decoder 300 may sub-sample the plurality of sub-blocks.

[0142] In one example, the video encoder 200 and the video decoder 300 are configured to perform motion compensation and distortion cost calculation on every other row and column of sub-blocks of a block in an affine DMVR process. Affine DMVR processing is skipped for other sub-blocks. That is, a sub-sampling rate of 1 / 4 is used.

[0143] Figure 3A and 3B An example of a sub-block skip mode for affine motion search according to the disclosed technology is shown. Figure 3A and 3B As shown, the video encoder 200 and the video decoder 300 skip performing motion compensation on the sub-block 600 (e.g., the second subset of sub-blocks) and calculating the distortion between the generated predictors using the predefined cost criteria as described above. Instead, the video encoder 200 and the video decoder 300 perform motion compensation and calculate the distortion between the generated predictors using the predefined cost criteria on the sub-block 610 (e.g., the first subset of sub-blocks). Figure 3A and 3B In the example of , the video encoder 200 and the video decoder 300 can be configured to skip all sub-blocks in every other row and every other column of sub-blocks. In this example, only one quarter of the sub-blocks are processed in the affine DMVR process to determine the final offset.

[0144] The following describes a general process that the video encoder 200 and the video decoder 300 can use to subsample subblocks of a block of video data to determine a first subset of subblocks for performing affine DMVR offset determination. The subblock width is represented as dx and the subblock height is represented as dy. In one example, stepX is set equal to 2*dx and stepY is set equal to 2*dy, and the upper left sample coordinate of the subblock is represented as (lx, ly). In this example, the video encoder 200 and the video decoder 300 are configured to perform motion compensation and distortion cost calculations on the subblocks when lx%stepX is 0 and ly%stepY is 0, where % is a modulus operation. stepX and stepY refer to the frequency at which the video encoder 200 and / or the video decoder 300 selects subblocks for motion compensation and distortion calculations. In the horizontal direction, a subblock is selected every stepX samples. In the vertical direction, a subblock is selected every stepY samples.

[0145] In one example, the video encoder 200 and the video decoder 300 can be configured to set the step size to stepX and stepY and then loop on the coordinates. In another example, the step size looped on the upper left sample coordinates of the sub-block is stepX and stepY of lx and ly respectively. In this way, motion compensation is only applied to a quarter of all sub-blocks.

[0146] In one example, the video encoder 200 and the video decoder 300 are configured to perform motion compensation and distortion cost calculation on every other row of sub-blocks. Figure 4A and 4B In this example, only half of the sub-blocks are processed. In another example, the video encoder 200 and the video decoder 300 are configured to perform motion compensation and distortion cost calculation on the sub-blocks in every other column, such as Figure 5A and 5B In this example, only half of the sub-blocks are processed.

[0147] In yet another example, the sub-block skipping pattern is a "checkerboard" pattern, such as Figure 6 As shown. Figure 6 In the example of , the video encoder 200 and the video decoder 300 are configured to perform motion compensation and distortion cost calculation for the sub-block 700 and skip motion compensation and distortion cost calculation for the sub-block 710. Of course, in other examples, the sub-blocks 700 and 710 may also be swapped. Figure 7 In the example shown in Figure 2, only half of the sub-blocks are processed.

[0148] Figure 3A , 3B , 4A, 4B, 5A, 5B and Figure 6Some possible examples of sub-sampling sub-blocks for affine DMVR processing are shown.Other sub-block patterns may be used as the first subset of sub-blocks for affine DMVR processing.

[0149] In some examples, the video encoder 200 and the video decoder 300 may operate according to constraints on when the sub-block skipping techniques of the present disclosure may be applied. In one example, if the number of sub-blocks in a block is less than a certain threshold (e.g., 4), the sub-block skipping techniques of the present disclosure are not applied. In another example, if the number of sub-blocks in a row is less than a certain threshold (e.g., 2), skipping is not applicable in the x-direction. In yet another example, if the number of sub-blocks in a column is less than a certain threshold (e.g., 2), skipping is not applicable in the y-direction.

[0150] The sub-block skipping technology disclosed herein can be used for any affine DMVR technology, including the affine DMVR technology disclosed in U.S. patent application No. 18 / 351,342 filed on July 12, 2023 (hereinafter referred to as 'Application No. 342').

[0151] An example affine DMVR process may be performed as follows. If the candidate satisfies the DMVR condition, the video decoder 300 may apply a translational MV offset (e.g., the candidate offset) to all CPMVs of the candidate from the affine merge list. The final offset may be derived by minimizing the cost of bilateral matching. The offset search process for affine DMVR is the same as the first pass of multi-pass DMVR. A 3×3 square search pattern may be used to loop through a candidate offset search range (e.g., [-8, +8] horizontally and [-8, +8] vertically) to find the best integer offset. In some examples, a half-frequency search may be performed around the best integer offset, and an error surface estimation may be performed to find the final offset with an accuracy of 1 / 16.

[0152] To calculate the bilateral matching cost for a given candidate offset, the video decoder 300 may apply the following steps: a) first add the candidate offset to each CPMV of the two prediction directions; b) derive sub-block motion fields based on the updated CPMVs; c) apply sub-block based motion compensation based on the sub-block motion fields in each direction; and d) apply prediction refinement with affine motion (as described above) to refine the predictor generated from step c).

[0153] According to the disclosed techniques, the video decoder 300 may add candidate offsets to each CPMV in two directions for a subset of sub-blocks in a block. The video decoder 300 may derive a sub-block motion field based on the updated CPMV for the subset of sub-blocks in the block. The video decoder 300 may apply sub-block based motion compensation based on the sub-block motion field in each direction for the subset of sub-blocks in the block. The video decoder 300 may apply prediction refinement of affine motion (as described above) to refine the predictor generated by applying sub-block based motion compensation based on the sub-block motion field in each direction.

[0154] The '342 application describes a different DMVR design for an affine motion model, where the sub-block motion field is generated only once. The '342 application's DMVR design can be summarized in the following steps:

[0155] 1) Divide the current block into sub-blocks.

[0156] 2) Based on the initial affine motion model, generate initial motion vectors (in both prediction directions) for each sub-block (sub-block motion field).

[0157] 3) Loop through each sub-block and calculate the bilateral matching cost of all possible offset sub-blocks.

[0158] 4) For each possible offset, accumulate the sub-block bilateral matching costs to generate a bilateral matching cost corresponding to the entire block.

[0159] 5) Determine the best offset by choosing the offset with the smallest bilateral matching cost corresponding to the entire block.

[0160] It should be noted that this approach generates the sub-block motion field only once, rather than for each candidate offset.

[0161] The sub-block size in the above process can be the same as the sub-block size used for affine motion compensation, which is usually 4×4. The size of the sub-block can also be different. In some examples, the sub-block size can be a larger sub-block (e.g., 8×8, 16×16), that is, the number of sub-blocks is small, to reduce the complexity of the DMVR process.

[0162] In step 3) above, given the offset and the initial motion vector (generated in step 2), a candidate motion vector can be derived (when mirror bilateral matching, the offset is added to the motion vector in one direction and subtracted from the motion vector in the other direction), and then motion compensation is performed to generate a predictor for the corresponding subblock. For simplicity, prediction refinement can be skipped. In addition, it should be noted that pre-interpolation can be applied to generate predictors for all possible offsets in one step, thereby greatly reducing complexity. Bilinear interpolation can be used instead of the 8-tap (6-tap or 12-tap) interpolation filter typically used for final motion compensation.

[0163] Sub-pixel offset estimation based on parameter error surface can also be applied after step 5) to generate sub-pixel offset.

[0164] Certain size constraints may be applied. For example, DMVR is only applied to affine blocks larger than N×N, where N is set equal to 8, 16, 32, etc. In another example, the size constraint depends on the sub-block size used in the DMVR process, where N is set equal to the sub-block size.

[0165] A high-level syntax may be used to control whether DMVR for affine blocks is applied and signaled in the bitstream, e.g., in a sequence parameter set, picture header, slice header, etc.

[0166] According to the disclosed techniques, the affine DMVR process in the aforementioned '342 application may be modified as follows. The video encoder 200 and the video decoder 300 may receive a current block of video data to be decoded using an affine DMVR mode. The video encoder 200 and the video decoder 300 may divide the current block into a plurality of sub-blocks. In one example, to divide the block into the plurality of sub-blocks, the video encoder 200 and the video decoder 300 may sub-sample the plurality of sub-blocks to determine a first subset of the plurality of sub-blocks on which the affine DMVR process is performed.

[0167] In one example, the first subset of the plurality of sub-blocks is half of the plurality of sub-blocks. For example, the first subset of the plurality of sub-blocks may include every other row of the plurality of sub-blocks in the block or every other row of sub-blocks in the block. In another example, the first subset of the plurality of sub-blocks is in a checkerboard (or pentagonal) pattern in the block. In other examples, the first subset of the plurality of sub-blocks is one-quarter of the sub-blocks in the block, for example, including sub-blocks in every other column and every other row of sub-blocks in the block.

[0168] The video encoder 200 and the video decoder 300 may determine the final offset of the affine DMVR pattern using the first subset of the plurality of sub-blocks. For example, the video encoder 200 and the video decoder 300 may determine the final offset of the affine DMVR pattern using only the first plurality of sub-blocks, and may skip bilateral matching cost calculation on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks.

[0169] To determine the final offset, the video encoder 200 and the video decoder 300 may determine a corresponding initial motion vector (for both the first prediction direction and the second prediction direction) for each sub-block that is not skipped (e.g., a first subset of sub-blocks) based on the initial affine motion model. The video encoder 200 and the video decoder 300 may determine the initial affine motion model from the candidate affine motion models (e.g., candidate CPMVs or motion vectors) in the affine candidate merge list.

[0170] The video encoder 200 and the video decoder 300 may generate a plurality of candidate motion vectors for each of the first plurality of sub-blocks. Generating a plurality of candidate motion vectors may add each of the plurality of candidate offsets to the corresponding initial motion vector. For example, as described above, the candidate offsets may be within a search range of [-8, +8] in the horizontal direction and a search range of [-8, +8] in the vertical direction. In other examples, other search ranges may be used.

[0171] The video encoder 200 and the video decoder 300 may loop over each sub-block that is not skipped (e.g., a first subset of sub-blocks) and perform an affine motion compensation process to generate a predictor for each prediction direction. Based on these predictors, the video encoder 200 and the video decoder 300 may calculate the sub-block bilateral matching costs for all possible candidate offsets. For example, the video encoder 200 and the video decoder 300 may calculate the corresponding bilateral matching costs for each sub-block in the first plurality of sub-blocks for each candidate motion vector in the plurality of candidate motion vectors.

[0172] For each possible offset, the video encoder 200 and the video decoder 300 may accumulate the corresponding sub-block bilateral matching costs to generate a bilateral matching cost corresponding to all non-skipped sub-blocks (e.g., the first subset of sub-blocks). For example, the video encoder 200 and the video decoder 300 may accumulate the corresponding bilateral matching costs of all sub-blocks of the first plurality of sub-blocks for each candidate motion vector in the plurality of candidate motion vectors to generate a corresponding accumulated bilateral matching cost.

[0173] Then, the video encoder 200 and the video decoder 300 may determine the best offset by selecting the candidate offset with the smallest cumulative bilateral matching cost corresponding to the entire block. For example, the video encoder 200 and the video decoder 300 may determine the final offset as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

[0174] The video encoder 200 and the video decoder 300 may encode or decode (e.g., respectively encode or decode) the video data block using the final offsets to generate an encoded or decoded video data block. In one example, to encode or decode the video data block using the final offsets, the video encoder 200 and the video decoder 300 may determine a control point motion vector for the video data block, add the final offsets to the control point motion vector to create a refined control point motion vector, and encode the video data block using the refined control point motion vector.

[0175] Figure 7 is a block diagram illustrating an example video encoder 200 that may implement the disclosed techniques. Figure 7 The purpose of this disclosure is for explanation and should not be considered as limiting the techniques widely exemplified and described in this disclosure. For the purpose of explanation, this disclosure describes the video encoder 200 according to VVC and HEVC techniques. However, the disclosed techniques can be performed by video encoding devices configured for other video codec standards and video codec formats, such as AV1 and subsequent formats of the AV1 video codec format.

[0176] exist Figure 7 In the example of , the video encoder 200 includes a video data memory 230, a mode selection unit 202, a residual generation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a filter unit 216, a decoded picture buffer (DPB) 218, and an entropy coding unit 220. Any or all of the video data memory 230, the mode selection unit 202, the residual generation unit 204, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the filter unit 216, the DPB 218, and the entropy coding unit 220 can be implemented in one or more processors or processing circuits. For example, the units of the video encoder 200 can be implemented as part of a hardware circuit, or as part of a processor, ASIC, or FPGA, in the form of one or more circuits or logic elements. In addition, the video encoder 200 can also include additional or alternative processors or processing circuits to perform these functions and other functions.

[0177] The video data memory 230 may store video data to be encoded by the components of the video encoder 200. The video encoder 200 may receive video data from, for example, the video source 104 ( Figure 1 ) receives video data stored in the video data memory 230. The DPB 218 can be used as a reference picture memory that stores reference video data used by the video encoder 200 to predict subsequent video data. The video data memory 230 and the DPB 218 can be formed by any of a variety of memory devices, such as a dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM) or other types of memory devices. The video data memory 230 and the DPB 218 can be provided by the same memory device or a separate memory device. In various examples, the video data memory 230 can be located on-chip with other components of the video encoder 200 (as shown in the figure), or it can be located off-chip relative to these components.

[0178] In the present disclosure, reference to the video data memory 230 should not be interpreted as limited to the internal memory of the video encoder 200 (unless otherwise specified) or the external memory of the video encoder 200 (unless otherwise specified). Instead, reference to the video data memory 230 should be understood as a reference memory that stores video data received by the video encoder 200 for encoding (e.g., video data of a current block to be encoded). Figure 1 The memory 106 in the video encoder 200 may also temporarily store outputs from various units.

[0179] Figure 7 The various units shown are helpful in understanding the operations performed by the video encoder 200. These units can be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide specific functions and preset the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functions in the executable operations. For example, a programmable circuit can execute software or firmware so that the programmable circuit works in a manner specified by the software or firmware instructions. Fixed-function circuits can execute software instructions (e.g., receive parameters or output parameters), but the type of operation performed by the fixed-function circuit is generally unchangeable. In some examples, one or more units may be different circuit blocks (fixed function or programmable), and in some examples, one or more units may be integrated circuits.

[0180] The video encoder 200 may include an arithmetic logic unit (ALU), an elementary function unit (EFU), a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example in which the operation of the video encoder 200 is performed using software executed by a programmable circuit, the memory 106 ( Figure 1 ) may store instructions (eg, object code) for software received and executed by the video encoder 200, or another memory (not shown) within the video encoder 200 may store such instructions.

[0181] The video data memory 230 is configured to store received video data. The video encoder 200 may retrieve a video data picture from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 may be original video data to be encoded.

[0182] The mode selection unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra prediction unit 226. The mode selection unit 202 may include additional functional units to perform video prediction according to other prediction modes. For example, the mode selection unit 202 may include a palette unit, an intra-block copy unit (which may be part of the motion estimation unit 222 and / or the motion compensation unit 224), an affine unit, a linear model (LM) unit, or the like.

[0183] The mode selection unit 202 generally coordinates multiple encoding passes to test encoding parameter combinations and generate rate-distortion values ​​for these combinations. The encoding parameters may include partitioning a CTU into CUs, a prediction mode for a CU, a transform type for residual data of a CU, a quantization parameter for residual data of a CU, etc. The mode selection unit 202 may ultimately select an encoding parameter combination that has a rate-distortion value that is better than other tested combinations.

[0184] The video encoder 200 may partition the picture retrieved from the video data memory 230 into a series of CTUs, and encapsulate one or more CTUs in a slice. The mode selection unit 202 may partition the CTUs of the picture according to a tree structure (such as an MTT structure, a QTBT structure, a super block structure, or the above-mentioned quadtree structure). As described above, the video encoder 200 may partition the CTU according to the tree structure to form one or more CUs. Such CUs may also be generally referred to as "video blocks" or "blocks".

[0185] In general, the mode selection unit 202 also controls its components (e.g., the motion estimation unit 222, the motion compensation unit 224, and the intra prediction unit 226) to generate a prediction block for a current block (e.g., a current CU, or in HEVC, the overlapping portion of a PU and a TU). For inter prediction of the current block, the motion estimation unit 222 may perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously encoded pictures stored in the DPB 218). Specifically, the motion estimation unit 222 may calculate a value representing how similar the potential reference blocks are to the current block, for example, based on a sum of absolute differences (SAD), a sum of squared differences (SSD), a mean absolute difference (MAD), a mean squared difference (MSD), or a similar value. The motion estimation unit 222 may generally perform these calculations using sample-by-sample differences between the current block and the reference block under consideration. The motion estimation unit 222 may identify the reference block having the lowest value of these calculation results, indicating the reference block that most closely matches the current block.

[0186] The motion estimation unit 222 may form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to the position of a current block in a current picture. The motion estimation unit 222 may then provide the motion vectors to the motion compensation unit 224. For example, for unidirectional inter prediction, the motion estimation unit 222 may provide a single motion vector, and for bidirectional inter prediction, the motion estimation unit 222 may provide two motion vectors. The motion compensation unit 224 may then use the motion vectors to generate a prediction block. For example, the motion compensation unit 224 may use the motion vectors to retrieve data for the reference block. As another example, if the motion vector has fractional sample accuracy, the motion compensation unit 224 may interpolate the prediction block according to one or more interpolation filters. In addition, for bidirectional inter prediction, the motion compensation unit 224 may retrieve data for two reference blocks identified by corresponding motion vectors and merge the retrieved data (e.g., by sample-by-sample averaging or weighted averaging).

[0187] When operating according to the AV1 video coding format, the motion estimation unit 222 and the motion compensation unit 224 may be configured to encode codec blocks of video data (e.g., luma and chroma codec blocks) using translational motion compensation, affine motion compensation, overlapped block motion compensation (OBMC), and / or composite intra prediction.

[0188] As another example, for intra prediction or intra prediction coding, the intra prediction unit 226 can generate a prediction block from neighboring samples of the current block. For example, for directional mode, the intra prediction unit 226 can generally combine the values ​​of neighboring samples by mathematical methods and populate these calculated values ​​in the defined direction of the current block to generate a prediction block. As another example, for direct current mode, the intra prediction unit 226 can calculate the average value of neighboring samples of the current block and generate a prediction block to include the average value of each sample in the prediction block.

[0189] When operating according to the AV1 video codec format, the intra prediction unit 226 can be configured to encode codec blocks (e.g., luma and chroma codec blocks) of video data using directional intra prediction, non-directional intra prediction, recursive filtering intra prediction, chroma-luminance (CFL) prediction, intra block copy (IBC), and / or palette mode. The mode selection unit 202 can include additional functional units to perform video prediction according to other prediction modes.

[0190] The mode selection unit 202 provides the prediction block to the residual generation unit 204. The residual generation unit 204 receives the original, uncoded version of the current block from the video data memory 230 and receives the prediction block from the mode selection unit 202. The residual generation unit 204 calculates the sample-by-sample difference between the current block and the prediction block. The generated sample-by-sample difference defines a residual block for the current block. In some examples, the residual generation unit 204 can also determine the difference between the sample values ​​in the residual block to generate the residual block using residual differential pulse code modulation (RDPCM). In some examples, the residual generation unit 204 can be formed using one or more subtractor circuits that perform binary subtraction.

[0191] In the example where the mode selection unit 202 partitions the CU into PUs, each PU may be associated with a luma prediction unit and a corresponding chroma prediction unit. The video encoder 200 and the video decoder 300 may support PUs of various sizes. As described above, the size of the CU may refer to the size of the luma codec block of the CU, and the size of the PU may refer to the size of the luma prediction unit of the PU. Assuming that the size of a specific CU is 2N×2N, the video encoder 200 may support PU sizes of 2N×2N or N×N for intra prediction, as well as 2N×2N, 2N×N, N×2N, N×N or similar sizes for inter prediction for intra prediction. The video encoder 200 and the video decoder 300 may also support asymmetric partitioning, with PU sizes of 2N×nU, 2N×nD, nL×2N and nR×2N for intra prediction.

[0192] In an example where the mode selection unit 202 does not further partition the CU into PUs, each CU may be associated with a luma codec block and a corresponding chroma codec block. As described above, the size of a CU may refer to the size of the luma codec block of the CU. The video encoder 200 and the video decoder 300 may support a CU size of 2N×2N, 2N×N, or N×2N.

[0193] For other video coding techniques (such as intra-block copy mode coding, affine mode coding, and linear model (LM) mode coding), as some examples, the mode selection unit 202 generates a prediction block for the current block being encoded via a corresponding unit associated with the coding technique. In some examples, such as palette mode coding, the mode selection unit 202 may not generate a prediction block, but instead generate syntax elements indicating how to reconstruct the block based on the selected palette. In this mode, the mode selection unit 202 can provide these syntax elements to the entropy coding unit 220 for encoding.

[0194] As described above, the residual generation unit 204 receives the video data of the current block and the corresponding prediction block. Then, the residual generation unit 204 generates a residual block of the current block. To generate the residual block, the residual generation unit 204 calculates the difference between the prediction block and the current block sample by sample.

[0195] The transform processing unit 206 performs one or more transforms on the residual block to generate a transform coefficient block (referred to herein as a "transform coefficient block"). The transform processing unit 206 may perform various transforms on the residual block to form a transform coefficient block. For example, the transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karhunen-Loeve transform (KLT), or a similar conceptual transform to the residual block. In some examples, the transform processing unit 206 may perform multiple transforms on the residual block, such as a primary transform and a secondary transform (such as a rotation transform). In some examples, the transform processing unit 206 does not apply a transform to the residual block.

[0196] When operating according to AV1, the transform processing unit 206 may apply one or more transforms to the residual block to generate a transform coefficient block (referred to herein as a "transform coefficient block"). The transform processing unit 206 may perform various transforms on the residual block to form a transform coefficient block. For example, the transform processing unit 206 may apply a horizontal / vertical transform combination, which may include a discrete cosine transform (DCT), an asymmetric discrete sine transform (ADST), a flipped ADST (e.g., an ADST in reverse order), and an identity transform (IDTX). When the same transform is used, the transform in one of the vertical or horizontal directions is skipped. In some examples, the transform process may be skipped.

[0197] The quantization unit 208 may quantize the transform coefficients in the transform coefficient block to generate a quantized transform coefficient block. The quantization unit 208 may quantize the transform coefficients in the transform coefficient block according to a quantization parameter (QP) value associated with the current block. The video encoder 200 (e.g., via the mode selection unit 202) may adjust the degree of quantization applied to the transform coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization may result in a loss of information, and therefore, the quantized transform coefficients may have a lower precision than the original transform coefficients generated by the transform processing unit 206.

[0198] The inverse quantization unit 210 and the inverse transform processing unit 212 may apply inverse quantization and inverse transform to the quantized transform coefficient block, respectively, to reconstruct a residual block from the transform coefficient block. The reconstruction unit 214 may generate a reconstructed block corresponding to the current block (although there may be a certain degree of distortion) based on the reconstructed residual block and the prediction block generated by the mode selection unit 202. For example, the reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples of the prediction block generated by the mode selection unit 202 to generate a reconstructed block.

[0199] Filter unit 216 may perform one or more filtering operations on the reconstructed blocks. For example, filter unit 216 may perform a deblocking operation to reduce blocking artifacts at the edges of the CU. In some examples, the operations of filter unit 216 may be skipped.

[0200] When operating according to AV1, filter unit 216 may perform one or more filtering operations on the reconstructed blocks. For example, filter unit 216 may perform a deblocking operation to reduce blocking artifacts along the edges of the CU. In other examples, filter unit 216 may apply a constrained directional enhancement filter (CDEF), which may be applied after deblocking and may include applying a non-separable, non-linear, low-pass directional filter based on an estimated edge direction. Filter unit 216 may also include a loop recovery filter, which is applied after CDEF and may include a separable symmetric normalized Wiener filter or a dual self-guided filter.

[0201] The video encoder 200 stores the reconstructed blocks in the DPB 218. For example, in an example where the filter unit 216 operation is not performed, the reconstruction unit 214 can store the reconstructed blocks in the DPB 218. In an example where the filter unit 216 operation is performed, the filter unit 216 can store the filtered reconstructed blocks in the DPB 218. The motion estimation unit 222 and the motion compensation unit 224 can retrieve a reference picture from the DPB 218, which is formed by the reconstructed (and possibly filtered) blocks, for inter-prediction of blocks of subsequent encoded pictures. In addition, the intra-prediction unit 226 can use the reconstructed blocks in the current picture DPB 218 to perform intra-prediction on other blocks in the current picture.

[0202] In general, the entropy coding unit 220 may entropy encode syntax elements received from other functional components of the video encoder 200. For example, the entropy coding unit 220 may entropy encode a block of quantized transform coefficients from the quantization unit 208. As another example, the entropy coding unit 220 may entropy encode prediction syntax elements (e.g., motion information for inter-prediction or intra-mode information for intra-prediction) from the mode selection unit 202. The entropy coding unit 220 may perform one or more entropy coding operations on the syntax elements (another example of video data) to generate entropy-encoded data. For example, the entropy coding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a probability interval partitioning entropy (PIPE) coding operation, an exponential-gollon coding operation, or other types of entropy coding operations on the data. In some examples, the entropy coding unit 220 may operate in a bypass mode, in which the syntax elements are not entropy-encoded.

[0203] The video encoder 200 may output a bitstream including entropy-encoded syntax elements required for the reconstructed blocks of a slice or picture. Specifically, the entropy encoding unit 220 may output a bitstream.

[0204] According to AV1, the entropy coding unit 220 can be configured as a symbol-to-symbol adaptive multi-symbol arithmetic encoder. The syntax elements in AV1 include an alphabet of N elements, and the context (e.g., a probability model) includes N probability sets. The entropy coding unit 220 can store the probabilities as an n-bit (e.g., 15-bit) cumulative distribution function (CDF). The entropy coding unit 220 can perform recursive scaling using an update factor based on the alphabet size to update the context.

[0205] The above operations are described for blocks. This description should be understood as operations for luma codec blocks and / or chroma codec blocks. As described above, in some examples, the luma codec block and the chroma codec block are the luma and chroma components of the CU. In some examples, the luma codec block and the chroma codec block are the luma and chroma components of the PU.

[0206] In some examples, operations related to luma codec blocks do not need to be repeated for chroma codec blocks. For example, when identifying a motion vector (MV) and a reference picture for a chroma block, the operations of identifying a motion vector (MV) and a reference picture do not need to be repeated. Instead, the motion vector for the luma codec block can be scaled to determine the motion vector for the chroma block, and the reference picture can be the same. Another example is that the intra prediction process for the luma codec block can be the same as that for the chroma codec block.

[0207] Video encoder 200 represents an example of a device configured to encode and decode video data, the device including a memory configured to store the video data, and one or more processing units implemented in a circuit, the processing unit configured to: receive a block of video data to be encoded using an affine DMVR mode; divide the block into a plurality of sub-blocks; determine a final offset of the affine DMVR mode using a first subset of the plurality of sub-blocks; and encode the block of video data using the final offset to generate an encoded block of video data.

[0208] Figure 8 is a block diagram illustrating an example video decoder 300 that may perform the disclosed techniques. Figure 8 The purpose is to explain, not to limit the techniques widely exemplified and described in this disclosure. For the purpose of explanation, this disclosure describes the video decoder 300 according to VVC and HEVC techniques. However, the disclosed techniques can be performed by video codec devices configured for other video codec standards.

[0209] exist Figure 8In the example of , the video decoder 300 includes a coded picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filter unit 312, and a DPB 314. Any or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the filter unit 312, and the DPB 314 can be implemented in one or more processors or processing circuits. For example, the units of the video decoder 300 can be implemented as part of a hardware circuit, or as part of a processor, ASIC, or FPGA, in the form of one or more circuits or logic elements. In addition, the video decoder 300 can also include additional or alternative processors or processing circuits to perform these functions and other functions.

[0210] The prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. The prediction processing unit 304 may include additional units to perform predictions according to other prediction modes. For example, the prediction processing unit 304 may include a palette unit, an intra-block copy unit (which may form part of the motion compensation unit 316), an affine unit, a linear model (LM) unit, or the like. In other examples, the video decoder 300 may include more, fewer, or different functional components.

[0211] When operating in accordance with AV1, the motion compensation unit 316 may be configured to decode codec blocks of video data (e.g., luma and chroma codec blocks) using translational motion compensation, affine motion compensation, OBMC, and / or composite intra prediction, as described above. As described above, the intra prediction unit 318 may be configured to decode codec blocks of video data (e.g., luma and chroma codec blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, CFL, IBC, and / or palette mode.

[0212] CPB memory 320 may store video data, such as an encoded video bitstream, for decoding by components of video decoder 300. The video data stored in CPB memory 320 may be, for example, obtained from computer-readable medium 110 ( Figure 1). The CPB memory 320 may include a memory for storing encoded video data (e.g., syntax elements) from an encoded video bitstream. In addition, the CPB memory 320 may also store video data other than syntax elements of encoded and decoded pictures (such as temporary data representing the output of various units of the video decoder 300). The DPB 314 typically stores decoded pictures, which the video decoder 300 may output and / or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. The CPB memory 320 and the DPB 314 may be composed of any of a variety of storage devices, such as DRAM (including SDRAM, MRAM, RRAM or other types of storage devices). The CPB memory 320 and the DPB 314 may be provided by the same memory device or a separate memory device. In various examples, the CPB memory 320 may be located on-chip with other components of the video decoder 300, or may be located off-chip relative to these components.

[0213] Additionally or alternatively, in some examples, video decoder 300 may retrieve data from memory 120 ( Figure 1 ) retrieves the encoded and decoded video data. That is, the memory 120 may store the data discussed in the CPB memory 320. Similarly, when part or all of the functions of the video decoder 300 are implemented in the form of software and executed by the processing circuit of the video decoder 300, the memory 120 may store instructions executed by the video decoder 300.

[0214] Figure 8 The various units shown help illustrate the operations performed by video decoder 300. These units can be implemented as fixed function circuits, programmable circuits, or a combination thereof. Figure 7 Similarly, a fixed-function circuit refers to a circuit that provides a specific function and has preset operations that can be performed. A programmable circuit refers to a circuit that can be programmed to perform various tasks and provides flexible functions in the operations that can be performed. For example, a programmable circuit can drive software or firmware so that the programmable circuit works in a manner specified by the software or firmware instructions. A fixed-function circuit can execute software instructions (for example, receive parameters or output parameters), but the type of operation performed by the fixed-function circuit is generally unchangeable. In some examples, one or more units may be different circuit blocks (fixed function or programmable), and in some examples, one or more units may be integrated circuits.

[0215] The video decoder 300 may include an ALU, an EFU, a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example where the operation of the video decoder 300 is performed by software executed on the programmable circuit, an on-chip or off-chip memory may store instructions (e.g., object code) of the software received and executed by the video decoder 300.

[0216] The entropy decoding unit 302 may receive the encoded video data from the CPB and entropy decode the video data to reproduce the syntax elements. The prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, and the filter unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0217] Generally speaking, the video decoder 300 may reconstruct a picture on a block-by-block basis. The video decoder 300 may perform a reconstruction operation on each block individually (where the block currently being reconstructed, ie, the decoded block, may be referred to as a "current block").

[0218] The entropy decoding unit 302 may entropy decode syntax elements defining quantized transform coefficients of the quantized transform coefficient block and transform information, such as a quantization parameter (QP) and / or (multiple) transform mode indications. The inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine a degree of quantization and, likewise, a degree of inverse quantization to be applied by the inverse quantization unit 306. For example, the inverse quantization unit 306 may perform a bitwise left shift operation to inverse quantize the quantized transform coefficients. The inverse quantization unit 306 may thereby form a transform coefficient block including the transform coefficients.

[0219] After the inverse quantization unit 306 forms the transform coefficient block, the inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, the inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse directional transform, or other inverse transforms to the transform coefficient block.

[0220] In addition, prediction processing unit 304 generates a prediction block based on the prediction information syntax element entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax element indicates that the current block is inter-predicted, motion compensation unit 316 can generate the prediction block. In this case, the prediction information syntax element can indicate a reference picture in DPB 314 from which to retrieve the reference block, and a motion vector that identifies the position of the reference block in the reference picture relative to the current block in the current picture. Motion compensation unit 316 can generally generate a prediction block in the same manner as motion compensation unit 224 ( Figure 7 ) performs inter-prediction processing in a substantially similar manner.

[0221] As another example, if the prediction information syntax element indicates that the current block is intra-predicted, the intra-prediction unit 318 may generate a prediction block according to the intra-prediction mode indicated by the prediction information syntax element. Similarly, the intra-prediction unit 318 may generally generate a prediction block in the same manner as the intra-prediction unit 226 ( Figure 7 ) performs intra prediction processing in a substantially similar manner. The intra prediction unit 318 may retrieve neighboring sample data of the current block from the DPB 314.

[0222] The reconstruction unit 310 may reconstruct the current block using the prediction block and the residual block. For example, the reconstruction unit 310 may add samples of the residual block to corresponding samples of the prediction block to reconstruct the current block.

[0223] The filter unit 312 may perform one or more filtering operations on the reconstructed block. For example, the filter unit 312 may perform a deblocking operation to reduce blocking artifacts at the reconstructed block edges. The operations of the filter unit 312 may not necessarily be performed in all examples.

[0224] The video decoder 300 may store the reconstructed blocks in the DPB 314. For example, in examples where the operation of the filtering unit 312 is not performed, the reconstruction unit 310 may store the reconstructed blocks in the DPB 314. In examples where the operation of the filtering unit 312 is performed, the filtering unit 312 may store the filtered reconstructed blocks in the DPB 314. As described above, the DPB 314 may provide reference information to the prediction processing unit 304, such as current picture samples for intra-prediction and previously decoded picture samples for subsequent motion compensation. In addition, the video decoder 300 may output a decoded picture (e.g., a decoded video) from the DPB 314 for subsequent display on a display device (such as a video device). Figure 1 The image is presented on a display device 118 in the image processing unit.

[0225] In this manner, video decoder 300 represents an example of a video decoding device that includes a memory configured to store video data, and one or more processing units implemented in circuitry and configured to: receive a block of video data to be decoded using an affine DMVR pattern; divide the block into a plurality of sub-blocks; determine a final offset for the affine DMVR pattern using a first subset of the plurality of sub-blocks; and decode the block of video data using the final offset to generate a decoded block of video data.

[0226] Fig. 9 1 is a flowchart showing an example method for encoding a current block according to the disclosed technology. The current block may be or include a current CU. Although for the video encoder 200 ( Figure 1 and Figure 7), but it should be understood that other devices may be configured to perform similar Fig. 9 method.

[0227] In this example, the video encoder 200 starts by predicting a current block (350). For example, the video encoder 200 may form a prediction block for the current block. The video encoder 200 may then calculate a residual block for the current block (352). To calculate the residual block, the video encoder 200 may calculate the difference between the unencoded original block and the prediction block for the current block. The video encoder 200 may then transform the residual block and quantize the transform coefficients of the residual block (354). Next, the video encoder 200 may scan the quantized transform coefficients of the residual block (356). During or after the scan, the video encoder 200 may entropy encode the transform coefficients (358). For example, the video encoder 200 may encode the transform coefficients using CAVLC or CABAC. The video encoder 200 may then output the entropy encoded data of the block (360).

[0228] Fig.10 is a flowchart showing an example method for decoding a current block of video data according to the disclosed technology. The current block may be or include a current CU. Although for the video decoder 300 ( Figure 1 and Figure 8 ), but it should be understood that other devices may be configured to perform the same Fig.10 Similar approach.

[0229] The video decoder 300 may receive entropy-encoded data of a current block, such as entropy-encoded prediction information and entropy-encoded data of transform coefficients of a residual block corresponding to the current block (370). The video decoder 300 may entropy decode the entropy-encoded data to determine prediction information of the current block and regenerate transform coefficients of the residual block (372). The video decoder 300 may predict the current block (374), for example, by calculating a prediction block of the current block using an intra or intra prediction mode based on the prediction information of the current block. The video decoder 300 may then reverse scan the regenerated transform coefficients (376) to create a quantized transform coefficient block. The video decoder 300 may then inverse quantize the transform coefficients and inverse transform the transform coefficients to generate a residual block (378). The video decoder 300 may ultimately decode the current block by combining the prediction block and the residual block (380).

[0230] Fig.11 is a flowchart illustrating another example method of encoding video data according to the disclosed techniques. Fig.11The techniques of may be performed by one or more components of video encoder 200 , including motion estimation unit 222 and motion compensation unit 224 .

[0231] In one example, the video encoder 200 may be configured to receive a block of video data to be encoded using an affine DMVR mode (1100), and divide the block into a plurality of sub-blocks (1102). The video encoder 200 may determine a final offset for the affine DMVR mode using a first subset of the plurality of sub-blocks (1104).

[0232] The video encoder 200 may subsample the plurality of subblocks to determine a first subset of the plurality of subblocks. In one example, the first subset of the plurality of subblocks is half of the plurality of subblocks. For example, the first subset of the plurality of subblocks includes every other row of the plurality of subblocks in the block or every other column of the subblocks in the block. In another example, the first subset of the plurality of subblocks is a checkerboard pattern in the block. In other examples, the first subset of the plurality of subblocks is a quarter of the subblocks in the block, such as every other column and every other row of subblocks in the block.

[0233] In one example, to determine the final offset of the affine DMVR pattern, the video encoder 200 is configured to determine the final offset of the affine DMVR pattern using only the first plurality of sub-blocks, and skip bilateral matching cost calculation on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks. For example, the video encoder 200 may determine a corresponding initial motion vector for a first prediction direction and a second prediction direction for each sub-block of the first subset of the plurality of sub-blocks. In some examples, the video encoder 200 may determine the corresponding initial motion vector from the affine candidate merge list. Then, the video encoder 200 may generate a plurality of candidate motion vectors for each of the first plurality of sub-blocks, wherein generating the plurality of candidate motion vectors includes adding each of the plurality of candidate offsets to the corresponding initial motion vector. The video encoder 200 may calculate a corresponding bilateral matching cost for each of the first plurality of sub-blocks for each of the plurality of candidate motion vectors, and accumulate the corresponding bilateral matching costs of all of the sub-blocks in the first plurality of sub-blocks for each of the plurality of candidate motion vectors to generate a corresponding accumulated bilateral matching cost. Video encoder 200 may then determine the final offset as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

[0234] The video encoder 200 may encode the block of video data using the final offsets to generate an encoded block of video data 1106. For example, to encode the block of video data using the final offsets, the video encoder 200 may determine a control point motion vector for the block of video data, add the final offsets to the control point motion vector to create a refined control point motion vector, and encode the block of video data using the refined control point motion vector.

[0235] Fig.12 is a flow chart illustrating another example method of decoding video data according to the disclosed techniques. Fig.12 The techniques may be performed by one or more components of video decoder 300 , including motion compensation unit 316 .

[0236] In one example, the video decoder 300 may be configured to receive a block of video data to be decoded using an affine DMVR mode (1200), and divide the block into a plurality of sub-blocks (1202). The video decoder 300 may determine a final offset for the affine DMVR mode using a first subset of the plurality of sub-blocks (1204).

[0237] The video decoder 300 may subsample the plurality of subblocks to determine a first subset of the plurality of subblocks. In one example, the first subset of the plurality of subblocks is half of the plurality of subblocks. For example, the first subset of the plurality of subblocks includes every other row of the plurality of subblocks in the block or every other column of the subblocks in the block. In another example, the first subset of the plurality of subblocks is in a checkerboard pattern in the block. In other examples, the first subset of the plurality of subblocks is a quarter of the subblocks in the block, such as every other column and every other row of the subblocks in the block.

[0238] In one example, to determine the final offset of the affine DMVR pattern, the video decoder 300 is configured to determine the final offset of the affine DMVR pattern using only the first plurality of sub-blocks, and skip bilateral matching cost calculation on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks. For example, the video decoder 300 may determine a corresponding initial motion vector for a first prediction direction and a second prediction direction for each sub-block of the first subset of the plurality of sub-blocks. In some examples, the video decoder 300 may determine the corresponding initial motion vector from the affine candidate merge list. Then, the video decoder 300 may generate a plurality of candidate motion vectors for each sub-block in the first plurality of sub-blocks, wherein generating the plurality of candidate motion vectors includes adding each candidate offset in the plurality of candidate offsets to the corresponding initial motion vector in the block. The video decoder 300 may calculate a corresponding bilateral matching cost for each sub-block in the first plurality of sub-blocks for each candidate motion vector in the plurality of candidate motion vectors, and accumulate the corresponding bilateral matching costs of all sub-blocks in the first plurality of sub-blocks for each candidate motion vector in the plurality of candidate motion vectors to generate a corresponding accumulated bilateral matching cost. Video decoder 300 may then determine the final offset as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

[0239] The video decoder 300 may decode the block of video data using the final offsets to generate a decoded block of video data 1206. For example, to decode the block of video data using the final offsets, the video decoder 300 may determine a control point motion vector for the block of video data, add the final offsets to the control point motion vector to create a refined control point motion vector, and decode the block of video data using the refined control point motion vector.

[0240] The following numbered clauses describe one or more aspects of the devices and techniques described herein.

[0241] Aspect 1A - A method of encoding video data, the method comprising: receiving a block of video data to be encoded using affine motion compensation; dividing the block into a plurality of sub-blocks; and performing affine motion compensation on a first subset of the plurality of sub-blocks, wherein performing affine motion compensation comprises skipping at least one of motion compensation and distortion calculation on a second subset of the plurality of sub-blocks.

[0242] Aspect 2A - The method according to aspect 1A, further comprising: sub-sampling the plurality of sub-blocks to determine a first subset of the plurality of sub-blocks.

[0243] Aspect 3A - The method of aspect 1A, wherein performing affine motion compensation comprises performing motion compensation and distortion calculation on only a first subset of the plurality of sub-blocks.

[0244] Aspect 4A—The method according to aspect 1A, wherein affine motion compensation includes decoder-side motion vector refinement, and wherein at least one processing of affine motion compensation on a subset of skipped sub-blocks includes: generation of initial motion vectors for the subset of skipped sub-blocks.

[0245] Aspect 5A - The method of aspect 1A, wherein the first subset of the plurality of sub-blocks is half of the sub-blocks of the block.

[0246] Aspect 6A—The method of aspect 5A, wherein the first subset of the plurality of sub-blocks includes sub-blocks in every other row of the block.

[0247] Aspect 7A—The method of aspect 5A, wherein the first subset of the plurality of sub-blocks comprises sub-blocks in every other column of the block.

[0248] Aspect 8A—The method according to aspect 5A, wherein a first subset of the plurality of sub-blocks is a checkerboard pattern in the block.

[0249] Aspect 9A—The method of aspect 1A, wherein the first subset of the plurality of sub-blocks is one quarter of the sub-blocks in the block.

[0250] Aspect 10A - The method according to aspect 5A, wherein the first subset of the plurality of sub-blocks includes sub-blocks in every other column and every other row of sub-blocks in the block.

[0251] Aspect 11A—The method according to any of aspects 1A-10A, wherein the encoding comprises decoding.

[0252] Aspect 12A—The method according to any of aspects 1A-10A, wherein the encoding comprises encoding.

[0253] Aspect 13A - An apparatus for encoding video data, the apparatus comprising one or more means for performing the method of any of aspects 1A-12A.

[0254] Aspect 14A—The apparatus of Aspect 13A, wherein the one or more components include one or more processors implemented in circuitry.

[0255] Aspect 15A - The apparatus according to any of Aspects 13A and 14A, further comprising a memory for storing the video data.

[0256] Aspect 16A - The apparatus according to any of Aspects 13A-15A, further comprising a display configured to display the decoded video data.

[0257] Aspect 17A—The device of any of Aspects 13A-16A, wherein the device comprises one or more of: a camera, a computer, a sports device, a broadcast receiving device, or a set-top box.

[0258] Aspect 18A—The apparatus according to any of Aspects 13A-17A, wherein the apparatus comprises a video decoder.

[0259] Aspect 19A—The apparatus according to any of Aspects 13A-18A, wherein the apparatus comprises a video encoder.

[0260] Aspect 20A - A computer-readable storage medium having stored thereon instructions which, when executed, cause one or more processors to perform the method of any of Aspects 1A-12A.

[0261] Aspect 21A - An apparatus for encoding video data, the apparatus comprising: means for receiving a block of video data to be encoded using affine motion compensation; means for dividing the block into a plurality of sub-blocks; and means for performing affine motion compensation on a first subset of the plurality of sub-blocks, wherein performing affine motion compensation comprises skipping at least one of motion compensation and distortion calculation on a second subset of the plurality of sub-blocks.

[0262] Aspect 1B - A method of decoding video data, the method comprising: receiving a block of video data to be decoded using an affine decoder-side motion vector refinement (DMVR) mode; dividing the block into a plurality of sub-blocks; determining a final offset of the affine DMVR mode using a first subset of the plurality of sub-blocks; and decoding the block of video data using the final offset to generate a decoded block of video data.

[0263] Aspect 2B - A method according to Aspect 1B, wherein determining the final offset of the affine DMVR pattern includes: determining the final offset of the affine DMVR pattern using only the first plurality of sub-blocks and skipping bilateral matching cost calculation on a second subset of the plurality of sub-blocks different from the first subset of the plurality of sub-blocks.

[0264] Aspect 3B - A method according to any one of Aspects 1B-2B, wherein determining the final offset includes: determining a corresponding initial motion vector in a first prediction direction and a second prediction direction for each sub-block of a first subset of multiple sub-blocks; generating multiple candidate motion vectors for each sub-block in the first multiple sub-blocks, wherein generating the multiple candidate motion vectors includes adding each candidate offset in the multiple candidate offsets to the corresponding initial motion vector; calculating a corresponding bilateral matching cost for each sub-block in the first multiple sub-blocks for each candidate motion vector in the multiple candidate motion vectors; accumulating the corresponding bilateral matching costs of all sub-blocks in the first multiple sub-blocks for each candidate motion vector in the multiple candidate motion vectors to generate a corresponding cumulative bilateral matching cost; and determining the final offset as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

[0265] Aspect 4B - The method according to aspect 3B, wherein determining the corresponding initial motion vector comprises: determining the corresponding initial motion vector from an affine candidate merge list.

[0266] Aspect 5B - A method according to any of Aspects 1B-4B, wherein decoding the video data block using the final offset includes: determining a control point motion vector for the video data block; adding the final offset to the control point motion vector to create a refined control point motion vector; and decoding the video data block using the refined control point motion vector.

[0267] Aspect 6B - The method according to any of aspects 1B-5B, further comprising: sub-sampling the plurality of sub-blocks to determine a first subset of the plurality of sub-blocks.

[0268] Aspect 7B - The method according to Aspect 6B, wherein the first subset of the plurality of sub-blocks is half of the plurality of sub-blocks.

[0269] Aspect 8B - The method according to Aspect 7B, wherein the first subset of the plurality of sub-blocks includes every other row of the plurality of sub-blocks in the block or every other column of the sub-blocks in the block.

[0270] Aspect 9B—The method according to Aspect 7B, wherein a first subset of the plurality of sub-blocks is a checkerboard pattern in the block.

[0271] Aspect 10B - The method according to aspect 6B, wherein the first subset of the plurality of sub-blocks is one quarter of the sub-blocks of the block.

[0272] Aspect 11B - The method according to aspect 10B, wherein the first subset of the plurality of sub-blocks includes sub-blocks in every other column and every other row of sub-blocks in the block.

[0273] Aspect 12B - The method according to any of aspects 1B-11B, further comprising: displaying a picture including the decoded block of video data.

[0274] Aspect 13B - A device configured to process video data, the device comprising: a memory configured to store a block of video data; and processing circuitry in communication with the memory, the processing circuitry configured to: receive a block of video data to be decoded using an affine decoder-side motion vector refinement (DMVR) mode; divide the block into a plurality of sub-blocks; determine a final offset of the affine DMVR mode using a first subset of the plurality of sub-blocks; and decode the block of video data using the final offset to generate a decoded block of video data.

[0275] Aspect 14B - A device according to Aspect 13B, wherein, in order to determine the final offset of the affine DMVR pattern, the processing circuit is further configured to: determine the final offset of the affine DMVR pattern using only a first plurality of sub-blocks, and skip bilateral matching cost calculation on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks.

[0276] Aspect 15B - An apparatus according to any of Aspects 13B-14B, wherein, in order to determine the final offset, the processing circuit is further configured to: determine a corresponding initial motion vector for a first prediction direction and a second prediction direction for each sub-block of a first subset of multiple sub-blocks; generate multiple candidate motion vectors for each sub-block in the first multiple sub-blocks, wherein generating the multiple candidate motion vectors includes adding each candidate offset in the multiple candidate offsets to the corresponding initial motion vector; calculate a corresponding bilateral matching cost for each sub-block in the first multiple sub-blocks for each candidate motion vector in the multiple candidate motion vectors; accumulate the corresponding bilateral matching costs of all sub-blocks in the first multiple sub-blocks for each candidate motion vector in the multiple candidate motion vectors to generate a corresponding cumulative bilateral matching cost; and determine the final offset as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

[0277] Aspect 16B—The apparatus according to Aspect 15B, wherein, to determine the corresponding initial motion vector, the processing circuit is further configured to: determine the corresponding initial motion vector from an affine candidate merge list.

[0278] Aspect 17B - An apparatus according to any of Aspects 13B-16B, wherein, in order to decode a block of video data using the final offset, the processing circuit is further configured to: determine a control point motion vector for the block of video data; add the final offset to the control point motion vector to create a refined control point motion vector; and decode the block of video data using the refined control point motion vector.

[0279] Aspect 18B—The apparatus of any of Aspects 13B-17B, wherein the processing circuit is further configured to: subsample the plurality of sub-blocks to determine a first subset of the plurality of sub-blocks.

[0280] Aspect 19B—The apparatus of Aspect 18B, wherein the first subset of the plurality of sub-blocks is half of the plurality of sub-blocks.

[0281] Aspect 20B - The apparatus according to Aspect 19B, wherein the first subset of the plurality of sub-blocks includes every other row of the plurality of sub-blocks in the block or every other column of the sub-blocks in the block.

[0282] Aspect 21B - The apparatus of Aspect 19B, wherein the first subset of the plurality of sub-blocks is a checkerboard pattern in the block.

[0283] Aspect 22B - The apparatus of Aspect 18B, wherein the first subset of the plurality of sub-blocks is one quarter of the sub-blocks of the block.

[0284] Aspect 23B - The apparatus of Aspect 22B, wherein the first subset of the plurality of sub-blocks comprises sub-blocks in every other column and every other row of sub-blocks in the block.

[0285] Aspect 24B - The apparatus according to any of Aspects 13B-23B, further comprising: a display configured to display a picture including the decoded video data.

[0286] Aspect 25B - An apparatus configured to decode video data, the apparatus comprising: means for receiving a block of video data to be decoded using an affine decoder-side motion vector refinement (DMVR) mode; means for dividing the block into a plurality of sub-blocks; means for determining a final offset for the affine DMVR mode using a first subset of the plurality of sub-blocks; and means for decoding the block of video data using the final offset to generate a decoded block of video data.

[0287] Aspect 26B - A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors of a device configured to decode video data to: receive a block of video data to be decoded using an affine decoder-side motion vector refinement (DMVR) mode; divide the block into a plurality of sub-blocks; determine a final offset for the affine DMVR mode using a first subset of the plurality of sub-blocks; and decode the block of video data using the final offset to generate a decoded block of video data.

[0288] Aspect 27B - A method of encoding video data, the method comprising: receiving a block of video data to be encoded using an affine decoder-side motion vector refinement (DMVR) mode; dividing the block into a plurality of sub-blocks; determining a final offset for the affine DMVR mode using a first subset of the plurality of sub-blocks; and encoding the block of video data using the final offset to generate an encoded block of video data.

[0289] Aspect 28B - An apparatus configured to encode video data, the apparatus comprising: a memory configured to store a block of video data; and processing circuitry in communication with the memory, the processing circuitry configured to: receive a block of video data to be encoded using an affine decoder-side motion vector refinement (DMVR) mode; divide the block into a plurality of sub-blocks; determine a final offset for the affine DMVR mode using a first subset of the plurality of sub-blocks; and encode the block of video data using the final offset to generate an encoded block of video data.

[0290] Aspect 29B - An apparatus according to Aspect 28B, wherein, in order to determine the final offset of the affine DMVR pattern, the processing circuit is further configured to: determine the final offset of the affine DMVR pattern using only a first plurality of sub-blocks, and skip bilateral matching cost calculation on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks.

[0291] Aspect 30B - An apparatus according to any of Aspects 28B-29B, wherein, in order to determine the final offset, the processing circuit is further configured to: determine a corresponding initial motion vector for a first prediction direction and a second prediction direction for each sub-block of a first subset of multiple sub-blocks; generate multiple candidate motion vectors for each sub-block in the first multiple sub-blocks, wherein generating the multiple candidate motion vectors includes adding each candidate offset in the multiple candidate offsets to the corresponding initial motion vector; calculate a corresponding bilateral matching cost for each sub-block in the first multiple sub-blocks for each candidate motion vector in the multiple candidate motion vectors; accumulate the corresponding bilateral matching costs of all sub-blocks in the first multiple sub-blocks for each candidate motion vector in the multiple candidate motion vectors to generate a corresponding cumulative bilateral matching cost; and determine the final offset as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

[0292] Aspect 31B - The apparatus according to aspect 30B, wherein, to determine the corresponding initial motion vector, the processing circuit is further configured to: determine the corresponding initial motion vector from the affine candidate merge list.

[0293] Aspect 32B - An apparatus according to any of Aspects 28B-31B, wherein, to encode a block of video data using the final offset, the processing circuit is further configured to: determine a control point motion vector for the block of video data; add the final offset to the control point motion vector to create a refined control point motion vector; and encode the block of video data using the refined control point motion vector.

[0294] Aspect 33B—The apparatus of any of Aspects 28B-32B, wherein the processing circuit is further configured to: subsample the plurality of sub-blocks to determine a first subset of the plurality of sub-blocks.

[0295] Aspect 34B—The apparatus of Aspect 33B, wherein the first subset of the plurality of sub-blocks is half of the plurality of sub-blocks.

[0296] Aspect 35B - The apparatus of Aspect 34B, wherein the first subset of the plurality of sub-blocks comprises every other row of the plurality of sub-blocks in the block or every other column of the sub-blocks in the block.

[0297] Aspect 36B—The apparatus of Aspect 34B, wherein the first subset of the plurality of sub-blocks is a checkerboard pattern in the block.

[0298] Aspect 37B - The apparatus of Aspect 33B, wherein the first subset of the plurality of sub-blocks is one quarter of the sub-blocks in the block.

[0299] Aspect 38B—The apparatus of Aspect 37B, wherein the first subset of the plurality of sub-blocks comprises sub-blocks in every other column and every other row of sub-blocks in the block.

[0300] Aspect 39B—The apparatus according to any of Aspects 28B-38B, further comprising: being configured to capture a picture comprising a block of video data.

[0301] It should be appreciated that, depending on the example, certain actions or events of any technique described herein may be performed in a different order, may be added, combined, or omitted entirely (e.g., not all of the actions or events described are necessary for the practice of the technique). In addition, in some examples, actions or events may be performed concurrently, such as through multithreading, interrupt handling, or multiple processors, rather than sequentially.

[0302] In one or more examples, the functions may be implemented by hardware, software, firmware, or any combination thereof. If implemented by software, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media (corresponding to tangible media such as data storage media) or communication media (including any media that facilitates the transmission of a computer program from one place to another, for example, according to a communication protocol). Thus, computer-readable media may generally correspond to (1) non-temporary tangible computer-readable storage media or (2) communication media, such as signals or carrier waves. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in the present disclosure. A computer program product may include a computer-readable medium.

[0303] As an example and not limitation, such computer-readable storage media may include one or more of RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, flash memory or any other medium that can be used to store the required program code in the form of instructions or data structures and can be accessed by a computer. In addition, any connection can be referred to as a computer-readable medium. For example, if instructions are sent from a website, server or other remote source using coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave, then coaxial cable, optical cable, twisted pair, digital subscriber line or wireless technologies such as infrared, radio and microwave are included in the definition of medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carriers, signals or other transient media, but refer to non-transient tangible storage media. Disks and optical disks used in this article include compact disks (CDs), laser optical disks, optical disks, digital versatile disks (DVDs), floppy disks and blue-ray disks, where disks usually copy data magnetically, while optical disks copy data optically by lasers. Combinations of the above media should also be included in the scope of computer-readable media.

[0304] Instructions may be executed by one or more processors, such as one or more DSPs, general-purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuits. Therefore, the terms "processor" and "processing circuit" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functions described herein may be provided in dedicated hardware and / or software modules that are configured for encoding and decoding, or integrated in a combined codec. In addition, these techniques may also be fully implemented in one or more circuits or logic elements.

[0305] The disclosed techniques may be implemented in a variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs), or sets of integrated circuits (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require implementation by different hardware units. Instead, as described above, the various units may be combined in a codec hardware unit, or provided by a collection of interoperable hardware units, including one or more processors as described above, in combination with appropriate software and / or firmware.

[0306] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A method for decoding video data, the method comprising: receiving a block of video data to be decoded using an affine decoder side motion vector refinement (DMVR) mode; dividing the block into a plurality of sub-blocks; determining a final offset for the affine DMVR pattern using a first subset of the plurality of sub-blocks; as well as The block of video data is decoded using the final offset to generate a decoded block of video data.

2. The method according to claim 1, wherein: Determining the final offset for the affine DMVR pattern includes: Using only the first plurality of sub-blocks, a final offset for the affine DMVR pattern is determined, and bilateral matching cost computation on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks is skipped.

3. The method according to claim 1, wherein: Determining the final offset includes: Determining a corresponding initial motion vector for a first prediction direction and a second prediction direction of each sub-block of a first subset of the plurality of sub-blocks; generating a plurality of candidate motion vectors for each of the first plurality of sub-blocks, wherein generating the plurality of candidate motion vectors comprises adding each respective candidate offset of a plurality of candidate offsets to the respective initial motion vector; calculating, for each candidate motion vector in the plurality of candidate motion vectors, a corresponding bilateral matching cost for each sub-block in the first plurality of sub-blocks; accumulating, for each candidate motion vector in the plurality of candidate motion vectors, respective bilateral matching costs of all sub-blocks in the first plurality of sub-blocks to generate respective accumulated bilateral matching costs; and The final offset is determined as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

4. The method according to claim 3, wherein: Determining the corresponding initial motion vector includes: The corresponding initial motion vector is determined from the affine candidate merge list.

5. The method according to claim 1, wherein: Decoding the video data block using the final offset comprises: Determining a control point motion vector of the video data block; adding the final offset to the control point motion vector to create a refined control point motion vector; and The video data block is decoded using the refined control point motion vectors.

6. The method according to claim 1, further comprising: The plurality of sub-blocks are sub-sampled to determine a first subset of the plurality of sub-blocks.

7. The method according to claim 6, wherein: The first subset of the plurality of sub-blocks is half of the plurality of sub-blocks.

8. The method according to claim 7, wherein: The first subset of the plurality of sub-blocks includes every other row of the plurality of sub-blocks in the block or every other column of the sub-blocks in the block.

9. The method according to claim 7, wherein: A first subset of the plurality of sub-blocks is a checkerboard pattern in the block.

10. The method according to claim 6, wherein: The first subset of the plurality of sub-blocks is one quarter of the sub-blocks in the block.

11. The method according to claim 10, wherein: The first subset of the plurality of sub-blocks includes sub-blocks in every other column and every other row of sub-blocks in the block.

12. The method according to claim 1, further comprising: A picture including the decoded block of video data is displayed.

13. A device for decoding video data, the device comprising: a memory configured to store video data blocks; as well as a processing circuit in communication with the memory, the processing circuit being configured to: receiving a block of video data to be decoded using an affine decoder side motion vector refinement (DMVR) mode; dividing the block into a plurality of sub-blocks; determining a final offset for the affine DMVR pattern using a first subset of the plurality of sub-blocks; as well as The block of video data is decoded using the final offset to generate a decoded block of video data.

14. The device according to claim 13, wherein: To determine the final offset for the affine DMVR pattern, the processing circuit is further configured to: Using only the first plurality of sub-blocks, a final offset for the affine DMVR pattern is determined, and bilateral matching cost computation on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks is skipped.

15. The device according to claim 13, wherein: To determine the final offset, the processing circuit is further configured to: Determining a corresponding initial motion vector for a first prediction direction and a second prediction direction of each sub-block of the first subset of the plurality of sub-blocks; generating a plurality of candidate motion vectors for each of the first plurality of sub-blocks, wherein generating the plurality of candidate motion vectors comprises adding each of a plurality of candidate offsets to the corresponding initial motion vector; calculating a corresponding bilateral matching cost for each of the first plurality of sub-blocks for each of the plurality of candidate motion vectors; accumulating, for each candidate motion vector in the plurality of candidate motion vectors, respective bilateral matching costs of all sub-blocks in the first plurality of sub-blocks to generate respective accumulated bilateral matching costs; and The final offset is determined as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

16. The device according to claim 15, wherein: In order to determine the corresponding initial motion vector, the processing circuit is further configured to: The corresponding initial motion vector is determined from the affine candidate merge list.

17. The device according to claim 13, wherein: In order to decode the video data block using the final offset, the processing circuit is further configured to: Determining a control point motion vector of the video data block; adding the final offset to the control point motion vector to create a refined control point motion vector; as well as The block of video data is decoded using the refined control point motion vectors.

18. The device according to claim 13, wherein: The processing circuit is further configured to: The plurality of sub-blocks are sub-sampled to determine a first subset of the plurality of sub-blocks.

19. The device according to claim 18, wherein: The first subset of the plurality of sub-blocks is half of the plurality of sub-blocks.

20. The device according to claim 19, wherein The first subset of the plurality of sub-blocks includes every other row of the plurality of sub-blocks in the block or every other column of the sub-blocks in the block.

21. The device according to claim 19, wherein A first subset of the plurality of sub-blocks is a checkerboard pattern in the block.

22. The device according to claim 18, wherein The first subset of the plurality of sub-blocks is one quarter of the sub-blocks in the block.

23. The device according to claim 22, wherein: The first subset of the plurality of sub-blocks includes sub-blocks in every other column and every other row of sub-blocks in the block.

24. The apparatus of claim 13, further comprising: A display is configured to display a picture including the decoded video data.

25. An apparatus configured to decode video data, the apparatus comprising: means for receiving a block of video data to be decoded using an affine decoder side motion vector refinement (DMVR) mode; means for dividing the block into a plurality of sub-blocks; means for determining a final offset for said affine DMVR pattern using a first subset of said plurality of sub-blocks; as well as Means for decoding the block of video data using the final offset to generate a decoded block of video data.

26. A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors of a device configured to decode video data: receiving a block of video data to be decoded using an affine decoder side motion vector refinement (DMVR) mode; dividing the block into a plurality of sub-blocks; determining a final offset for the affine DMVR pattern using a first subset of the plurality of sub-blocks; as well as The block of video data is decoded using the final offset to generate a decoded block of video data.

27. A method for encoding video data, the method comprising: receiving a block of video data to be encoded using an affine decoder-side motion vector refinement (DMVR) mode; dividing the block into a plurality of sub-blocks; determining a final offset for the affine DMVR pattern using a first subset of the plurality of sub-blocks; as well as The block of video data is encoded using the final offset to generate an encoded block of video data.

28. An apparatus configured to encode video data, the apparatus comprising: a memory configured to store video data blocks; as well as a processing circuit in communication with the memory, the processing circuit being configured to: receiving a block of video data to be encoded using an affine decoder-side motion vector refinement (DMVR) mode; dividing the block into a plurality of sub-blocks; determining a final offset for the affine DMVR pattern using a first subset of the plurality of sub-blocks; as well as The block of video data is encoded using the final offset to generate an encoded block of video data.

29. The device according to claim 28, wherein To determine a final offset for the affine DMVR pattern, the processing circuit is further configured to: The final offset of the affine DMVR pattern is determined using only a first plurality of sub-blocks, and bilateral matching cost computation is skipped on a second subset of the plurality of sub-blocks that is different from the first subset of the plurality of sub-blocks.

30. The device according to claim 28, wherein To determine the final offset, the processing circuit is further configured to: Determining a corresponding initial motion vector for a first prediction direction and a second prediction direction of each sub-block of the first subset of the plurality of sub-blocks; generating a plurality of candidate motion vectors for each of the first plurality of sub-blocks, wherein generating the plurality of candidate motion vectors comprises adding each of a plurality of candidate offsets to the corresponding initial motion vector; calculating a corresponding bilateral matching cost for each of the first plurality of sub-blocks for each of the plurality of candidate motion vectors; accumulating, for each candidate motion vector in the plurality of candidate motion vectors, respective bilateral matching costs of all sub-blocks in the first plurality of sub-blocks to generate respective accumulated bilateral matching costs; and The final offset is determined as the corresponding candidate offset associated with the lowest corresponding cumulative bilateral matching cost.

31. The device according to claim 30, wherein In order to determine the corresponding initial motion vector, the processing circuit is further configured to: The corresponding initial motion vector is determined from the affine candidate merge list.

32. The apparatus of claim 28, wherein: In order to encode the video data block using the final offset, the processing circuit is further configured to: Determining a control point motion vector of the video data block; adding the final offset to the control point motion vector to create a refined control point motion vector; as well as The block of video data is encoded using the refined control point motion vectors.

33. The apparatus of claim 28, wherein: The processing circuit is further configured to: The plurality of sub-blocks are sub-sampled to determine a first subset of the plurality of sub-blocks.

34. The device according to claim 33, wherein: The first subset of the plurality of sub-blocks is half of the plurality of sub-blocks.

35. The device according to claim 34, wherein The first subset of the plurality of sub-blocks includes every other row of the plurality of sub-blocks in the block or every other column of the sub-blocks in the block.

36. The device according to claim 34, wherein A first subset of the plurality of sub-blocks is a checkerboard pattern in the block.

37. The device according to claim 33, wherein: The first subset of the plurality of sub-blocks is one quarter of the sub-blocks in the block.

38. The device according to claim 37, wherein The first subset of the plurality of sub-blocks includes sub-blocks in every other column and every other row of sub-blocks in the block.

39. The apparatus of claim 28, further comprising: A camera is configured to capture a picture including a block of video data.

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