Straight-beam double-island structure high-pressure pressure sensor chip with stress holes and preparation method thereof

Abstract

The invention discloses a linear beam double-island structure high-pressure pressure sensor chip with stress holes and a preparation method. The linear beam double-island structure high-pressure pressure sensor chip comprises a supporting layer, an insulating layer and a device layer which are arranged from bottom to top, a cavity is etched on the back of the supporting layer, a sensitive film is arranged right above the cavity, and a linear beam double-island structure is arranged on the sensitive film; the edge and the center of the straight beam double-island structure are respectively provided with four piezoresistor strips, the four piezoresistor strips are connected into a semi-open-loop Wheatstone bridge through five P-type heavily-doped silicon leads, five metal point electrodes are arranged at the center of the five P-type heavily-doped silicon lead areas, sealing rings are arranged on the outer sides of the peripheries of the five metal point electrodes, and the metal point electrodes are connected with the metal point electrodes through the P-type heavily-doped silicon leads. The adjacent P-type heavily-doped silicon leads and the sealing rings are separated by fine slits; according to the invention, the pressure bearing limit is effectively improved, the high range is ensured, excellent sensitivity and linearity performance are realized, the high pressure measuring capability of dozens of to hundreds of MPa is realized, the tolerable temperature is up to 400 DEG C, and the sensor is widely applied to the fields of petroleum, natural gas, chemical engineering, high-pressure equipment monitoring and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon-based piezoresistive high-pressure pressure sensors, and in particular to a high-pressure pressure sensor chip with a straight beam and double island structure and a preparation method thereof. Background Art

[0002] Silicon-based piezoresistive pressure sensors use the piezoresistive effect of silicon materials to directly convert the mechanical strain caused by pressure into electrical signal output. When pressure acts on the sensor diaphragm, the deformation of the diaphragm causes the resistance of the piezoresistive element to change, and then the resistance change is converted into a voltage signal through a Wheatstone bridge. This sensor has low cost and a wide range of applications. With the superior performance of silicon materials and mature manufacturing processes, it exhibits high sensitivity, high precision, and fast response. It has been widely used in the fields of automobiles, aerospace, medical equipment, and industrial automation.

[0003] High-pressure pressure sensors are designed for extreme pressure conditions. The patent application entitled "An oil-filled core of a MEMS pressure sensor suitable for high-pressure small molecule media" (publication number: CN116989933A) adopts an oil-filled packaged pressure sensor. Through the synergistic effect of a corrugated metal diaphragm and silicone oil, the input high pressure is effectively reduced to the tolerance range of the sensor chip; however, in a high temperature environment exceeding 200°C, the volume of silicone oil will increase due to thermal expansion, which may cause liquid leakage and lead to sensor failure. In addition, the filling process of silicone oil has high requirements on technical precision and the packaging process is complicated, which increases the manufacturing difficulty and cost. The patent application entitled "A pressure sensor chip and a high-pressure resistant pressure sensor and a manufacturing method thereof" (publication number: CN113551815A) bonds the pressure sensor chip to the surface of the partition through silicone gel. The bottom of the partition is connected to the external environment. When pressure is applied, the glass substrate and the silicon-based pressure strain gauge on the surface of the partition are subjected to force, causing the resistance of the varistor on the chip to change, thereby outputting a corresponding signal. The packaging structure effectively prevents the connecting wire from contacting the external environment, significantly improving the sensor's anti-interference ability and temperature resistance. However, since the back of the sensor chip is under pressure, during long-term use, the additional stress on the connecting wire and the pad caused by the upward protrusion of the chip will increase the risk of the connecting wire falling off, which may cause the sensor to fail. Reference "Zhang GD, Zhao YL, Zhao Y, et al. Research of a Novel Ultra-High Pressure Sensor with High-Temperature Resistance[J]. Micromachines, 2018, 9(1): 5." Compared with the front or back pressure-bearing method of traditional sensors, the sensor range is successfully increased to the GPa level by attaching the sensor chip to the side of the cylinder and adopting a chip lateral pressure-bearing design; however, since the pressure is applied to the cylinder, its deformation behavior will be affected by the mass distribution and shape factors, resulting in deformation non-uniformity. The resulting output signal is small and accompanied by significant nonlinear characteristics, which limits the wide application of this design in engineering practice.

[0004] In summary, existing high-pressure pressure sensors have the disadvantages of liquid leakage in high-temperature environments, complex packaging processes, lead shedding after long-term use, low sensitivity and poor linearity. Summary of the invention

[0005] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a high-pressure pressure sensor chip with a straight beam and double island structure with stress holes and a preparation method. By introducing a rectangular thick film structure in the sensor chip, its pressure bearing limit is effectively improved, and the straight beam and double island structure with stress holes are etched on the chip surface, the stress distribution and partial structural stiffness of the stress concentration area are greatly enhanced, thereby ensuring high range while achieving excellent sensitivity and linearity performance; in addition, in order to meet the reliability requirements in high temperature environments, the chip is connected to the external circuit through silicon via (TSV) technology and electron beam evaporation conductive metal filling hole process design, avoiding the problem of lead falling off during long-term use, and solving the risk of silicone oil leakage of oil-filled packaged sensors under conditions exceeding 200°C; the sensor has a high-pressure measurement capability of tens to hundreds of MPa, and can withstand temperatures up to 400°C, and is widely used in fields such as petroleum, natural gas, chemical industry and high-voltage equipment monitoring.

[0006] In order to achieve the above object, the present invention is implemented by the following technical solutions:

[0007] A high-pressure pressure sensor chip with a straight beam double island structure and a stress hole comprises a support layer 1, an insulating layer 2 and a device layer 3 arranged from bottom to top; a cavity 1-1 is etched on the back of the support layer 1, a sensitive film 1-2 is directly above the cavity 1-1, and a straight beam double island structure 4 is arranged on the sensitive film 1-2; four piezoresistors 5-1, 5-2, 5-3, 5-4 are arranged at the edge and center of the straight beam double island structure 4, respectively. 4 is connected to form a semi-open-loop Wheatstone bridge through five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, 6-5, five metal point electrodes 7-1, 7-2, 7-3, 7-4, 7-5 are arranged at the center of the five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, 6-5, and a sealing ring 8 is arranged on the outer side thereof, and adjacent P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, 6-5 are separated from the sealing ring 8 by a fine gap 9.

[0008] The sensitive film 1-2 is a rectangular thick film, and the film thickness is 0.5-0.7 times the thickness of the chip; the upper surface of the cavity 1-1 is the same size as the plane shape of the sensitive film 1-2; the arrangement of the four varistor strips 5-1, 5-2, 5-3, and 5-4 adopts a "center-edge" design, and the effective length directions of the four varistor strips 5-1, 5-2, 5-3, and 5-4 are all along the crystal direction with the largest piezoresistance coefficient of the (100) crystal plane.

[0009] The one-beam double-island structure 4 includes two square islands 4-1 and 4-2, and the two square islands 4-1 and 4-2 are respectively connected to a beam 4-3. A stress hole 4-4 is arranged at the center of the beam 4-3, and the depth of the stress hole 4-4 is consistent with the height of the two square islands 4-1 and 4-2 and the beam 4-3; the distance and side length between the two square islands 4-1 and 4-2, the width of the beam 4-3 and the length and width of the stress hole 4-4 are all determined through simulation optimization.

[0010] The thickness of the beam 4 - 3 is 10-40 μm, and the thickness of the beam is adjusted according to different sensitivity ranges.

[0011] The transverse and longitudinal stress differences of the two varistor strips 5-1 and 5-4 at the upper edge and the two varistor strips 5-2 and 5-3 at the center of the one-beam double-island structure 4 are in opposite directions, and the corresponding Wheatstone bridge resistance changes are opposite.

[0012] The varistor strips 5-1, 5-2, 5-3, and 5-4 are heavily doped with P type, and the doping concentration is the same as that of the P type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5. The upper surfaces of the varistor strips 5-1, 5-2, 5-3, and 5-4 are flush with the upper surfaces of the P type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5.

[0013] The depth of the fine slit 9 is 1.5 μm, which is equal to the depth of the device layer 3 .

[0014] The front side of the device layer 3 is vacuum bonded to the silicon wafer 10 , so that the sensitive circuit is protected in a vacuum cavity formed by the device layer 3 and the silicon wafer 10 .

[0015] The silicon wafer 10 is provided with five silicon through holes 11-1, 11-2, 11-3, 11-4, and 11-5, which correspond to the shapes of the five metal point electrodes 7-1, 7-2, 7-3, 7-4, and 7-5 respectively; the five silicon through holes 11-1, 11-2, 11-3, 11-4, and 11-5 are filled with conductive metal 12; a groove 13 is provided in the center of the silicon wafer 10, and the shape of the groove 13 is rectangular. The width of the groove 13 corresponds to the sensitive film 1-2, and the length of the groove 13 corresponds to the farthest distance between the two varistor strips 5-1 and 5-4 at the edge. The depth of the groove 13 ensures that when there is high voltage input, the bottom surface of the groove 13 will not contact the one-beam double island structure 4.

[0016] The method for preparing a high-pressure pressure sensor chip with a straight beam and double island structure and stress holes comprises the following steps:

[0017] 1) The chip adopts SOI silicon wafer, which consists of device layer 3, insulating layer 2 and support layer 1 from top to bottom. The device layer 3 and support layer 1 are N-type single crystal silicon, the upper surface of the device layer 3 is (100) crystal plane, and the insulating layer 2 is SiO2 layer;

[0018] 2) The chip is thermally oxidized, and the surface of the device layer 3 is heavily doped with boron ions and annealed to make the implanted ions evenly distributed in the device layer 3 to achieve electrical activation;

[0019] 3) Using ICP technology to etch away the silicon of the device layer 3, four varistor strips 5-1, 5-2, 5-3, 5-4 are formed; five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, 6-5; and a sealing ring 8;

[0020] 4) Using PECVD technology to deposit silicon dioxide and silicon nitride 2-1 on the entire chip surface;

[0021] 5) Using ICP technology to etch away the silicon dioxide and silicon nitride 2-1 on the back of the support layer 1, the etching area is based on the positive surface area of ​​the cavity 1-1, and then wet etching is used to etch to the bottom of the sensitive film 1-2 (0.5-0.7 times the thickness of the chip);

[0022] 6) Using ICP technology to etch away silicon dioxide and silicon nitride 2-1 on the surface of the chip to expose the point electrode area, and then forming five metal point electrodes 7-1, 7-2, 7-3, 7-4, and 7-5 through metal sputtering and lift-off processes;

[0023] 7) Etching the device layer 3, the insulating layer 2 and the support layer 1 by using ICP technology, with an etching depth of 10-40 μm, so as to form a complete three-dimensional structure of a one-beam double-island structure 4 with stress holes;

[0024] 8) vacuum bonding the surface of the device layer 3 to the silicon wafer 10, with the five through silicon vias 11-1, 11-2, 11-3, 11-4, and 11-5 aligned with the positions of the five metal point electrodes 7-1, 7-2, 7-3, 7-4, and 7-5 on the device layer 3 during bonding;

[0025] 9) The five through silicon vias 11 - 1 , 11 - 2 , 11 - 3 , 11 - 4 , and 11 - 5 are filled with conductive metal 12 using electron beam evaporation technology.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The sensitive membrane of the present invention adopts a rectangular shape. Compared with square and circular diaphragms, the rectangular diaphragm can maintain a higher natural frequency and overload capacity. The advantage of this design is that it improves the output stability of the sensor under high-frequency dynamic response conditions, ensuring that the sensor can respond quickly and accurately in a rapidly changing high-pressure environment, thereby meeting the needs of modern industry for high-performance sensors.

[0028] The present invention uses a stress concentration structure consisting of a straight beam double-island structure with stress holes on the front, a sensitive membrane and a back cavity as the chip structure of a piezoresistive pressure sensor. Compared with the traditional beam structure, the design of the straight beam double-island structure allows the lateral and longitudinal stress differences in the stress concentration area to be significantly enhanced by accurately adjusting the distance between islands and the side length of the islands. At the same time, in order to make the stress concentration effect more significant, it is proposed to etch stress holes in the central area of ​​the straight beam double-island structure to further improve the sensitivity of the sensor; the sensitive membrane adopts a flat membrane structure, which successfully solves the acceleration interference caused by the mass block that may be introduced in the back etching process of the traditional beam membrane-mass block structure. This improvement effectively reduces the noise output, thereby improving the clarity and accuracy of the signal.

[0029] The present invention adopts P-type heavily doped silicon leads and P-type heavily doped piezoresistive strips to form the sensitive circuit of the sensor chip. This choice shows excellent stability in high temperature environments. Compared with the P-type lightly doped piezoresistive strips and metal leads used in traditional sensors, the heavily doped materials not only have a small sensitivity temperature drift, but also effectively simplify the production process, reduce the use of materials and process steps, thereby improving the overall production efficiency, reducing production costs, and ensuring higher output.

[0030] The present invention adopts a semi-open-loop Wheatstone bridge, is provided with five P-type heavily doped silicon leads and five metal point electrodes, allows the temperature compensation circuit to be conveniently added later, thereby further enhancing the temperature resistance of the sensor, improving its measurement accuracy in different temperature environments, and ensuring that good performance and stability are maintained under complex operating conditions.

[0031] The pressure sensor of the present invention is designed with a sealing ring on the periphery of the pad, which is beneficial to improving the sealing of the pressure sensor chip after vacuum bonding, and further reducing the impact of the sensor chip on corrosive gases and steam in the test environment. The sensor structure is flexible and diverse, suitable for all-solid-state packaging and leadless packaging, and can meet the needs of different application scenarios.

[0032] The present invention adopts SOI silicon wafer, which has low process preparation cost and high yield rate, can meet the needs of large-scale production, and its theoretical operating temperature can reach 600°C. Under high temperature conditions, the presence of the insulating layer effectively prevents the occurrence of PN junction breakdown and leakage, ensuring the long-term stability and reliability of the sensor, so that it still performs well in high-temperature applications.

[0033] The present invention uses silicon wafers instead of glass for vacuum bonding. Compared with silicon-glass bonding, silicon-silicon bonding generates less thermal stress under thermal cycle conditions, which can greatly improve the service life of the sensor in a wide temperature range.

[0034] In summary, compared with the prior art, the sensor chip of the present invention provides stronger adaptability and accuracy for sensors in practical applications and has broad market prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a front isometric schematic diagram of a high-pressure pressure sensor chip according to an embodiment of the present invention.

[0036] Figure 2 Schematic diagram of the back side isometric view of the high-pressure pressure sensor chip according to an embodiment of the present invention.

[0037] Figure 3 It is a schematic diagram of a double-island structure of a straight beam with stress holes according to an embodiment of the present invention.

[0038] Figure 4 This is an axonometric diagram of a high-pressure pressure sensor chip bonded to a silicon wafer according to an embodiment of the present invention.

[0039] Figure 5 Schematic diagram of the front axonometric view of a silicon wafer according to an embodiment of the present invention.

[0040] Figure 6 Schematic diagram of the back side isometric view of a silicon wafer according to an embodiment of the present invention.

[0041] Figure 7 This is a half-section isometric schematic diagram of a high-pressure pressure sensor chip after bonding to a silicon wafer filled with a conductive metal according to an embodiment of the present invention.

[0042] Figure 8 Schematic diagram of the sensor chip preparation method according to an embodiment of the present invention: Figure (a) is a schematic diagram of the SOI substrate structure; Figure (b) is a schematic diagram of heavy doping; Figure (c) is a schematic diagram of dry etching of varistor strips, P-type heavily doped silicon leads, a double-island structure of a straight beam with stress holes and a sealing ring; Figure (d) is a schematic diagram of depositing silicon nitride and silicon dioxide; Figure (e) is a schematic diagram of wet etching of the cavity after etching the back silicon dioxide and silicon nitride; Figure (f) is a schematic diagram of metal sputtering point electrodes after etching the front silicon dioxide and silicon nitride; Figure (g) is a schematic diagram of dry etching the front to form a complete double-island structure of a straight beam with stress holes; Figure (h) is a schematic diagram of bonding; Figure (i) is a schematic diagram of electron beam evaporation of conductive metal.

[0043] Fig. 9 This is a comparison diagram of stress distribution of rectangular membranes, square membranes and circular membranes under the same pressure load in an embodiment of the present invention.

[0044] Fig.10 This is a comparison chart of the simulation performance of the rectangular membrane, square membrane and circular membrane according to the embodiment of the present invention.

[0045] Fig.11This is a comparison diagram of stress distribution under the same pressure load between the one-beam double-island structure with stress holes in an embodiment of the present invention and other beam island (mass block) structures.

[0046] Fig.12 This is a comparison chart of the simulation performance of the one-beam double-island structure with stress holes and other beam-island (mass block) structures according to an embodiment of the present invention.

[0047] Fig.13 Graph showing the relationship between the P-type silicon piezoresistance coefficient factor and the doping concentration and temperature according to an embodiment of the present invention.

[0048] Fig.14 This is a temperature compensation circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention is described in detail below in conjunction with embodiments and drawings.

[0050] Reference Figure 1 , Figure 2 A high-pressure pressure sensor chip with a straight beam double island structure and a stress hole comprises a support layer 1, an insulating layer 2 and a device layer 3 arranged from bottom to top; a cavity 1-1 is etched on the back of the support layer 1, a sensitive film 1-2 is directly above the cavity 1-1, and a straight beam double island structure 4 is arranged on the sensitive film 1-2; four piezoresistors 5-1, 5-2, 5-3, 5-4 are arranged at the edge and center of the straight beam double island structure 4, and the arrangement of the four piezoresistors 5-1, 5-2, 5-3, 5-4 adopts a "middle edge" design, and the effective length directions of the four piezoresistors 5-1, 5-2, 5-3, 5-4 are all along the (100) The crystal direction with the largest piezoresistance coefficient; the four varistor strips 5-1, 5-2, 5-3, and 5-4 are connected to form a semi-open-loop Wheatstone bridge through five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5. Five metal point electrodes 7-1, 7-2, 7-3, 7-4, and 7-5 are arranged at the center of the five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5. A sealing ring 8 is arranged around the outside. Adjacent P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5 are separated from the sealing ring 8 by a 10-20μm wide gap 9.

[0051] The sensitive film 1-2 is a rectangular thick film, and the film thickness is 0.5-0.7 times the thickness of the chip; the upper surface of the cavity 1-1 is the same in shape and size as the plane of the sensitive film 1-2.

[0052] Reference Figure 3The one-beam double-island structure 4 includes two square islands 4-1 and 4-2. The two square islands 4-1 and 4-2 are respectively connected to a beam 4-3. A stress hole 4-4 is arranged at the center of the beam 4-3. The depth of the stress hole 4-4 is consistent with the height of the two square islands 4-1 and 4-2 and the beam 4-3. The distance and side length between the two square islands 4-1 and 4-2, the width of the beam 4-3 and the length and width of the stress hole 4-4 are all determined by simulation optimization.

[0053] The thickness of the beam 4 - 3 is 10-40 μm, and the thickness of the beam is adjusted according to different sensitivity ranges.

[0054] The transverse and longitudinal stress differences of the two varistor strips 5-1 and 5-4 at the upper edge and the two varistor strips 5-2 and 5-3 at the center of the one-beam double-island structure 4 are in opposite directions, and the corresponding Wheatstone bridge resistance changes are opposite.

[0055] The varistor strips 5-1, 5-2, 5-3, and 5-4 are heavily doped with P type, and the doping concentration is the same as that of the P type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5. The upper surfaces of the varistor strips 5-1, 5-2, 5-3, and 5-4 are flush with the upper surfaces of the P type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5.

[0056] The depth of the fine slit 9 is 1.5 μm, which is equal to the depth of the device layer 3 .

[0057] Reference Figure 4 The front side of the device layer 3 is vacuum bonded to the silicon wafer 10 , and the sensitive circuit is protected in a vacuum cavity formed by the device layer 3 and the silicon wafer 10 .

[0058] Reference Figure 5 , Figure 6 , Figure 7 The silicon wafer 10 is provided with five through silicon vias 11-1, 11-2, 11-3, 11-4, and 11-5, which correspond to the shapes of the five metal point electrodes 7-1, 7-2, 7-3, 7-4, and 7-5 respectively; the five through silicon vias 11-1, 11-2, 11-3, 11-4, and 11-5 are filled with conductive metal 12; a groove 13 is provided in the center of the silicon wafer 10, and the shape of the groove 13 is rectangular. The width of the groove 13 corresponds to the sensitive film 1-2, and the length of the groove 13 corresponds to the farthest distance between the two varistor strips 5-1 and 5-4 at the edge. The depth of the groove 13 ensures that when there is high voltage input, the bottom surface of the groove 13 will not contact the one-beam double island structure 4.

[0059] Reference Figure 8 The method for preparing a high-pressure pressure sensor chip with a straight beam and double island structure and a stress hole comprises the following steps:

[0060] 1) The chip uses SOI silicon wafer, which consists of device layer 3, insulating layer 2, and support layer 1 from top to bottom. The device layer 3 and support layer 1 are N-type single crystal silicon, the upper surface of the device layer 3 is a (100) crystal plane, and the insulating layer 2 is a SiO2 layer. Figure 8 As shown in (a);

[0061] 2) The chip is thermally oxidized, and the surface of the device layer 3 is heavily doped with boron ions and annealed to make the implanted ions evenly distributed in the device layer 3 to achieve electrical activation, such as Figure 8 As shown in (b);

[0062] 3) Using ICP technology, the silicon of the device layer 3 is etched away to form four varistor strips 5-1, 5-2, 5-3, and 5-4; five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5; a sealing ring 8, such as Figure 8 As shown in (c);

[0063] 4) Using PECVD technology to deposit silicon dioxide and silicon nitride 2-1 on the entire chip surface, such as Figure 8 As shown in (d);

[0064] 5) Use ICP technology to etch away the silicon dioxide and silicon nitride 2-1 on the back of the support layer 1. The etching area is based on the positive surface area of ​​the cavity 1-1, and then wet etching is used to etch to the bottom of the sensitive film 1-2 (0.5-0.7 times the thickness of the chip). Figure 8 As shown in (e);

[0065] 6) Using ICP technology to etch away the silicon dioxide and silicon nitride 2-1 on the surface of the chip, exposing the point electrode area, and then forming five metal point electrodes 7-1, 7-2, 7-3, 7-4, and 7-5 through metal sputtering and stripping processes, as shown in FIG. Figure 8 As shown in (f);

[0066] 7) The device layer 3, the insulating layer 2 and the support layer 1 are etched using ICP technology, with an etching depth of 10-40 μm to form a complete three-dimensional structure of a beam double island structure 4 with stress holes, such as Figure 8 As shown in (g);

[0067] 8) The surface of the device layer 3 is vacuum bonded to the silicon wafer 10, and during the bonding, the five through silicon vias 11-1, 11-2, 11-3, 11-4, and 11-5 are aligned with the positions of the five metal point electrodes 7-1, 7-2, 7-3, 7-4, and 7-5 on the device layer 3, such as Figure 8 As shown in (h);

[0068] 9) Using electron beam evaporation technology, the five through silicon vias 11-1, 11-2, 11-3, 11-4, and 11-5 are filled with conductive metal 12, such as Figure 8 As shown in (i).

[0069] Reference Fig. 9 and Fig.10 In this embodiment, the sensitive membrane 1-2 adopts a rectangular membrane (aspect ratio of 2.04:1). Compared with the square membrane and the circular membrane, the rectangular membrane exhibits the smallest diaphragm displacement and the largest natural frequency under different working conditions; this shows that the rectangular membrane has higher stiffness and overload capacity when subjected to external force, and can effectively suppress excessive deformation of the diaphragm. The rectangular membrane sensor can provide the best output stability under high-frequency dynamic response conditions, especially in a rapidly changing high-pressure environment, and can quickly and accurately respond to external pressure changes, ensuring that the sensor maintains high performance stability and response accuracy under extreme working conditions. This structure is therefore suitable for high-pressure detection applications that require high precision and fast response.

[0070] Reference Fig.11 , Fig.12 , compared with the cross beam structure, the cross beam structure, the cross beam single island structure, the cross beam single island-mass block structure, the cross beam four island structure, the cross beam four island-mass block structure, the single beam single island structure, the single beam single island-mass block structure, the double island structure, and the double island-mass block structure, the double island structure with stress holes has the highest stress difference, indicating that the structure can produce a more significant strain response under the action of external pressure; in addition, the first-order mode (working mode) natural frequency of the structure is relatively high, ensuring that it has good dynamic response characteristics during operation. Taking into account its stress sensitivity and natural frequency, the double island structure with stress holes can effectively meet the requirements of high-pressure sensors in terms of high sensitivity and high linearity, and therefore has the best performance among all compared structures, and is suitable for high-precision and high-pressure detection applications.

[0071] Reference Fig.13 , the variation law of the piezoresistance coefficient factor of P-type silicon with doping concentration and temperature in this embodiment can draw the following conclusions: with the increase of doping concentration, the difference between the piezoresistance coefficient factors of P-type silicon at different temperatures gradually decreases; this indicates that P-type silicon materials with higher doping concentrations exhibit smaller temperature drift (temperature drift) within different temperature ranges. This phenomenon indicates that highly doped P-type silicon materials have better temperature stability, thereby reducing the sensitivity error caused by temperature changes, and are suitable for use in environments with large temperature changes, especially in applications such as high-temperature and high-pressure sensors, with strong adaptability and accuracy.

[0072] Reference Fig.14The temperature compensation circuit of this embodiment is composed of a varistor strip and a compensation resistor, and its specific composition and functions are as follows: resistors R1, R2, R3, and R4 are the resistances of the varistor strips 5-1, 5-2, 5-3, and 5-4, respectively, which are used to sense external pressure and convert it into a corresponding electrical signal; Rz is a zero-point output compensation resistor, which is used to correct the initial output deviation of the sensor; Rp is a thermal zero-point drift compensation resistor, which is used to compensate for the zero-point drift caused by temperature change; Rs is a thermal sensitivity compensation resistor, which is used to correct the influence of temperature change on sensitivity; the resistors in the circuit are connected through P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5 to form a complete Wheatstone bridge structure. Through the synergistic effect of the varistor strips and the compensation resistors, accurate compensation for temperature drift and sensitivity drift is achieved.

Claims

1. A high-pressure pressure sensor chip with a straight beam and double island structure and a stress hole, comprising a support layer (1), an insulating layer (2) and a device layer (3) arranged from bottom to top; a cavity (1-1) is etched on the back of the support layer (1), and a sensitive film (1-2) is located directly above the cavity (1-1), characterized in that: A straight-beam double-island structure (4) is provided on the sensitive film (1-2); four varistor strips (5-1, 5-2, 5-3, 5-4) are arranged at the edge and center of the straight-beam double-island structure (4), respectively; the four varistor strips (5-1, 5-2, 5-3, 5-4) are connected to form a semi-open-loop Wheatstone bridge through five P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5); five metal point electrodes (7-1, 7-2, 7-3, 7-4, 7-5) are arranged at the center of the area of ​​the five P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5); a sealing ring (8) is provided on the outer side of the surrounding area; and adjacent P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5) and the sealing ring (8) are separated by a fine gap (9).

2. The chip according to claim 1, characterized in that: The sensitive film (1-2) is a rectangular thick film, and the film thickness is 0.5-0.7 times the thickness of the chip; the upper surface of the cavity (1-1) is the same size as the plane shape of the sensitive film (1-2); the arrangement of the four varistor strips (5-1, 5-2, 5-3, 5-4) adopts a "center-edge" design, and the effective length directions of the four varistor strips (5-1, 5-2, 5-3, 5-4) are all along the crystal direction with the largest piezoresistance coefficient of the (100) crystal plane.

3. The chip according to claim 1, characterized in that: The one-beam double-island structure (4) comprises two square islands (4-1, 4-2), the two square islands (4-1, 4-2) are respectively connected to a beam (4-3), a stress hole (4-4) is arranged at the center of the beam (4-3), the depth of the stress hole (4-4) is consistent with the height of the two square islands (4-1, 4-2) and the beam (4-3); the distance and side length between the two square islands (4-1, 4-2), the width of the beam (4-3) and the length and width of the stress hole (4-4) are all determined through simulation optimization.

4. The chip according to claim 3, characterized in that: The thickness of the beam (4-3) is 10-40 μm, and the thickness of the beam is adjusted according to different sensitivity ranges.

5. The chip according to claim 1, characterized in that: The transverse and longitudinal stress differences of the two varistor strips (5-1, 5-4) at the upper edge and the two varistor strips (5-2, 5-3) at the center of the one-beam double-island structure (4) are in opposite directions, and the corresponding Wheatstone bridge pair resistance changes are in opposite directions.

6. The chip according to claim 1, characterized in that: The varistor strips (5-1, 5-2, 5-3, 5-4) are heavily P-doped, and the doping concentration is the same as that of the P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5). The upper surface of the varistor strips (5-1, 5-2, 5-3, 5-4) is flush with the upper surface of the P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5).

7. The chip according to claim 1, characterized in that: The depth of the fine slit (9) is 1.5 μm, which is equal to the depth of the device layer (3).

8. The chip according to claim 1, characterized in that: The front side of the device layer (3) is vacuum bonded to the silicon wafer (10), so that the sensitive circuit is protected in a vacuum cavity formed by the device layer 3 and the silicon wafer (10).

9. The chip according to claim 8, characterized in that: The silicon wafer (10) is provided with five silicon through holes (11-1, 11-2, 11-3, 11-4, 11-5), which respectively correspond to the shapes of the five metal point electrodes (7-1, 7-2, 7-3, 7-4, 7-5); the five silicon through holes (11-1, 11-2, 11-3, 11-4, 11-5) are filled with conductive metal (12); a groove (13) is provided at the center of the silicon wafer (10), the shape of the groove (13) is rectangular, the width of the groove (13) corresponds to the sensitive film (1-2), the length of the groove (13) corresponds to the farthest distance between two varistor strips (5-1, 5-4) at the edge, and the depth of the groove (13) ensures that when there is high voltage input, the bottom surface of the groove (13) will not contact the one-beam double island structure (4).

10. A method for preparing a high-pressure pressure sensor chip with a straight beam and double island structure and stress holes as claimed in any one of claims 1 to 9, characterized in that: The following steps are involved: 1) The chip adopts an SOI silicon wafer, and the SOI silicon wafer comprises a device layer (3), an insulating layer (2), and a support layer (1) from top to bottom, wherein the device layer (3) and the support layer (1) are N-type single crystal silicon, the upper surface of the device layer (3) is a (100) crystal plane, and the insulating layer (2) is a SiO2 layer; 2) thermally oxidizing the chip, heavily doping the surface of the device layer (3) with boron ions, and annealing to make the implanted ions evenly distributed in the device layer (3) to achieve electrical activation; 3) using ICP technology to etch away silicon of the thickness of the device layer (3) to form four varistor strips (5-1, 5-2, 5-3, 5-4); five P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5); and a sealing ring (8); 4) Using PECVD technology to deposit silicon dioxide and silicon nitride (2-1) on the entire chip surface; 5) using ICP technology to etch away the silicon dioxide and silicon nitride (2-1) on the back of the support layer (1), the etching area being based on the positive surface area of ​​the cavity (1-1), and then using wet etching until the etching depth of the sensitive film (1-2) is 0.5-0.7 times the thickness of the chip; 6) Using ICP technology to etch away silicon dioxide and silicon nitride (2-1) on the surface of the chip to expose the point electrode area, and then forming five metal point electrodes (7-1, 7-2, 7-3, 7-4, 7-5) through metal sputtering and lift-off processes; 7) using ICP technology to etch the device layer (3), the insulating layer (2) and the support layer (1) to a depth of 10-40 μm to form a complete three-dimensional structure of a one-beam double-island structure (4) with stress holes; 8) vacuum bonding the surface of the device layer (3) to the silicon wafer (10), wherein during bonding, five through silicon vias (11-1, 11-2, 11-3, 11-4, 11-5) are aligned with the positions of five metal point electrodes (7-1, 7-2, 7-3, 7-4, 7-5) on the device layer (3); 9) Filling the five through silicon vias (11-1, 11-2, 11-3, 11-4, 11-5) with conductive metal (12) using electron beam evaporation technology.

Images