JTAG (Joint Test Action Group) delay self-correction processing method and system for boundary scan test

Abstract

The invention discloses a JTAG (Joint Test Action Group) delay self-correction processing method and a JTAG delay self-correction processing system for a boundary scan test. The JTAG delay self-correction processing method comprises the following steps: generating and acquiring first data corresponding to JTAG delay correction processing in a boundary scan test system through the method; wherein the first data is JTAG signal data and comprises clock signal data, state signal data, input signal data and return signal data; generating second data corresponding to the boundary scan test system according to the first data; wherein the second data is delay data in the boundary scan test system; based on the second data, the data delay state in the boundary scan test system is subjected to real-time self-correction processing, and the self-correction function can be realized, that is, when an application person uses a product, delay does not need to be obtained, delay correction is only needed to be performed on a BS chain through one key of an upper computer, the signal test rate and the signal stability are improved, and the user experience is improved. And the convenience of delay correction is remarkably improved, and the operation difficulty of system delay correction is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of boundary scan testing, and in particular relates to a JTAG delay self-correction processing method and system for boundary scan testing. Background Art

[0002] In the field of boundary scan testing, boundary scan testing is inseparable from JTAG signals. JTAG signals mainly include: clock signal TCK, status signal TMS, input signal TDI, return signal TDO. Boundary scan testing is based on boundary scan chain (BS chain). BS chain is composed of 1 to multiple boundary scan chips (BS chips) connecting JTAG signals in series. BS chain includes BS chain on the board under test (DUT), and BS chain composed of 1 to multiple analog test cards (DUMMY chain, there are also BS chips on DUMMY cards) for auxiliary DUT connectors and pin point testing. These links will have JTAG delay during the test process. Conventional boundary scan controller (BS controller) collects return signal TDO through clock signal TCK. TCK, TMS, and TDI data are synchronously input to BS chain, and the delay between them is negligible. However, due to the existence of delays such as line length and comparator of BS chain TDO return path, it is easy to have unstable data collected by BS controller end or collection errors due to data misalignment. Conventional boundary scan test TCK clock frequency cannot be too high, and the test rate cannot be increased.

[0003] Patent CN117783842A proposes a delay correction processing method for boundary scan testing. The method for obtaining the JTAG delay of the BS chain is obtained through observation with an oscilloscope, and the obtained delay needs to be sent down. The debugging process is relatively cumbersome and highly professional.

[0004] In addition, the research found that by simulating a certain length of line, short-circuiting the TDI and TDO of the BS controller through this certain length of line, the TDI of the BS controller sends a pulse, and the TDO of the BS controller receives the pulse, it is only necessary to obtain the pulse time between TDI sending and TDO receiving, and delay calibration can be performed. This correction method does not need to consider opening up the boundary scan chain, but the simulated line length cannot fully reflect the actual situation of the actual test, so the accuracy of obtaining the delay is not enough. In addition, the simulated line length requires manual measurement intervention and cannot achieve automatic correction, so it is not the best method.

[0005] Therefore, in view of the above-mentioned technical problems and defects, it is urgent to design and develop a JTAG delay self-correction processing method and system for boundary scan testing. Summary of the invention

[0006] In order to overcome the shortcomings and difficulties of the above-mentioned prior art, the purpose of the present invention is to provide a JTAG delay self-correction processing method, system and platform for boundary scan testing to realize the self-correction function, that is, when the application personnel use the product, there is no need to obtain the delay, but only need to correct the delay of the BS chain with one click through the host computer.

[0007] The first purpose of the present invention is to provide a JTAG delay self-correction processing method for boundary scan testing; the second purpose of the present invention is to provide a JTAG delay self-correction processing system for boundary scan testing; the third purpose of the present invention is to provide a JTAG delay self-correction processing platform for boundary scan testing.

[0008] The first object of the present invention is achieved in that the method comprises the following steps:

[0009] Generate and obtain first data corresponding to a JTAG delay correction process to be performed in a boundary scan test system; wherein the first data is JTAG signal data, including clock signal data, status signal data, input signal data and return signal data;

[0010] generating second data corresponding to a boundary scan test system according to the first data; wherein the second data is delay data in the boundary scan test system;

[0011] Based on the second data, a data delay state in the boundary scan test system is processed by real-time self-correction.

[0012] Furthermore, the generating and acquiring of first data corresponding to the JTAG delay correction process to be processed in the boundary scan test system further includes:

[0013] Generate and acquire third data corresponding to the clock signal of the boundary scan test system, generate corresponding first level data according to the third data processing, and flip the first level data; wherein the third data is the clock rising edge data of the boundary scan test system; the first level data is the level data corresponding to the third data and subjected to value assignment processing;

[0014] Generate and acquire fourth data corresponding to the state signal of the boundary scan test system, and generate corresponding second level data according to the fourth data; wherein the fourth data is the clock rising edge data of the boundary scan test system; the second level data is the level data corresponding to the fourth data and after the assignment processing;

[0015] Generate and obtain fifth data corresponding to the input signal of the boundary scan test system, and generate corresponding third level data according to the fifth data processing; wherein the fifth data is the clock rising edge data or the clock falling edge data of the boundary scan test system; the third level data is the level data corresponding to the fifth data and has been assigned a value.

[0016] Further, the generating, according to the first data, second data corresponding to the boundary scan test system further includes:

[0017] The boundary register units of the boundary register of the boundary scan chip in the boundary scan chain are arranged sequentially; wherein the head and the tail of the boundary register unit are TDI input and TDO output respectively; and the TDI signal is input to the boundary scan chain.

[0018] Further, the generating, according to the first data, second data corresponding to the boundary scan test system further includes:

[0019] Generate and obtain first instruction data corresponding to the boundary scan chip, send and process the first instruction data in sequence, and serially shift the first instruction data to the corresponding instruction register;

[0020] Generate and acquire sixth data corresponding to the boundary scan test system, and generate second data corresponding to the boundary scan test system according to the sixth data; wherein the sixth data is clock frequency data.

[0021] Furthermore, the real-time self-correction of the data delay state in the boundary scan test system based on the second data further includes:

[0022] Generate and obtain seventh data corresponding to the return signal of the boundary scan test system, and generate corresponding fourth level data according to the seventh data; wherein the seventh data is the rising edge data of the boundary scan test system clock; and the fourth level data is the level data corresponding to the seventh data and after the assignment processing;

[0023] Based on the fourth level data, eighth data corresponding to the boundary scan test system is generated, and combined with the sent data length status, the eighth data is assigned and processed in sequence; wherein the eighth data is the return signal data after delay correction.

[0024] The second object of the present invention is achieved in this way: the system is applied to the JTAG delay self-correction processing method for boundary scan testing, and the system comprises:

[0025] A first data generating unit, configured to generate and obtain first data corresponding to a JTAG delay correction process to be performed in a boundary scan test system; wherein the first data is JTAG signal data, including clock signal data, state signal data, input signal data and return signal data;

[0026] A second data generating unit, configured to generate second data corresponding to the boundary scan test system according to the first data; wherein the second data is delay data in the boundary scan test system;

[0027] The delay correction processing unit is used for real-time self-correction of the data delay state in the boundary scan test system based on the second data.

[0028] Furthermore, the first data generating unit further includes:

[0029] A first generating module is used to generate and obtain third data corresponding to the clock signal of the boundary scan test system, and generate corresponding first level data according to the third data, and flip the first level data; wherein the third data is the clock rising edge data of the boundary scan test system; the first level data is the level data corresponding to the third data and subjected to value assignment processing;

[0030] A second generating module is used to generate and obtain fourth data corresponding to the state signal of the boundary scan test system, and generate corresponding second level data according to the fourth data; wherein the fourth data is the clock rising edge data of the boundary scan test system; and the second level data is the level data corresponding to the fourth data and after the assignment processing;

[0031] A third generating module is used to generate and obtain fifth data corresponding to the input signal of the boundary scan test system, and generate corresponding third level data according to the fifth data; wherein the fifth data is the clock rising edge data or the clock falling edge data of the boundary scan test system; and the third level data is the level data corresponding to the fifth data and having been processed by the assignment process;

[0032] And / or, the second data generating unit further includes:

[0033] The first processing module is used to sequentially arrange and process the boundary register units of the boundary register of the boundary scan chip in the boundary scan chain; wherein the first and last boundary register units are TDI input and TDO output respectively; and the TDI signal is input to the boundary scan chain;

[0034] And / or, the delay correction processing unit further includes:

[0035] A second processing module is used to generate and obtain seventh data corresponding to the return signal of the boundary scan test system, and generate corresponding fourth level data according to the seventh data; wherein the seventh data is the rising edge data of the boundary scan test system clock; and the fourth level data is the level data corresponding to the seventh data and after the assignment processing;

[0036] The third processing module is used to generate eighth data corresponding to the boundary scan test system based on the fourth level data, and to assign values ​​to process the eighth data in sequence in combination with the sent data length status; wherein the eighth data is the return signal data after delay correction.

[0037] Furthermore, the second data generating unit further includes:

[0038] a fourth processing module, configured to generate and obtain first instruction data corresponding to the boundary scan chip, and sequentially send and process the first instruction data, and serially shift the first instruction data to a corresponding instruction register;

[0039] The fourth generating module is used to generate and obtain sixth data corresponding to the boundary scan test system, and generate second data corresponding to the boundary scan test system according to the sixth data; wherein the sixth data is clock frequency data.

[0040] The third object of the present invention is achieved as follows: the platform includes a processor, a memory and a JTAG delay self-correction processing platform control program for boundary scan testing; wherein, the JTAG delay self-correction processing platform control program for boundary scan testing is executed on the processor, the JTAG delay self-correction processing platform control program for boundary scan testing is stored in the memory, and the JTAG delay self-correction processing platform control program for boundary scan testing implements the JTAG delay self-correction processing method for boundary scan testing.

[0041] The present invention generates and obtains first data corresponding to the JTAG delay correction processing in the boundary scan test system through a method; wherein the first data is JTAG signal data, including clock signal data, state signal data, input signal data and return signal data; according to the first data, second data corresponding to the boundary scan test system is generated; wherein the second data is the delay data in the boundary scan test system; based on the second data, the data delay state in the boundary scan test system is processed by real-time self-correction, and the self-correction function can be realized, that is, when the application personnel use the product, there is no need to obtain the delay, and only one key is needed to perform delay correction on the BS chain through the host computer.

[0042] In other words, the solution of the present invention does not require delay acquisition outside the system for correction; the delay self-correction of multiple test ports is performed independently, which significantly improves the signal test rate and signal stability, significantly improves the convenience of delay correction, and reduces the operational difficulty of system delay correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic diagram of TCK signal generation in an embodiment of a JTAG delay self-correction processing method for boundary scan testing of the present invention;

[0045] Figure 2 A schematic diagram of TDI signal generation in an embodiment of a JTAG delay self-correction processing method for boundary scan testing of the present invention;

[0046] Figure 3 A waveform diagram of JTAG delay when the clock frequency is Ftck0 in an embodiment of a JTAG delay self-correction processing method for boundary scan testing of the present invention;

[0047] Figure 4 A waveform diagram of an actual boundary scan test JTAG delay before correction in an embodiment of a JTAG delay self-correction processing method for boundary scan test of the present invention;

[0048] Figure 5 A waveform diagram of an actual boundary scan test after correction according to an embodiment of a JTAG delay self-correction processing method for boundary scan test of the present invention;

[0049] Figure 6 A schematic diagram of a JTAG delay self-correction system according to an embodiment of a JTAG delay self-correction processing method for boundary scan testing of the present invention;

[0050] Figure 7 A schematic flow chart of the steps of a JTAG delay self-correction processing method for boundary scan testing of the present invention;

[0051] Figure 8 The present invention is a schematic diagram of the architecture of a JTAG delay self-correction processing system for boundary scan testing;

[0052] Fig. 9The present invention is a schematic diagram of the structure of a JTAG delay self-correction processing platform for boundary scan testing. DETAILED DESCRIPTION

[0053] In order to better understand the purpose, technical solutions and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0054] The present invention may also be implemented or applied through other different specific examples, and the details in this specification may also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0056] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. Secondly, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0057] Preferably, the JTAG delay self-correction processing method for boundary scan testing of the present invention is applied in one or more terminals or servers. The terminal is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASIC), programmable gate arrays (FPGA), digital signal processors (DSP), embedded devices, etc.

[0058] The terminal can be a computing device such as a desktop computer, a notebook, a PDA, a cloud server, etc. The terminal can interact with the client through a keyboard, a mouse, a remote control, a touch pad, or a voice control device.

[0059] The present invention is to realize a JTAG delay self-correction processing method, system and platform for boundary scan testing.

[0060] like Figure 7 , which is a flow chart of a JTAG delay self-correction processing method for boundary scan testing provided by an embodiment of the present invention.

[0061] In this embodiment, the JTAG delay self-correction processing method for boundary scan testing can be applied to a terminal or a fixed terminal with a display function. The terminal is not limited to a personal computer, a smart phone, a tablet computer, a desktop computer or an all-in-one computer equipped with a camera, etc.

[0062] The JTAG delay self-correction processing method for boundary scan testing can also be applied to a hardware environment composed of a terminal and a server connected to the terminal through a network. The network includes but is not limited to: a wide area network, a metropolitan area network or a local area network. The JTAG delay self-correction processing method for boundary scan testing of the embodiment of the present invention can be executed by a server, can be executed by a terminal, or can be executed by a server and a terminal together.

[0063] For example, for a terminal that needs to perform JTAG delay self-correction processing for boundary scan testing, the JTAG delay self-correction processing function for boundary scan testing provided by the method of the present invention can be directly integrated on the terminal, or a client for implementing the method of the present invention can be installed. For another example, the method provided by the present invention can also be run on a server or other device in the form of a software development kit (SDK), and an interface for the JTAG delay self-correction processing function for boundary scan testing is provided in the form of SDK. The terminal or other device can implement the JTAG delay self-correction processing function for boundary scan testing through the provided interface. The present invention is further described below in conjunction with the accompanying drawings.

[0064] The present invention will be further described in detail below in conjunction with the accompanying drawings. Figure 1-Figure 7 As shown, the present invention provides a JTAG delay self-correction processing method for boundary scan testing, wherein the method comprises the following steps:

[0065] S01, generating and acquiring first data corresponding to a JTAG delay correction process to be processed in a boundary scan test system; wherein the first data is JTAG signal data, including clock signal data, state signal data, input signal data and return signal data;

[0066] S02. Generate second data corresponding to a boundary scan test system according to the first data; wherein the second data is delay data in the boundary scan test system;

[0067] S03. Based on the second data, perform real-time self-correction on the data delay state in the boundary scan test system.

[0068] The generating and acquiring first data corresponding to the JTAG delay correction process to be processed in the boundary scan test system also includes:

[0069] S011, generating and acquiring third data corresponding to a clock signal of a boundary scan test system, and generating corresponding first level data according to the third data, and flipping the first level data; wherein the third data is clock rising edge data of the boundary scan test system; the first level data is level data corresponding to the third data and having been assigned a value;

[0070] S012, generating and acquiring fourth data corresponding to the state signal of the boundary scan test system, and generating corresponding second level data according to the fourth data; wherein the fourth data is the clock rising edge data of the boundary scan test system; and the second level data is the level data corresponding to the fourth data and having been assigned a value;

[0071] S013. Generate and obtain fifth data corresponding to the input signal of the boundary scan test system, and generate corresponding third level data according to the fifth data; wherein the fifth data is the clock rising edge data or the clock falling edge data of the boundary scan test system; the third level data is the level data corresponding to the fifth data and has been assigned a value.

[0072] The step of generating second data corresponding to the boundary scan test system according to the first data further includes:

[0073] S021. Sequentially arrange the boundary register units of the boundary scan chip in the boundary scan chain; wherein the first and the last of the boundary register unit are TDI input and TDO output respectively; and the TDI signal is input to the boundary scan chain.

[0074] The step of generating second data corresponding to the boundary scan test system according to the first data further includes:

[0075] S022, generating and acquiring first instruction data corresponding to the boundary scan chip, and sending and processing the first instruction data in sequence, and serially shifting the first instruction data to the corresponding instruction register;

[0076] S023. Generate and acquire sixth data corresponding to the boundary scan test system, and generate second data corresponding to the boundary scan test system according to the sixth data; wherein the sixth data is clock frequency data.

[0077] The real-time self-correction processing of the data delay state in the boundary scan test system based on the second data also includes:

[0078] S031, generating and acquiring seventh data corresponding to a return signal of a boundary scan test system, and generating corresponding fourth level data according to the seventh data; wherein the seventh data is clock rising edge data of the boundary scan test system; and the fourth level data is level data corresponding to the seventh data and having been valued;

[0079] S032. Based on the fourth level data, generate eighth data corresponding to the boundary scan test system, and assign values ​​to process the eighth data in sequence in combination with the sent data length status; wherein the eighth data is the return signal data after delay correction.

[0080] Specifically, in the embodiment of the present invention, the BS controller (BS controller) main control chip model refers to the ZYNQ series, such as the common XC7Z020-1CLG484I, which is an integrated chip of ARM and FPGA, and has two types of functions. The ARM function pin is the PS pin, and the FPGA function pin is the PL pin. The present invention takes the setting of the system clock 200MHz as an example (the common system clock frequency at the board level), and stipulates that the maximum TCK clock frequency of the boundary scan test is 25MHz, and the minimum is 500kHz.

[0081] The signals TCK, TMS, and TDI output by the BS controller act on the BS chain, and the TDO return signal of the BS chain will be received by the BS controller.

[0082] The generation of TCK, TMS, TDI signals and the reception of TDO signals are all completed by FPGA in parallel with the system clock.

[0083] Set an array of length a = Fclk / (2*Ftck), where Fclk represents the system clock frequency 200MHz, and Ftck represents the TCK clock frequency of JTAG, which can be freely set within the range of 500kHz to 25MHz.

[0084] The value of a is determined, such as: TCK is set to 500kHz,

[0085] Then a=Fclk / (2*Ftck)=200MHz / (2*500kHz)=200, TCK is set to 5MHz,

[0086] Then a=Fclk / (2*Ftck)=200MHz / (2*5MHz)=20, TCK is set to 12.5MHz,

[0087] Then a=Fclk / (2*Ftck)=200MHz / (2*12.5MHz)=8, TCK is set to 25MHz,

[0088] Then a=Fclk / (2*Ftck)=200MHz / (2*25MHz)=4. The present invention always ensures that the system clock size 200MHz can be divided by the set frequency size of TCK, thereby ensuring that a is an integer.

[0089] The steps to generate the TCK clock signal are as follows:

[0090] Set up an array: M = [m1, m2, m3, m4, ... ma], the initial state array values ​​are m1 = 1, m2 = T3 = m4 ... m(a-1) = ma = 0.

[0091] Combination Figure 1 As shown,

[0092] Step 1: When the rising edge of the first system clock is detected, the array is in the initial state, M = [1, 0, 0, 0, ... 0, 0], m1 = 1, and TCK starts to generate a high level 1.

[0093] Step 2, assign the numbers at the back of the array to the front: m1=m2, m2=m3, m3=m4, ....m(a-1)=ma, ma=m1, at this time the array is [0,0,0,0,...0,1]. When the second system clock rising edge comes, since m1=0, TCK maintains a high level of 1.

[0094] Step 3: still execute the assignment operation of step 2: m1=m2, m2=m3, m3=m4, ....m(a-1)=ma, ma=m1. At this time, the array is [0,0,0,0,...1,0]. When the third system clock rising edge comes, since m1=0, TCK still maintains a high level of 1.

[0095] And so on, …

[0096] In step a, the assignment operation of step 2 is still executed. At this time, the array is [0,1,0,0,...0,0]. When the a-th system clock rising edge comes, since m1=0, TCK still maintains a high level 1.

[0097] In step a+1, the assignment operation of step 2 is still executed. At this time, the array is [1,0,0,0,...0,0]. When the rising edge of the a+1 system clock comes, since m1=0, the level of TCK is flipped to low level 0.

[0098] And so on, ... step 2a, still execute the assignment operation of step 2, at this time the array [0,1,0,0,...0,0], when the 2ath system clock rising edge comes, since m1=0, TCK still maintains a low level of 0.

[0099] In step 2a+1, the assignment operation of step 2 is still executed. At this time, the array is [1,0,0,0,...0,0]. When the rising edge of the 2a+1 system clock comes, since m1=1, the level of TCK is flipped to high level 1.

[0100] And so on, ... the level of each system clock TCK flips once, thereby generating a stable JTAG clock signal TCK;

[0101] TDI signal generation: Whenever m1=1, the level of JTAG's TCK signal will flip once, and TDI data is generated synchronously at the falling edge of TCK (the moment when TCK flips from 1 to 0). Combined with the boundary scan, the data that needs to be sent to the BS chain (DUT end) completes the corresponding level generation. When each TCK falling edge comes, the TDI level changes by 1 bit. The purpose of sending TDI data synchronously at the falling edge of TCK is to ensure that the BS chain BS chip can capture the TDI data sent by the BS controller at the best position of the TCK rising edge, and to ensure that the TDI signal received by the DUT end from JTAG is stable.

[0102] The specific method is as follows. The TDI signal is still generated in combination with the system clock to achieve the above effect. TDI and TCK are generated in parallel with the system clock. The generation of the TDI signal requires setting a new array N. The length of the array is (2a), N = [n1, n2, n3, n4, ... na, n(a+1), n(a+2), n(a+3), n(a+4), ..., n(2a)],

[0103] The values ​​of the initial state array are: n1=n2=n3=n4…=na=0, n(a+1)=1, n(a+2)=n(a+3)=n(a+4)…=n(2a)=0,

[0104] Combination Figure 2 As shown,

[0105] Step 1: When the first rising edge of the system clock is detected, the array is in the initial state M = [0,0,0,0,...0,0,1,0,0,0,...0,0], n1 = 0, and TDI data is not generated.

[0106] Step 2: Assign the numbers at the back of the array to the numbers at the front: n1=n2, n2=n3, n3=n4, ....na=n(a+1), n(a+1)=n(a+2), n(a+2)=n(a+3), n(a+3)=n(a+4),

[0107] ...n(2a)-1)=n(2a), n(2a)=n1, at this time the array is [0,0,0,0,...0,1,0,0,0,0,...0,0]. When the second system clock rising edge comes, since m1=0, the TDI signal is not generated.

[0108] Step 3, still execute step 2, n1=n2, n2=n3, n3=n4, ....na=n(a+1), n(a+1)=n(a+2), n(a+2)=n(a+3), n(a+3)=n(a+4), ...n(2a)-1)=n(2a), at this time the array is [0,0,0,0,...1,0,0,0,0,0,...0,0]. When the third system clock rising edge comes, since m1=0, the TDI signal is not generated at this time.

[0109] And so on, …

[0110] In step a+1, the assignment operation of step 2 is still executed. At this time, the array is: [1,0,0,0,...0,0,0,0,0,0,...0,0]. When the a+1th system clock rising edge comes, since m1=1, TDI starts to generate the 1st bit level signal, as shown in the figure as high level 1.

[0111] And so on, …

[0112] In step 3a+1, the assignment operation of step 2 is still executed. At this time, the array is: [1,0,0,0,...0,0,0,0,0,0,...0,0]. When the rising edge of the 3a+1 system clock comes, since m1=1, TDI starts to generate the second-bit level signal, such as the low level 0 in the figure.

[0113] By analogy, a TDI level signal is generated every 2a system clocks, thereby generating a TDI input signal;

[0114] TMS signal generation: By the same token, each 1-bit level signal of TMS occurs either synchronously at the rising edge of TCK or synchronously at the falling edge of TCK. In short, the status signal TMS enters the boundary scan mode according to the needs of the JTAG state machine. The method is the same as the generation of the TDI signal, and both are implemented in parallel processing in conjunction with the same system clock.

[0115] After the TCK, TMS, and TDI signals are generated, the boundary scan test mode is entered according to the rules of the JTAG state machine. The data output by the BS controller TDI is input to the BS chain at the DUT end in the form of IR instructions and DR data. The DR data input is accompanied by the output of the BS chain TDO data.

[0116] From the perspective of boundary scan register, the boundary register cells of the BS chip of the BS chain are arranged in sequence. The head and tail of the cell are TDI input and TDO output respectively. The TDI signal is input to the BS chain, which actually moves the TDI data into the boundary register cell. Every time TDI moves 1 bit of data into the boundary register cell, 1 bit of data will be moved out from TDO, and the moved data will be returned to the BS controller through the TDO signal.

[0117] The JTAG delay mainly comes from the delay between the JTAG signal TDO returned to the BS controller and the JTAG signals TCK, TMS, and TDI output from the BS controller. TCK, TMS, and TDI are all generated based on the same system clock. To achieve self-correction of the delay, we must start with the system clock and try to find a solution.

[0118] The TCK of JTAG can provide a stable delay reference, and the comparison of TDI and TDO signal waveforms can more clearly show the delay. Therefore, the present invention uses TCK, TDI and TDO signals as references and combines them with the system clock to elaborate on the delay self-correction method.

[0119] In the initial state, the TDI and TDO lines of the present invention are low level 0, which is very critical in the implementation of the present invention (all implementation processes are based on this condition).

[0120] The delay self-correction effect of the present invention is as follows:

[0121] The host computer can perform delay calibration on one chain with one button. After successful calibration, it can directly perform conventional BS chain boundary scan test.

[0122] To realize the delay self-correction of the BS chain, it is very important to open the channel of the DR data register of the BS chain composed of the BS chip to realize the shift, so that TDO will have the expected output.

[0123] Therefore, it is necessary to send the IR command to the IR command register first. The IR command is like a key to open the channel of the DR data register to achieve shifting.

[0124] BS chip has multiple IR instructions, IDcode instruction is one of them. Taking the chip 10M25DAF484I7G of Altera as an example, the IDcode instruction is 0000000110, and the expected IDcode data is 00000011000100000100000011011101. The expected IDcode data is 32 bits.

[0125] If there are multiple BS chips in the BS chain, they will send their respective IDcode instructions serially shifted to the IDcode instruction register in turn, and serially shift out their expected IDcode data. The data signals are received by the boundary scan register in turn.

[0126] The present invention takes a BS chain of a BS chip as an example to explain in detail the delay self-correction method. As for the delay self-correction of multiple chips, the method is the same.

[0127] In the actual boundary scan test process, the TCK clock frequency will be as high as 25MHz. At a higher test frequency, due to the existence of JTAG delay, TDO data will be misaligned. In order to improve the test rate and test stability, delay correction is required. For the convenience of users, users do not need to consider the delay size. They only need to set up the hardware project according to the conventional method. Each test port can achieve one-key delay self-correction, which is very convenient.

[0128] The delay self-correction firstly ensures the signal stability. The present invention sets the TCK clock frequency of the delay self-correction to Ftck0, and Ftck0 needs to be as small as possible.

[0129] Reason 1: By sending the IDcode instruction, it is ensured that the IDcode data register channel of the BS chain is opened and the expected IDcode data is correctly shifted out. If the TCK clock frequency is set too high, the IDcode instruction may not be correctly received by the IDcode instruction register of the BS chain due to the influence of signal quality. Only when the IDcode instruction register correctly receives the IDcode instruction can the expected IDcode data be correctly shifted out;

[0130] Reason 2: When the TCK clock frequency is too high, the frequency of the TDO return signal also increases, and the TDO number may also be wrong;

[0131] Reason 3: A new array of a system clock cycles can be set. Starting from sending the first signal of IDcode, the controller's TDI will collect data in sequence within a system clock. Within a system clock, a collected TDO data will be recorded to ensure that among a TDO data, TDO data without delay or misalignment can be stably collected to avoid TDO data misalignment. Delay correction needs to consider multiple misalignment situations. Although it can be handled, the process is more complicated.

[0132] Figure 3 This is a waveform diagram of JTAG delay when the TCK clock frequency is Ftck0. Figure 3 As shown, after the TDI of the BS controller shifts the known IDcode instruction 0000000110 to the BS chain, it shifts in any data with the same number of bits as the expected IDcode data (the TDI data of the present invention is ... 1101, which is sent from right to left by the BS controller in sequence).

[0133] The expected IDcode data 00000011000100000100000011011101 can be shifted out (as shown in the figure ...1101, from right to left, the BS controller receives it in sequence), and the TDO return signal is received by the BS controller in sequence. The present invention is derived from the actual situation.

[0134] The specific method is as follows: Combine Figures 1 to 3 As shown in the figure, the data of TDI starts to be sent out at the rising edge of the a+1 system clock. Theoretically, the TDO return signal should be received by the TDO of the BS controller at the rising edge of the 2a+1 system clock. However, due to the existence of JTAG delay, the data of TDO is delayed by TDI by Td, and the rising edge of the 2a+1 system clock is no longer the best collection position. Figure 3 It can be seen that at the rising edge of the 2a+1 system clock, the low level 0 generated by the 1st TDO signal can still receive the correct TDO data. This is because the TCK clock frequency Ftck0 is a lower frequency. At this time, even if the delay Td exists, data collection will not be misaligned.

[0135] In the case of a lower TCK clock frequency Ftck0, it is guaranteed that the JTAG delay will not exceed half a TCK clock cycle in any case, that is, the JTAG delay is controlled within a system clock cycle, and the delay situation will be maintained Figure 3 This brings convenience to the delay self-correction.

[0136] To achieve delay self-correction, you must first obtain the delay. The method for obtaining the delay is as follows:

[0137] There is a very important detail in the acquisition of the delay of the present invention, and the present invention is also implemented based on this point, that is, in the IEEE1149 protocol of boundary scanning, the first IDcode data (the first one from right to left) is defined as 1, that is, after sending the IDcode instruction to the BS chain through TDI, the first expected IDcode data moved out to TDO is 1. Based on this, the present invention obtains the JTAG delay according to the following method:

[0138] Define a new array X = [x1, x2, x3, x4, ... xa], in the initial state, x1 = x2 = x3 = x4 = ... = x(a-1) = xa = 0, continue the beginning of TDI to generate the a+1th step of the TDI signal,

[0139] When the a+1th system clock rising edge comes, the BS controller TDI starts to send a level signal and starts to collect the first bit of data k1 returned by TDO, performs the assignment operation, x1=k1, and records it in the array X.

[0140] When the rising edge of the a+2th system clock arrives, the second bit of data k2 returned by TDO is collected, x2=k2, and recorded in array X.

[0141] When the rising edge of the a+3th system clock arrives, the third bit of data k3 returned by TDO is collected, x3=k3, and recorded in array X.

[0142] When the rising edge of the a+4th system clock arrives, the 4th bit of data k4 returned by TDO is collected, x4=k4, and recorded in array X.

[0143] …

[0144] When the 2ath system clock rising edge comes, the ath bit data ka returned by TDO is collected, xa=ka, and recorded in array X.

[0145] Until the 2a+1th system rising edge comes, m1=1, which will be a sign that data will no longer be collected.

[0146] Therefore, combined with Figure 3As shown, array X records the TDO data collected from the rising edge of the a+1th system clock to the 2ath system clock, and X records the delay information, wherein the number of low-level 0 data reflects the JTAG delay size. Assuming that the number of low-level data collected from the rising edge of the a+1th to the 2ath system clock is p, (the p value is calculated by combining array X with the system clock after the recording is completed, and the method is relatively conventional), then 1≤p≤a, p is a very critical parameter of the present invention, which is the number of system clocks of JTAG delay. Therefore, in the actual test process, as long as the delay of p clock cycles is skipped and the first TDO return data is collected, and then collected once every 2a cycles, the delay correction effect can be achieved.

[0147] The JTAG delay can be calculated from p, Td≈Tclk×p, where Tclk is the period of the system clock. From the frequency of the system clock Fclk=200MHz, we know that Tclk=5ns, and the error is within one system clock period.

[0148] The clock frequency Ftck0 of TCK is a relatively low frequency, and the lowest 500kHz can be taken. Under this TCK frequency, the calibration is carried out, the data is stable, and the return data of TDO will not be misplaced. When Ftck0=500kHz, a=200, the occurrence of the above TCK, TMS, and TDI signals is also determined.

[0149] Under the condition of a lower TCK clock frequency Ftck0=500kHz, assuming that k1=k2=k3=k4...kp=0, k(p+1)=k(p+2)=...=Ka, p=19 is calculated, and a=200 is known, then Td≈Tclk×p=5ns*19=95ns (the delay self-correction of the present invention can calculate the delay, but does not care about the specific delay, only the p system clock cycles of the delay).

[0150] Combination Figure 4 The figure shows the waveform diagram of the actual boundary scan test JTAG delay before correction. The TCK signal is a fixed frequency signal. In order to increase the test rate, the TCK clock frequency is usually higher. The JTAG return signal data will be misaligned. At the rising edge of the 2a+1 system clock, the correct data cannot be received. Therefore, in the actual boundary scan test process, the delay of p system clocks can be fundamentally eliminated and correction can be achieved, which will greatly increase the test rate and improve the test stability. In order to achieve this goal,

[0151] Get the self-corrected p system clock delays, TCK clock frequency Ftck0 is set to the lowest 500kHz, and in the actual boundary scan test, TCK clock frequency Ftck1, the user can freely set between 500k to 25MHz, the actual boundary scan test delay correction, the system clock TCK, TMS, TDI generation method is the same as the method of obtaining Td delay generation, but TCK clock frequency Ftck1 will be set larger, no longer Figure 3 As shown in the waveform, JTAG delay will cause TDO data to be collected at a wrong position.

[0152] When actually testing, at different Ftck1 clock frequencies, the calculated JTAG delay Td = 95ns is a fixed value and will not change. Assuming that when the TCK clock frequency is Ftck1 = 8MHz, Figure 4 The data collection misalignment phenomenon occurs. The TCK clock period Ttck1 corresponding to 8MHz is 125ns. Since Td=95ns>(Ttck1) / 2=62.5ns, the data cannot be correctly collected at the rising edge of the 2a+1 system clock, resulting in collection misalignment.

[0153] Combination Figure 5 No matter how many bits of delay are misaligned, the present invention adopts a unified delay correction method in actual testing. p is the number of system clocks of JTAG delay. The delay self-correction is divided into three parts:

[0154] In the first part of delay correction implementation, the original rising edge acquisition position of TDO occurs at the rising edge of the second system clock cycle, so it is necessary to start correction from the second TCK clock rising edge. Set array S, S = [s1, s2, s3, s4, ... s(2a-1), s(2a)], the length of the array is 2a, and array S can just delay one TCK cycle. In the initial state, s1 = s2 = s3 = s4 = s(2a-1) = 0, s(2a) = 1,

[0155] Step 1. When the rising edge of the first system clock is detected, in addition to starting to generate TCK, S = [0,0,0,0,...0,1]. Since s1 = 0, the return data of TDO is not collected at this time. Then the assignment operation is performed, s1 = s2, s2 = s3, s3 = s4, s(2a-1) = s(2a), s(2a) = s1,

[0156] Step 2: When the rising edge of the second system clock is detected, S = [0,0,0,0,...1,0]. Since s1 = 0, the return data of TDO is not collected at this time, and the assignment operation of step 1 is executed.

[0157] And so on…

[0158] In step 2a-1, when the rising edge of the 2a-1 system clock is detected, S = [0,1,0,0,...0,0]. Since s1 = 0, the return data of TDO is not collected at this time, and the assignment operation in step 1 is executed.

[0159] Step 2a: When the rising edge of the 2a system clock is detected, S = [1, 0, 0, 0, ... 0, 0]. Since s1 = 1, the return data of TDO is still not collected.

[0160] s1=1 is the mark of the second part of the delay correction implementation. In the embodiment of the present invention, a=200.

[0161] Part 2: When s1=1 is detected, Part 2 is started.

[0162] Set array Y, Y = [y1, y2, y3, y4, ... y(p-1), yp], where in the initial state, y1 = y2 = y3 = y4 = ... = y(p-1) = 0, yp = 1,

[0163] The acquisition of TDO return signal is different from the generation of TDI. The generation of TDI starts from the first falling edge of TCK, while the acquisition of TDO starts from the first rising edge after TDI sends the first complete level signal. Due to the existence of JTAG delay, in actual testing, data will be misplaced or the data acquisition position will be bad. Therefore, it is necessary to correct the JTAG delay of p system clocks.

[0164] Part 2 of the delay self-correction follows Part 1.

[0165] In step 2a+1, when the rising edge of the 2a+1th system clock is detected, Y=[0,0,0,0,...0,1]. Since y1=0, the return data of TDO is not collected at this time. Then the assignment operation is performed, y1=y2, y2=y3, y3=y4,...y(p-1)=y(p), y(p)=y1.

[0166] In step 2a+2, when the rising edge of the 2a+2 system clock is detected, Y=[0,0,0,0,...1,0]. Since y1=0, the return data of TDO is not collected at this time. Then the assignment operation is performed, y1=y2, y2=y3, y3=y4,...y(p-1)=y(p), y(p)=y1.

[0167] And so on…

[0168] In step 2a+p-1, when the rising edge of the 2a+p1th system clock is detected, Y=[0,1,0,0,...0,0]. Since y1=0, the return data of TDO is not collected at this time. Then the assignment operation is performed, y1=y2, y2=y3, y3=y4,...y(p-1)=y(p), y(p)=y1.

[0169] In step 2a+p, when the rising edge of the 2a+pth system clock is detected, Y=[1,0,0,0,...0,0]. Since y1=1, the return data of TDO is still not collected at this time.

[0170] y1=1 is the symbol of the third part of the delay correction implementation. In the embodiment of the present invention, p=19.

[0171] In order to collect the TDO return data after delay correction, a new array Z needs to be set. The length of array Z is (2a).

[0172] Z=[z1,z2,z3,z4,...,z(a-1),za,z(a+1),z(a+2),z(a+3),z(a+4),...,z(2a-1),z(2 a)], the value of the initial state array, z1=1, z2=z3=z4...=za=0, z(a+1)=z(a+2)=z(a+3)=z(a+4)...=z(2a)=0,

[0173] Part 3 of the delay self-correction follows Part 2.

[0174] In step 2a+p+1, when the rising edge of the 2a+p+1 system clock is detected, Z=[1,0,0,0,...,0,0,0,0,0,0,...,0,0]. Since z1=1, the correct TDO return data after the first bit of delay correction is collected (such as Figure 5 In the process of collecting TDO data in the middle of the TDO data waveform), the assignment operation is then performed, z1=z2, z2=s3, z3=z4, ...z(2a-1)=z(2a), z(2a)=z1,

[0175] In step 2a+p+2, when the rising edge of the 2a+p+2 system clock is detected, Z=[0,0,0,0,...,0,0,0,0,0,0,...,1,0]. Since z1=0, TDO return data is not collected at this time, and then the assignment operation is performed, z1=z2, z2=z3, z3=z4, ...z(2a-1)=z(2a), z(2a)=z1,

[0176] And so on…

[0177] In step 2a+p+a, when the rising edge of the 2a+p+a system clock is detected, Z=[0,0,0,0,...,0,1,0,0,0,0,...,0,0]. Since z1=0, the TDO return data is not collected at this time, and the assignment operation is still performed, z1=z2, z2=z3, z3=z4, ...z(2a-1)=z(2a), z(2a)=z1,

[0178] And so on…

[0179] In step 2a+p+2a, when the rising edge of the 2a+p+2a system clock is detected, Z=[0,1,0,0,...,0,0,0,0,0,0,...,0,0]. Since z1=0, the TDO return data is not collected at this time, and the assignment operation is still performed, z1=z2, z2=z3, z3=z4, ...z(2a-1)=z(2a), z(2a)=z1,

[0180] In step 2a+p+2a+1, when the rising edge of the 2a+p+2a+1 system clock is detected, Z=[1,0,0,0,...,0,0,0,0,0,0,...,0,0], since z1=1, the correct TDO return data after the second bit delay correction is collected, and then the assignment operation is performed, z1=z2, z2=s3, z3=z4, z(2a-1)=z(2a), z(2a)=z1;

[0181] And so on...

[0182] Every 2a step, the correct TDO return data after 1-bit delay correction is collected, corresponding to Figure 5 The first TDO signal is generated, and TDO data is collected at the middle position of the TDO waveform, which cleverly overcomes the delay of TDO and achieves the effect of delay self-correction. In this embodiment of the present invention, p=19 and a=200.

[0183] Every 2a steps, collect 1 bit of correct TDO return data after delay correction, set a new array W, W = [w1, w2, w3, w4, ... wq], assign each bit of TDO data collected after delay correction to w1, w2, w3, w4, ... wq in turn, the length q is determined according to the actual length of data to be sent, taking the IDcode data expected by the present invention as an example, q = 32, assign these collected correct TDO return data after delay correction in turn, and get:

[0184] W=[1,0,1,1,1,0,1,1,0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,0,0,1,1,0,0,0,0,0,0], the left-right order of the internal data of array W is opposite to the left-right order of the expected IDcode data. The above realizes the JTAG delay self-correction of boundary scan test.

[0185] like Figure 6 As shown in the figure, it is a system block diagram of JTAG delay self-correction. Figures 1 to 6 As shown, the JTAG delay self-correction of chain 1 of the embodiment of the present invention is realized above. The model of a single chip in chain 1 is: 10M25DAF484I7G. The IDcode instruction and expected IDcode data of the embodiment of the present invention correspond to this model. The delay self-correction of BS chain 1 can be completed through the delay self-correction button of test port 1 on the host computer interface.

[0186] Similarly, the delay self-calibration of BS chain 1 can be completed through the delay self-calibration button of test port 2 on the host computer interface. The method is the same as above. Test port 1 and test port 2 complete the delay self-calibration of their respective channels independently without affecting each other.

[0187] In addition to realizing the BS chain self-calibration of each test port by a key, the present invention can also realize automatic delayed self-calibration by detecting power-on, and the method is the same as that of replacing the triggering of a key by power-on.

[0188] The present invention combines the system clock to operate the TCK clock frequency of the boundary scan chain at 500kHz, first automatically obtains p system clock delays, and then, in the actual boundary scan test process, can flexibly perform JTAG delay correction on the boundary scan test with a TCK frequency of 500kHz to 25MHz according to the p system clock delays, and achieves the effect of self-correcting the delay of the boundary scan chain through the host computer with one key, and the JTAG delay data p is automatically obtained in the system, and there is no need to obtain the delay outside the system for correction. The delay self-correction of multiple test ports is performed independently, which significantly improves the signal test rate and signal stability, significantly improves the convenience of delay correction, and reduces the operational difficulty of system delay correction.

[0189] To achieve the above object, the present invention also provides a JTAG delay self-correction processing system for boundary scan testing, such as Figure 8 As shown, the system is applied to the JTAG delay self-correction processing method for boundary scan testing, and the system includes:

[0190] A first data generating unit, configured to generate and obtain first data corresponding to a JTAG delay correction process to be performed in a boundary scan test system; wherein the first data is JTAG signal data, including clock signal data, state signal data, input signal data and return signal data;

[0191] A second data generating unit, configured to generate second data corresponding to the boundary scan test system according to the first data; wherein the second data is delay data in the boundary scan test system;

[0192] The delay correction processing unit is used for real-time self-correction of the data delay state in the boundary scan test system based on the second data.

[0193] The first data generating unit further includes:

[0194] A first generating module is used to generate and obtain third data corresponding to the clock signal of the boundary scan test system, and generate corresponding first level data according to the third data, and flip the first level data; wherein the third data is the clock rising edge data of the boundary scan test system; the first level data is the level data corresponding to the third data and subjected to value assignment processing;

[0195] A second generating module is used to generate and obtain fourth data corresponding to the state signal of the boundary scan test system, and generate corresponding second level data according to the fourth data; wherein the fourth data is the clock rising edge data of the boundary scan test system; and the second level data is the level data corresponding to the fourth data and after the assignment processing;

[0196] A third generating module is used to generate and obtain fifth data corresponding to the input signal of the boundary scan test system, and generate corresponding third level data according to the fifth data; wherein the fifth data is the clock rising edge data or the clock falling edge data of the boundary scan test system; and the third level data is the level data corresponding to the fifth data and having been processed by the assignment process;

[0197] And / or, the second data generating unit further includes:

[0198] The first processing module is used to sequentially arrange and process the boundary register units of the boundary register of the boundary scan chip in the boundary scan chain; wherein the first and last boundary register units are TDI input and TDO output respectively; and the TDI signal is input to the boundary scan chain;

[0199] And / or, the delay correction processing unit further includes:

[0200] A second processing module is used to generate and obtain seventh data corresponding to the return signal of the boundary scan test system, and generate corresponding fourth level data according to the seventh data; wherein the seventh data is the rising edge data of the boundary scan test system clock; and the fourth level data is the level data corresponding to the seventh data and after the assignment processing;

[0201] The third processing module is used to generate eighth data corresponding to the boundary scan test system based on the fourth level data, and to assign values ​​to process the eighth data in sequence in combination with the sent data length status; wherein the eighth data is the return signal data after delay correction.

[0202] The second data generating unit further includes:

[0203] a fourth processing module, configured to generate and obtain first instruction data corresponding to the boundary scan chip, and sequentially send and process the first instruction data, and serially shift the first instruction data to a corresponding instruction register;

[0204] The fourth generating module is used to generate and obtain sixth data corresponding to the boundary scan test system, and generate second data corresponding to the boundary scan test system according to the sixth data; wherein the sixth data is clock frequency data.

[0205] In the system solution embodiment of the present invention, the method steps involved in the JTAG delay self-correction processing for boundary scan testing have been described above in detail, that is, the functional modules in the system are used to implement the steps or sub-steps in the above method embodiment, which will not be repeated here.

[0206] To achieve the above object, the present invention also provides a JTAG delay self-correction processing platform for boundary scan testing, such as Fig. 9 As shown, it includes a processor, a memory, and a JTAG delay self-correction processing platform control program for boundary scan testing; wherein, the JTAG delay self-correction processing platform control program for boundary scan testing is executed in the processor, the JTAG delay self-correction processing platform control program for boundary scan testing is stored in the memory, and the JTAG delay self-correction processing platform control program for boundary scan testing implements the steps of the JTAG delay self-correction processing method for boundary scan testing. For example:

[0207] S01, generating and acquiring first data corresponding to a JTAG delay correction process to be processed in a boundary scan test system; wherein the first data is JTAG signal data, including clock signal data, state signal data, input signal data and return signal data;

[0208] S02. Generate second data corresponding to a boundary scan test system according to the first data; wherein the second data is delay data in the boundary scan test system;

[0209] S03. Based on the second data, perform real-time self-correction on the data delay state in the boundary scan test system.

[0210] The specific details of the steps have been explained above and will not be repeated here.

[0211] In the embodiment of the present invention, the built-in processor of the JTAG delay self-correction processing platform for boundary scan test can be composed of integrated circuits, for example, can be composed of a single packaged integrated circuit, or can be composed of multiple integrated circuits with the same or different functions, including one or more central processing units (CPU), microprocessors, digital processing chips, graphics processors and various control chips. The processor uses various interfaces and lines to connect various components, and executes various functions and processes data of the JTAG delay self-correction processing for boundary scan test by running or executing programs or units stored in the memory, and calling data stored in the memory;

[0212] The memory is used to store program codes and various data. It is installed in the JTAG delay self-correction processing platform used for boundary scan testing, and realizes high-speed and automatic access to programs or data during operation.

[0213] The memory includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electronically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0214] The present invention generates and obtains first data corresponding to the JTAG delay correction processing in the boundary scan test system through a method; wherein the first data is JTAG signal data, including clock signal data, state signal data, input signal data and return signal data; according to the first data, second data corresponding to the boundary scan test system is generated; wherein the second data is the delay data in the boundary scan test system; based on the second data, the data delay state in the boundary scan test system is processed by real-time self-correction, and the self-correction function can be realized, that is, when the application personnel use the product, there is no need to obtain the delay, and only one key is needed to perform delay correction on the BS chain through the host computer.

[0215] In other words, the solution of the present invention does not require delay acquisition outside the system for correction; the delay self-correction of multiple test ports is performed independently, which significantly improves the signal test rate and signal stability, significantly improves the convenience of delay correction, and reduces the operational difficulty of system delay correction.

[0216] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A JTAG delay self-correction processing method for boundary scan testing, characterized in that: The method comprises: Generate and obtain first data corresponding to a JTAG delay correction process to be performed in a boundary scan test system; wherein the first data is JTAG signal data, including clock signal data, status signal data, input signal data and return signal data; generating second data corresponding to a boundary scan test system according to the first data; wherein the second data is delay data in the boundary scan test system; Based on the second data, a data delay state in the boundary scan test system is processed by real-time self-correction.

2. A JTAG delay self-correction processing method for boundary scan testing according to claim 1, characterized in that: The generating and acquiring first data corresponding to the JTAG delay correction process to be processed in the boundary scan test system also includes: Generate and acquire third data corresponding to the clock signal of the boundary scan test system, generate corresponding first level data according to the third data processing, and flip the first level data; wherein the third data is the clock rising edge data of the boundary scan test system; the first level data is the level data corresponding to the third data and subjected to value assignment processing; Generate and acquire fourth data corresponding to the state signal of the boundary scan test system, and generate corresponding second level data according to the fourth data; wherein the fourth data is the clock rising edge data of the boundary scan test system; the second level data is the level data corresponding to the fourth data and after the assignment processing; Generate and obtain fifth data corresponding to the input signal of the boundary scan test system, and generate corresponding third level data according to the fifth data processing; wherein the fifth data is the clock rising edge data or the clock falling edge data of the boundary scan test system; the third level data is the level data corresponding to the fifth data and has been assigned a value.

3. A JTAG delay self-correction processing method for boundary scan testing according to claim 1, characterized in that: The step of generating second data corresponding to the boundary scan test system according to the first data further includes: The boundary register units of the boundary register of the boundary scan chip in the boundary scan chain are arranged sequentially; wherein the head and the tail of the boundary register unit are TDI input and TDO output respectively; and the TDI signal is input to the boundary scan chain.

4. A JTAG delay self-correction processing method for boundary scan testing according to claim 1 or 3, characterized in that: The step of generating second data corresponding to the boundary scan test system according to the first data further includes: Generate and obtain first instruction data corresponding to the boundary scan chip, send and process the first instruction data in sequence, and serially shift the first instruction data to the corresponding instruction register; Generate and acquire sixth data corresponding to the boundary scan test system, and generate second data corresponding to the boundary scan test system according to the sixth data; wherein the sixth data is clock frequency data.

5. The JTAG delay self-correction processing method for boundary scan testing according to claim 1, characterized in that: The real-time self-correction processing of the data delay state in the boundary scan test system based on the second data also includes: Generate and obtain seventh data corresponding to the return signal of the boundary scan test system, and generate corresponding fourth level data according to the seventh data; wherein the seventh data is the rising edge data of the boundary scan test system clock; and the fourth level data is the level data corresponding to the seventh data and after the assignment processing; Based on the fourth level data, eighth data corresponding to the boundary scan test system is generated, and combined with the sent data length status, the eighth data is assigned and processed in sequence; wherein the eighth data is the return signal data after delay correction.

6. A JTAG delay self-correction processing system for boundary scan testing, characterized in that: The system is applied to the JTAG delay self-correction processing method for boundary scan testing as claimed in any one of claims 1 to 5, and the system comprises: A first data generating unit, configured to generate and obtain first data corresponding to a JTAG delay correction process to be performed in a boundary scan test system; wherein the first data is JTAG signal data, including clock signal data, state signal data, input signal data and return signal data; A second data generating unit, configured to generate second data corresponding to the boundary scan test system according to the first data; wherein the second data is delay data in the boundary scan test system; The delay correction processing unit is used for real-time self-correction of the data delay state in the boundary scan test system based on the second data.

7. A JTAG delay self-correction processing system for boundary scan testing according to claim 6, characterized in that: The first data generating unit further includes: A first generating module is used to generate and obtain third data corresponding to the clock signal of the boundary scan test system, and generate corresponding first level data according to the third data, and flip the first level data; wherein the third data is the clock rising edge data of the boundary scan test system; the first level data is the level data corresponding to the third data and subjected to value assignment processing; A second generating module is used to generate and obtain fourth data corresponding to the state signal of the boundary scan test system, and generate corresponding second level data according to the fourth data; wherein the fourth data is the clock rising edge data of the boundary scan test system; and the second level data is the level data corresponding to the fourth data and after the assignment processing; A third generating module is used to generate and obtain fifth data corresponding to the input signal of the boundary scan test system, and generate corresponding third level data according to the fifth data; wherein the fifth data is the clock rising edge data or the clock falling edge data of the boundary scan test system; and the third level data is the level data corresponding to the fifth data and having been processed by the assignment process; And / or, the second data generating unit further includes: The first processing module is used to sequentially arrange and process the boundary register units of the boundary register of the boundary scan chip in the boundary scan chain; wherein the first and last boundary register units are TDI input and TDO output respectively; and the TDI signal is input to the boundary scan chain; And / or, the delay correction processing unit further includes: A second processing module is used to generate and obtain seventh data corresponding to the return signal of the boundary scan test system, and generate corresponding fourth level data according to the seventh data; wherein the seventh data is the rising edge data of the boundary scan test system clock; and the fourth level data is the level data corresponding to the seventh data and after the assignment processing; The third processing module is used to generate eighth data corresponding to the boundary scan test system based on the fourth level data, and to assign values ​​to process the eighth data in sequence in combination with the sent data length status; wherein the eighth data is the return signal data after delay correction.

8. A JTAG delay self-correction processing system for boundary scan testing according to claim 6 or 7, characterized in that: The second data generating unit further includes: a fourth processing module, configured to generate and obtain first instruction data corresponding to the boundary scan chip, and sequentially send and process the first instruction data, and serially shift the first instruction data to a corresponding instruction register; The fourth generating module is used to generate and obtain sixth data corresponding to the boundary scan test system, and generate second data corresponding to the boundary scan test system according to the sixth data; wherein the sixth data is clock frequency data.

9. A JTAG delay self-correction processing platform for boundary scan testing, characterized in that: The invention comprises a processor, a memory and a JTAG delay self-correction processing platform control program for boundary scan test; wherein the JTAG delay self-correction processing platform control program for boundary scan test is executed by the processor, the JTAG delay self-correction processing platform control program for boundary scan test is stored in the memory, and the JTAG delay self-correction processing platform control program for boundary scan test implements the JTAG delay self-correction processing method for boundary scan test as described in any one of claims 1 to 5.

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