Code updating method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a code updating method and device, electronic equipment, a chip and a storage medium, and relates to the technical field of data processing.The method comprises the steps that at least one target sub-graph is determined from a directed acyclic graph associated with a to-be-updated program; the target sub-graph comprises at least two adjacent logical operation nodes; determining a plurality of to-be-fused instructions corresponding to any target sub-graph from the to-be-updated program; fusing the plurality of to-be-fused instructions corresponding to any target directed acyclic sub-graph to obtain a target fusion instruction corresponding to any target sub-graph; and updating the to-be-updated program by adopting the target fusion instruction corresponding to each target sub-graph to obtain a target program code. Therefore, by constructing the directed acyclic graph associated with the to-be-updated program, identifying the target sub-graph in the directed acyclic graph and merging the to-be-fused instructions corresponding to the target sub-graph in the to-be-updated program, the number of the instructions can be reduced, program codes can be remarkably optimized, the execution efficiency can be improved, and resource consumption can be reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a code updating method, device, electronic device, chip and storage medium. Background Art

[0002] With the continuous advancement of processor technology, instruction fusion, as an efficient optimization method, can reduce the cycles required for the processor to execute instructions and significantly improve code execution efficiency. Since the code structure has changed after instruction fusion, the original instruction sequence is replaced by a new compound instruction, which may cause the logic and dependencies of the original code to change. Therefore, after completing instruction fusion, the program code needs to be updated accordingly to ensure that the updated code can be executed correctly and efficiently. Summary of the invention

[0003] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the present application proposes a code updating method, device, electronic device, chip and storage medium, so as to realize the merging of multiple instructions to be merged corresponding to the target subgraph in the program to be updated by constructing a directed acyclic graph associated with the program to be updated and identifying the target subgraph in the directed acyclic graph, and finally updating the program to be updated with the fused target instructions, thereby realizing the merging of multiple instructions in the program to be updated, thereby reducing the number of instructions, significantly optimizing the program code, improving execution efficiency and reducing resource consumption.

[0005] In one aspect, an embodiment of the present application provides a code update method, including:

[0006] Determine at least one target subgraph from a directed acyclic graph associated with the program to be updated; wherein the nodes in the directed acyclic graph include a plurality of operand nodes and operation nodes, the edges between the nodes are used to indicate the dependency relationship between the nodes, and the target subgraph includes at least two adjacent logic operation nodes;

[0007] Determine, from the program to be updated, a plurality of instructions to be merged corresponding to any target subgraph;

[0008] Fusing a plurality of instructions to be fused corresponding to any target directed acyclic subgraph to obtain a target fusion instruction corresponding to any target subgraph;

[0009] The target fusion instructions corresponding to each of the target subgraphs are used to update the program to be updated to obtain the target program code.

[0010] Another aspect of the present application provides a code updating device, including:

[0011] A first determination module is used to determine at least one target subgraph from a directed acyclic graph associated with the program to be updated; wherein the nodes in the directed acyclic graph include a plurality of operand nodes and operation nodes, the edges between the nodes are used to indicate the dependency relationship between the nodes, and the target subgraph includes at least two adjacent logic operation nodes;

[0012] A second determination module is used to determine a plurality of instructions to be merged corresponding to any target subgraph from the program to be updated;

[0013] A fusion module, used for fusing a plurality of instructions to be fused corresponding to any target directed acyclic subgraph to obtain a target fusion instruction corresponding to any target subgraph;

[0014] An updating module is used to update the program to be updated by using the target fusion instructions corresponding to each of the target subgraphs to obtain a target program code.

[0015] Another aspect of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the code updating method as described in the aforementioned aspect is implemented.

[0016] Another aspect of the present application provides a chip, which includes an interface circuit and a processing circuit coupled to each other, wherein the interface circuit is used to input or output a signal, and the processing circuit is configured to execute the code update method as described in the aforementioned aspect.

[0017] Another aspect of the present application provides a non-temporary computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the code updating method as described in the aforementioned aspect.

[0018] Another aspect of the present application provides a computer program product on which a computer program is stored, and when the program is executed by a processor, the code updating method as described in the above aspect is implemented.

[0019] The code updating method, device, electronic device, chip and storage medium proposed in the present application extract a target subgraph containing at least two adjacent logical operation nodes from a directed acyclic graph associated with the program to be updated, and fuse the instructions to be fused corresponding to these target subgraphs, and finally update the program code with the fused target instructions, thereby realizing the merging of multiple instructions in the program to be updated, thereby reducing the number of instructions, significantly optimizing the program code, improving execution efficiency, and reducing resource consumption.

[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1 This is a schematic diagram of the implementation principle of instruction fusion;

[0023] Figure 2 A flowchart of the first code updating method provided in the embodiment of the present application;

[0024] Figure 3 A schematic diagram of a directed acyclic graph provided in an embodiment of the present application;

[0025] Figure 4 A flowchart of a second code updating method provided in an embodiment of the present application;

[0026] Figure 5 A flowchart of a third code updating method provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of the structure of a code updating device provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0029] Figure 8 It is a schematic diagram of the structure of a chip proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0030] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0031] In the related art, programmers are allowed to insert LOP3 instructions (a three-input logic operation instruction) into the code to replace the basic logic operation instruction, so as to reduce the number of instructions and optimize program performance. LOP3 instructions have one output (Output), three input operands (Input Operand) and one function operand (Function Operand), and are equipped with a truth table. The function operand determines the logical mapping relationship that the instruction queries from the truth table, so that the programmer can implement any logic operation by configuring the function operand. The execution steps of LOP3 instructions are as follows: Figure 1 As shown, this solution only relies on programmers' own observation and manual insertion of LOP3 instructions, and its generalization ability is insufficient.

[0032] In response to the above problems, the present application further proposes a code updating method, device, electronic device, chip and storage medium.

[0033] The following describes the code updating method, device, electronic device, chip and storage medium of the embodiments of the present application with reference to the accompanying drawings.

[0034] Figure 2 A flowchart of the first code updating method provided in an embodiment of the present application.

[0035] The embodiment of the present application takes the code updating method configured in a code updating device as an example. The code updating device can be applied to any electronic device with computing capability so that the electronic device can perform a code updating function.

[0036] Among them, the electronic devices can be mobile terminals, Internet of Things (IoT) devices, etc. Mobile terminals are, for example, vehicle-mounted devices, mobile phones, watches, wearable devices, tablet computers, personal digital assistants and other hardware devices with various operating systems.

[0037] In any embodiment of the present application, the code updating method may be executed by a chip, such as a code updating chip.

[0038] In any embodiment of the present application, the chip can be integrated into electronic devices such as mobile terminals and watches.

[0039] like Figure 2 As shown, the code updating method may include the following steps S201 to S204:

[0040] Step S201: determining at least one target subgraph from a directed acyclic graph associated with the program to be updated.

[0041] The nodes in the directed acyclic graph include multiple operand nodes and operation nodes, the edges between the nodes are used to indicate the dependency relationship between the nodes, and the target subgraph includes at least two adjacent logic operation nodes.

[0042] In an embodiment of the present application, a directed acyclic graph is created based on multiple operands in the program to be updated and the dependencies between the multiple operands, wherein the nodes in the directed acyclic graph include multiple operand nodes and operation nodes, and the edges between the nodes are used to indicate the dependencies between the multiple operands. The dependency relationship includes an operation relationship, such as a logical operation, or other mathematical operations.

[0043] In the embodiment of the present disclosure, the program to be updated may be referred to as a program to be processed.

[0044] As an example, the program to be updated is scanned to obtain multiple operands and dependencies between the multiple operands in the program to be updated, and then a directed acyclic graph is created according to the multiple operands and the dependencies between the multiple operands.

[0045] That is to say, the program to be updated is scanned to identify multiple operands and dependencies between the multiple operands in the program to be updated, and then, based on the multiple operands and the dependencies between the multiple operands, a directed acyclic graph (DAG) is created, wherein the nodes of the directed acyclic graph include operands or operation operators, and the edges between the nodes are used to indicate the dependencies between the nodes.

[0046] For example, Figure 3 As shown in the figure, assume that there are three operands a, b, and c in the program to be updated; first, an AND operation is performed between a and b, the result is ORed with c, and the result is XORed with a to obtain the final result. Based on the dependency relationship between a, b, and c, create Figure 3 The directed acyclic graph shown.

[0047] In an embodiment of the present application, a directed acyclic graph is traversed to identify candidate subgraphs containing at least two adjacent logic operation nodes, and a target subgraph that meets the set conditions is screened out from the candidate subgraphs. Adjacent logic operation nodes refer to two logic operation nodes that are directly connected by a directed edge in the DAG. For example, in the DAG, if the output of an "and" node is used as the input of an "or" node, then the two nodes are adjacent.

[0048] Step S202: Determine, from the program to be updated, a plurality of instructions to be merged corresponding to any target subgraph.

[0049] In an embodiment of the present application, each node in the DAG corresponds to an operation or instruction in the program to be updated, and the edge represents the dependency relationship between the nodes. According to the logical operation nodes in the target subgraph, the corresponding logical operation instructions in the program to be updated are found, and the logical operation instructions are used as instructions to be fused.

[0050] For example, if the target subgraph contains two adjacent logic operation nodes "and" and "or", find the corresponding "and" and "or" instructions from the program to be updated, and use the corresponding "and" and "or" instructions as instructions to be fused.

[0051] Step S203, fusing multiple instructions to be fused corresponding to any target directed acyclic subgraph to obtain a target fused instruction corresponding to any target subgraph.

[0052] Furthermore, multiple instructions to be fused are merged into a compound instruction, and the compound instruction is used as a target fusion instruction.

[0053] Step S204: update the program to be updated using the target fusion instructions corresponding to each target subgraph to obtain the target program code.

[0054] Furthermore, the target fusion instructions corresponding to each target subgraph are used to replace the original multiple logic operation instructions in the program to be processed with the generated target fusion instructions corresponding to each target subgraph, ensuring that the operands and outputs of the target fusion instructions are consistent with the original logic operation instructions to ensure semantic correctness.

[0055] The code updating method of the embodiment of the present application extracts a target subgraph containing at least two adjacent logical operation nodes from a directed acyclic graph, and fuses the instructions to be fused corresponding to these target subgraphs, and finally updates the program code with the fused target instructions, thereby merging multiple instructions in the program to be updated, thereby reducing the number of instructions, significantly optimizing the program code, improving execution efficiency, and reducing resource consumption.

[0056] It should be noted that in the technical solution of this application, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are all carried out with the user's consent, and are in compliance with relevant laws and regulations and do not violate public order and good morals.

[0057] This application embodiment provides another code update method. Figure 4 A flowchart of the second code updating method provided in an embodiment of the present application.

[0058] It should be noted that the code update method can be executed alone, or it can be executed in combination with any embodiment of the present application or a possible implementation method in the embodiment, or it can be executed in combination with any technical solution in the related technology, and the embodiments of the present application are not limited to this.

[0059] like Figure 4 As shown, the code updating method may include the following steps S401 to S405:

[0060] Step S401, extracting multiple candidate subgraphs from a directed acyclic graph.

[0061] The candidate subgraph includes at least two adjacent logic operation nodes.

[0062] In an embodiment of the present application, a directed acyclic graph associated with the program to be updated is traversed to find at least two adjacent logical operation nodes, and these nodes and the edges therebetween are extracted to form a candidate subgraph. The nodes in the directed acyclic graph include a plurality of operand nodes and operation operation nodes, and the edges are used to indicate the dependency relationship between the nodes.

[0063] Step S402: determining at least one target subgraph from multiple candidate subgraphs according to the number and in-degree of logic operation nodes in each candidate subgraph.

[0064] In order to ensure that the fused instructions can not only reduce the number of instructions but also improve parallelism and execution efficiency, in an embodiment of the present application, the number of logical operation nodes and the in-degree of the nodes in each candidate subgraph are comprehensively considered, and a target subgraph is determined from multiple candidate subgraphs.

[0065] As an example, reasonable weights are set for the number and in-degree of logical operation nodes, and the comprehensive score of each candidate subgraph is calculated. Then, the candidate subgraph with the highest score or the top score is selected as the target subgraph.

[0066] As another example, for any candidate subgraph, the first running cost of multiple candidate instructions corresponding to any candidate subgraph is determined based on the number of logical operation nodes in any candidate subgraph; the second running cost of the fused instruction after fusing the multiple candidate instructions is determined based on the in-degree of each logical operation node in any candidate subgraph; and at least one target subgraph is determined from the multiple candidate subgraphs based on the first running cost and the second running cost corresponding to each candidate subgraph.

[0067] That is to say, for any candidate subgraph, traverse the candidate subgraph to determine the number of logic operation nodes in the candidate subgraph, wherein the logic operation node represents the logic operation to be executed in the program to be processed, such as and, or, not, etc. The number of logic operation nodes directly reflects the basic amount of operation required to execute the target subgraph. Therefore, the first running cost of multiple candidate instructions corresponding to the candidate subgraph can be estimated according to the number of logic operation nodes; wherein the first running cost is proportional to the number of logic operation nodes, and the more the number of logic operation nodes, the more resources and time required for execution; then, obtain the in-degree of each logic operation node in any candidate subgraph, wherein the in-degree is the number of edges pointing to the logic operation node, which reflects the number of inputs that the logic operation node depends on. If multiple logic operation nodes can be fused to reduce input dependence or simplify data flow, then the fused instruction has a lower running cost. Therefore, the second running cost of the fused instruction is evaluated according to the in-degree of each node in the candidate subgraph; then, by comparing the first running cost and the second running cost corresponding to each candidate subgraph, at least one target subgraph is determined. For example, when the first running cost of any candidate subgraph is greater than the second running cost, any candidate subgraph is used as the target subgraph.

[0068] It should be noted that the steps for determining the second running cost are as follows:

[0069] (1) Traverse the logical operation nodes in any candidate subgraph in turn and determine the in-degree of each logical operation node;

[0070] (2) determining a target logic operation node from among the logic operation nodes according to the in-degree of each logic operation node; wherein the in-degree of the target logic operation node is greater than a specified number (e.g., 1);

[0071] (3) According to the number of target logic operation nodes, the initial running cost is updated to obtain a second running cost.

[0072] For example, continuing with Figure 3 For example, Figure 3 The number of logical operation nodes (and, or and xor) is 3, the first running cost CostPre=3, the initial running cost is 1, that is, CostPost=1, and the number of logical operation nodes with in-degree greater than 1 in the logical operation nodes is 1, then the initial running cost is updated to obtain CostPost=2, that is, every time a logical operation node with in-degree greater than 1 is traversed, CostPost is automatically increased by 1.

[0073] Step S403: determining a plurality of instructions to be merged corresponding to any target subgraph from the program to be updated.

[0074] Step S404, fusing multiple instructions to be fused corresponding to any target directed acyclic subgraph to obtain a target fused instruction corresponding to any target subgraph.

[0075] Step S405 , using the target fusion instructions corresponding to each target subgraph to update the program to be updated, so as to obtain the target program code.

[0076] It should be noted that the explanation of steps S403 to S405 can be found in the relevant description in any embodiment of the present application and will not be repeated here.

[0077] The code updating method of the embodiment of the present application extracts multiple candidate subgraphs from a directed acyclic graph, and determines at least one target subgraph from the multiple candidate subgraphs according to the number and in-degree of logic operation nodes in each candidate subgraph. Thus, a comprehensive evaluation method based on the number and in-degree of logic operation nodes is implemented to select candidate subgraphs containing more logic operation nodes and higher in-degree for optimization, thereby improving the generalization capability of instruction fusion, reducing the number of instructions, reducing instruction scheduling overhead, and optimizing resource utilization.

[0078] This application embodiment provides another code update method. Figure 5 A flowchart of the third code updating method provided in an embodiment of the present application.

[0079] It should be noted that the code update method can be executed alone, or it can be executed in combination with any embodiment of the present application or a possible implementation method in the embodiment, or it can be executed in combination with any technical solution in the related technology, and the embodiments of the present application are not limited to this.

[0080] like Figure 5 As shown, the code updating method may include the following steps S501 to S506:

[0081] Step S501, performing a reverse post-order traversal on the directed acyclic graph to obtain a plurality of candidate node sequences.

[0082] Among them, the nodes in the directed acyclic graph include multiple operand nodes and operation nodes, the edges between the nodes are used to indicate the dependency relationship between the nodes, and the candidate node sequence includes at least three operand nodes and at least two logical operation nodes other than the at least three operand nodes.

[0083] In order to generate a node sequence that reflects the node dependency, a directed acyclic graph (DAG) is traversed in reverse order. During the reverse order traversal, not only the traversal order of the nodes is taken into consideration, but also the type and number of nodes. Each candidate node sequence must meet the following conditions: at least three operand nodes (representing data or constants) and at least two logical operation nodes (performing logical operations such as AND, OR, and NOT). It should be noted that the reverse order traversal of the directed acyclic graph ensures that during the traversal, if there is an edge from node (u) to node (v), (v) will be visited before (u), so that the result of the reverse order traversal is a topological sort, that is, each node appears after all its predecessor nodes, which can clearly express the dependency relationship between nodes.

[0084] Step S502: extracting candidate subgraphs matching each candidate node sequence from the directed acyclic graph.

[0085] Furthermore, for each candidate node sequence, the corresponding nodes and the edges between them are extracted to form a candidate subgraph, wherein the candidate subgraph not only includes at least three operand nodes and at least two logical operation nodes, but also retains some nodes and connection relationships in the original DAG.

[0086] Step S503: determining at least one target subgraph from multiple candidate subgraphs according to the number and in-degree of logic operation nodes in each candidate subgraph.

[0087] Step S504: determining a plurality of instructions to be merged corresponding to any target subgraph from the program to be updated.

[0088] Step S505 , fusing multiple instructions to be fused corresponding to any target directed acyclic subgraph to obtain a target fused instruction corresponding to any target subgraph.

[0089] Step S506 , using the target fusion instructions corresponding to each target subgraph to update the program to be updated, so as to obtain the target program code.

[0090] It should be noted that the explanation of steps S503 to S506 can be found in the relevant description in any embodiment of the present application and will not be repeated here.

[0091] The code updating method of the embodiment of the present application performs a reverse post-order traversal on a directed acyclic graph to obtain multiple candidate node sequences, and extracts candidate subgraphs matching each candidate node sequence from the directed acyclic graph. Thus, by performing a reverse post-order traversal on the directed acyclic graph and extracting candidate subgraphs from the directed acyclic graph based on the obtained node sequences, the correctness of the dependency relationship between nodes can be ensured; at the same time, by constructing candidate subgraphs, redundant instructions can be reduced and the processing process can be simplified.

[0092] As an example, the implementation principle of the code update solution provided in this application mainly includes the following steps:

[0093] Step 1: Scan the input program code (program to be updated) and construct a directed acyclic graph;

[0094] Step 2: Traverse the directed acyclic graph in reverse order and recursively find a pattern (candidate subgraph) through depth-first search: it has three operands, and all nodes in the pattern except the operands are logical operation instructions;

[0095] Step 3: Calculate and compare the running cost before and after fusion:

[0096] (1) Assume that the number of logical operations of Pattern before fusion is N;

[0097] (2) Let the running cost of Pattern before fusion be CostPre (first running cost), and the running cost after fusion be CostPost (second running cost). Before the calculation starts, CostPre = N, CostPost = 1;

[0098] (3) Traverse each logical operation node in the fusion pattern, and when encountering a node with an in-degree greater than 1, increase CostPost by 1;

[0099] (4) After the traversal is completed, CostPre and CostPost are compared. If CostPre<=CostPost, the fusion operation is not continued on the current Pattern; otherwise, if CostPre>CostPost, the current Pattern is the Pattern output by this technical solution (target subgraph) and can be further fused into LOP;

[0100] Step 4: Use the fused LOP to replace instructions in the program code to implement code update.

[0101] In summary, based on the directed acyclic graph, we search for the logical operation pattern (target subgraph) that meets the fusion conditions in the program code with good generalization ability, fuse the instructions to be fused corresponding to the target subgraph, and finally update the program code with the fused target instructions, thereby realizing the merging of multiple instructions in the program to be updated, thereby reducing the number of instructions, significantly optimizing the program code, improving execution efficiency, and reducing resource consumption.

[0102] In order to implement the above embodiment, the embodiment of the present application also proposes a code updating device.

[0103] Figure 6 A schematic diagram of the structure of a code updating device provided in an embodiment of the present application.

[0104] like Figure 6 As shown, the code updating device 600 may include: a first determining module 610 , a second determining module 620 , a fusion module 630 and an updating module 640 .

[0105] A first determination module 610 is used to determine at least one target subgraph from a directed acyclic graph associated with the program to be updated; wherein the nodes in the directed acyclic graph include a plurality of operand nodes and operation nodes, the edges between the nodes are used to indicate the dependency relationship between the nodes, and the target subgraph includes at least two adjacent logic operation nodes;

[0106] A second determination module 620 is used to determine a plurality of instructions to be merged corresponding to any target subgraph from the program to be updated;

[0107] A fusion module 630 is used to fuse multiple instructions to be fused corresponding to any target directed acyclic subgraph to obtain a target fusion instruction corresponding to any target subgraph;

[0108] The updating module 640 is used to update the program to be updated by using the target fusion instructions corresponding to each target subgraph to obtain the target program code.

[0109] Furthermore, in an implementation of an embodiment of the present application, the first determination module 610 is specifically used to extract multiple candidate subgraphs from a directed acyclic graph; wherein the candidate subgraphs include at least two adjacent logical operation nodes; and according to the number and in-degree of the logical operation nodes in each candidate subgraph, determine at least one target subgraph from the multiple candidate subgraphs.

[0110] In one implementation of the embodiment of the present application, the first determination module 610 is specifically used to determine, for any candidate subgraph, a first running cost of multiple candidate instructions corresponding to any candidate subgraph according to the number of logical operation nodes in any candidate subgraph; determine a second running cost of a fused instruction after fusing multiple candidate instructions according to the in-degree of each logical operation node in any candidate subgraph; and determine at least one target subgraph from multiple candidate subgraphs according to the first running cost and the second running cost corresponding to each candidate subgraph.

[0111] In one implementation of the embodiment of the present application, the first determination module 610 is specifically used to traverse the logic operation nodes in any candidate subgraph in sequence to determine the in-degree of each logic operation node; determine the target logic operation node from each logic operation node according to the in-degree of each logic operation node; wherein the in-degree of the target logic operation node is greater than a specified number; and update the initial running cost according to the number of the target logic operation nodes to obtain a second running cost.

[0112] In an implementation of the embodiment of the present application, the first determination module 610 is specifically configured to use any candidate subgraph as a target subgraph in response to a first running cost of any candidate subgraph being greater than a second running cost.

[0113] In one implementation of an embodiment of the present application, the first determination module 610 is specifically used to perform a reverse post-order traversal on a directed acyclic graph to obtain multiple candidate node sequences; wherein the candidate node sequence includes at least three operand nodes and at least two logical operation nodes other than the at least three operand nodes; and extract a candidate subgraph matching each candidate node sequence from the directed acyclic graph.

[0114] In an implementation manner of the embodiment of the present application, the code updating device further includes: a creation module.

[0115] A module is created to scan the program to be updated to obtain multiple operands and dependencies between the multiple operands in the program to be updated; wherein the dependencies include logical operations and mathematical operations; and a directed acyclic graph is created based on the multiple operands and the dependencies between the multiple operands.

[0116] The code updating device proposed in the present application constructs a directed acyclic graph associated with the program to be updated, identifies the target subgraph of the directed acyclic graph, fuses multiple instructions to be merged corresponding to the target subgraph in the program to be updated, and finally updates the program to be updated with the fused target instructions, thereby merging multiple instructions in the program to be updated, thereby reducing the number of instructions, significantly optimizing the program code, improving execution efficiency, and reducing resource consumption.

[0117] In order to implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the code update method as described in any of the above embodiments is implemented.

[0118] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. For example, the electronic device 700 may be a vehicle, a mobile phone, a computer, a digital broadcast terminal, a message transceiver device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0119] Reference Figure 7 , the electronic device 700 may include one or more of the following components: a processing component 702 , a memory 704 , a power component 706 , a multimedia component 708 , an audio component 710 , an input / output (I / O) interface 712 , a sensor component 714 , and a communication component 716 .

[0120] The processing component 702 generally controls the overall operation of the electronic device 700, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 702 may include one or more processors 720 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 702 may include one or more modules to facilitate the interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate the interaction between the multimedia component 708 and the processing component 702.

[0121] The memory 704 is configured to store various types of data to support operations on the electronic device 700. Examples of such data include instructions for any application or method operating on the electronic device 700, contact data, phone book data, messages, pictures, videos, etc. The memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0122] The power component 706 provides power to the various components of the electronic device 700. The power component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 700.

[0123] The multimedia component 708 includes a screen that provides an output interface between the electronic device 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 708 includes a front camera and / or a rear camera. When the electronic device 700 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0124] The audio component 710 is configured to output and / or input audio signals. For example, the audio component 710 includes a microphone (MIC), and when the electronic device 700 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 704 or sent via the communication component 716. In some embodiments, the audio component 710 also includes a speaker for outputting audio signals.

[0125] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0126] The sensor assembly 714 includes one or more sensors for providing various aspects of status assessment for the electronic device 700. For example, the sensor assembly 714 can detect the open / closed state of the electronic device 700, the relative positioning of components, such as the display and keypad of the electronic device 700, and the sensor assembly 714 can also detect the position change of the electronic device 700 or a component of the electronic device 700, the presence or absence of user contact with the electronic device 700, the orientation or acceleration / deceleration of the electronic device 700, and the temperature change of the electronic device 700. The sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 714 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 714 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0127] The communication component 716 is configured to facilitate wired or wireless communication between the electronic device 700 and other devices. The electronic device 700 can access a wireless network based on a communication standard, such as WiFi, 4G or 5G, or a combination thereof. In an exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0128] In an exemplary embodiment, the electronic device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0129] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 704 including instructions, and the instructions can be executed by a processor 720 of an electronic device 700 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0130] In order to implement the above embodiments, the present application also proposes a chip, including: the chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to execute the code update method provided in any of the above embodiments.

[0131] Figure 8 Schematic diagram of a chip structure proposed in the embodiment of the present application. Figure 8 The structure of the chip 800 is shown, but is not limited to this.

[0132] The chip 800 includes a processing circuit 801 , and the processing circuit 801 is configured to execute any of the above code updating methods.

[0133] In some embodiments, the chip 800 further includes one or more interface circuits 802. Optionally, the interface circuit 802 is connected to the memory 803, and the interface circuit 802 can be used to receive signals from the memory 803 or other devices, and the interface circuit 802 can be used to send signals to the memory 803 or other devices. For example, the interface circuit 802 can read instructions stored in the memory 803 and send the instructions to the processing circuit 801.

[0134] In some embodiments, the interface circuit 802 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 801 performs other steps.

[0135] In some embodiments, terms such as interface circuit, interface, transceiver pin, and transceiver may be used interchangeably.

[0136] In some embodiments, the chip 800 further includes one or more memories 803 for storing instructions. Optionally, all or part of the memory 803 may be outside the chip 800.

[0137] In order to implement the above embodiments, the present application also proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the code updating method as described in any of the above method embodiments is implemented.

[0138] In order to implement the above embodiments, the present application also proposes a computer program product, on which a computer program is stored, and when the computer program is executed by a processor, the code updating method as described in any of the above method embodiments is implemented.

[0139] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0140] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0141] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0142] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0143] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0144] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0145] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0146] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A code updating method, characterized in that: include: Determine at least one target subgraph from a directed acyclic graph associated with the program to be updated; wherein the nodes in the directed acyclic graph include a plurality of operand nodes and operation nodes, the edges between the nodes are used to indicate the dependency relationship between the nodes, and the target subgraph includes at least two adjacent logic operation nodes; Determine, from the program to be updated, a plurality of instructions to be merged corresponding to any target subgraph; Fusing a plurality of instructions to be fused corresponding to any target directed acyclic subgraph to obtain a target fusion instruction corresponding to any target subgraph; The target fusion instructions corresponding to each of the target subgraphs are used to update the program to be updated to obtain the target program code.

2. The method according to claim 1, characterized in that The step of determining at least one target subgraph from a directed acyclic graph associated with the program to be updated comprises: Extracting a plurality of candidate subgraphs from the directed acyclic graph; wherein the candidate subgraphs include at least two adjacent logical operation nodes; At least one target subgraph is determined from the multiple candidate subgraphs according to the number and in-degree of the logic operation nodes in each of the candidate subgraphs.

3. The method according to claim 2, characterized in that Determining at least one target subgraph from the plurality of candidate subgraphs according to the number of logic operation nodes and the in-degree of the logic operation nodes in each of the candidate subgraphs comprises: For any candidate subgraph, determining first running costs of a plurality of candidate instructions corresponding to the any candidate subgraph according to the number of logic operation nodes in the any candidate subgraph; Determining, according to the in-degree of each logic operation node in any candidate subgraph, a second running cost of a fused instruction after the plurality of candidate instructions are fused; At least one target subgraph is determined from the plurality of candidate subgraphs according to the first running costs and the second running costs corresponding to the candidate subgraphs.

4. The method according to claim 3, characterized in that The determining, according to the in-degree of each logic operation node in any candidate subgraph, a second running cost of a fused instruction after fusion of the plurality of candidate instructions comprises: Traversing the logic operation nodes in any candidate subgraph in sequence, and determining the in-degree of each logic operation node; According to the in-degree of each of the logic operation nodes, a target logic operation node is determined from each of the logic operation nodes; wherein the in-degree of the target logic operation node is greater than a specified number; The initial operation cost is updated according to the number of the target logic operation nodes to obtain the second operation cost.

5. The method according to claim 3, characterized in that: The determining at least one target subgraph from the plurality of candidate subgraphs according to the first running cost and the second running cost corresponding to each of the candidate subgraphs comprises: In response to the first running cost of any candidate subgraph being greater than the second running cost, taking any candidate subgraph as the target subgraph.

6. The method according to claim 2, characterized in that The step of extracting a plurality of candidate subgraphs from the directed acyclic graph comprises: Performing a reverse post-order traversal on the directed acyclic graph to obtain a plurality of candidate node sequences; wherein the candidate node sequences include at least three operand nodes and at least two logic operation nodes other than the at least three operand nodes; Extracting candidate subgraphs matching each of the candidate node sequences from the directed acyclic graph.

7. The method according to claim 1, characterized in that The directed acyclic graph is created using the following steps: Scanning the program to be updated to obtain a plurality of operands in the program to be updated and dependencies between the plurality of operands; wherein the dependencies include logical operations and mathematical operations; The directed acyclic graph is created according to the plurality of operands and the dependency relationships between the plurality of operands.

8. A code updating device, characterized in that: include: A first determination module is used to determine at least one target subgraph from a directed acyclic graph associated with the program to be updated; wherein the nodes in the directed acyclic graph include a plurality of operand nodes and operation nodes, the edges between the nodes are used to indicate the dependency relationship between the nodes, and the target subgraph includes at least two adjacent logic operation nodes; A second determination module is used to determine a plurality of instructions to be merged corresponding to any target subgraph from the program to be updated; A fusion module, used for fusing a plurality of instructions to be fused corresponding to any target directed acyclic subgraph to obtain a target fusion instruction corresponding to any target subgraph; An updating module is used to update the program to be updated by using the target fusion instructions corresponding to each of the target subgraphs to obtain a target program code.

9. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A chip, characterized in that: The chip comprises an interface circuit and a processing circuit coupled to each other, the interface circuit is used to input or output a signal, and the processing circuit is used to implement the method according to any one of claims 1 to 7.

11. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the program instructions are executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

12. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 7.

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