Task scheduling method and system, electronic equipment and storage medium

Abstract

The invention discloses a task scheduling method and system, electronic equipment and a storage medium, and relates to the technical field of computers, and the task scheduling system can be compatible with computing nodes of various node types. The node types at least comprise a first type and a second type, and the calculation efficiency and the data processing efficiency of the first type and the second type are different. The host node may identify and tag the node type of the compute node. When the to-be-executed task is obtained, the host node can evaluate the node type suitable for the to-be-executed task so as to select the computing node suitable for the to-be-executed task as the target node, and the to-be-executed task is scheduled to the target node to be executed. If yes, the technical problem of poor task execution efficiency can be solved, and the technical effects of being compatible with multiple computing nodes to reasonably schedule and execute the computing nodes of the to-be-executed task and further improving the task execution efficiency are achieved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a task scheduling method, a task scheduling system, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the rapid development of big data, artificial intelligence, and high-performance computing, the computing bottlenecks and latency issues of traditional computing architectures are becoming increasingly apparent. To solve the aforementioned problems, a variety of computing architectures adapted to application scenarios and different computing needs have emerged. Just as different computing architectures are mainly designed to adapt to different computing needs, there are still obvious computing bottlenecks and latency issues when executing some other types of computing needs, resulting in poor task execution efficiency. Summary of the invention

[0003] The present application provides a task scheduling method, a task scheduling system, an electronic device and a computer-readable storage medium to at least solve the problem of poor task execution efficiency in the related art.

[0004] The present application provides a task scheduling method, which includes: a host node of a server obtains node information of a computing node, identifies the node type represented by the node information, and assigns a type label that matches the computing node with its node type; wherein the node type includes at least a first type and a second type, the computing efficiency of the first type is higher than the computing efficiency of the second type, and the data processing efficiency of the second type is higher than the data processing efficiency of the first type; the host node obtains a task to be executed and evaluates the task type of the task to be executed; the host node uses the node type that matches the task type as the target type, selects the computing node carrying the target type label as the target node, and schedules the task to be executed to the target node, so that the target node executes the task to be executed.

[0005] The present application also provides a task scheduling system, which is used to implement any of the above-mentioned task scheduling methods; the task scheduling system includes: a host node, a computing node and a switch module; the computing node includes computing nodes of multiple node types; the node types include at least a first type and a second type, the computing efficiency of the first type is higher than the computing efficiency of the second type, and the data processing efficiency of the second type is higher than the data processing efficiency of the first type; the switch module is connected to the host node and the computing node respectively, and the host node and the computing node communicate with each other through the switch module.

[0006] The present application also provides an electronic device, which includes: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned task scheduling methods when executing the computer program.

[0007] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned task scheduling methods are implemented.

[0008] Through the present application, the task scheduling system is compatible with computing nodes of multiple node types. That is, the node types include at least a first type and a second type, and the computing efficiency and data processing efficiency of the first type and the second type are different. The host node can identify the node type of the computing node and assign a label. When obtaining a task to be executed, the host node can evaluate the node type suitable for the task to be executed, select the computing node that is suitable for the task to be executed as the target node, and schedule the task to be executed to the target node for execution. Therefore, the technical problem of poor task execution efficiency can be solved, and compatibility with multiple computing nodes can be achieved to reasonably schedule the computing nodes that execute the task to be executed, thereby improving the technical effect of task execution efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 This is a structural diagram of an embodiment of a task scheduling application scenario of the present application; Figure 2 This is a structural diagram of an embodiment of a task scheduling system of the present application; Figure 3 This is a structural diagram of another embodiment of the task scheduling system of the present application; Figure 4 This is a flow chart of an embodiment of a task scheduling method of the present application; Figure 5 A schematic diagram of a flow chart of an embodiment of identifying the node type of a computing node in the present application; Figure 6 This is a flow chart of another embodiment of the task scheduling method of the present application; Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0012] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0013] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0014] In conjunction with the specific application environment architecture or the specific hardware architecture on which the execution of the task scheduling method depends, the specific application environment architecture or the specific hardware architecture is described herein.

[0015] See also Figure 1 , Figure 1 This is a structural diagram of an embodiment of a task scheduling application scenario of the present application.

[0016] In one embodiment, a user, administrator, or other person can send a task execution request to the server 12 through the external device 11. The task execution request can carry the task to be executed, or the server 12 can obtain the task to be executed after responding to the task execution request, or the server 12 can generate the task to be executed after responding to the task execution request, which is not limited here. This is to achieve the acquisition of the task to be executed as described above.

[0017] The external device 11 may include smart wearable devices such as smart watches, mobile phones, computers, other servers, etc., which are not limited here.

[0018] The server 12 is a specific IT device that provides computing power and runs software applications in a network environment, and can provide computing or application services to other clients (such as personal computers, smart phones and other terminal devices) in the network. Generally speaking, the server 12 can have the ability to respond to service requests, provide services, and ensure services.

[0019] It should be noted that the server described in this embodiment may represent a single server or a server cluster, etc., which is not limited here. As the name implies, a server cluster includes multiple servers, which are connected to each other and can collaborate to achieve tasks to be performed.

[0020] Furthermore, the server may include a task scheduling system, so that the task scheduling system schedules and executes the tasks to be executed. That is, the embodiment of the present application provides a task scheduling system.

[0021] See also Figure 2 , Figure 2 This is a structural diagram of an embodiment of a task scheduling system of the present application.

[0022] In one embodiment, the task scheduling system may include a host node, a switch module, and a computing node.

[0023] The host usually refers to the main collective part of the computer except the input and output devices, and is also a control box for placing the motherboard and other main components. The host usually includes a CPU (Central Processing Unit) and the like. The host node in this embodiment can be considered as a server host, that is, a special computer system that can be used to provide services and manage network resources, etc., and can be responsible for storing, processing, and distributing data, etc. It can also run various applications to provide the required services to the client, that is, at least be able to achieve the acquisition of task execution requests and execute tasks to be executed as described in the previous text.

[0024] As the name implies, a computing node is a node that is responsible for taking on computing tasks and performing data processing and storage in a server. In this embodiment, the computing node may include computing nodes of multiple node types.

[0025] Among them, the node type may include at least a first type and a second type, the computing efficiency of the first type is higher than the computing efficiency of the second type, and the data processing efficiency of the second type is higher than the data processing efficiency of the first type. In this way, the present embodiment can at least adapt to a variety of tasks to be executed. In layman's terms, when the task to be executed focuses on computing efficiency, the computing nodes of the first type can be scheduled for execution with priority; when the task to be executed focuses on data processing, the computing nodes of the second type can be scheduled for execution with priority. In other words, when there are no idle or available computing nodes of the node type that is more suitable for the task to be executed, computing nodes of other node types can also be scheduled to execute the task to be executed, so as to reduce the queuing time of the task to be executed, and also improve the task scheduling and task execution efficiency.

[0026] A switch means "switch", which means that a switch can be considered as a network device used for forwarding electrical (optical) signals. A switch can provide an exclusive electrical signal path for any two network nodes of an access point. In this embodiment, the switch module can be connected to the host node and the computing node respectively, and the host node and the computing node communicate through the switch module.

[0027] Furthermore, the present embodiment may also include computing nodes of three or four node types, so as to facilitate adapting to more application scenarios and computing requirements. Moreover, in the present embodiment, the host node and the computing node are connected through the switch module, which can be beneficial to improving the scalability of the task scheduling system. Even if the task scheduling system and the server have been put into actual use, new computing nodes of existing node types or computing nodes of other node types can still be added, and the newly added computing nodes can be coupled to the switch module to realize the incorporation of the new computing nodes into the task scheduling system.

[0028] See also Figure 3 , Figure 3 This is a structural diagram of another embodiment of the task scheduling system of the present application.

[0029] In one embodiment, the first type of computing nodes described above may be equivalent to near memory computing nodes, and the second type of computing nodes may be near storage computing nodes.

[0030] The task scheduling system may also include host memory and storage devices.

[0031] The host memory is connected to the switch module, and is connected to the host node and the first type of computing node through the switch module.

[0032] The storage device is connected to the computing node of the second type, and is connected to the switch module and the host node through the computing node of the second type.

[0033] Relatively speaking, in this embodiment, the storage device is directly connected to the second type of computing node, and the first type of computing node is indirectly connected to the host memory. The reason for the design of this application is that, considering that the main function of the storage device is the storage device, a storage device can be attached to each second type of computing node to effectively shorten the physical link between the computing node and the storage device, thereby further improving the data processing efficiency. While the host memory cooperates with the first type of computing node, it also needs to implement the relevant computing work of the host node. Therefore, the host memory, the first type of computing node and the host node are connected to each other through a switch module to balance the working links between the host memory and each party.

[0034] Optionally, the switch module may further include a first module and a second module. The first module and the second module are connected, and at least one of the first module and the second module is connected to the host node. Figure 3 As shown in the example, the first module can be connected to the host node, or the second module can be connected to the host node, so that the interface resources of the host node can be saved; or both the first module and the second module can be connected to the host node, so that both the first type of computing node and the second type of computing node can be connected to the host node through a shorter link, taking into account the task scheduling efficiency of various tasks to be executed.

[0035] Specifically, the first module is used to manage the links of the host node, the host memory and the computing node of the first type, that is, the first module can be connected to the host memory and the computing node of the first type.

[0036] The first module is used to manage the links of the host node and the computing nodes of the first type. The second module is connected to the computing nodes of the second type.

[0037] It can be seen that in this embodiment, computing nodes of each node type are respectively connected to a switch module. In other words, computing nodes of the same node type can be connected to the same switch module, which is conducive to improving the rationality of the modular architecture of the task scheduling system and can also facilitate the subsequent incorporation of computing nodes of new node types. At the same time, computing nodes of different node types can also be decoupled.

[0038] Please continue reading Figure 3 In one embodiment, the component modules of a first type of computing node are integrated into a field programmable gate array.

[0039] like Figure 3 As shown in the example, the components of the first type of computing node may include a target bus protocol, a target bus protocol host connection module, a heterogeneous device memory controller, an embedded processor, a heterogeneous device memory, and a near memory computing accelerator. The target bus protocol may be a protocol such as PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard), CXL (Compute ExpressLink, an open interconnect standard), etc. Figure 3 The CXL protocol is used as an example to illustrate the .mem and .cache protocols. .mem can be used to expand system storage, and .cache can be used to expand system cache. In other words, Figure 3The component modules shown in the example can be integrated into a field programmable gate array (FPGA). In this way, the rich resources of the FPGA can be used to reduce the need for additional mounting of component modules, thereby further shortening the communication link within the first type of computing node, and improving the computing efficiency of the first type of computing node itself through adjustments at the hardware level.

[0040] Similarly, the constituent modules of a second type of computing node may be integrated into a field programmable gate array.

[0041] like Figure 3 As shown in the example, the components of the second type of computing node may include a hard disk controller, a target bus protocol, a target bus protocol host connection module, a heterogeneous device memory controller, an embedded processor, a heterogeneous device memory, and a near memory computing accelerator. Among them, the target bus protocol can be such as PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) protocol, CXL (Compute ExpressLink, an open interconnection standard), etc. Figure 3 In the example of CXL protocol, the target bus protocol of the second type of computing node supports three protocols: .io, .mem and .cache. .io can be used for discovery, configuration, register access, error reporting, host node physical address lookup, interruption, etc. .mem can be used to expand system storage, and .cache can be used to expand system cache. In other words, Figure 3 The component modules shown as examples can be integrated into a field programmable gate array (FPGA).

[0042] Furthermore, the flash memory storage particles of the storage device (eg, flash (flash memory) storage particles) may also be integrated into the field programmable gate array of the second type of computing node.

[0043] In this way, the rich resources of FPGA can be utilized to reduce the need for additional mounted component modules, thereby further shortening the communication link within the second type of computing node. For example, the computing efficiency of the second type of computing node itself can be improved through adjustments at the hardware level.

[0044] As exemplified in this embodiment, the target bus protocol may be a CXL protocol, and the switch module may include a CXLSwitch (switch). The target bus protocol communication module may be a CXL Device EP (CXL device), which is used to implement high-speed and efficient interconnection devices between a CPU and an accelerator such as a GPU (Graphics Processing Unit), an FPGA, etc. The target bus protocol included in the first type and / or second type of computing nodes may also be a CXL DeviceEP. The target bus protocol host connection module may be a CXL Host Bridge, which is a concept in the CXL protocol, which may represent a set of CXL Root Ports (root ports) or other paired structures that share logic, and may be considered as a software abstraction concept that can be used to identify and manage CXL devices.

[0045] In an alternative embodiment, the computing node may also be integrated into a programmable controller such as a CPLD (Complex Programmable Logic Device), which is not limited here.

[0046] As described above, the node types may be three or four, for example, including near-memory GPU type computing nodes and near-memory FPGA type computing nodes. Furthermore, a switch module may be assigned to each node type computing node, and connected to other switch modules or host nodes through the switch module, which is not limited here.

[0047] The host node, the first type of computing node and the second type of computing node of the present application are respectively described in detail below.

[0048] The host node serves as the core engine of the unified architecture of the task scheduling system of this application, and it can adopt a CPU and main memory architecture. The CPU can be responsible for the overall control of the system, task scheduling and general computing tasks. Through the logical processing capabilities of the CPU, it can handle complex operating systems and applications. The CXL Host Bridge interface can be integrated in the CPU, and connected to the CXL Switch Internet network through this interface to ensure that the CPU can perform high-speed data interaction and instruction transmission with other nodes in the entire network architecture. The main memory can be connected to the CXL Switch Internet network through the CXL Device EP chip, so that the main memory can perform data transmission in the efficient CXL network.

[0049] In such Figure 3In the task scheduling system shown as an example, the first type of computing node can be considered to be the near memory computing node in the first type and the second type.

[0050] Near-memory computing nodes can integrate computing logic near the host memory, which can reduce memory access latency and increase data processing speed while offloading CPU workload. The memory can use high-speed DRAM (dynamic random access memory) or other emerging memory technologies such as HBM (high-bandwidth memory) to provide large-capacity, high-bandwidth memory support.

[0051] Near-memory computing nodes can be integrated near the host memory and use FPGA as the basis. The FPGA contains the CXLDevice EP interface, which mainly realizes the connection between the near-memory computing node and the CXL Switch interconnection network. It relies on the ability of the CXL interface to support memory semantic access, connects to the device memory through the CXL.mem and CXL.cache modules, and enables the host node and the second type of computing node to access the device memory like accessing local memory. This helps to ensure the consistency of the device memory in the system. Near-memory computing can use the embedded processor + accelerator method. The embedded processor and accelerator access the device memory and host memory through the CXL Host Bridge.

[0052] Near-memory computing nodes are used to directly compute data in memory, and can offload a large number of computing tasks from the CPU through high-performance computing capabilities. For example, during machine learning training, near-memory computing units can perform computing operations such as matrix multiplication on batch data, reducing the pressure of data calculation and transmission.

[0053] In such Figure 3 In the task scheduling system shown as an example, the second type of computing node can be considered to be the near storage computing node in the first type and the second type.

[0054] Near-storage computing nodes mean that computing functions can be integrated near storage devices to reduce data transmission delays between storage and computing units. Storage devices can use high-performance storage media, such as Flash storage particles, NVMe (non-volatile memory host controller interface specification) new storage, etc., to provide large-capacity data storage capabilities.

[0055] Near storage computing nodes can be integrated near storage devices and use FPGA as the basis. The FPGA can include CXL Device EP interface, which mainly realizes the connection between near storage computing unit and CXL Switch interconnection network, and connects SSD (Solid State Disk or Solid State Drive) storage controller through CXL.io module, thereby realizing end-to-end high-speed data transmission between storage device and host node, near storage computing node and near memory computing node. It can also rely on the ability of CXL interface to support memory semantic access, connect device memory through CXL.mem and CXL.cache modules, and realize host computing node and near memory computing node to access device memory like accessing local memory, ensuring the consistency of device memory in the system. Near storage computing adopts embedded processor + accelerator mode, and embedded processor and accelerator access device memory and host memory through CXL Host Bridge.

[0056] The near-storage accelerated computing unit is used to pre-process data, such as filtering, sorting, and compressing data, to reduce the amount of data that needs to be transmitted to the host computing node. For example, in database applications, the near-storage computing unit can perform preliminary screening of data at the storage end and only transmit data that meets the conditions to the host computing node for further processing.

[0057] The difference between the target bus protocols of the first type computing nodes and the second type computing nodes is that the first type computing nodes omit CXL.io for accessing storage devices.

[0058] As exemplified above, in this embodiment, an interconnection network can be formed through CXL, which is equivalent to using CXL as a communication bridge of the task scheduling system.

[0059] The CXL interconnect network can connect host computing nodes, near storage computing nodes, and near memory computing nodes. Figure 3 The multi-level CXL Switch used in the example above builds and expands the CXL network, which can support the connection between the host node and multiple near-storage computing nodes and near-memory computing nodes. It should be noted that Figure 3 Only one computing node of the first type and one computing node of the second type are exemplified. In an actual task scheduling system, there may be multiple computing nodes of the first type and multiple computing nodes of the second type.

[0060] By supporting unified addressing of all system memories through the CXL interconnection network, CXL Switch can quickly forward data according to the destination address of the data packet, realizing high-speed, low-latency, and consistent data transmission under the unified architecture of near storage and near memory.

[0061] Through the above-mentioned unified CXL interface, unified data access to storage devices, host memory, and device memory can be achieved. Relying on the above-mentioned hardware architecture foundation and integrating the characteristics of near storage and near memory computing, task execution under a unified computing architecture is proposed. Through this method, efficient execution of tasks under a unified computing architecture is achieved; a different cache management mode that supports the CXL consistency protocol is also proposed. This mode is committed to solving the system performance bottleneck and limited scalability problems faced when supporting CXL cache consistency in a large-scale node environment. It aims to build an efficient near storage and near memory unified computing architecture with data consistency capabilities. The details will be elaborated in the following text.

[0062] As Figure 3 As exemplified in , the task scheduling method in this embodiment may also involve cache management.

[0063] Specifically, the server selects a current cache management mode from a plurality of cache management modes, wherein the cache management mode of the server at least includes a global mode and a local mode.

[0064] The global mode indicates that the server memory is globally byte-addressed so that the server memory can be globally scheduled by the host node; the server memory may include the host memory and the computing node memory.

[0065] In layman's terms, the global mode is equivalent to global asymmetric cache consistency management, and the control core is centralized, that is, the host node is the master node and the computing node is the slave node. The host node can perform global byte addressing on the host memory and computing node memory in the task scheduling system. The host node can achieve cache consistency of global memory on the host side through the CXL Host Bridge and CXL DeviceEP interfaces. At this time, the CXL HostBridge module inside the computing node can be invalidated, and the embedded processor is only used as a computing resource in the node and cannot access the memory resources of other nodes. The host node is responsible for maintaining data consistency and distributing control instructions to each slave node. The slave node is responsible for storing and providing data, updating data according to the instructions of the master node, and maintaining data consistency.

[0066] Through the centralized management of the master node, data updates and propagation can be effectively controlled, unnecessary message interactions can be reduced, maintenance efficiency and network overhead are better, and performance is higher than that of the asymmetric mode. In data-intensive tasks, in pursuit of higher performance, global asymmetric consistency dynamically adjusts the parameters of the cache consistency protocol based on the system load. Under high load conditions, the global protocol reduces the frequency of directory updates and reduces communication overhead; under low load conditions, the global protocol increases the frequency of directory updates and improves data consistency.

[0067] The local mode means that the compute node independently controls its compute node memory and synchronizes the data changes in the compute node memory with other compute nodes.

[0068] In layman's terms, the local mode is equivalent to global symmetric cache consistency management. The control core is distributed, and each computing node works in symmetric mode. The CXL Host Bridge and CXL Device EP interfaces in the computing node are both set to valid. At this time, the embedded processor not only serves as a computing resource within the node but also as a control node of the node to access the memory resources of other nodes. In this way, computing nodes can share data through the global symmetric cache consistency management mechanism without relying on the CPU of the host node. When the data of a cache node (a memory includes multiple cache nodes) changes, an update message can be sent to all other nodes (computing nodes and host nodes) to inform them of the data changes. After receiving the message, other nodes can update their own cache data according to the content of the message to ensure data consistency of all nodes.

[0069] In other words, the local mode has high flexibility and scalability, and computing nodes can join or exit the system relatively freely, reducing the risk of single point failures and the impact on the overall architecture.

[0070] Specifically, the computing node can maintain a local cache directory; the host node can maintain a global cache directory; wherein the global cache directory includes the node identifier of the computing node and the local cache directory. In this way, it is possible to switch between the global mode and the local mode.

[0071] The computing node may monitor the cache status of the cache blocks included in the computing node to update the local cache directory maintained by it, and then update the global cache directory; wherein the cache status includes at least a valid state, an invalid state, and a dirty state.

[0072] It should be noted that although the global mode and local mode are named "global" and "local" in this article, they are actually global cache management modes. The names are based on the server memory range that can be controlled by the cache control core. The global mode is that the host node performs macro scheduling of server memory, and the local mode is that each computing node manages its own computing node memory and synchronizes related information. It does not specifically limit the cache management of the task scheduling system.

[0073] The working principle and switchable principle of realizing global mode and local mode are described in detail below.

[0074] At the hardware design level, it can include two aspects: node interface integration and interface compatibility design.

[0075] Node interface integration includes integrating interfaces that support heterogeneous cache consistency protocols for all nodes (host nodes and computing nodes). For example, the CXL protocol can be designed to include CXL Host Bridge and CXL Device EP interfaces.

[0076] In the design of the host node motherboard, the CXL Host Bridge can be integrated into the motherboard circuit to make it responsible for communicating with other devices that support the CXL protocol, providing a high-speed data transmission channel, and being able to handle complex protocol interactions. For example, when designing, you can pair it with a motherboard that supports CXL, connect the CXL HostBridge through a specific slot and circuit, and enable efficient communication between the host and the computing node.

[0077] For computing nodes, the CXL Device EP interface can be integrated. Computing nodes can be independent boards or modules. During design, the CXL Device EP chip can be embedded in the board and connected to the storage or memory module inside the computing node through appropriate PCB (Printed Circuit Board) wiring. For example, when designing the second type of computing node, the CXL Device EP chip can be connected to the SSD controller so that the data in the SSD can interact with the host or other nodes through the CXL interface.

[0078] The purpose of interface compatibility design is to ensure that CXL Host Bridge and CXL Device EP have good compatibility in design and can adapt to two cache management modes.

[0079] In terms of protocol version support, the interface can be controlled to support multiple CXL protocol versions to ensure normal operation in different system environments and application scenarios. For example, CXL 1.0, CXL 2.0, CXL 3.0 and other versions can be supported at the same time, so that when the system is upgraded or different devices are used, the interface can automatically adapt to the corresponding protocol version.

[0080] The implementation of the global mode is described in detail below. The implementation of the global mode mainly involves the cache consistency management of the host node and the response of the computing node.

[0081] Specifically, cache consistency management of the host node can be subdivided into cache directory maintenance and consistency instruction distribution.

[0082] Cache directory maintenance mainly involves that the host node can use CXL Host Bridge to collect cache status information from each compute node and maintain a global cache directory as described above. The global cache directory records the status of each data block in each node cache (such as valid, invalid, dirty, etc.). For example, the host node can obtain cache status information by periodic polling or by active reporting by the compute node, and store it in the host memory of the host node.

[0083] The consistency instruction distribution mainly involves that when the host node detects that the state of a data block has changed, it can send consistency instructions to the corresponding near storage and near memory computing nodes through the CXL Host Bridge interface. For example, if the host node finds that a data block has been modified to a dirty state in the cache of the near memory computing node, it will send invalidation instructions to other nodes holding copies of the data block to ensure data consistency.

[0084] The response of the computing node can be divided into status reporting, instruction execution, etc.

[0085] Status reporting means that the compute node periodically reports its cache status information to the host node through the CXL Device EP. For example, each compute node can maintain a cache status table locally, and when the cache status changes, the change information is sent to the host node through the corresponding CXL interface in a timely manner.

[0086] Instruction execution means that when a computing node receives a consistency instruction sent by a host node, it can receive the instruction through CXLDevice EP and update the local cache state according to the requirements of the received instruction. For example, if an invalidation instruction is received, the computing node marks the corresponding data block as invalid and clears the data block from the local cache.

[0087] The implementation of the local mode is described in detail below. The implementation of the local mode mainly involves symmetric communication between nodes and distributed cache consistency maintenance.

[0088] Specifically, symmetric communication between nodes may involve aspects such as direct data transmission and message passing.

[0089] Direct data transmission means that data can be directly transmitted between nodes through the CXL interface. For example, computing nodes of the same node type and / or computing nodes of different node types can directly exchange data without being transferred through the host node.

[0090] When performing message passing, computing nodes can pass messages through the CXL interface to coordinate cache consistency. For example, when a computing node modifies a data block, it can send an update message to other nodes holding copies of the data block through the CXL interface to notify other nodes to update their cache status.

[0091] Distributed cache consistency maintenance designs local cache management and collaborative consistency algorithms.

[0092] When managing the local cache, the computing nodes and the host nodes can be considered to be at the same level, that is, there is no master-slave distinction between them. The computing node can be responsible for managing its own local cache and maintaining the local cache directory. At the same time, the computing node can update and eliminate the local cache according to local access requirements and received messages. For example, when a computing node receives an update message from other nodes, it can check whether there is a copy of the data block in the local cache, and if so, update the status of the data block copy.

[0093] The collaborative consistency algorithm means that the host node and the computing node can use the same addressing for the server memory and storage, that is, the same address can access the same place. At the same time, a collaborative consistency algorithm (such as a directory-based consistency algorithm or a bus-sniffing consistency algorithm) can also be used to ensure the cache consistency of the entire system. In other words, in the local mode of cache management, the central node that manages the cache consistency can be omitted, and the consistency maintenance between the server nodes can be achieved through mutual cooperation.

[0094] That is to say, the task scheduling system of the present application is a relatively universal system architecture, which can work in different cache management modes, that is, it can work in global mode or local mode. In addition, the hardware architecture differences between task scheduling systems working in different cache management modes are small, which can improve the versatility of the task scheduling system.

[0095] Furthermore, in order to further improve the versatility of the task scheduling system, the general data structure may be designed accordingly in this embodiment.

[0096] Specifically, node information, global cache directory, and cache status can be defined. Among them, node information is identification information that can identify the identity information of the computing node, and can also manage local cache and maintain local cache directory. The global cache directory represents the global cache directory maintained by the host node in global mode. Even in global mode, each computer node can maintain its own local cache directory. The local cache directory can be considered as a local "global" information. The cache status is a pre-defined state that a buffer block may exist in, such as valid, invalid, dirty, etc., which is not limited here.

[0097] To expand on this, the cache status as exemplified above can include valid, invalid, and dirty. Three cache status constants can also be defined, namely VALID (valid), INVALID (invalid), and DIRTY (dirty), which are used to represent different cache statuses of cache blocks. VALID means that the data in the cache block is valid and consistent with the data in the main memory; INVALID means that the data in the cache block is invalid and cannot be used; DIRTY means that the data in the cache block has been modified and is inconsistent with the data in the main memory.

[0098] You can also define computing node classes (Node) and host node classes (HostNode).

[0099] The compute node class may include node_id, local_cache, local_cache_directory, update_local_cache, invalidate_local_cache.

[0100] Among them, node_id represents the unique identifier of the node; local_cache is used to store the data blocks and their status in the local cache; local_cache_directory is used to record the nodes that hold copies of each data block in the local cache; update_local_cache is used to update the status of the local cache and update the local cache directory at the same time; invalidate_local_cache is used to mark a data block in the local cache as invalid and update the local cache directory.

[0101] The host node class can inherit from Node and is applicable to the cache management mode of the global mode. The host node class can include global_cache_directory, collect_cache_status, and detect_status_change_and_send_instructions.

[0102] The global cache directory can be recorded as global_cache_directory, which is used to record the cache status of each data block on each node.

[0103] Optionally, the host node class can be a nested dictionary to maintain a global cache directory. The key of the outer dictionary is the identifier of the data block (such as block1), and the value is another dictionary. The key of the inner dictionary is the node object, and the value is the cache status of the corresponding data block on the node. The specific structure can be as follows: "{ 'block1': { <NearNode object1> : 'valid', <NearNode object3> : 'dirty' }, 'block2': { <NearNode object2> : 'invalid' } }” collect_cache_status can collect cache status information of each node to the global cache directory. detect_status_change_and_send_instructions can detect changes in data block status. If a data block becomes dirty, send invalidation instructions to other nodes holding valid copies of the data block.

[0104] Thus, through the data structure design of the computing node class (Node) and the host node class (HostNode), it can meet the needs of each computing node to independently manage the cache in the local mode, and can also meet the needs of the host node to uniformly manage the cache in the global mode.

[0105] The following is an example of how cache management works through the global mode.

[0106] Cache management in global mode may include steps such as initialization, computing nodes updating local caches, host nodes collecting cache states, host nodes detecting state changes and distributing management instructions to adapt to state changes.

[0107] Specifically, when initializing the global mode, you can create a HostNode object and multiple Node objects. Each Node object represents a computing node. The HostNode object represents the host node and is responsible for global cache consistency management. The specific definition code can be as follows: "host = HostNode(0) node1 = Node(1) node2 = Node(2)" When a computing node updates its local cache, it can update the local cache status according to its own access needs, and update and maintain the local cache directory. When a computing node updates its local cache, it can call the update_local_cache method. The specific calling code can be as follows: "node1.update_local_cache('block1', VALID) node2.update_local_cache('block1', VALID)" Thus, in the update_local_cache method, the computing node can update the state of the data block to the local_cache, and update the local_cache_directory to record the copy of the data block it holds.

[0108] When the host node collects the cache status, the host node can collect the cache status information of each computing node through periodic polling or active reporting by the computing node. This can be achieved by calling the collect_cache_status method. The specific calling code can be as follows: "host.collect_cache_status(node1) host.collect_cache_status(node2)” If so, the collect_cache_status method can integrate the local cache status information of the computing node into the global_cache_directory of the host node.

[0109] When the host node detects state changes and distributes instructions, the host node can periodically detect state changes of data blocks in the global_cache_directory. If a data block is found to be dirty on a node, an invalidation instruction can be sent to other nodes holding valid copies of the data block. The specific code can be as follows: "node1.update_local_cache('block1', DIRTY) host.collect_cache_status(node1) host.detect_status_change_and_send_instructions()” Thus, in the detect_status_change_and_send_instructions method, the host node can traverse the global_cache_directory, find the dirty data block, and send invalidation instructions to other nodes holding valid copies of the dirty data block. After receiving the instructions, other nodes can call the invalidate_local_cache method to mark the corresponding data block as invalid.

[0110] The following is an example of how cache management works through local mode.

[0111] Cache management in local mode may include steps such as initialization, computing node access to data blocks, computing node modification of data blocks, and computing node receiving update messages.

[0112] Specifically, when initializing the local mode, you can create multiple Node objects so that each computing node can manage its internal cache independently. The specific creation code can be as follows: "node1 = Node(1) node2 = Node(2)" When a computing node accesses a data block, if the data block is not in the local cache, it will load the data block into the local cache and mark it as valid; if the data block is already in the local cache, it can be used directly. The specific code can be as follows: "node1.update_local_cache('block1', VALID) node2.update_local_cache('block1', VALID)" When a computing node modifies a data block, it can mark the state of the data block as dirty in advance and send an update message to other nodes that hold copies of the data block. The message transmission process can be accomplished by adding message sending logic in the update_local_cache method. The message transmission process will not be elaborated in detail here. The specific code for sending an update message can be as follows: "node1.update_local_cache('block1', DIRTY)" When the computing node receives the update message as another node, the computing node may check whether there is a copy of the data block in the local cache. When there is a copy of the data block in the local cache of the computing node, the copy status of the data block may be marked as invalid.

[0113] Taking computing node 2 receiving the update message as an example, its code logic can be as follows: "node2.invalidate_local_cache('block1')" As such, in this embodiment, in global mode, the host node can be used as the core to implement management functions. The host node can collect and process the cache status information of each computing node and distribute consistency instructions. In local mode, each computing node can be considered to be at the same level in terms of cache management, and can maintain cache consistency through mutual communication and collaboration. The computing node can independently manage its internal cache and update the local cache status based on the received message.

[0114] That is to say, in this embodiment, the compatibility of the global mode and the local mode is achieved through the unified design of the hardware interface and the integration of the software control logic.

[0115] In the hardware design of the computing nodes, each computing node can be equipped with an interface that supports target bus protocols such as CXL, such as the CXL Host Bridge and CXL Device EP interfaces described above. The interfaces that support the target bus protocol can work normally in multiple cache management modes to provide a hardware foundation for data transmission and consistency maintenance. In the global mode, the above interfaces of the host node realize the cache consistency of the global memory on the host side; in the local mode, each computing node uses the above interfaces to achieve symmetric communication and data sharing between computing nodes.

[0116] At the same time, this embodiment realizes software control logic integration through general software control logic. By designing a relatively unified cache management module, the cache management module can integrate the algorithms and processes of the global mode and the local mode. When the server or host node is configured in global mode, the cache management module follows the centralized control logic, and the host node is responsible for maintaining data consistency and distributing instructions to the slave nodes; when the server or host node is configured in local mode, the cache management module switches to distributed control logic, and each computing node can autonomously maintain and share data consistency.

[0117] Furthermore, in response to the fact that the task scheduling system in this embodiment can adapt to multiple cache management modes, the present application can further flexibly switch the cache management mode according to configuration or runtime requirements. In other words, it can switch between multiple cache management modes according to the system state of the task scheduling system.

[0118] In detail, the configuration switching of the cache management mode may include, during the system initialization phase, setting the currently used cache management mode through a configuration file or a system parameter. A global mode or a local mode may be selected as the default current cache management mode according to the characteristics and requirements of the application scenario.

[0119] In layman's terms, based on the system flexibility requirements and data consistency requirements of the server application scenario, one of the global mode and the local mode can be selected as the current cache mode.

[0120] In response to application scenarios that have high requirements for data consistency and relatively low network overhead, the global mode can be selected as the current cache management mode. In response to application scenarios that focus more on system flexibility and scalability and have slightly lower requirements for consistency and real-time performance, the local mode can be selected as the current cache management mode.

[0121] Furthermore, this embodiment can support switching the current cache management mode during the operation of the task scheduling system. That is, in response to the demand to switch the cache management mode as the current cache management mode, the configuration file can be modified and the related services can be restarted, so that the system loads the new configuration and switches to the cache management mode specified by the modification.

[0122] Specifically, during the initialization process of the server and / or task scheduling system, the cache consistency management mode can be specified by editing the configuration file or setting the system parameters before the system starts according to the characteristics and requirements of the application scenario, so as to configure the configuration file or set the parameters.

[0123] Taking the configuration file config.yaml as an example, the specific configuration code can be as follows: "yaml cache_consistency_mode:"global_asymmetric" # or "global_symmetric"" Among them, global_asymmetric represents the global mode; global_symmetric represents the local mode.

[0124] When the server or task scheduling system starts, it can read the configuration file or parameters and initialize according to the specified cache management mode to realize the system loading configuration. The specific loading process code can be as follows: "import yaml def load_config(): with open('config.yaml', 'r') as f: config = yaml.safe_load(f) return config config = load_config() cache_mode = config.get('cache_consistency_mode') if cache_mode == 'global_asymmetric': # Initialize global mode # Such as creating host nodes and computing nodes host = HostNode(0) nodes = [Node(i) for i in range(1, 10)] # Perform related initialization operations, such as setting up communication between nodes, etc. elif cache_mode == 'global_symmetric': # Initialize local mode nodes = [Node(i) for i in range(10)] # Perform initialization operations in local mode, such as peer-to-peer communication settings between nodes" The text after “#” indicates code comments.

[0125] When you need to switch the cache management mode during the operation of the server or task scheduling system, you may need to modify the mode settings in the configuration file.

[0126] For example, change cache_consistency_mode from "global_asymmetric" to "global_symmetric".

[0127] In response to modifying the configuration file, the relevant system services can be restarted to make the new configuration effective. That is, when the service is restarted, the server and task scheduling system can re-read the configuration file and initialize according to the new current cache management mode.

[0128] Optionally, during the operation of the task scheduling system, the system performance indicators and task execution status can be monitored to determine whether the current cache management mode has a performance bottleneck, so as to automatically determine whether it is necessary to switch the cache consistency management mode. The system performance indicators may include at least one of cache hit rate, data transmission delay, and network bandwidth utilization.

[0129] In response to determining whether the current cache management mode has a performance bottleneck, another cache management mode is selected as a new current cache management mode, wherein the other cache management mode refers to a cache management mode that is not used as the current cache management mode.

[0130] For example, as described above, the cache management mode may include a global mode and a local mode. If the global mode is used as the current cache management mode, when the host node load is too high (for example, the current load exceeds the load threshold) and causes cache consistency maintenance delays, it can be dynamically switched to the local mode as the current cache management mode, thereby distributing the load and improving the overall performance of the task scheduling system and the server. In other words, the above-mentioned adaptive switching mechanism can optimize cache consistency management according to the real-time status of the task scheduling system, which can help improve the stability and efficiency of the system.

[0131] The following is an example to illustrate the detailed principle of adaptive switching.

[0132] The performance indicators of the task scheduling system can be monitored. For example, performance indicators such as cache hit rate, data transmission delay, and network bandwidth utilization can be continuously monitored. You can use monitoring tools or add monitoring logic in the code. The following is an example of monitoring logic in the code: “import time def monitor_system(): cache_hit_rate = 0.8 # Example cache hit rate data_transfer_delay = 10 # Example data transfer delay, unit: ms network_bandwidth_utilization = 0.6 # Example network bandwidth utilization return cache_hit_rate, data_transfer_delay, network_bandwidth_utilization while True: cache_hit_rate, data_transfer_delay, network_bandwidth_utilization =monitor_system() # Make judgments based on monitoring results if data_transfer_delay>20 and network_bandwidth_utilization>0.8: # Trigger mode switching conditions break time.sleep(1) # Monitor once per second" If so, it can be determined whether the cache management mode needs to be switched based on the monitored performance indicators and the preset performance thresholds. For example, in the global mode, the host node load is too high, causing the data transmission delay to exceed the threshold, and the network bandwidth utilization is too high, so it is switched to the local mode. In this process, the performance indicators may include the current load, data transmission delay, and network bandwidth; accordingly, the performance thresholds may include load thresholds, delay thresholds, and bandwidth thresholds, which will not be described in detail here.

[0133] When it is determined that the current cache management mode needs to be switched, the task scheduling system can dynamically switch to a new cache management mode as the current cache management mode. In this process, steps such as node reconfiguration and communication protocol adjustment can be performed. Specifically, in the control code, the mode switching can be achieved by modifying global variables and reinitializing related objects. The specific code can be as follows: "if cache_mode == 'global_asymmetric': cache_mode = 'global_symmetric' # Initialize the global symmetry mode nodes = [Node(i) for i in range(10)] # Adjust the communication method between nodes, etc. else: cache_mode = 'global_asymmetric' host = HostNode(0) nodes = [Node(i) for i in range(1, 10)] # Perform global asymmetric mode initialization operation" As such, in this embodiment, the cache consistency management mode can be flexibly switched according to different computing requirements and system states, thereby significantly improving the performance and stability of the task scheduling system and the server.

[0134] For the description of the features in the embodiment corresponding to the task scheduling system, please refer to the relevant description of the embodiment corresponding to the task scheduling method in the following text, which will not be repeated here.

[0135] The embodiment of the present application further provides a task scheduling method. In combination with the execution process of the task scheduling method, the detailed working principle of the task scheduling method is described below with examples.

[0136] See also Figure 4 , Figure 4 This is a flow chart of an embodiment of a task scheduling method of the present application.

[0137] S101: The host node of the server obtains the node information of the computing node, identifies the node type represented by the node information, and assigns the computing node a type label that matches its node type; wherein the node type includes at least a first type and a second type, the computing efficiency of the first type is higher than the computing efficiency of the second type, and the data processing efficiency of the second type is higher than the data processing efficiency of the first type.

[0138] In this embodiment, the host node can be responsible for the overall control of the task scheduling system, task scheduling and general computing tasks. The computing node is a node that specifically executes the task to be executed. In this embodiment, computing nodes of various node types are compatible.

[0139] The node types include at least the first type and the second type, the computing efficiency of the first type is higher than the computing efficiency of the second type, and the data processing efficiency of the second type is higher than the data processing efficiency of the first type. In layman's terms, the computing nodes of the first type are better at tasks that focus on computing, and the computing nodes of the second type are better at processing tasks that focus on data.

[0140] In this way, after the server is powered on / started, the host node can identify the node type of each computing node contained in the server, and assign each computing node a type label that matches its node type, which is beneficial for improving the efficiency of obtaining computing nodes of the corresponding node type when performing subsequent task scheduling of tasks to be executed.

[0141] S102: The host node obtains the task to be executed and evaluates the task type of the task to be executed.

[0142] In this embodiment, the task to be executed is a task that needs to be scheduled and executed by the host node and the computing node. In this embodiment, multiple types of computing nodes are compatible, so the task type of the task to be executed can be evaluated to select a suitable computing node based on the task type of the task to be executed, so as to improve the processing efficiency of the task to be executed.

[0143] S103: The host node uses the node type that matches the task type as the target type, selects the computing node that carries the target type label as the target node, and schedules the task to be executed to the target node, so that the target node executes the task to be executed.

[0144] In this embodiment, in response to obtaining the task type of the task to be executed, the host node can use the node type suitable for executing the task to be executed as the target type, that is, the node type matching the task type as the target node. As described above, the node type of the computing node is identified in advance and assigned a corresponding label, and the computing node carrying the target type label can be selected as the target node, and the task to be executed is scheduled to the target node, so that the target node executes the task to be executed.

[0145] That is to say, as explained above, the task scheduling system can be compatible with computing nodes of multiple node types, that is, at least including computing nodes of the first type and computing nodes of the second type, and the computing efficiency and data processing efficiency of the first type and the second type are different. As such, in this embodiment, the host node can identify the node type of the computing node and assign a label. When obtaining a task to be executed, the host node can evaluate the node type suitable for the task to be executed, so as to select the computing node that is suitable for the task to be executed as the target node, and schedule the task to be executed to the target node for execution. Therefore, the technical problem of poor task execution efficiency can be solved, and compatibility with multiple computing nodes can be achieved to reasonably schedule the computing nodes that execute the task to be executed, thereby improving the technical effect of task execution efficiency.

[0146] Optionally, the node information may further include a first link length between the computing node and the storage device, and a second link length between the computing node and the host memory.

[0147] When identifying the node type of the computing node, the host node may obtain the link topology of the computing node, the storage device, and the host memory to obtain and compare the first link length and the second link length of the computing node.

[0148] In response to the first link length being longer than the second link length, the host node determines that the computing node belongs to the first type; in response to the first link length being shorter than the second link length, the host node determines that the computing node belongs to the second type.

[0149] In this way, the node type of the computing node can be further verified, identified, and assisted in determination at the software level, which is beneficial to improving the reliability of node type identification.

[0150] See also Figure 5 , Figure 5 A flowchart of an embodiment of identifying the node type of a computing node in the present application.

[0151] S201: The host node accesses the base address register of the computing node through the target bus protocol.

[0152] In this embodiment, the target bus protocol refers to the communication protocol between the host node and the computing node, that is, both the host node and the computing node support the target bus protocol. The target bus protocol may be the PCIe protocol, CXL protocol, etc., as exemplified in the above text.

[0153] The base address register (BAR) represents a data register that can be used to store operands or intermediate results to reduce the number of memory accesses.

[0154] In this embodiment, the base address register supports the target bus protocol, and a code that can represent the node type of the computing node can be pre-assigned in the base address register of the computing node, so that after the server is powered on, the host node can access the base address register of the computing node through the target bus protocol and obtain the relevant encoded data in the base address memory as node information for evaluating the node type.

[0155] That is to say, in this embodiment, the node type identification of the computing node is realized through hardware-level design, which is beneficial to reduce the software computing burden of the host node, save computing power resources and improve the efficiency of node type determination.

[0156] S202: The host node reads the type code in the base address register of the computing node.

[0157] In this embodiment, the host node may read the initial value of the reserved type bit in the base address register and use the initial value as the type code.

[0158] Specifically, an initial value of the BAR may be reserved for each computing node. For example, the lower 8 bits (bit[7:0]) of the BAR may be used as a type address for storing the type code.

[0159] S203: The host node evaluates the node type of the computing node based on the type code.

[0160] In this embodiment, when the host node determines that the node type of the computing node is the first type, step S204 is executed; when the host node determines that the node type of the computing node is the first type, step S205 is executed.

[0161] The host node can obtain the type code of the computing node and use the type code as node information.

[0162] As explained in the foregoing examples, the node type of the computing node may include a first type and a second type, and accordingly, the type code may include a first code and a second code, and the first code is different from the second code.

[0163] In response to the type code being the first code, the host node determines that the computing node belongs to the first type. In response to the type code being the second code, the host node determines that the computing node belongs to the second type.

[0164] For example, when 8'b00000000 (ie, the type code in the BAR is 00000000) represents a computing node of the first type; 8'b11111111 (ie, the type code in the BAR is 11111111) represents a computing node of the second type, other values ​​can be reserved for future expansion device identification.

[0165] S204: The host node assigns a first type type label to the computing node.

[0166] In this embodiment, in response to the host node determining that the node type of the computing node is the first type, a type label of the first type is assigned to the computing node.

[0167] S205: The host node assigns a second type of type label to the computing node.

[0168] In this embodiment, in response to the host node determining that the node type of the computing node is the second type, a type label of the second type is assigned to the computing node.

[0169] That is, in this embodiment, the host node can identify the node type and assign a type label that matches the node type to the computing node.

[0170] As explained in the example above, the first type of computing nodes are the near memory computing nodes in the first type and the second type; the second type of computing nodes are the near storage computing nodes in the first type and the second type. In this way, in layman's terms, the second type of computing nodes can be labeled with the near-storage label, and the first type of computing nodes can be labeled with the near-memory label.

[0171] S206: The host node registers the computing node to the system resource manager.

[0172] In this embodiment, the host node can register the computing node with the system resource manager in response to assigning the computing node a type tag that matches its node type. In detail, the device information can be registered in the system resource manager for use by the task scheduler. Among them, the task scheduler is a component module of the host node for implementing the task scheduling method.

[0173] See also Figure 6 , Figure 6 This is a flowchart of another embodiment of the task scheduling method of the present application.

[0174] S301: The host node obtains the task to be executed.

[0175] In this embodiment, the host node obtains the pending tasks to be scheduled and executed.

[0176] S302: The host node divides the task to be executed into multiple functional subtasks.

[0177] In this embodiment, the host node can divide the tasks to be executed according to the task functions to form multiple functional subtasks.

[0178] For example, when the task to be executed is a database query task, the task to be executed can be divided into functional subtasks such as data preprocessing, database page table connection, data aggregation calculation, data storage, etc. In this way, the functional subtasks can be controlled to be executed in parallel or dependently according to the dependency relationship between the functional subtasks, thereby improving the execution efficiency of the task to be executed.

[0179] S303: The host node divides the functional subtask into multiple data subtasks.

[0180] In this embodiment, the host node may further divide at least part of the functional subtasks into a plurality of data subtasks, wherein the task functions of the plurality of data subtasks match, and the task processing data are different.

[0181] In this way, multiple data subtasks of the same functional subtask can be executed in parallel, further improving the execution efficiency of the functional subtasks, thereby significantly improving the execution efficiency of the tasks to be executed. That is to say, in this embodiment, the tasks to be executed can be divided into at least two levels, so as to improve the execution efficiency of the tasks based on the task dependency relationship, further improve the execution efficiency of the single functional subtask, and make full use of the computing resources of the task scheduling system.

[0182] Optionally, the data requirement factor of the functional subtask can be evaluated. In response to the data requirement factor not reaching the data threshold, it is considered that the amount of data to be processed by the functional subtask is small, and a single computing node can be used for execution, thereby ensuring data consistency while reducing unnecessary consumption of horizontal computing resources. In response to the data requirement factor reaching the data threshold, it is considered that the amount of data to be processed by the functional subtask is large, and multiple computing nodes can be used for distributed execution to improve the execution efficiency of the functional subtask. The data requirement factor will be explained in detail later, so it will not be repeated here.

[0183] Furthermore, it is also possible to judge whether the functional subtask is suitable for data segmentation. If it is not suitable for data segmentation, the functional subtask is not segmented to form multiple data subtasks.

[0184] In an alternative embodiment, the host node may not divide the functional subtasks on the data side and use the functional subtasks as the minimum task execution unit, which is not limited here.

[0185] S304: The host node evaluates the computing power requirement factor of the task to be executed.

[0186] In this embodiment, the computing power requirements of the tasks to be executed may be quantitatively analyzed to confirm the node type of the computing node applicable to the tasks to be executed.

[0187] It should be noted that in this implementation, the task to be executed, the functional subtask, or the data subtask can be used as the evaluation subject to evaluate the computing power requirement factor.

[0188] Optionally, the task to be executed can be used as the evaluation subject to reduce the evaluation amount; or, the data subtask can be used as the evaluation subject to improve the evaluation precision; or, the functional subtask can be used as the evaluation subject to take into account both the evaluation amount and the evaluation precision.

[0189] The computing power requirement factors will be explained in detail later, so I will not go into details here.

[0190] S305: The host node evaluates the data requirement factor of the task to be executed.

[0191] In this embodiment, the data processing requirements of the tasks to be executed may be quantitatively analyzed to confirm the node type of the computing node applicable to the tasks to be executed.

[0192] As described above, in this implementation, the task to be executed, the functional subtask, or the data subtask may be used as an evaluation subject to evaluate the data requirement factor.

[0193] Optionally, the task to be executed can be used as the evaluation subject to reduce the evaluation amount; or, the data subtask can be used as the evaluation subject to improve the evaluation precision; or, the functional subtask can be used as the evaluation subject to take into account both the evaluation amount and the evaluation precision.

[0194] The computing power requirement factors will be explained in detail later, so I will not go into details here.

[0195] The data demand factors will be elaborated in detail later and will not be elaborated here.

[0196] S306: The host node evaluates the task type of the task to be executed.

[0197] In this embodiment, the host node can evaluate the task type of the task to be executed by comprehensively considering the computing power requirement factor and the data requirement factor, wherein the task type includes computing power type, memory type, and transmission type.

[0198] S307: Select a computing node carrying a first type of label as a target node.

[0199] In this embodiment, in response to the task type of the task to be executed being a computing type, the host node may use the first type as the target type and select a computing node carrying a first type label as the target node.

[0200] Furthermore, the host node may preferentially select a computing node that includes a graphics processor and carries a first type of label as the target node.

[0201] Priority selection means that if there is no suitable target type of computing node at present, computing nodes of other node types can be selected as target nodes, which is conducive to reducing the queue time of tasks to be executed, thereby improving the execution efficiency of tasks to be executed, and further improving the performance of the task scheduling system. Priority selection can express similar meanings in the following text, and will not be repeated in the following text.

[0202] S308: Select a computing node carrying a first type of label as a target node.

[0203] In this embodiment, in response to the task type of the task to be executed being a memory type, the host node may use the first type as the target type and select a computing node carrying a first type label as the target node.

[0204] Furthermore, the host node may preferentially select a computing node that carries a first type of tag and includes a central processing unit and a programmable controller as the target node.

[0205] S309: Select a computing node carrying a second type of label as a target node.

[0206] In this embodiment, in response to the task type of the task to be executed being a transmission type, the host node may use the second type as the target type and select a computing node carrying a first type label as the target node.

[0207] Furthermore, the host node may preferentially select a computing node that carries a second type of tag and includes a central processing unit and a programmable controller as the target node.

[0208] S310: The host node dispatches the task to be executed to the target node, so that the target node executes the task to be executed.

[0209] In this embodiment, the host node can schedule the task to be executed to the target node in response to selecting the computing node carrying the target type tag as the target node. After the target node obtains the task to be executed, it can execute the task to be executed.

[0210] Furthermore, as described above, the task to be executed can be split into multiple levels to form multiple data subtasks, and multiple computing nodes can be selected as target nodes to schedule the data subtasks to multiple target nodes, and the multiple target nodes can collaborate to execute the task to be executed.

[0211] The data demand factors and computing power demand factors are explained in detail below and will not be elaborated here.

[0212] The code to be executed can be statically analyzed based on the code analysis tool to build the code abstract syntax tree (AST). The code structure can be obtained by analyzing the AST. The code structure can include the location and nested relationship of function definitions, loop statements, conditional statements, etc.

[0213] The number of function calls, the number of loops, and the proportion of each type of execution are used as statistical key indicators to obtain each key indicator.

[0214] Code analysis tools can traverse the AST, count the number of times each function is called, understand the frequency of use of functions in the code, and obtain the number of function calls.

[0215] Identify loop structures in the code (such as for and while loops) and calculate the number of loop iterations. For loops with fixed iterations, the number of loops can be obtained directly; for loops with dynamic iterations, take the average value = (maximum number of loops + minimum number of loops) / 2 and make an approximate estimate to obtain the number of loops.

[0216] The instructions in the code are divided into different types, such as calculation instructions (such as arithmetic operations, logical operations), memory access instructions (such as reading and writing memory operations), etc., and the proportion of each type of instruction in the code is counted to obtain the proportion of each type of instruction.

[0217] The key indicators obtained can be used as computing power demand factors and data demand factors, and the key indicators can be analyzed to determine the task type of the task to be executed.

[0218] As described above, the task type of the task to be executed may include computing power type, memory type, and transmission type.

[0219] The computing power type can be considered as a computationally intensive task. If the loop body of the task code to be executed contains a large number of computing instructions, and the computing instructions account for a high proportion of the total number of instructions (for example, the threshold is set to exceed 60%), then the task to be executed can be judged as a computationally intensive task. For example, in a scientific computing program, there are a large number of matrix operations, and the loop contains a large number of multiplication and addition operations, which can be judged to meet the characteristics of a computationally intensive task.

[0220] The memory type can be considered as a memory-intensive task. If a function frequently accesses memory data structures, the amount of data accessed is large, and the memory access instructions account for a high proportion of the total number of instructions (the threshold is set to be greater than 50%), then the task to be executed may be a memory-intensive task. For example, in a big data processing program, functions continuously read and write large arrays or linked lists.

[0221] The transfer type can be considered as an I / O (Input / Output) intensive task. If the function frequently accesses the storage device, the code contains a large number of I / O operation statements such as file reading and writing, network requests, and these operations are frequently called during the execution of the task to be executed, the execution time accounts for a large proportion, and the calculation operations are relatively small (the threshold is set to exceed 50%), then the task to be executed can be judged as an I / O intensive task. For example, in a data processing program, there are a large number of open() functions (open window functions) for file reading and writing, or request libraries for network requests, and the execution time exceeds 50%. In this case, the task is I / O intensive.

[0222] Furthermore, the data subtask can be used as an evaluation subject to evaluate the computing power requirement factor and the data requirement factor. In this way, in this embodiment, the task type of the data subtask can also be represented by a fixed-length variable.

[0223] For example, an 8-bit fixed-length variable can be used, the upper 2 bits represent the subtask type, 2'b00 represents the functional subtask, 2'b01 represents the data subtask, and 2'b11 represents unrecognized. The last 6 bits represent the feature category, 6'b000000 represents unrecognized, 6'b000001 represents the computing power type, 6'b000010 represents the memory type, and 6'b000011 represents the transmission type.

[0224] In this embodiment, further, before selecting a computing node carrying a target type label as a target node, the current state of each computing node may be scored to select a computing node with a relatively high score as the target node.

[0225] Specifically, the host node evaluates the performance score of the computing node. The performance score is used to represent the computing power performance of the performance modules contained in the computing node, and the performance module types include graphics processors, central processing units, and programmable controllers. The host node evaluates the memory score and transmission score of the computing node. The host node fits the performance score, memory score, and transmission score of the computing node to obtain a comprehensive score of the computing node. The host node selects the computing node based on the performance score and / or the comprehensive score.

[0226] That is to say, in this embodiment, resource evaluation of computing nodes can be performed to quantitatively evaluate resource status of computing nodes such as computing capacity, memory capacity, transmission capacity, and comprehensive capacity.

[0227] System performance tools and task queue monitoring tools can be used to collect system status data of computing nodes in real time. System status data may include but is not limited to CPU utilization, memory bandwidth, and I / O bandwidth.

[0228] CPU utilization reflects the workload of the computing unit. Memory bandwidth reflects the rate of memory data transfer. Available memory space represents the amount of data that a computing node can carry. I / O bandwidth represents the data transfer efficiency of input and output operations.

[0229] Based on the collected system status data, an evaluation score of available capacity is generated for the computing node, namely, performance score, memory score, transmission score and comprehensive score.

[0230] The evaluation score can be used as a key indicator to measure the availability and performance level of node resources. It can present the real-time status of computing nodes relatively intuitively. At the same time, considering that the load of the task scheduling system is in dynamic change, the evaluation score can be dynamically updated according to the real-time fluctuation of the load. By continuously adjusting the evaluation score, the continuous tracking of the system resource status can be achieved. During the task execution process, the execution path of the data subtask / functional subtask / task to be executed is dynamically adjusted according to the real-time updated evaluation score. Data subtasks / functional subtasks / tasks to be executed can be preferentially assigned to nodes with high evaluation scores, abundant resources and superior performance, thereby effectively reducing the risk of idle or over-concentrated resources.

[0231] The specific node resource evaluation method can be described as follows. The three dimensions of computing power, memory capacity, and I / O capacity can be scored separately, and the comprehensive score can be calculated by combining the weights. The score of each dimension is based on specific performance indicators, and is converted into a unified score range through standardization. The following takes the score range of 0-100 as an example to illustrate the specific calculation formula.

[0232] Performance scoring is equivalent to evaluating the computing power of computing nodes, which can focus on the computing performance of computing nodes. The specific evaluation formula can be as follows: CPU score = (CPU actual value − CPU minimum value) / (CPU maximum value − CPU minimum value) × 100 GPUscore = (CPU actual value − CPU minimum value) / (CPU maximum value − CPU minimum value) × 100 Among them, CPUscore represents the CPU score; CPU actual value represents the actual performance value of the current CPU of the task scheduling system; CPU minimum value represents the minimum performance value of the CPU calibration; CPU maximum value represents the maximum performance value of the CPU calibration. GPUscore represents the GPU score; GPU actual value represents the actual performance value of the current GPU of the task scheduling system; GPU minimum value represents the minimum performance value of the GPU calibration; GPU maximum value represents the maximum performance value of the GPU calibration.

[0233] FPGAscore = (number of used logic units / total number of logic units) * 100 Among them, FPGAscore represents the performance score of FPGA.

[0234] For example, the performance modes of the current computing node include CPU and FPGA, and the calculation formula for the performance score can be as follows: Performancescore=i* CPUscore+j* FPGAscore Among them, Performancescore represents the performance score; i and j represent the weight factors of each performance module, and the sum of the two can be 1. That is, the scores of each performance module of the computing node can be weighted and integrated to obtain the performance score of the computing node.

[0235] The memory score can be obtained through the embedded processor, the total amount of physical memory and the available physical memory size of the computing node, and the kernel tool is used to test the read and write bandwidth of the computing node memory. The specific evaluation formula can be as follows: Memoryscore = k*available physical memory / total physical memory + l*actual memory bandwidth / reference memory bandwidth Among them, Memoryscore represents the memory score; k and l are weight coefficients, and k+l=1.

[0236] The transfer score can obtain the compute node disk I / O performance through the embedded processor, test the disk read and write performance, and obtain the disk read and write speed. At the same time, read the disk size and available disk space. The specific evaluation formula can be as follows: IOscore = q * disk read / write speed / reference disk read / write speed + r * available disk space / disk size; Among them, IOscore represents the transmission score; q and r are weight coefficients, and q+r=1.

[0237] The performance score, memory score, and transmission score can be weighted and integrated. Specifically, a weight can be assigned to each dimension according to the needs of the application scenario, and the weight can be adjusted according to specific needs.

[0238] For example, when the task to be executed is database table preprocessing, computing capability can be assigned a weight of 40%, memory capability can be assigned a weight of 30%, and I / O capability can be assigned a weight of 30%. The specific evaluation formula for the comprehensive score can be: Comprehensive score = (Performancescore*0.4)+(Memoryscore*0.3)+(IOscore *0.3).

[0239] That is to say, if the task type of the task to be executed is a transmission type, the weight of the I / O capability can be increased; if the task type of the task to be executed is a computing power type, the weight of the computing power can be increased, and so on.

[0240] That is to say, during the execution of the task to be executed, the task execution path can be planned according to the task characteristics and resource status.

[0241] In the process of planning the task execution path, the input information may include array task information, including the priority of the subtask, waiting time, required memory space, data processing volume, subtask type, subtask feature category and dependent task array number; resource evaluation information of each node, including computing power score, memory power score, I / O power score and comprehensive power score. Among them, the subtask can represent a functional subtask or a data subtask.

[0242] The execution path of the task to be executed is planned based on the input information. In response to the completion of the planning, the output information may include the subtask execution path, specifically including the execution order and data transmission path of the subtask between the first type and the second type of computing nodes.

[0243] In layman's terms, in this application, when scheduling tasks, tasks can be sorted according to their priority, with high-priority tasks being prioritized. If they need to rely on other tasks, the dependent tasks will be prioritized to ensure that key tasks are completed in a timely manner. Then, when scheduling tasks of the same priority, tasks with longer waiting times will be prioritized. If they need to rely on other tasks, the dependent tasks will be prioritized.

[0244] After confirming the subtask to be executed, schedule the accelerated computing node according to the task type.

[0245] If the task type is a compute-intensive task, it will be scheduled to the near-memory GPU computing node with a high computing resource score and low load first, and the score will be updated according to the GPU computing performance scoring rules, and the computing node with the highest score will be selected. This ensures that the task can be executed quickly. For example, for tasks such as regular expressions and sorting in the database.

[0246] If the task type is memory-intensive, it is assigned to a node with a high memory resource score, such as a near-memory node or a near-storage computing node equipped with large-capacity memory, to ensure that the task has enough memory space to process data. For example, data caching and preprocessing tasks in big data analysis are preferentially assigned to nodes with sufficient memory.

[0247] If the task type is an I / O intensive task, it is assigned to a near-storage computing node with good storage I / O performance, taking advantage of its proximity to the storage device to reduce data transmission latency. For example, a database query task is scheduled to a near-storage computing node with high-speed SSD storage and sufficient I / O bandwidth. For memory or IO intensive tasks, CPU and FPGA nodes are preferred. The evaluation score is calculated according to the rules, the required weight ratio is set, the comprehensive score is obtained, and the node with the highest score is selected.

[0248] In summary, this application uses the cache consistency, memory semantics, and low-latency communication characteristics of the target bus protocol to provide a task scheduling system architecture that is compatible with computing nodes of multiple node types, and provides a task scheduling method. HIA also covers different cache management modes that support target bus protocol consistency. For example, by integrating near-storage computing and near-memory computing, the synergistic advantages of the two can be achieved. On the premise of ensuring support for heterogeneous cache consistency, computing tasks can be efficiently offloaded to acceleration devices near storage and memory to achieve nearby task execution.

[0249] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0250] An embodiment of the present application also provides an electronic device.

[0251] See also Figure 7 , Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application.

[0252] In an embodiment, an electronic device may include a memory and a processor.

[0253] The memory stores a computer program.

[0254] The processor is configured to run a computer program to execute the steps in any of the above-mentioned task scheduling method embodiments.

[0255] The embodiment of the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned task scheduling method embodiments when running.

[0256] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0257] The embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned task scheduling method embodiments are implemented.

[0258] The embodiment of the present application also provides another computer program product. The computer program product includes a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned task scheduling method embodiments are implemented.

[0259] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0260] The above describes in detail a task scheduling method, a task scheduling system, an electronic device, and a computer-readable storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application, and the description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A task scheduling method, characterized in that: The task scheduling method comprises: The host node of the server obtains node information of the computing node, identifies the node type represented by the node information, and assigns a type label to the computing node that matches its node type; wherein the node type includes at least a first type and a second type, the computing efficiency of the first type is higher than the computing efficiency of the second type, and the data processing efficiency of the second type is higher than the data processing efficiency of the first type; The host node obtains the task to be executed and evaluates the task type of the task to be executed; The host node uses the node type matching the task type as the target type, selects the computing node carrying the target type label as the target node, and schedules the task to be executed to the target node, so that the target node executes the task to be executed.

2. The task scheduling method according to claim 1, characterized in that: The node information includes a type code; the identifying the node type represented by the node information includes: The host node obtains the type code of the computing node; In response to the type code being a first code, the host node determines that the computing node belongs to the first type; In response to the type code being a second code, the host node determines that the computing node belongs to the second type.

3. The task scheduling method according to claim 2, characterized in that: The host node obtains the node information of the computing node to which it is connected, including: The host node accesses the base address register of the computing node through the target bus protocol; The host node reads the initial value of the reserved type bit in the base address register, and uses the initial value as the type code.

4. The task scheduling method according to claim 1, characterized in that: The task type of evaluating the task to be performed includes: The host node evaluates the computing power requirement factor and the data requirement factor of the task to be executed; The host node comprehensively considers the computing power requirement factor and the data requirement factor to assess the task type of the task to be executed; wherein the task type includes computing power type, memory type, and transmission type.

5. The task scheduling method according to claim 4, characterized in that: The host node uses the node type matching the task type as the target type, and selecting the computing node carrying the target type label as the target node includes: In response to the task type of the task to be executed being a computing type, the host node uses the first type as the target type; preferentially selects a computing node that includes a graphics processor and carries a first type label as the target node; and / or, In response to the task type of the task to be executed being a memory type, the host node uses the first type as the target type; preferentially selects a computing node that carries the first type label and includes a central processing unit and a programmable controller as the target node; and / or, In response to the task type of the task to be executed being a transmission type, the host node uses the second type as the target type; and preferentially selects a computing node that carries a second type label and includes a central processing unit and a programmable controller as the target node.

6. The task scheduling method according to claim 1, characterized in that: The step of scheduling the task to be executed to the target node comprises: The host node divides the to-be-executed task according to the task function to form a plurality of functional subtasks; divides the functional subtasks into a plurality of data subtasks; wherein the task functions of the plurality of data subtasks match, and there are differences in the task processing data; The host node dispatches the data subtask to the plurality of target nodes.

7. The task scheduling method according to claim 1 or 6, characterized in that: The step of selecting a computing node carrying a target type label as a target node includes: The host node evaluates the performance score of the computing node; wherein the performance score is used to represent the computing performance of the performance module included in the computing node, and the performance module types include a graphics processor, a central processing unit, and a programmable controller; The host node evaluates the memory score and the transmission score of the computing node; The host node fits the performance score, memory score and transmission score of the computing node to obtain a comprehensive score of the computing node; The host node selects the computing node based on the performance score and / or the comprehensive score.

8. The task scheduling method according to claim 1, characterized in that: The task scheduling method comprises: The server selects a current cache management mode from a plurality of cache management modes; Among them, the cache management mode of the server includes at least a global mode and a local mode; the global mode indicates that the server memory is globally byte addressed so that the host node can globally schedule the server memory; the server memory includes host memory and computing node memory; the local mode indicates that the computing node independently controls its computing node memory and synchronizes data changes in the computing node memory with other computing nodes.

9. The task scheduling method according to claim 8, characterized in that: The server includes, before selecting a current cache management mode from a plurality of cache management modes: The computing node maintains a local cache directory; the host node maintains a global cache directory; wherein the global cache directory includes a node identifier of the computing node and the local cache directory; The computing node monitors the cache status of the cache blocks included in the computing node; wherein the cache status at least includes a valid state, an invalid state, and a dirty state.

10. A task scheduling system, characterized in that: The task scheduling system is used to implement the task scheduling method according to any one of claims 1 to 9; The task scheduling system comprises: Host node; A computing node, including computing nodes of multiple node types; the node types include at least a first type and a second type, the computing efficiency of the first type is higher than the computing efficiency of the second type, and the data processing efficiency of the second type is higher than the data processing efficiency of the first type; The switch module is connected to the host node and the computing node respectively, and the host node and the computing node communicate with each other through the switch module.

11. The task scheduling system according to claim 10, characterized in that: The task scheduling system also includes a host memory and a storage device; The host memory is connected to the switch module, and is connected to the host node and the computing node of the first type through the switch module; The storage device is connected to the computing node of the second type, and is connected to the switch module and the host node through the computing node of the second type.

12. The task scheduling system according to claim 10 or 11, characterized in that: The switch module includes a first module and a second module; the first module and the second module are connected, and at least one of the first module and the second module is connected to the host node; The first module is connected to the host memory and the computing nodes of the first type; The second module is connected to the computing nodes of the second type.

13. The task scheduling system according to claim 10, characterized in that: A component module of a computing node of the first type is integrated into a field programmable gate array; a component module of a computing node of the second type is integrated into a field programmable gate array.

14. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the task scheduling method as claimed in any one of claims 1 to 9 when executing the computer program.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the task scheduling method according to any one of claims 1 to 9.

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