CPU (Central Processing Unit) external high-precision timer and design method thereof

Abstract

The invention provides a CPU (Central Processing Unit) external high-precision timer and a design method thereof. The CPU external high-precision timer comprises a CPU, an FPGA (Field Programmable Gate Array) and a high-frequency crystal oscillator, the CPU is used for issuing timing duration parameters and timing start and end commands, receiving timing hard interruption, processing timing interruption and finishing timing task processing; the FPGA is used for accurately metering time and triggering hard interrupt of the CPU after the time is up; the high-frequency crystal oscillator is used for providing an accurate time metering reference for the FPGA; the CPU is connected and intercommunicated with the FPGA through any communication mode; and the FPGA connects an output pin of the FPGA to a GPIO pin capable of mounting interruption of the CPU, and simultaneously connects a certain input pin of the FPGA to the output of the high-frequency crystal oscillator. According to the technical scheme, the high-precision clock which is more stable, occupies less CPU resources and has cross-system transportability can be realized.

Description

Technical Field

[0001] The invention belongs to the field of electronic information technology, and particularly relates to a CPU external high-precision timer and a design method thereof. Background Art

[0002] In computer systems and embedded systems, high-precision timers have always been an indispensable part and are widely used. In computers and embedded systems, they mainly handle events such as delays, sleep, and task scheduling, and are a key link in the precise control of time in the system. In current communication application scenarios, it is often necessary to use high-precision timers to accurately control and schedule communication time slots to achieve time-division multiplexing communication. In other scenarios, high-precision timers are also used between various devices in certain systems to synchronize system time.

[0003] At present, embedded systems on various CPU platforms widely support low-precision timers and high-precision timers. However, the high-precision clock implemented on the CPU often relies on the CPU's main frequency to achieve actual time by using the difference in the main frequency's timestamp. Although this method has high precision, the counting accuracy will be affected in scenarios such as multi-core processing, heavy task load, and overclocking. Secondly, this method often takes up more CPU resources, and it also has certain complexity in software implementation. The interfaces are different on different operating systems, and it cannot be transplanted, which is inconvenient to use.

[0004] Therefore, how to provide a CPU external high-precision timer and a design method thereof, which can realize a more stable high-precision clock with less CPU resource usage and cross-system portability, has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The embodiment of the present invention provides a CPU external high-precision timer and a design method thereof, which can realize a high-precision clock that is more stable, occupies less CPU resources and has cross-system portability.

[0006] In one embodiment of the present invention, a high-precision timer external to a CPU is provided, comprising: a CPU, an FPGA and a high-frequency crystal oscillator; The CPU is used to issue the timing duration parameters and the timing start and end commands, receive the timing hardware interrupt, process the timing interrupt and complete the timing task processing; The FPGA is used for accurate measurement of time and triggers a hard interrupt of the CPU when the time is reached; The high frequency crystal oscillator is used to provide the FPGA with an accurate time measurement reference; The CPU is connected to the FPGA through any communication method; the FPGA connects its output pin to a GPIO pin of the CPU that can mount an interrupt, and connects one of its input pins to the output of a high-frequency crystal oscillator.

[0007] Furthermore, the CPU communicates with the FPGA via at least a PCIe interface, and sends to the FPGA at least a command including a timing duration parameter, a timer start, a timer stop, and a GPIO level setting; After the interrupt is triggered, the CPU enters the callback function and processes the pending tasks at a fixed time.

[0008] Furthermore, the CPU sends various instructions to the FPGA to customize the communication protocol; The message sent by the CPU to the FPGA includes at least: a timer-related command start bit, a command type, a command length, a timing duration, an on or off command, a GPIO status bit that needs to be set, and a check bit.

[0009] Furthermore, the FPGA protocol chip adopts SMQ7K325T, which is used to receive relevant parameters and instructions sent by the CPU, and perform timing and counting based on the crystal oscillator output, change the GPIO level state, and trigger the CPU hard interrupt.

[0010] Furthermore, the CPU uses Loongson 2K1000 equipped with ReWorks operating system, including: PCIe driver, memory mapping to the FPGA, sends timer timing parameters, switch timer instructions, and GPIO level status parameters; A hard interrupt triggered by a falling edge or a rising edge of a GPIO, used to trigger an interrupt when a level change of the output of the FPGA on the GPIO is reached at a timing time; The callback function is used to process the tasks that need to be processed by the timing after the interrupt is triggered.

[0011] Furthermore, the CPU sends instructions to the FPGA using the following protocol: The first byte is fixed to 0xaa, indicating the start of sending timer-related instructions; the second byte is the length of the entire information sent; the third byte is the command type; the fourth to seventh bytes are the timing duration, in seconds. If the command does not need to send the timing duration, write 0; the eighth byte is the GPIO level state that needs to be set, 0 is low level and 1 is high level; the ninth byte is the timer start or stop instruction parameter, 0 represents off, 1 represents on; the tenth byte is the parity check.

[0012] Furthermore, the command type of the third byte is set as follows: 0x01 is the command to start the timer, which should include the initial GPIO level status; 0x02 is the command to stop the timer, which should include the GPIO level status after the end; 0x3 is the command to set the timing duration, which needs to be issued before the command to start the timer.

[0013] Furthermore, after receiving the command to start the timer, the FPGA chip sets the GPIO level state according to the command; uses the output of the high-frequency crystal oscillator as its own counting reference; obtains the count value by calculating the CPU timing time multiplied by the crystal oscillator frequency of the high-frequency crystal oscillator and then dividing by 2, and starts counting from 0; when the count value is reached, changes the GPIO level state, and immediately starts counting again from 0.

[0014] In another embodiment of the present invention, a design method for a CPU external high-precision timer is provided. Based on any one of the above CPU external high-precision timers, the method includes: S101, the CPU configures the PCIe register, sets the memory mapping to the FPGA, and communicates with the FPGA; S102, the CPU configures an unoccupied GPIO hard interrupt, mounts a callback function, sets a task to be completed on time in the function, and sets the interrupt trigger mode to falling edge trigger; S103, configuring the FPGA to recognize various instructions issued by the CPU, including turning on and off the timer, configuring the GPIO level state, and setting the timing duration; S104, configuring the FPGA to store the received timing duration, and calculating the count value by multiplying the timing duration (in seconds) by the crystal oscillator frequency and then dividing by 2, where the duration is in seconds and the frequency is in Hertz; S105, configuring the FPGA to set the corresponding GPIO level state when receiving the start timer instruction, and simultaneously start counting from 0 until the count value, and after reaching the count value, change the GPIO level from low to high or from high to low, and then start counting from 0 again until the count value, and repeat this cycle; S106, when the FPGA is configured to receive a timer shutdown instruction, the corresponding GPIO level state is set, the timing duration and the count value are cleared, and the counting is stopped; S107, the CPU sends a timing duration parameter to the FPGA through PCIe, and sends a start timer instruction, which includes a GPIO level state parameter; S108, FPGA starts counting from 0 to the count value, changes the GPIO level to another state after reaching the count value, and then immediately starts counting again from 0, and repeats this cycle; S109, after the timer is turned on and the time length has passed, the CPU periodically enters an interrupt and calls the callback function to process the timing task; S1010, the CPU sends a command to the FPGA through the PCIe to turn off the timer, and configures the GPIO level to the required final level state; S1011: After receiving the instruction, the FPGA sets the GPIO level state according to the received instruction, clears the timing duration and count, and stops counting.

[0015] The beneficial effects brought by the present invention are as follows: It can be seen from the above scheme that the embodiment of the present invention provides a CPU external high-precision timer and its design method, including: CPU, FPGA and high-frequency crystal oscillator; the CPU is used to issue the timing duration parameters and timing start and end commands, receive timing hard interrupts, and process timing interrupts and complete timing task processing; the FPGA is used for accurate measurement of time, and triggers the CPU hard interrupt after the time is reached; the high-frequency crystal oscillator is used to provide the FPGA with an accurate time measurement reference; the CPU is connected and interoperable with the FPGA through any communication method; the FPGA connects its own output pin to a GPIO pin of the CPU that can mount interrupts, and at the same time connects one of its own input pins to the output of the high-frequency crystal oscillator. The technical solution of the present invention can achieve a more stable, CPU resource-less, and cross-system portable high-precision clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram showing the component structure of a CPU external high-precision timer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] In the embodiment of the present invention, a CPU external high-precision timer and its design method are provided, which measures time by counting with an external FPGA of the CPU, greatly reducing the consumption and occupation of CPU resources by the high-precision timer; the technical solution of the present invention adopts an external high-frequency crystal oscillator as the time reference, which can avoid the problem of unstable fluctuation of the timing time when the CPU's own main frequency is used as the reference for measuring time, and the timing time is stable, accurate and reliable. Among them, the technical solution of the present invention only involves the interrupt mounting of the CPU and the communication interface debugging of the FPGA. The FPGA calculates the count, sets the GPIO level, commands the logic processing and the input and output of the two pins. The amount of code is small, and it is simpler to implement than using the high-precision timer of the CPU system itself.

[0019] Figure 1 A schematic diagram showing the component structure of a CPU external high-precision timer according to an embodiment of the present invention.

[0020] Figure 1 A high-precision timer external to a CPU includes: a CPU, an FPGA, and a high-frequency crystal oscillator; The CPU is used to issue the timing duration parameters and the timing start and end commands, receive the timing hardware interrupt, process the timing interrupt and complete the timing task processing; The FPGA is used for accurate measurement of time and triggers a hard interrupt of the CPU when the time is reached; The high frequency crystal oscillator is used to provide the FPGA with an accurate time measurement reference; The CPU is connected to the FPGA through any communication method; the FPGA connects its output pin to a GPIO pin of the CPU that can mount an interrupt, and connects one of its input pins to the output of a high-frequency crystal oscillator.

[0021] In one embodiment of the present invention, the CPU communicates with the FPGA via at least a PCIe interface, and sends to the FPGA at least a command including a timing duration parameter, a timer start, a timer stop, and a GPIO level setting command; After the interrupt is triggered, the CPU enters the callback function and processes the pending tasks at a fixed time.

[0022] In one embodiment of the present invention, the CPU sends various instructions to the FPGA to customize the communication protocol; The message sent by the CPU to the FPGA includes at least: a timer-related command start bit, a command type, a command length, a timing duration, an on or off command, a GPIO status bit that needs to be set, and a check bit.

[0023] In one embodiment of the present invention, the FPGA protocol chip adopts SMQ7K325T, which is used to receive relevant parameters and instructions sent by the CPU, and perform timing and counting based on the crystal oscillator output, change the GPIO level state, and trigger the CPU hard interrupt.

[0024] In one embodiment of the present invention, the CPU uses Loongson 2K1000 equipped with ReWorks operating system, including: PCIe driver, memory mapping to the FPGA, sends timer timing parameters, switch timer instructions, and GPIO level status parameters; A hard interrupt triggered by a falling edge or a rising edge of a GPIO, used to trigger an interrupt when a level change of the output of the FPGA on the GPIO is reached at a timing time; The callback function is used to process the tasks that need to be processed by the timing after the interrupt is triggered.

[0025] In one embodiment of the present invention, the CPU sends instructions to the FPGA using the following protocol: The first byte is fixed to 0xaa, indicating the start of sending timer-related instructions; the second byte is the length of the entire information sent; the third byte is the command type; the fourth to seventh bytes are the timing duration, in seconds. If the command does not need to send the timing duration, write 0; the eighth byte is the GPIO level state that needs to be set, 0 is low level and 1 is high level; the ninth byte is the timer start or stop instruction parameter, 0 represents off, 1 represents on; the tenth byte is the parity check.

[0026] In one embodiment of the present invention, the command type of the third byte is set as follows: 0x01 is the command to start the timer, which should include the initial GPIO level status; 0x02 is the command to stop the timer, which should include the GPIO level status after the end; 0x3 is the command to set the timing duration, which needs to be issued before the command to start the timer.

[0027] In one embodiment of the present invention, after receiving the command to start the timer, the FPGA chip sets the GPIO level state according to the command; uses the output of the high-frequency crystal oscillator as its own counting reference; obtains the count value by calculating the timing time of the CPU multiplied by the crystal frequency of the high-frequency crystal oscillator and then dividing by 2, and starts counting from 0; when the count value is reached, changes the GPIO level state, and immediately starts counting again from 0.

[0028] In the embodiment of the present invention, the CPU is a processor with a native PCIe interface, and vxWorks, Linux or other operating systems that support hard interrupts and multitasking can be used. In this example, Loongson 2K1000 is selected to carry the ReWorks operating system. FPGA is an FPGA chip with PCIe function and input and output ports. In this example, SMQ7K325T is selected. The high-frequency crystal oscillator uses a constant temperature crystal oscillator with a higher frequency. In the example of the present invention, YY01-C5F18MA-14.7456MHz is selected.

[0029] The CPU uses Loongson 2K1000 equipped with ReWorks operating system, including: PCIe driver, memory mapped to FPGA, sends timer timing parameters, switch timer instructions, and GPIO level status parameters; hard interrupts that can be triggered by the falling or rising edge of GPIO are used to trigger interrupts when the level change of FPGA output on GPIO reaches the timing time; callback function is used to process the tasks that need to be processed by the timing after the interrupt is triggered.

[0030] Among them, Loongson 2K1000 is a low-power general-purpose processor for industrial control and terminal fields, with a main frequency of 1GHz, supporting multiple startup modes, power consumption between 1W-5W, and supporting PCIe interface; ReWorks operating system is a real-time embedded system development and operation platform, compatible with VxWorks embedded real-time operating system, and integrates design / development / debugging / simulation in an integrated development environment, supports hard interrupts, interrupt callback mounting, and has a default PCIe driver configuration.

[0031] In one embodiment of the present invention, the FPGA protocol chip uses SMQ7K325T, which is used to receive relevant parameters and instructions sent by the CPU, perform timing and counting based on the crystal oscillator output, change the GPIO level state, and trigger the CPU hard interrupt.

[0032] SMQ7K325T is a programmable logic device, i.e., an FPGA chip, with very rich internal resources. It contains 840 signal processors, 445 36Kb BRAMs, 326080 logic units, 10 CMTs, 1 PCIe2.1, 16 GTX and other programmable resources, which is very suitable for the application needs of the present invention.

[0033] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. PCIe uses serial communication and point-to-point transmission. Each device has its own bus. This design provides higher data transmission rates and better scalability. Compared with the traditional parallel bus structure, PCIe's serial transmission method can reduce signal interference and increase data transmission rates. In addition, PCIe supports multiple channels, each of which can transmit data independently, thereby increasing the overall bandwidth. This design makes PCIe an ideal choice for connecting computer hardware devices, especially for peripheral devices that require high-speed data transmission, including FPGA chips.

[0034] In the embodiment of the present invention, the high frequency crystal oscillator model is YY01-C5F18MA-14.7456MHz, which is a constant temperature crystal oscillator with a vibration frequency of 14.7456MHz.

[0035] In another embodiment of the present invention, a design method for a CPU external high-precision timer is provided. Based on any one of the above CPU external high-precision timers, the method includes: S101, the CPU configures the PCIe register, sets the memory mapping to the FPGA, and communicates with the FPGA; S102, the CPU configures an unoccupied GPIO hard interrupt, mounts a callback function, sets a task to be completed on time in the function, and sets the interrupt trigger mode to falling edge trigger; S103, configuring the FPGA to recognize various instructions issued by the CPU, including turning on and off the timer, configuring the GPIO level state, and setting the timing duration; S104, configuring the FPGA to store the received timing duration, and calculating the count value by multiplying the timing duration (in seconds) by the crystal oscillator frequency and then dividing by 2, where the duration is in seconds and the frequency is in Hertz; S105, configuring the FPGA to set the corresponding GPIO level state when receiving the start timer instruction, and simultaneously start counting from 0 until the count value, and after reaching the count value, change the GPIO level from low to high or from high to low, and then start counting from 0 again until the count value, and repeat this cycle; S106, when the FPGA is configured to receive a timer shutdown instruction, the corresponding GPIO level state is set, the timing duration and the count value are cleared, and the counting is stopped; S107, the CPU sends a timing duration parameter to the FPGA through PCIe, and sends a start timer instruction, which includes a GPIO level state parameter; S108, FPGA starts counting from 0 to the count value, changes the GPIO level to another state after reaching the count value, and then immediately starts counting again from 0, and repeats this cycle; S109, after the timer is turned on and the time length has passed, the CPU periodically enters an interrupt and calls the callback function to process the timing task; S1010, the CPU sends a command to the FPGA through the PCIe to turn off the timer, and configures the GPIO level to the required final level state; S1011: After receiving the instruction, the FPGA sets the GPIO level state according to the received instruction, clears the timing duration and count, and stops counting.

[0036] In one embodiment of the present invention, a design method for a CPU external high-precision timer measures time by counting with an external FPGA of the CPU, which greatly reduces the consumption and occupation of CPU resources by the high-precision timer. The method uses an external high-frequency crystal oscillator as a time reference, avoiding the problem of unstable fluctuations in timing time when the CPU's own main frequency is used as a reference for measuring time, and the timing time is stable, accurate and reliable. The design method only involves CPU interrupt mounting and FPGA communication interface debugging, FPGA calculation counting, GPIO level setting, command logic processing and input and output of two pins, and the amount of code is small, so it is easier to implement than using the CPU system's own high-precision timer.

[0037] The above are preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A high-precision timer external to a CPU, characterized in that: The timer includes: a CPU, an FPGA and a high-frequency crystal oscillator; The CPU is used to issue the timing duration parameters and the timing start and end commands, receive the timing hardware interrupt, process the timing interrupt and complete the timing task processing; The FPGA is used for accurate measurement of time and triggers a hard interrupt of the CPU when the time is reached; The high frequency crystal oscillator is used to provide the FPGA with an accurate time measurement reference; The CPU is connected to the FPGA through any communication method; the FPGA connects its output pin to a GPIO pin of the CPU that can mount an interrupt, and connects one of its input pins to the output of a high-frequency crystal oscillator.

2. The high-precision timer external to a CPU according to claim 1, characterized in that: The CPU communicates with the FPGA via at least a PCIe interface, and sends to the FPGA at least a command including a timing duration parameter, a timer start, a timer stop, and a GPIO level setting command; After the interrupt is triggered, the CPU enters the callback function and processes the pending tasks at a fixed time.

3. The high-precision timer external to a CPU according to claim 1, characterized in that: The CPU sends various instructions to the FPGA and customizes the communication protocol; The message sent by the CPU to the FPGA includes at least: a timer-related command start bit, a command type, a command length, a timing duration, an on or off command, a GPIO status bit that needs to be set, and a check bit.

4. The high-precision timer external to a CPU according to claim 1, characterized in that: The FPGA protocol chip adopts SMQ7K325T, which is used to receive relevant parameters and instructions sent by the CPU, and to perform timing and counting based on the crystal oscillator output, change the GPIO level state, and trigger the CPU hard interrupt.

5. The high-precision timer external to a CPU according to claim 1, characterized in that: The CPU uses Loongson 2K1000 equipped with ReWorks operating system, including: PCIe driver, memory mapping to the FPGA, sends timer timing parameters, switch timer instructions, and GPIO level status parameters; A hard interrupt triggered by a falling edge or a rising edge of a GPIO, used to trigger an interrupt when a level change of the output of the FPGA on the GPIO is reached at a timing time; The callback function is used to process the tasks that need to be processed by the timing after the interrupt is triggered.

6. The high-precision timer external to a CPU according to claim 1, characterized in that: The CPU sends instructions to the FPGA using the following protocol: The first byte is fixed to 0xaa, indicating the start of sending timer-related instructions; the second byte is the length of the entire information sent; the third byte is the command type; the fourth to seventh bytes are the timing duration, in seconds. If the command does not need to send the timing duration, write 0; the eighth byte is the GPIO level state that needs to be set, 0 is low level and 1 is high level; the ninth byte is the timer start or stop instruction parameter, 0 represents off, 1 represents on; the tenth byte is the parity check.

7. The high-precision timer external to a CPU according to claim 6, characterized in that: The command type of the third byte is set as follows: 0x01 is the command to start the timer, which should include the initial GPIO level status; 0x02 is the command to stop the timer, which should include the GPIO level status after the end; 0x3 is the command to set the timing duration, which needs to be issued before the command to start the timer.

8. The high-precision timer external to a CPU according to claim 6, characterized in that: After receiving the start timer command, the FPGA chip sets the GPIO level state according to the command; uses the output of the high-frequency crystal oscillator as its own counting reference; obtains the count value by calculating the timing time of the CPU multiplied by the crystal frequency of the high-frequency crystal oscillator and then dividing by 2, and starts counting from 0; When the count value is reached, the GPIO level state is changed and the count starts again from 0 immediately.

9. A method for designing a CPU external high-precision timer, based on a CPU external high-precision timer as claimed in any one of claims 1 to 8, the method comprising: S101, the CPU configures the PCIe register, sets the memory mapping to the FPGA, and communicates with the FPGA; S102, the CPU configures an unoccupied GPIO hard interrupt, mounts a callback function, sets a task to be completed on time in the function, and sets the interrupt trigger mode to falling edge trigger; S103, configuring the FPGA to recognize various instructions issued by the CPU, including turning on and off the timer, configuring the GPIO level state, and setting the timing duration; S104, configuring the FPGA to store the received timing duration, and calculating the count value by multiplying the timing duration (in seconds) by the crystal oscillator frequency and then dividing by 2, where the duration is in seconds and the frequency is in Hertz; S105, configuring the FPGA to set the corresponding GPIO level state when receiving the start timer instruction, and simultaneously start counting from 0 until the count value, and after reaching the count value, change the GPIO level from low to high or from high to low, and then start counting from 0 again until the count value, and repeat this cycle; S106, when the FPGA is configured to receive a timer shutdown instruction, the corresponding GPIO level state is set, the timing duration and the count value are cleared, and the counting is stopped; S107, the CPU sends a timing duration parameter to the FPGA through PCIe, and sends a start timer instruction, which includes a GPIO level state parameter; S108, FPGA starts counting from 0 to the count value, changes the GPIO level to another state after reaching the count value, and then immediately starts counting again from 0, and repeats this cycle; S109, after the timer is turned on and the time length has passed, the CPU periodically enters an interrupt and calls the callback function to process the timing task; S1010, the CPU sends a command to the FPGA through the PCIe to turn off the timer, and configures the GPIO level to the required final level state; S1011: After receiving the instruction, the FPGA sets the GPIO level state according to the received instruction, clears the timing duration and count, and stops counting.

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